Sensor chip

Abstract

A sensor chip is provided. The sensor chip includes: a first substrate; the piezoresistor is located on the first substrate base plate; the second substrate is positioned on one side, far away from the first substrate, of the piezoresistor; a metal wire bond extending through the second substrate; and the pressure reference chamber is positioned between the first substrate and the second substrate. The first substrate and the second substrate encapsulate at least a portion of the varistor within the pressure reference chamber.

Description

Technical Field

[0001] The present invention relates to sensing technology, and in particular to a sensor chip. Background Art

[0002] A pressure sensor is an electronic device that converts a pressure signal into an electrical signal. Based on the principle of the pressure chip, these sensors can be divided into four main types: resistive pressure sensors, capacitive pressure sensors, resonant pressure sensors, and piezoelectric pressure sensors. Among them, silicon resistive pressure sensors are the most widely used due to their advantages, such as simple manufacturing process, low cost, high reliability, and compatibility with complementary metal oxide semiconductor (CMOS) technology. In 2020, resistive pressure sensors accounted for approximately 85% of the entire market for microelectromechanical systems (MEMS) pressure sensors, establishing them as the main choice. These sensors have a wide range of applications in various industries including automotive, industrial control, consumer electronics, construction, medical, and other sectors. Therefore, they are currently considered to be the most widely used MEMS pressure sensors. Summary of the invention

[0003] On the one hand, the present disclosure provides a sensor chip, comprising: a first substrate; a piezoresistor located on the first substrate; a second substrate located on a side of the piezoresistor away from the first substrate; a metal wire bond extending through the second substrate; and a pressure reference chamber located between the first substrate and the second substrate; wherein the first substrate and the second substrate encapsulate at least a portion of the piezoresistor within the pressure reference chamber.

[0004] Optionally, the sensor chip further comprises a resistor lead on the first substrate substrate; wherein the resistor lead is connected to the piezoresistor and to the metal wire bond.

[0005] Optionally, the sensor chip further comprises a redistribution layer located on a side of the second substrate substrate away from the first substrate substrate; wherein the redistribution layer is connected to the metal wire bonding.

[0006] Optionally, the sensor chip further comprises: an under bump metallization layer located on a side of the second substrate away from the first substrate; and a welding joint located on a side of the under bump metallization layer away from the second substrate and connected to the under bump metallization layer.

[0007] Optionally, the sensor chip further comprises a via extending through the second substrate substrate; wherein the metal wire bonding is at least partially located in the via.

[0008] Optionally, the via hole has a trapezoidal shape, and an angle is formed between a top surface and a side surface of the trapezoidal shape; and the angle is in a range of 80 degrees to 90 degrees.

[0009] Optionally, the sensor chip includes a pressure sensing layer, which is configured to convert a pressure signal into a deformation signal; wherein the pressure sensing layer includes a portion of the first substrate located between two piezoresistors; and the piezoresistors are configured to convert the deformation signal into an electrical signal.

[0010] Optionally, a surface of a portion of the first substrate between the two piezoresistors is exposed to the pressure reference chamber.

[0011] Optionally, the sensor chip also includes an insulating layer located on the first substrate; wherein the piezoresistor is located on a side of the insulating layer away from the first substrate; the pressure reference chamber is located between the insulating layer and the second substrate; and the insulating layer and the second substrate encapsulate at least a portion of the piezoresistor within the pressure reference chamber.

[0012] Optionally, the sensor chip includes a pressure sensing layer, which is configured to convert a pressure signal into a deformation signal; wherein the pressure sensing layer includes a portion of the first substrate located between the two piezoresistors and a portion of the insulating layer located between the two piezoresistors; and the piezoresistors are configured to convert the deformation signal into an electrical signal.

[0013] Optionally, a surface of a portion of the insulating layer located between the two piezoresistors is exposed to the pressure reference chamber.

[0014] Optionally, the sensor chip further comprises a thermistor located on a side of the second substrate away from the first substrate.

[0015] Optionally, the sensor chip further comprises a hygrometer located on a side of the second substrate away from the first substrate.

[0016] Optionally, the sensor chip further comprises one or more zero adjustment resistors located on a side of the second substrate away from the first substrate.

[0017] Optionally, the sensor chip includes: a first piezoresistor located on the first substrate; a first metal wire bond located on a side of the second substrate away from the first substrate and electrically connected to the first piezoresistor; at least one of a first under-bump metallization layer, a second under-bump metallization layer or a third under-bump metallization layer located on a side of the second substrate away from the first substrate; and at least one of a first zero adjustment resistor, a second zero adjustment resistor or a third zero adjustment resistor, wherein the first zero adjustment resistor is connected to the first metal wire bond and connected to the first under-bump metallization layer, the second zero adjustment resistor is connected to the first metal wire bond and connected to the second under-bump metallization layer, and the third zero adjustment resistor is connected to the first metal wire bond and connected to the third under-bump metallization layer.

[0018] Optionally, the sensor chip also includes: a fourth piezoresistor, which is located on the first substrate; an eighth metal wire bond, which is located on the side of the second substrate away from the first substrate and is electrically connected to the fourth piezoresistor; at least one of a fourth under-bump metallization layer, a fifth under-bump metallization layer or a sixth under-bump metallization layer, which is located on the side of the second substrate away from the first substrate; and at least one of a fourth zero adjustment resistor, a fifth zero adjustment resistor or a sixth zero adjustment resistor, wherein the fourth zero adjustment resistor is connected to the eighth metal wire bond and connected to the fourth under-bump metallization layer, the fifth zero adjustment resistor is connected to the eighth metal wire bond and connected to the fifth under-bump metallization layer, and the sixth zero adjustment resistor is connected to the eighth metal wire bond and connected to the sixth under-bump metallization layer.

[0019] Optionally, the sensor chip also includes a second piezoresistor and a third piezoresistor located on the first substrate; wherein, when no pressure is applied to the sensor chip, the resistance of the second piezoresistor, the resistance of the third piezoresistor, the resistance of the first piezoresistor and one of the first zero adjustment resistor, the second zero adjustment resistor or the third zero adjustment resistor, and the resistance of the fourth piezoresistor and one of the fourth zero adjustment resistor, the fifth zero adjustment resistor or the sixth zero adjustment resistor are substantially the same.

[0020] Optionally, the sensor chip further comprises one or more fixed resistors located on a side of the second substrate away from the first substrate.

[0021] Optionally, the sensor chip also includes: a first piezoresistor and a second piezoresistor, which are located on the first substrate; a first fixed resistor and a second fixed resistor, which are located on a side of the second substrate away from the first substrate; a first metal wire bond, which is located on a side of the second substrate away from the first substrate and is electrically connected to the first piezoresistor; a second metal wire bond, which is located on a side of the second substrate away from the first substrate and is electrically connected to the first piezoresistor; a third metal wire bond, which is located on a side of the second substrate away from the first substrate and is electrically connected to the second piezoresistor; and a fourth metal wire bond, which is located on a side of the second substrate away from the first substrate and is electrically connected to the second piezoresistor; wherein the first fixed resistor is electrically connected to the first metal wire bond and is electrically connected to the second fixed resistor; and the second fixed resistor is electrically connected to the fourth metal wire bond and is electrically connected to the first fixed resistor.

[0022] Optionally, the sensor chip also includes a first under-bump metallization layer, a second under-bump metallization layer, a third under-bump metallization layer and a fourth under-bump metallization layer located on a side of the second substrate away from the first substrate; wherein the first under-bump metallization layer is connected to the first metal wire bond and to the first fixed resistor; the second under-bump metallization layer is connected to the second metal wire bond and to the third metal wire bond; the third under-bump metallization layer is connected to the first fixed resistor and to the second fixed resistor; and the fourth under-bump metallization layer is connected to the second fixed resistor and to the fourth metal wire bond. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0024] Figure 1 is a schematic diagram showing the structure of a sensor chip in some embodiments of the present disclosure.

[0025] Figure 2 Shows the Wheatstone bridge principle.

[0026] Figure 3 is a schematic diagram showing the structure of a Wheatstone bridge.

[0027] Figure 4 is a schematic diagram showing the structure of a sensor chip in some embodiments of the present disclosure.

[0028] Figure 5The layout of piezoresistors and resistor leads on a first substrate substrate of a sensor chip according to some embodiments of the present disclosure is shown.

[0029] Figure 6 Layout of metal wire bonding and under bump metallization layers on a second substrate substrate of a sensor chip according to some embodiments of the present disclosure is shown.

[0030] 7A to 7J The process of manufacturing a sensor chip according to some embodiments of the present disclosure is shown.

[0031] Figure 8 A via extending through a second substrate substrate is shown in accordance with some embodiments of the present disclosure.

[0032] Fig. 9 is a schematic diagram showing the structure of a sensor chip in some embodiments of the present disclosure.

[0033] FIG. 10A to FIG. 10J The process of manufacturing a sensor chip according to some embodiments of the present disclosure is shown.

[0034] Fig.11 is a schematic diagram showing the structure of a sensor chip in some embodiments of the present disclosure.

[0035] Fig.12 Layout of piezoresistors, thermistors, and resistor leads on a first substrate substrate of a sensor chip according to some embodiments of the present disclosure is shown.

[0036] FIG. 13A to FIG. 13J The process of manufacturing a sensor chip according to some embodiments of the present disclosure is shown.

[0037] Fig.14 is a schematic diagram showing the structure of a sensor chip in some embodiments of the present disclosure.

[0038] Fig.15 Layout of piezoresistors, thermistors, and resistor leads on a first substrate substrate of a sensor chip according to some embodiments of the present disclosure is shown.

[0039] FIG. 16A to FIG. 16J The process of manufacturing a sensor chip according to some embodiments of the present disclosure is shown.

[0040] Fig.17 is a schematic diagram showing the structure of a sensor chip in some embodiments of the present disclosure.

[0041] Fig.18 The layout of piezoresistors and resistor leads on a first substrate substrate of a sensor chip according to some embodiments of the present disclosure is shown.

[0042] Fig.19 Layout of metal wire bonding, under bump metallization layers, and zeroing resistors on a second substrate substrate of a sensor chip according to some embodiments of the present disclosure is shown.

[0043] Fig. 20 is a schematic diagram showing the circuit structure of a sensor chip in some embodiments of the present disclosure.

[0044] FIG. 21A to FIG. 21K The process of manufacturing a sensor chip according to some embodiments of the present disclosure is shown.

[0045] Fig. 22 is a schematic diagram showing the structure of a sensor chip in some embodiments of the present disclosure.

[0046] Fig.23 The layout of piezoresistors and resistor leads on a first substrate substrate of a sensor chip according to some embodiments of the present disclosure is shown.

[0047] Fig.24 Layout of metal wire bonds, fixed resistors, and under bump metallization layers on a second substrate substrate of a sensor chip according to some embodiments of the present disclosure is shown.

[0048] FIG. 25A to FIG. 25K The process of manufacturing a sensor chip according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0049] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0050] Pressure sensors usually consist of three main components: sensor chip, processing circuit and packaging. As the core component, the sensor chip directly detects the pressure signal. Figure 1 is a schematic diagram showing the structure of a sensor chip in some embodiments of the present disclosure. Figure 1In some embodiments, the sensor chip includes: a first substrate BS1; a metal lead ML located on the first substrate BS1; a second substrate BS2 located on a side of the metal lead ML away from the first substrate BS1; a piezoresistor PR and a resistor lead RL located on a side of the second substrate BS2 away from the metal lead ML; an electrode E located on a side of the piezoresistor PR and the resistor lead RL away from the second substrate BS2; and a pressure reference chamber PRC located on a side of the electrode E away from the second substrate BS2. It is worth noting that the piezoresistor PR responsible for the main electrical function is exposed to the external environment outside the pressure reference chamber PRC (e.g., a vacuum chamber). Therefore, it becomes susceptible to external influences, which leads to potential drift or failure of electrical performance. The inventors of the present disclosure have found that the environmental adaptability of a sensor chip having such a configuration is limited, which leads to lower reliability.

[0051] exist Figure 1 In the sensor chip depicted in Figure 1, the chip's measuring circuit is based on the Wheatstone bridge principle. Figure 2 Shows the Wheatstone bridge principle. Figure 2 , the input voltage of the Wheatstone bridge is defined as V in =V in+ -V in- , and the output voltage is denoted as V out =V out+ -V out- The varistors R1, R2, R3 and R4 correspond to the four bridge arms of the Wheatstone bridge, and V out It can be expressed as:

[0052]

[0053]

[0054] In the process of manufacturing the sensor chip, R1=R2=R3=R4=R. When external pressure acts on the sensor chip, the resistance of the piezoresistors R1 and R3 decreases by ΔR, that is, their resistance becomes R-ΔR. On the contrary, the resistance of the piezoresistors R2 and R4 increases by ΔR, that is, their resistance becomes R+ΔR. As a result, V out changes, and V out The change in is proportional to the pressure applied to the sensor chip. This process converts the pressure signal into a voltage signal.

[0055] Figure 3 is a schematic diagram showing the structure of a Wheatstone bridge. Figure 2 and Figure 3 The sensor chip depicted in FIG. 1 includes piezoresistors R1, R2, R3 and R4, electrodes V in+ 、Vin- 、V out+ 、V out , and resistor leads RL1, RL2, RL3 and RL4 connecting the varistor and the electrodes. Figure 3 As shown, the electrodes and resistor leads occupy more than 50% of the total circuit area. The inventors of the present disclosure have found that this is one of the reasons why current varistor chips have relatively large sizes. With the development of miniaturization, intelligence and integration of electronic devices, the demand for smaller varistor pressure chips is growing.

[0056] Therefore, the present disclosure provides, among other things, a sensor chip that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, the present disclosure provides a sensor chip. In some embodiments, the sensor chip includes: a first substrate substrate; a piezoresistor and a resistor lead, which are located on the first substrate substrate; a second substrate substrate, which is located on the side of the piezoresistor and the resistor lead away from the first substrate substrate; a metal wire bond, which extends through the second substrate substrate and is connected to the resistor lead; a redistribution layer, which is located on the side of the second substrate substrate away from the first substrate substrate; and a pressure reference chamber, which is located between the first substrate substrate and the second substrate substrate. Optionally, the first substrate substrate and the second substrate substrate encapsulate at least a portion of the piezoresistor within the pressure reference chamber. Optionally, the metal wire bond is connected to the resistor lead and to the redistribution layer. Optionally, the resistor lead is connected to the piezoresistor.

[0057] Figure 4 is a schematic diagram showing the structure of a sensor chip in some embodiments of the present disclosure. Figure 4 In some embodiments, the sensor chip includes: a first substrate BS1; a piezoresistor PR and a resistor lead RL, which are located on the first substrate BS1; a second substrate BS2, which is located on a side of the piezoresistor PR and the resistor lead RL away from the first substrate BS1; a metal wire bond MWB, which extends through the second substrate BS2 and is connected to the resistor lead RL; a redistribution layer RDL and an under-bump metallization layer UBM, which are located on a side of the second substrate BS2 away from the first substrate BS1; and a solder joint SLD, which is located on a side of the under-bump metallization layer UBM away from the second substrate BS2 and is connected to the under-bump metallization layer UBM.

[0058] In some embodiments, the sensor chip further includes a pressure reference chamber PRC located between the first substrate BS1 and the second substrate BS2. The first substrate BS1 and the second substrate BS2 encapsulate at least a portion of the piezoresistors PR in the pressure reference chamber PRC.

[0059] In some embodiments, the first substrate BS1 includes a portion located between the two piezoresistors. Optionally, the surface of the portion of the first substrate BS1 located between the two piezoresistors is exposed to the pressure reference chamber PRC. In some embodiments, the sensor chip includes a pressure sensing layer PSL. The pressure sensing layer PSL includes a portion of the first substrate BS1 located between the two piezoresistors.

[0060] In some embodiments, a metal wire bond MWB extending through the second substrate BS2 connects the resistor lead RL to the redistribution layer RDL. The resistor lead RL is connected to the varistor PR. In some embodiments, the signal in the varistor PR is transmitted to the redistribution layer RDL through the resistor lead RL and the metal wire bond MWB. The redistribution layer RDL is configured to transmit the signal to the under-bump metallization layer UBM, and then to the solder joint SLD. Optionally, the solder joint SLD is an output terminal of the sensor chip.

[0061] In some embodiments, the solder joint SLD is configured to transmit an input signal to the redistribution layer RDL through the under bump metallization layer UBM. The redistribution layer RDL is configured to transmit an input signal to the resistor lead RL and the varistor PR through the metal wire bond MWB. Optionally, the solder joint SLD is an input terminal of the sensor chip.

[0062] The under bump metallization layer UBM serves as an electrical connection structure of the sensor chip to transmit electrical signals from the redistribution layer RDL to the solder joint SLD, serves as a bonding layer between the redistribution layer RDL and the solder joint SLD, and prevents the solder joint material from diffusing into the redistribution layer RDL.

[0063] The pressure inside the pressure reference chamber PRC is used as a reference pressure for measuring the pressure of the sensor chip. When the external pressure is equal to the pressure inside the pressure reference chamber PRC, the output of the sensor chip is zero. When the external pressure exceeds the pressure inside the pressure reference chamber PRC, the output of the sensor chip is the difference between the external atmospheric pressure and the pressure inside the pressure reference chamber PRC.

[0064] The piezoresistors PR are configured to convert deformation of the pressure sensing layer PSL into electrical signals.

[0065] The pressure sensing layer PSL is configured to convert a pressure signal into a deformation signal.

[0066] Figure 5 FIG. 4 shows a layout of a piezoresistor and resistor leads on a first substrate of a sensor chip according to some embodiments of the present disclosure. Figure 5In some embodiments, the sensor chip includes piezoresistors R1, R2, R3, and R4, and resistor leads RL1, RL2, RL3, RL4, RL5, RL6, RL7, and RL8. The first piezoresistors R1 are connected to the resistor leads RL1 and RL2. The second piezoresistors R2 are connected to the resistor leads RL3 and RL4. The third piezoresistors R3 are connected to the resistor leads RL5 and RL6. The fourth piezoresistors R4 are connected to the resistor leads RL7 and RL8.

[0067] Figure 5 The circuit structure depicted in Figure 3 The circuit structure depicted in the figure has been greatly miniaturized. Figure 5 The circuit structure depicted in FIG. 1 on the first substrate BS1 includes only piezoresistors and resistor leads, but not electrodes. The size of the resistor leads is correspondingly reduced, resulting in a significant reduction in the size of the sensor chip.

[0068] Figure 6 FIG. 4 shows a layout of metal wire bonding and under-bump metallization layers on a second substrate substrate of a sensor chip according to some embodiments of the present disclosure. Figure 6 In some embodiments, the sensor chip includes: metal wire bonds MWB1, MWB2, MWB3, MWB4, MWB5, MWB6, MWB7, and MWB8; and under-bump metallization layers UBM1, UBM2, UBM3, and UBM4. The metal wire bonds MWB1, MWB2, MWB3, MWB4, MWB5, MWB6, MWB7, and MWB8 are connected to Figure 5 Resistor leads RL1, RL2, RL3, RL4, RL5, RL6, RL7 and RL8 are depicted on a first substrate substrate.

[0069] 7A to 7J The process of manufacturing a sensor chip in some embodiments of the present disclosure is shown. Fig. 7A , forming a first substrate BS1. In some embodiments, the first substrate BS1 is a silicon-based substrate. In one example, a silicon substrate (e.g., an N(100) silicon substrate) is provided, and silicon nitride is grown on both sides as a mask. After depositing the silicon nitride, the desired shape of the pressure-sensitive film is photolithographically defined on the bottom of the silicon substrate. Wet etching of the silicon substrate is performed using a hot alkaline solution (e.g., potassium hydroxide or tetramethylammonium hydroxide). After etching, the silicon nitride mask layer is removed using a hot phosphoric acid solution.

[0070] Reference Figure 7B, a varistor PR is formed on the first substrate BS1. In some embodiments, the varistor PR is formed using a photolithography process. In one example, a photoresist is formed on the first substrate BS1 as a mask to perform ion implantation. After the ion implantation process, the photoresist is removed, and the first substrate BS1 is annealed. In one example, after annealing, the varistor PR has a resistance value of 100Ω / square to 1000Ω / square.

[0071] Reference Figure 7C , a resistor lead RL is formed on the first substrate BS1. In some embodiments, the resistor lead RL is formed using a photolithography process. In one example, a photoresist is formed on the first substrate BS1 as a mask to perform ion implantation. After the ion implantation process, the photoresist is removed, and the first substrate BS1 is annealed. In one example, after annealing, the resistor lead RL has a resistance value of 20Ω / square to 100Ω / square.

[0072] Reference Fig.7D , forming a via v extending through the second substrate BS2. In some embodiments, the second substrate BS2 is a glass-based substrate. In one example, a glass-based substrate (e.g., BF33 or 7740 glass) is provided. The glass substrate is patterned to produce a via v. In one example, the diameter of the via v is in the range of 10 μm to 1000 μm. In another example, laser induced etching technology can be used to form the via v. First, a laser is used to perform laser induced modification on the glass substrate to produce a modified area in the area where the via v is to be formed. Subsequently, wet etching is used to etch the laser modified area into a via v having a specific aspect ratio.

[0073] Figure 8 A via extending through the second substrate substrate is shown in accordance with some embodiments of the present disclosure. Figure 8 In some embodiments, the via v has a trapezoidal shape and has an angle θ between the top surface and the side surface. In some embodiments, the angle θ is in the range of 80 degrees to 90 degrees.

[0074] Reference Fig. 7E , forming chamber cb in the second substrate BS2. When the second substrate BS2 and the first substrate BS1 are assembled together, chamber cb becomes a pressure reference chamber. In one example, laser induced etching technology can be used to form chamber cb. Laser induced modification of the glass substrate substrate begins by processing the glass substrate substrate with a laser. The laser is used to scan the area where chamber cb is to be formed to produce a modified area. Subsequently, wet etching is used to etch the laser modified area into a desired shape to form chamber cb.

[0075] Reference Figure 7F , the first substrate substrate BS1 and the second substrate substrate BS2 are assembled together. In one example, the first substrate substrate BS1 and the second substrate substrate BS2 may be bonded together using an anodic bonding technique. During the bonding process, the first substrate substrate BS1 is connected to the positive terminal of a power source, and the second substrate substrate BS2 is connected to the negative terminal of the power source. In one example, a voltage in the range of 200V to 1000V and a temperature in the range of 100°C to 500°C are applied during the bonding process.

[0076] Reference Figure 7G , extending through the via in the second substrate BS2, forming a metal wire bond MWB. In one example, an adhesion layer is first deposited on the inner wall of the via, for example using a physical vapor deposition process or a chemical vapor deposition process. Next, a plating layer is deposited on the inner wall of the via. In another example, the adhesion layer has a thickness of 20nm to 50nm and includes titanium or chromium. In another example, the plating layer is made of copper and fills the via.

[0077] Reference Figure 7H , a redistribution layer RDL is formed on the second substrate BS2. In one example, an adhesion layer is first deposited on the surface of the second substrate BS2; then a plating layer is deposited on the adhesion layer, for example, using a physical vapor deposition process or a chemical vapor deposition process. In another example, the adhesion layer has a thickness of 20nm to 50nm and includes titanium or chromium. In another example, the plating layer has a thickness of 0.2nm to 0.5nm and is made of copper. After the plating process, a photolithography process is performed to produce a pattern of the redistribution layer RDL.

[0078] Reference Fig.7I , forming an under bump metallization layer UBM on the second substrate BS2. In one example, the under bump metallization layer material is deposited on the second substrate BS2 using a physical vapor deposition process or a chemical vapor deposition process. In one example, the thickness of the under bump metallization layer UBM is in the range of 2 μm to 15 μm. In another example, the under bump metallization layer material includes indium or an alloy material such as copper-tin.

[0079] Reference Figure 7J , forming a solder joint SLD on the under bump metallization layer UBM. In some embodiments, screen printing is used to form the solder joint SLD. In one example, a metal solder paste is applied on the second substrate BS2 by screen printing, and a reflow soldering process is performed to form the solder joint SLD.

[0080] In some embodiments, the piezoresistors PR are p-type diffused resistors, and the pressure sensing layer PSL is an n-type pressure sensing layer (e.g., a silicon-based pressure sensing layer). Electrical insulation between the piezoresistors PR and the pressure sensing layer PSL is achieved through a pn junction. The inventors of the present disclosure have found that when the operating temperature exceeds 125 degrees, it can cause intrinsic excitation of the semiconductor, resulting in more violent molecular motion. This causes electrons to break freely from covalent bonds, increasing the concentration of "free electrons" and the leakage current across the pn junction between the piezoresistors PR and the pressure sensing layer PSL. The pn junction becomes ineffective, making the sensor unable to measure pressure in a high temperature environment. With the development of applications in fields such as petroleum, chemistry, metallurgy, industrial process control, defense industry, and food industry, pressure measurement in high temperature environments has become particularly important.

[0081] In some embodiments, a silicon-on-insulator substrate may be used as the first substrate substrate. Fig. 9 is a schematic diagram showing the structure of a sensor chip in some embodiments of the present disclosure. Fig. 9 In some embodiments, the sensor chip includes: a first substrate substrate BS1; an insulating layer IN, which is located on the first substrate substrate BS1; a varistor PR and a resistor lead RL, which are located on the insulating layer IN away from the first substrate substrate BS1; a second substrate substrate BS2, which is located on the side of the varistor PR and the resistor lead RL away from the insulating layer IN; a metal wire bond MWB, which extends through the second substrate substrate BS2 and is connected to the resistor lead RL; a redistribution layer RDL and an under-bump metallization layer UBM, which are located on the side of the second substrate substrate BS2 away from the first substrate substrate BS1; and a solder joint SLD, which is located on the side of the under-bump metallization layer UBM away from the second substrate substrate BS2 and is connected to the under-bump metallization layer UBM.

[0082] The inventors of the present disclosure have found that, surprisingly and unexpectedly, the sensor chip can operate in a much higher temperature range by providing an insulating layer IN. In one example, the sensor chip with the insulating layer IN allows a maximum operating temperature of 500 degrees.

[0083] Various suitable insulating materials and various suitable manufacturing methods can be used to manufacture the insulating layer IN. For example, the insulating material can be deposited on the first substrate BS1 by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of materials suitable for manufacturing the insulating layer IN include, but are not limited to, silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof. In one example, the insulating layer IN includes silicon oxide.

[0084] In some embodiments, the sensor chip further comprises a pressure reference chamber PRC between the insulating layer IN and the second substrate BS2. The insulating layer IN and the second substrate BS2 encapsulate at least a portion of the piezoresistors PR in the pressure reference chamber PRC.

[0085] In some embodiments, the sensor chip includes a pressure sensing layer PSL. In some embodiments, the pressure sensing layer PSL includes a portion of the first substrate BS1 located between the two piezoresistors and a portion of the insulating layer IN located between the two piezoresistors. Optionally, the surface of the portion of the insulating layer IN located between the two piezoresistors is exposed to the pressure reference chamber PRC.

[0086] In some embodiments, a metal wire bond MWB extending through the second substrate BS2 connects the resistor lead RL to the redistribution layer RDL. The resistor lead RL is connected to the varistor PR. In some embodiments, the signal in the varistor PR is transmitted to the redistribution layer RDL through the resistor lead RL and the metal wire bond MWB. The redistribution layer RDL is configured to transmit the signal to the under-bump metallization layer UBM, and then to the solder joint SLD. Optionally, the solder joint SLD is an output terminal of the sensor chip.

[0087] In some embodiments, the solder joint SLD is configured to transmit an input signal to the redistribution layer RDL through the under bump metallization layer UBM. The redistribution layer RDL is configured to transmit an input signal to the resistor lead RL and the varistor PR through the metal wire bond MWB. Optionally, the solder joint SLD is an input terminal of the sensor chip.

[0088] The under bump metallization layer UBM serves as an electrical connection structure of the sensor chip to transmit electrical signals from the redistribution layer RDL to the solder joint SLD, serves as a bonding layer between the redistribution layer RDL and the solder joint SLD, and prevents the solder joint material from diffusing into the redistribution layer RDL.

[0089] The pressure inside the pressure reference chamber PRC is used as a reference pressure for measuring the pressure of the sensor chip. When the external pressure is equal to the pressure inside the pressure reference chamber PRC, the output of the sensor chip is zero. When the external pressure exceeds the pressure inside the pressure reference chamber PRC, the output of the sensor chip is the difference between the external atmospheric pressure and the pressure inside the pressure reference chamber PRC.

[0090] The piezoresistors PR are configured to convert deformation of the pressure sensing layer PSL into electrical signals.

[0091] The pressure sensing layer PSL is configured to convert a pressure signal into a deformation signal.

[0092] FIG. 10A to FIG. 10JThe process of manufacturing a sensor chip in some embodiments of the present disclosure is shown. Fig. 10A , forming a first substrate BS1 and forming an insulating layer IN on the first substrate BS1. In some embodiments, the first substrate BS1 is a silicon-based substrate. In one example, a silicon substrate (e.g., an N(100) silicon substrate) is provided, and silicon nitride is grown on both sides as a mask. After depositing the silicon nitride, the desired shape of the pressure-sensitive film is photolithographically defined on the bottom of the silicon substrate. Wet etching of the silicon substrate is performed using a hot alkaline solution (e.g., potassium hydroxide or tetramethylammonium hydroxide). After etching, the silicon nitride mask layer is removed using a hot phosphoric acid solution.

[0093] Reference Fig. 10B , a varistor PR is formed on the insulating layer IN. In some embodiments, the varistor PR is formed using a photolithography process. In one example, a photoresist is formed on the insulating layer IN as a mask for ion implantation. After the ion implantation process, inductively coupled plasma etching is performed, wherein the insulating layer IN serves as an etching stop layer for the etching process. After etching, the photoresist is removed, and the substrate is annealed. In one example, after annealing, the varistor PR has a resistance value of 5Ω / square to 1000Ω / square.

[0094] Reference Fig. 10C , a resistor lead RL is formed on the insulating layer IN. In some embodiments, the resistor lead RL is formed using a photolithography process. In one example, a photoresist is formed on the insulating layer IN as a mask for ion implantation. After the ion implantation process, inductively coupled plasma etching is performed, wherein the insulating layer IN serves as an etching stop layer for the etching process. After etching, the photoresist is removed, and the substrate is annealed. In one example, after annealing, the resistor lead RL has a resistance value of 5Ω / square to 1000Ω / square.

[0095] Reference Fig. 10D , forming a via v extending through the second substrate BS2. In some embodiments, the second substrate BS2 is a glass-based substrate. In one example, a glass-based substrate (e.g., BF33 or 7740 glass) is provided. The glass substrate is patterned to produce a via v. In one example, the diameter of the via v is in the range of 10 μm to 1000 μm. In another example, laser induced etching technology can be used to form the via v. First, a laser is used to perform laser induced modification on the glass substrate to produce a modified area in the area where the via v is to be formed. Subsequently, wet etching is used to etch the laser modified area into a via v having a specific aspect ratio.

[0096] Reference Figure 8In some embodiments, the via v has a trapezoidal shape and has an angle θ between the top surface and the side surface. In some embodiments, the angle θ is in the range of 80 degrees to 90 degrees.

[0097] Reference Fig.10E , forming chamber cb in the second substrate BS2. When the second substrate BS2 and the first substrate BS1 are assembled together, chamber cb becomes a pressure reference chamber. In one example, laser induced etching technology can be used to form chamber cb. Laser induced modification of the glass substrate substrate begins by processing the glass substrate substrate with a laser. The laser is used to scan the area where chamber cb is to be formed to produce a modified area. Subsequently, wet etching is used to etch the laser modified area into a desired shape to form chamber cb.

[0098] Reference Fig.10F , the first substrate substrate BS1 and the second substrate substrate BS2 are assembled together. In one example, the first substrate substrate BS1 and the second substrate substrate BS2 may be bonded together using an anodic bonding technique. During the bonding process, the first substrate substrate BS1 is connected to the positive terminal of a power source, and the second substrate substrate BS2 is connected to the negative terminal of the power source. In one example, a voltage in the range of 200V to 1000V and a temperature in the range of 100°C to 500°C are applied during the bonding process.

[0099] Reference Figure 10G , extending through the via in the second substrate BS2, forming a metal wire bond MWB. In one example, an adhesion layer is first deposited on the inner wall of the via, for example using a physical vapor deposition process or a chemical vapor deposition process. Next, a plating layer is deposited on the inner wall of the via. In another example, the adhesion layer has a thickness of 20nm to 50nm and includes titanium or chromium. In another example, the plating layer is made of copper and fills the via.

[0100] Reference Fig. 10H , a redistribution layer RDL is formed on the second substrate BS2. In one example, an adhesion layer is first deposited on the surface of the second substrate BS2; then a plating layer is deposited on the adhesion layer, for example, using a physical vapor deposition process or a chemical vapor deposition process. In another example, the adhesion layer has a thickness of 20nm to 50nm and includes titanium or chromium. In another example, the plating layer has a thickness of 0.2nm to 0.5nm and is made of copper. After the plating process, a photolithography process is performed to produce a pattern of the redistribution layer RDL.

[0101] Reference Fig.10I, forming an under bump metallization layer UBM on the second substrate BS2. In one example, the under bump metallization layer material is deposited on the second substrate BS2 using a physical vapor deposition process or a chemical vapor deposition process. In one example, the thickness of the under bump metallization layer UBM is in the range of 2 μm to 15 μm. In another example, the under bump metallization layer material includes indium or an alloy material such as copper-tin.

[0102] Reference Fig.10J , forming a solder joint SLD on the under bump metallization layer UBM. In some embodiments, screen printing is used to form the solder joint SLD. In one example, a metal solder paste is applied on the second substrate BS2 by screen printing, and a reflow soldering process is performed to form the solder joint SLD.

[0103] In some embodiments, the sensor chip also includes a thermistor, which is configured to detect temperature without increasing the volume of the sensor chip. A thermistor, also known as a temperature sensing resistor, is a sensor for measuring temperature. It works based on the property that the resistance of a material changes with temperature. Common thermistor materials include platinum and nickel. As the temperature changes, the resistance of the thermistor also changes, and this change can be used to calculate the temperature value. Typically, the thermistor material is mounted on a support structure to ensure proper contact with the temperature being measured. A certain amount of current is then passed through the circuit, and the temperature change is inferred by measuring the corresponding resistance change. In addition, calibration and compensation techniques are used to improve accuracy and stability.

[0104] Fig.11 is a schematic diagram showing the structure of a sensor chip in some embodiments of the present disclosure. Fig.11 In some embodiments, the sensor chip includes: a first substrate BS1; a piezoresistor PR and a resistor lead RL, which are located on the first substrate BS1; a second substrate BS2, which is located on a side of the piezoresistor PR and the resistor lead RL away from the first substrate BS1; a metal wire bond MWB, which extends through the second substrate BS2 and is connected to the resistor lead RL; a redistribution layer RDL, a thermistor TS and an under-bump metallization layer UBM, which are located on a side of the second substrate BS2 away from the first substrate BS1; and a solder joint SLD, which is located on a side of the under-bump metallization layer UBM away from the second substrate BS2 and is connected to the under-bump metallization layer UBM.

[0105] In some embodiments, the sensor chip further includes a pressure reference chamber PRC located between the first substrate BS1 and the second substrate BS2. The first substrate BS1 and the second substrate BS2 encapsulate at least a portion of the piezoresistors PR in the pressure reference chamber PRC.

[0106] In some embodiments, the first substrate BS1 includes a portion located between the two piezoresistors. Optionally, the surface of the portion of the first substrate BS1 located between the two piezoresistors is exposed to the pressure reference chamber PRC. In some embodiments, the sensor chip includes a pressure sensing layer PSL. The pressure sensing layer PSL includes a portion of the first substrate BS1 located between the two piezoresistors.

[0107] In some embodiments, a metal wire bond MWB extending through the second substrate BS2 connects the resistor lead RL to the redistribution layer RDL. The resistor lead RL is connected to the varistor PR. In some embodiments, the signal in the varistor PR is transmitted to the redistribution layer RDL through the resistor lead RL and the metal wire bond MWB. The redistribution layer RDL is configured to transmit the signal to the under-bump metallization layer UBM, and then to the solder joint SLD. Optionally, the solder joint SLD is an output terminal of the sensor chip.

[0108] In some embodiments, the solder joint SLD is configured to transmit an input signal to the redistribution layer RDL through the under bump metallization layer UBM. The redistribution layer RDL is configured to transmit an input signal to the resistor lead RL and the varistor PR through the metal wire bond MWB. Optionally, the solder joint SLD is an input terminal of the sensor chip.

[0109] The under bump metallization layer UBM serves as an electrical connection structure of the sensor chip to transmit electrical signals from the redistribution layer RDL to the solder joint SLD, serves as a bonding layer between the redistribution layer RDL and the solder joint SLD, and prevents the solder joint material from diffusing into the redistribution layer RDL.

[0110] The pressure inside the pressure reference chamber PRC is used as a reference pressure for measuring the pressure of the sensor chip. When the external pressure is equal to the pressure inside the pressure reference chamber PRC, the output of the sensor chip is zero. When the external pressure exceeds the pressure inside the pressure reference chamber PRC, the output of the sensor chip is the difference between the external atmospheric pressure and the pressure inside the pressure reference chamber PRC.

[0111] The piezoresistors PR are configured to convert deformation of the pressure sensing layer PSL into electrical signals.

[0112] The pressure sensing layer PSL is configured to convert a pressure signal into a deformation signal.

[0113] Fig.12 The layout of the piezoresistors, thermistors and resistor leads of the sensor chip on the first substrate substrate in some embodiments of the present disclosure is shown. Fig.12In some embodiments, the sensor chip includes: metal wire bonds MWB1, MWB2, MWB3, MWB4, MWB5, MWB6, MWB7, and MWB8; under bump metallization layers UBM1, UBM2, UBM3, UBM4, and UBM5; and a thermistor TS. In one example, the thermistor TS is connected to the under bump metallization layer UBM4 and to the under bump metallization layer UBM5.

[0114] FIG. 13A to FIG. 13J The process of manufacturing a sensor chip in some embodiments of the present disclosure is shown. Fig.13A , forming a first substrate BS1. In some embodiments, the first substrate BS1 is a silicon-based substrate. In one example, a silicon substrate (e.g., an N(100) silicon substrate) is provided, and silicon nitride is grown on both sides as a mask. After depositing the silicon nitride, the desired shape of the pressure-sensitive film is photolithographically defined on the bottom of the silicon substrate. Wet etching of the silicon substrate is performed using a hot alkaline solution (e.g., potassium hydroxide or tetramethylammonium hydroxide). After etching, the silicon nitride mask layer is removed using a hot phosphoric acid solution.

[0115] Reference Fig. 13B , a varistor PR is formed on the first substrate BS1. In some embodiments, the varistor PR is formed using a photolithography process. In one example, a photoresist is formed on the first substrate BS1 as a mask to perform ion implantation. After the ion implantation process, the photoresist is removed, and the first substrate BS1 is annealed. In one example, after annealing, the varistor PR has a resistance value of 100Ω / square to 1000Ω / square.

[0116] Reference Fig. 13C , a resistor lead RL is formed on the first substrate BS1. In some embodiments, the resistor lead RL is formed using a photolithography process. In one example, a photoresist is formed on the first substrate BS1 as a mask to perform ion implantation. After the ion implantation process, the photoresist is removed, and the first substrate BS1 is annealed. In one example, after annealing, the resistor lead RL has a resistance value of 20Ω / square to 100Ω / square.

[0117] Reference Fig.13D, forming a via v extending through the second substrate BS2. In some embodiments, the second substrate BS2 is a glass-based substrate. In one example, a glass-based substrate (e.g., BF33 or 7740 glass) is provided. The glass substrate is patterned to produce a via v. In one example, the diameter of the via v is in the range of 10 μm to 1000 μm. In another example, laser induced etching technology can be used to form the via v. First, a laser is used to perform laser induced modification on the glass substrate to produce a modified area in the area where the via v is to be formed. Subsequently, wet etching is used to etch the laser modified area into a via v having a specific aspect ratio.

[0118] Reference Figure 8 In some embodiments, the via v has a trapezoidal shape and has an angle θ between the top surface and the side surface. In some embodiments, the angle θ is in the range of 80 degrees to 90 degrees.

[0119] Reference Fig.13E , forming chamber cb in the second substrate BS2. When the second substrate BS2 and the first substrate BS1 are assembled together, chamber cb becomes a pressure reference chamber. In one example, laser induced etching technology can be used to form chamber cb. Laser induced modification of the glass substrate substrate begins by processing the glass substrate substrate with a laser. The laser is used to scan the area where chamber cb is to be formed to produce a modified area. Subsequently, wet etching is used to etch the laser modified area into a desired shape to form chamber cb.

[0120] Reference Fig.13F , the first substrate substrate BS1 and the second substrate substrate BS2 are assembled together. In one example, the first substrate substrate BS1 and the second substrate substrate BS2 may be bonded together using an anodic bonding technique. During the bonding process, the first substrate substrate BS1 is connected to the positive terminal of a power source, and the second substrate substrate BS2 is connected to the negative terminal of the power source. In one example, a voltage in the range of 200V to 1000V and a temperature in the range of 100°C to 500°C are applied during the bonding process.

[0121] Reference Figure 13G , extending through the via in the second substrate BS2, forming a metal wire bond MWB. In one example, an adhesion layer is first deposited on the inner wall of the via, for example using a physical vapor deposition process or a chemical vapor deposition process. Next, a plating layer is deposited on the inner wall of the via. In another example, the adhesion layer has a thickness of 20nm to 50nm and includes titanium or chromium. In another example, the plating layer is made of copper and fills the via.

[0122] Reference Fig.13H, a redistribution layer RDL is formed on the second substrate BS2. In one example, an adhesion layer is first deposited on the surface of the second substrate BS2; then a plating layer is deposited on the adhesion layer, for example, using a physical vapor deposition process or a chemical vapor deposition process. In another example, the adhesion layer has a thickness of 20nm to 50nm and includes titanium or chromium. In another example, the plating layer has a thickness of 0.2nm to 0.5nm and is made of copper. After the plating process, a photolithography process is performed to produce a pattern of the redistribution layer RDL.

[0123] Reference Fig.13H , a thermistor TS is formed on the second substrate BS2. In one example, an adhesion layer is first deposited on the surface of the second substrate BS2; then a temperature sensing layer is deposited on the adhesion layer, for example, using a physical vapor deposition process or a chemical vapor deposition process. In another example, the adhesion layer has a thickness of 20nm to 50nm and includes titanium or chromium. In another example, the temperature sensing layer has a thickness of 0.1μm to 1.0μm and is made of platinum or nickel. After deposition, a photolithography process is performed to form a pattern of the thermistor TS.

[0124] Reference Fig.13I , forming an under bump metallization layer UBM on the second substrate BS2. In one example, the under bump metallization layer material is deposited on the second substrate BS2 using a physical vapor deposition process or a chemical vapor deposition process. In one example, the thickness of the under bump metallization layer UBM is in the range of 2 μm to 15 μm. In another example, the under bump metallization layer material includes indium or an alloy material such as copper-tin.

[0125] Reference Fig.13J , forming a solder joint SLD on the under bump metallization layer UBM. In some embodiments, screen printing is used to form the solder joint SLD. In one example, a metal solder paste is applied on the second substrate BS2 by screen printing, and a reflow soldering process is performed to form the solder joint SLD.

[0126] In some embodiments, the sensor chip also includes a hygrometer that is configured to detect humidity without increasing the volume of the sensor chip. For example, a capacitive hygrometer measures humidity based on a change in capacitance in a capacitor caused by the adsorption or desorption of moisture on the surface of the capacitor. The basic principle of a capacitive hygrometer is that the dielectric constant of a material changes with the amount of moisture it absorbs. The sensor consists of two conductive plates with a dielectric material between them, and as the humidity changes, the dielectric constant of the material changes, thereby changing the capacitance of the sensor. By measuring this capacitance change, the humidity level can be determined.

[0127] Fig.14is a schematic diagram showing the structure of a sensor chip in some embodiments of the present disclosure. Fig.14 In some embodiments, the sensor chip includes: a first substrate BS1; a piezoresistor PR and a resistor lead RL, which are located on the first substrate BS1; a second substrate BS2, which is located on a side of the piezoresistor PR and the resistor lead RL away from the first substrate BS1; a metal wire bond MWB, which extends through the second substrate BS2 and is connected to the resistor lead RL; a redistribution layer RDL, a thermistor TS, a hygrometer HM and an under-bump metallization layer UBM, which are located on a side of the second substrate BS2 away from the first substrate BS1; and a solder joint SLD, which is located on a side of the under-bump metallization layer UBM away from the second substrate BS2 and is connected to the under-bump metallization layer UBM.

[0128] In some embodiments, the hygrometer HM includes: a first electrode E1 located on the second substrate BS2; a dielectric layer DL located on a side of the first electrode E1 away from the second substrate BS2; and a second electrode E2 located on a side of the dielectric layer DL away from the first electrode E1.

[0129] In some embodiments, the sensor chip further includes a pressure reference chamber PRC located between the first substrate BS1 and the second substrate BS2. The first substrate BS1 and the second substrate BS2 encapsulate at least a portion of the piezoresistors PR in the pressure reference chamber PRC.

[0130] In some embodiments, the first substrate BS1 includes a portion located between the two piezoresistors. Optionally, the surface of the portion of the first substrate BS1 located between the two piezoresistors is exposed to the pressure reference chamber PRC. In some embodiments, the sensor chip includes a pressure sensing layer PSL. The pressure sensing layer PSL includes a portion of the first substrate BS1 located between the two piezoresistors.

[0131] In some embodiments, a metal wire bond MWB extending through the second substrate BS2 connects the resistor lead RL to the redistribution layer RDL. The resistor lead RL is connected to the varistor PR. In some embodiments, the signal in the varistor PR is transmitted to the redistribution layer RDL through the resistor lead RL and the metal wire bond MWB. The redistribution layer RDL is configured to transmit the signal to the under-bump metallization layer UBM, and then to the solder joint SLD. Optionally, the solder joint SLD is an output terminal of the sensor chip.

[0132] In some embodiments, the solder joint SLD is configured to transmit an input signal to the redistribution layer RDL through the under bump metallization layer UBM. The redistribution layer RDL is configured to transmit an input signal to the resistor lead RL and the varistor PR through the metal wire bond MWB. Optionally, the solder joint SLD is an input terminal of the sensor chip.

[0133] The under bump metallization layer UBM serves as an electrical connection structure of the sensor chip to transmit electrical signals from the redistribution layer RDL to the solder joint SLD, serves as a bonding layer between the redistribution layer RDL and the solder joint SLD, and prevents the solder joint material from diffusing into the redistribution layer RDL.

[0134] The pressure inside the pressure reference chamber PRC is used as a reference pressure for measuring the pressure of the sensor chip. When the external pressure is equal to the pressure inside the pressure reference chamber PRC, the output of the sensor chip is zero. When the external pressure exceeds the pressure inside the pressure reference chamber PRC, the output of the sensor chip is the difference between the external atmospheric pressure and the pressure inside the pressure reference chamber PRC.

[0135] The piezoresistors PR are configured to convert deformation of the pressure sensing layer PSL into electrical signals.

[0136] The pressure sensing layer PSL is configured to convert a pressure signal into a deformation signal.

[0137] Fig.15 The layout of the piezoresistors, thermistors and resistor leads of the sensor chip on the first substrate substrate in some embodiments of the present disclosure is shown. Fig.15 In some embodiments, the sensor chip includes: metal wire bonds MWB1, MWB2, MWB3, MWB4, MWB5, MWB6, MWB7, and MWB8; under bump metallization layers UBM1, UBM2, UBM3, UBM4, UBM5, UBM6, and UBM7; a thermistor TS; and a hygrometer. In one example, the thermistor TS is connected to the under bump metallization layer UBM4 and to the under bump metallization layer UBM5. In another example, the hygrometer includes a first electrode E1, a dielectric layer DL, and a second electrode E2. In another example, the first electrode E1 is connected to the under bump metallization layer UBM6, and the second electrode E2 is connected to the under bump metallization layer UBM7.

[0138] FIG. 16A to FIG. 16J The process of manufacturing a sensor chip in some embodiments of the present disclosure is shown. Fig.16A, forming a first substrate BS1. In some embodiments, the first substrate BS1 is a silicon-based substrate. In one example, a silicon substrate (e.g., an N(100) silicon substrate) is provided, and silicon nitride is grown on both sides as a mask. After depositing the silicon nitride, the desired shape of the pressure-sensitive film is photolithographically defined on the bottom of the silicon substrate. Wet etching of the silicon substrate is performed using a hot alkaline solution (e.g., potassium hydroxide or tetramethylammonium hydroxide). After etching, the silicon nitride mask layer is removed using a hot phosphoric acid solution.

[0139] Reference Fig. 16B , a varistor PR is formed on the first substrate BS1. In some embodiments, the varistor PR is formed using a photolithography process. In one example, a photoresist is formed on the first substrate BS1 as a mask to perform ion implantation. After the ion implantation process, the photoresist is removed, and the first substrate BS1 is annealed. In one example, after annealing, the varistor PR has a resistance value of 100Ω / square to 1000Ω / square.

[0140] Reference Fig. 16C , a resistor lead RL is formed on the first substrate BS1. In some embodiments, the resistor lead RL is formed using a photolithography process. In one example, a photoresist is formed on the first substrate BS1 as a mask to perform ion implantation. After the ion implantation process, the photoresist is removed, and the first substrate BS1 is annealed. In one example, after annealing, the resistor lead RL has a resistance value of 20Ω / square to 100Ω / square.

[0141] Reference Fig.16D , forming a via v extending through the second substrate BS2. In some embodiments, the second substrate BS2 is a glass-based substrate. In one example, a glass-based substrate (e.g., BF33 or 7740 glass) is provided. The glass substrate is patterned to produce a via v. In one example, the diameter of the via v is in the range of 10 μm to 1000 μm. In another example, laser induced etching technology can be used to form the via v. First, a laser is used to perform laser induced modification on the glass substrate to produce a modified area in the area where the via v is to be formed. Subsequently, wet etching is used to etch the laser modified area into a via v having a specific aspect ratio.

[0142] Reference Figure 8 In some embodiments, the via v has a trapezoidal shape and has an angle θ between the top surface and the side surface. In some embodiments, the angle θ is in the range of 80 degrees to 90 degrees.

[0143] Reference Fig.16E, forming chamber cb in the second substrate BS2. When the second substrate BS2 and the first substrate BS1 are assembled together, chamber cb becomes a pressure reference chamber. In one example, laser induced etching technology can be used to form chamber cb. Laser induced modification of the glass substrate substrate begins by processing the glass substrate substrate with a laser. The laser is used to scan the area where chamber cb is to be formed to produce a modified area. Subsequently, wet etching is used to etch the laser modified area into a desired shape to form chamber cb.

[0144] Reference Fig.16F , the first substrate substrate BS1 and the second substrate substrate BS2 are assembled together. In one example, the first substrate substrate BS1 and the second substrate substrate BS2 may be bonded together using an anodic bonding technique. During the bonding process, the first substrate substrate BS1 is connected to the positive terminal of a power source, and the second substrate substrate BS2 is connected to the negative terminal of the power source. In one example, a voltage in the range of 200V to 1000V and a temperature in the range of 100°C to 500°C are applied during the bonding process.

[0145] Reference Figure 16G , extending through the via in the second substrate BS2, forming a metal wire bond MWB. In one example, an adhesion layer is first deposited on the inner wall of the via, for example using a physical vapor deposition process or a chemical vapor deposition process. Next, a plating layer is deposited on the inner wall of the via. In another example, the adhesion layer has a thickness of 20nm to 50nm and includes titanium or chromium. In another example, the plating layer is made of copper and fills the via.

[0146] Reference Fig.16H , a redistribution layer RDL is formed on the second substrate BS2. In one example, an adhesion layer is first deposited on the surface of the second substrate BS2; then a plating layer is deposited on the adhesion layer, for example, using a physical vapor deposition process or a chemical vapor deposition process. In another example, the adhesion layer has a thickness of 20nm to 50nm and includes titanium or chromium. In another example, the plating layer has a thickness of 0.2nm to 0.5nm and is made of copper. After the plating process, a photolithography process is performed to produce a pattern of the redistribution layer RDL.

[0147] Reference Fig.16H, a thermistor TS is formed on the second substrate BS2. In one example, an adhesion layer is first deposited on the surface of the second substrate BS2; then a temperature sensing layer is deposited on the adhesion layer, for example, using a physical vapor deposition process or a chemical vapor deposition process. In another example, the adhesion layer has a thickness of 20nm to 50nm and includes titanium or chromium. In another example, the temperature sensing layer has a thickness of 0.1μm to 1.0μm and is made of platinum or nickel. After deposition, a photolithography process is performed to produce a pattern of the thermistor TS.

[0148] Reference Fig.16H , a hygrometer HM is formed on a second substrate BS2. In one example, an adhesion layer is first deposited on the surface of the second substrate BS2. In another example, the adhesion layer has a thickness of 20 nm to 50 nm and includes titanium or chromium. Then a first electrode E1 is formed on the side of the adhesion layer away from the second substrate BS2. In one example, the first electrode E1 has a thickness of 0.1 μm to 1 μm and includes gold. After deposition, a photolithography process is performed to form a pattern of the first electrode E1. Then a dielectric layer DL is formed on the side of the first electrode E1 away from the adhesion layer. In one example, the dielectric layer DL is made of a polymer material having a humidity sensing function, such as polyethylene glycol or polyimide. The dielectric layer DL is coated by spin coating or spray coating, and then photolithography is performed to form a pattern of the dielectric layer DL. Then, a second electrode E2 is formed on the side of the dielectric layer DL away from the first electrode E1. In one example, the second electrode E2 has a thickness of 0.1 μm to 1 μm and includes gold. After deposition, a photolithography process is performed to form a pattern of the second electrode E2.

[0149] Reference Fig.16I , forming an under bump metallization layer UBM on the second substrate BS2. In one example, the under bump metallization layer material is deposited on the second substrate BS2 using a physical vapor deposition process or a chemical vapor deposition process. In one example, the thickness of the under bump metallization layer UBM is in the range of 2 μm to 15 μm. In another example, the under bump metallization layer material includes indium or an alloy material such as copper-tin.

[0150] Reference Fig.16J , forming a solder joint SLD on the under bump metallization layer UBM. In some embodiments, screen printing is used to form the solder joint SLD. In one example, a metal solder paste is applied on the second substrate BS2 by screen printing, and a reflow soldering process is performed to form the solder joint SLD.

[0151] During the manufacturing process of the sensor chip, the four arms of the Wheatstone bridge (e.g. Figure 2 , Figure 3 or Figure 5 The varistors R1, R2, R3, and R4 depicted in the drawings are designed to have the same resistance so that the initial zero output of the Wheatstone bridge is zero volts. However, the inventors of the present disclosure have discovered that in an actual manufacturing process, deviations in the manufacturing process may cause the four arms of the Wheatstone bridge to be unequal. In a related manufacturing process, an additional laser trimming device is used to adjust the Wheatstone bridge so that the zero output is approximately zero volts. The use of an additional laser trimming device greatly increases the manufacturing cost. The inventors of the present disclosure have discovered a novel manufacturing process and sensor chip that eliminates the high costs in related processes.

[0152] Fig.17 is a schematic diagram showing the structure of a sensor chip in some embodiments of the present disclosure. Fig.17 In some embodiments, the sensor chip includes: a first substrate BS1; a piezoresistor PR and a resistor lead RL, which are located on the first substrate BS1; a second substrate BS2, which is located on a side of the piezoresistor PR and the resistor lead RL away from the first substrate BS1; a metal wire bond MWB, which extends through the second substrate BS2 and is connected to the resistor lead RL; a redistribution layer RDL, a zero adjustment resistor ZR and an under-bump metallization layer UBM, which are located on a side of the second substrate BS2 away from the first substrate BS1; and a solder joint SLD, which is located on a side of the under-bump metallization layer UBM away from the second substrate BS2 and is connected to the under-bump metallization layer UBM.

[0153] In some embodiments, the sensor chip further includes a pressure reference chamber PRC located between the first substrate BS1 and the second substrate BS2. The first substrate BS1 and the second substrate BS2 encapsulate at least a portion of the piezoresistors PR in the pressure reference chamber PRC.

[0154] In some embodiments, the first substrate BS1 includes a portion located between the two piezoresistors. Optionally, the surface of the portion of the first substrate BS1 located between the two piezoresistors is exposed to the pressure reference chamber PRC. In some embodiments, the sensor chip includes a pressure sensing layer PSL. The pressure sensing layer PSL includes a portion of the first substrate BS1 located between the two piezoresistors.

[0155] In some embodiments, a metal wire bond MWB extending through the second substrate BS2 connects the resistor lead RL to the redistribution layer RDL. The resistor lead RL is connected to the varistor PR. In some embodiments, the signal in the varistor PR is transmitted to the redistribution layer RDL through the resistor lead RL and the metal wire bond MWB. The redistribution layer RDL is configured to transmit the signal to the under-bump metallization layer UBM, and then to the solder joint SLD. Optionally, the solder joint SLD is an output terminal of the sensor chip.

[0156] In some embodiments, the signal in the varistor PR is transmitted to the redistribution layer RDL through the resistor lead RL and the metal wire bond MWB. The redistribution layer RDL is configured to transmit the signal to the under-bump metallization layer UBM (for example, through the zeroing resistor ZR), and then to the solder joint SLD. Optionally, the solder joint SLD is the output terminal of the sensor chip.

[0157] In some embodiments, the solder joint SLD is configured to transmit an input signal to the redistribution layer RDL through the under bump metallization layer UBM. The redistribution layer RDL is configured to transmit an input signal to the resistor lead RL and the varistor PR through the metal wire bond MWB. Optionally, the solder joint SLD is an input terminal of the sensor chip.

[0158] In some embodiments, the solder joint SLD is configured to transmit the input signal to the redistribution layer RDL through the under bump metallization layer UBM (e.g., through the zeroing resistor ZR). The redistribution layer RDL is configured to transmit the input signal to the resistor lead RL and the varistor PR through the metal wire bond MWB. Optionally, the solder joint SLD is an input terminal of the sensor chip.

[0159] The under bump metallization layer UBM serves as an electrical connection structure of the sensor chip to transmit electrical signals from the redistribution layer RDL to the solder joint SLD, acts as a bonding layer between the redistribution layer RDL and the solder joint SLD, and prevents the solder joint material from diffusing into the redistribution layer RDL.

[0160] The pressure inside the pressure reference chamber PRC is used as a reference pressure for measuring the pressure of the sensor chip. When the external pressure is equal to the pressure inside the pressure reference chamber PRC, the output of the sensor chip is zero. When the external pressure exceeds the pressure inside the pressure reference chamber PRC, the output of the sensor chip is the difference between the external atmospheric pressure and the pressure inside the pressure reference chamber PRC.

[0161] The piezoresistors PR are configured to convert deformation of the pressure sensing layer PSL into electrical signals.

[0162] The pressure sensing layer PSL is configured to convert a pressure signal into a deformation signal.

[0163] Zeroing resistors ZR are used in the sensor chip to calibrate the output of the sensor chip and compensate for any deviations in the resistance of one or more arms of the Wheatstone bridge. When no pressure is applied to the sensor, ideally all four arm resistors should have the same resistance and the output should be at a "zero" or baseline value. However, in the actual manufacturing process, it is challenging to achieve perfect matching of the resistors, and small resistance differences may occur due to manufacturing tolerances. These resistance imbalances can cause an offset in the output of the sensor chip, causing a non-zero value to be read even when no pressure is applied. To correct this, a zeroing resistor ZR is introduced to calibrate the output of the sensor chip.

[0164] Fig.18 FIG. 4 shows a layout of a piezoresistor and resistor leads on a first substrate of a sensor chip according to some embodiments of the present disclosure. Fig.18 In some embodiments, the sensor chip includes piezoresistors R1, R2, R3, and R4, and resistor leads RL1, RL2, RL3, RL4, RL5, RL6, RL7, and RL8. The first piezoresistors R1 are connected to the resistor leads RL1 and RL2. The second piezoresistors R2 are connected to the resistor leads RL3 and RL4. The third piezoresistors R3 are connected to the resistor leads RL5 and RL6. The fourth piezoresistors R4 are connected to the resistor leads RL7 and RL8.

[0165] Fig.18 The circuit structure depicted in Figure 3 The circuit structure depicted in the figure has been greatly miniaturized. Fig.18 The circuit structure depicted in FIG. 1 on the first substrate BS1 includes only piezoresistors and resistor leads, but no electrodes. The size of the resistor leads is correspondingly reduced, resulting in a significant reduction in the size of the sensor chip.

[0166] Fig.19 Layout of metal wire bonding and under bump metallization layers on a second substrate substrate of a sensor chip according to some embodiments of the present disclosure is shown. Fig. 20 Schematic diagram showing the circuit structure of a sensor chip in some embodiments of the present disclosure. Fig.19 and Fig. 20In some embodiments, the sensor chip includes: metal wire bonds MWB1, MWB2, MWB3, MWB4, MWB5, MWB6, MWB7, and MWB8; and under bump metallization layers UBM1, UBM2, UBM3, UBM4, UBM5, UBM6, UBM7, UBM8, and UBM9. The metal wire bonds MWB1, MWB2, MWB3, MWB4, MWB5, MWB6, MWB7, and MWB8 are connected to Fig.18 Resistor leads RL1, RL2, RL3, RL4, RL5, RL6, RL7 and RL8 are depicted on a first substrate substrate.

[0167] In some embodiments, the sensor chip further includes one or more zeroing resistors. In some embodiments, the sensor chip further includes at least one of a first zeroing resistor r1 connected to the first metal wire bond MWB1 and connected to the first under bump metallization layer UBM1, a second zeroing resistor r2 connected to the first metal wire bond MWB1 and connected to the second under bump metallization layer UBM2, or a third zeroing resistor r3 connected to the first metal wire bond MWB1 and connected to the third under bump metallization layer UBM3. The output terminal may be selected by selecting one of the first under bump metallization layer UBM1, the second under bump metallization layer UBM2, or the third under bump metallization layer UBM3 as the output terminal. Fig. 20 As depicted in ("Vout1-", "Vout2-", or "Vout3-"), the resistance of the first varistor R1 is adjusted. Because the first zeroing resistor R1, the second zeroing resistor R2, and the third zeroing resistor R3 have different resistances, the resistance of the first varistor R1 can be adjusted to different values ​​depending on which under-bump metallization layer is selected as the output terminal. By setting the first zeroing resistor R1, the second zeroing resistor R2, or the third zeroing resistor R3, the output of the sensor chip can be calibrated. When no pressure is applied to the sensor chip, all four bridge arm resistors can achieve substantially the same resistance, and the output can be at a "zero" or baseline value. As used herein, the term "substantially the same" means that the difference between two values ​​does not exceed 10% of a base value (e.g., one of the two values), for example, not more than 8%, not more than 6%, not more than 4%, not more than 2%, not more than 1%, not more than 0.5%, not more than 0.1%, not more than 0.05%, and not more than 0.01% of the base value.

[0168] In some embodiments, the resistance values ​​of the first zeroing resistor r1 , the second zeroing resistor r2 , and the third zeroing resistor r3 are in the range of 1% to 10% of the resistance value of the first varistor R1 .

[0169] In some embodiments, the sensor chip further includes at least one of a fourth zeroing resistor r4 connected to the eighth metal wire bond MWB8 and to the fourth under bump metallization layer UBM4, a fifth zeroing resistor r5 connected to the eighth metal wire bond MWB8 and to the fifth under bump metallization layer UBM5, or a sixth zeroing resistor r6 connected to the eighth metal wire bond MWB8 and to the sixth under bump metallization layer UBM6. The output terminal may be selected by selecting one of the fourth under bump metallization layer UBM4, the fifth under bump metallization layer UBM5, or the sixth under bump metallization layer UBM6 as the output terminal. Fig. 20 The resistance of the fourth varistor R4 is adjusted as depicted in ("Vout4-", "Vout5-", or "Vout6-"). Because the fourth zeroing resistor R4, the fifth zeroing resistor R5, and the sixth zeroing resistor R6 have different resistances, the resistance of the fourth varistor R4 can be adjusted to different values ​​depending on which under-bump metallization layer is selected as the output terminal. By setting the fourth zeroing resistor R4, the fifth zeroing resistor R5, and the sixth zeroing resistor R6, the output of the sensor chip can be calibrated. When no pressure is applied to the sensor chip, all four bridge arm resistors can achieve substantially the same resistance, and the output can be at a "zero" or baseline value.

[0170] In some embodiments, the resistance values ​​of the fourth zeroing resistor r4 , the fifth zeroing resistor r5 , and the sixth zeroing resistor r6 are within a range of 1% to 10% of the resistance value of the fourth varistor R4 .

[0171] In some embodiments, when no pressure is applied to the sensor chip, the resistance of the second piezoresistor R2, the resistance of the third piezoresistor R3, the resistance of the first piezoresistor R1 and one of the first zero adjustment resistor R1, the second zero adjustment resistor R2, or the third zero adjustment resistor R3, and the resistance of the fourth piezoresistor R4 and one of the fourth zero adjustment resistor R4, the fifth zero adjustment resistor R5, or the sixth zero adjustment resistor R6 are substantially the same.

[0172] FIG. 21A to FIG. 21K The process of manufacturing a sensor chip in some embodiments of the present disclosure is shown. Fig.21A , forming a first substrate BS1. In some embodiments, the first substrate BS1 is a silicon-based substrate. In one example, a silicon substrate (e.g., an N(100) silicon substrate) is provided, and silicon nitride is grown on both sides as a mask. After depositing the silicon nitride, the desired shape of the pressure-sensitive film is photolithographically defined on the bottom of the silicon substrate. Wet etching of the silicon substrate is performed using a hot alkaline solution (e.g., potassium hydroxide or tetramethylammonium hydroxide). After etching, the silicon nitride mask layer is removed using a hot phosphoric acid solution.

[0173] Reference Fig. 21B , a varistor PR is formed on the first substrate BS1. In some embodiments, the varistor PR is formed using a photolithography process. In one example, a photoresist is formed on the first substrate BS1 as a mask to perform ion implantation. After the ion implantation process, the photoresist is removed, and the first substrate BS1 is annealed. In one example, after annealing, the varistor PR has a resistance value of 100Ω / square to 1000Ω / square.

[0174] Reference Fig. 21C , a resistor lead RL is formed on the first substrate BS1. In some embodiments, the resistor lead RL is formed using a photolithography process. In one example, a photoresist is formed on the first substrate BS1 as a mask to perform ion implantation. After the ion implantation process, the photoresist is removed, and the first substrate BS1 is annealed. In one example, after annealing, the resistor lead RL has a resistance value of 20Ω / square to 100Ω / square.

[0175] Reference Fig.21D , forming a via v extending through the second substrate BS2. In some embodiments, the second substrate BS2 is a glass-based substrate. In one example, a glass-based substrate (e.g., BF33 or 7740 glass) is provided. The glass substrate is patterned to produce a via v. In one example, the diameter of the via v is in the range of 10 μm to 1000 μm. In another example, laser induced etching technology can be used to form the via v. First, a laser is used to perform laser induced modification on the glass substrate to produce a modified area in the area where the via v is to be formed. Subsequently, wet etching is used to etch the laser modified area into a via v having a specific aspect ratio.

[0176] Reference Fig.21E , forming chamber cb in the second substrate BS2. When the second substrate BS2 and the first substrate BS1 are assembled together, chamber cb becomes a pressure reference chamber. In one example, laser induced etching technology can be used to form chamber cb. Laser induced modification of the glass substrate substrate begins by processing the glass substrate substrate with a laser. The laser is used to scan the area where chamber cb is to be formed, generating a modified area. Subsequently, wet etching is used to etch the laser modified area into a desired shape to form chamber cb.

[0177] Reference Fig.21F, the first substrate substrate BS1 and the second substrate substrate BS2 are assembled together. In one example, the first substrate substrate BS1 and the second substrate substrate BS2 may be bonded together using an anodic bonding technique. During the bonding process, the first substrate substrate BS1 is connected to the positive terminal of a power source, and the second substrate substrate BS2 is connected to the negative terminal of the power source. In one example, a voltage in the range of 200V to 1000V and a temperature in the range of 100°C to 500°C are applied during the bonding process.

[0178] Reference Figure 21G , extending through the via in the second substrate BS2, forming a metal wire bond MWB. In one example, an adhesion layer is first deposited on the inner wall of the via, for example using a physical vapor deposition process or a chemical vapor deposition process. Next, a plating layer is deposited on the inner wall of the via. In another example, the adhesion layer has a thickness of 20nm to 50nm and includes titanium or chromium. In another example, the plating layer is made of copper and fills the via.

[0179] Reference Fig.21H , a redistribution layer RDL is formed on the second substrate BS2. In one example, an adhesion layer is first deposited on the surface of the second substrate BS2; then a plating layer is deposited on the adhesion layer, for example, using a physical vapor deposition process or a chemical vapor deposition process. In another example, the adhesion layer has a thickness of 20nm to 50nm and includes titanium or chromium. In another example, the plating layer has a thickness of 0.2nm to 0.5nm and is made of copper. After the plating process, photolithography is performed to produce a pattern of the redistribution layer RDL.

[0180] Reference Fig.21I , a zero adjustment resistor ZR is formed on the second base substrate BS2. In one example, an adhesive material layer and a zero adjustment resistor material layer are deposited on the second base substrate BS2, for example, using a physical vapor deposition process or a chemical vapor deposition process, and then a patterning process is performed to form the zero adjustment resistor ZR. Various suitable adhesive materials can be used to form the adhesive material layer. Examples of suitable adhesive materials for forming the adhesive material layer include titanium and chromium. Various suitable zero adjustment resistor materials can be used to form the zero adjustment resistor material layer. Examples of suitable zero adjustment resistor materials include kama alloys. In one example, the thickness of the adhesive material layer is in the range of 20 nanometers to 50 nanometers. In another example, the thickness of the zero adjustment resistor material layer is in the range of 0.1 micrometers to 1 micrometer.

[0181] Reference Fig.21J, forming an under bump metallization layer UBM on the second substrate BS2. In one example, the under bump metallization layer material is deposited on the second substrate BS2 using a physical vapor deposition process or a chemical vapor deposition process. In one example, the thickness of the under bump metallization layer UBM is in the range of 2 μm to 15 μm. In another example, the under bump metallization layer material includes indium or an alloy material such as copper-tin.

[0182] Reference Figure 21K , forming a solder joint SLD on the under bump metallization layer UBM. In some embodiments, screen printing is used to form the solder joint SLD. In one example, a metal solder paste is applied on the second substrate BS2 by screen printing, and a reflow soldering process is performed to form the solder joint SLD.

[0183] Fig. 22 is a schematic diagram showing the structure of a sensor chip in some embodiments of the present disclosure. Fig. 22 In some embodiments, the sensor chip includes: a first substrate BS1; a varistor PR and a resistor lead RL, which are located on the first substrate BS1; a second substrate BS2, which is located on a side of the varistor PR and the resistor lead RL away from the first substrate BS1; a metal wire bond MWB, which extends through the second substrate BS2 and is connected to the resistor lead RL; a redistribution layer RDL, a fixed resistor FR and an under bump metallization layer UBM, which are located on a side of the second substrate BS2 away from the first substrate BS1; and a solder joint SLD, which is located on a side of the under bump metallization layer UBM away from the second substrate BS2 and is connected to the under bump metallization layer UBM. The varistor PR is a variable resistor, and the resistance of the varistor PR changes when subjected to external pressure. The resistance of the fixed resistor FR does not change with external pressure.

[0184] In some embodiments, the sensor chip further includes a pressure reference chamber PRC located between the first substrate BS1 and the second substrate BS2. The first substrate BS1 and the second substrate BS2 encapsulate at least a portion of the piezoresistors PR in the pressure reference chamber PRC.

[0185] In some embodiments, the first substrate BS1 includes a portion located between the two piezoresistors. Optionally, the surface of the portion of the first substrate BS1 located between the two piezoresistors is exposed to the pressure reference chamber PRC. In some embodiments, the sensor chip includes a pressure sensing layer PSL. The pressure sensing layer PSL includes a portion of the first substrate BS1 located between the two piezoresistors.

[0186] In some embodiments, a metal wire bond MWB extending through the second substrate BS2 connects the resistor lead RL to the redistribution layer RDL. The resistor lead RL is connected to the varistor PR. In some embodiments, the signal in the varistor PR is transmitted to the redistribution layer RDL through the resistor lead RL and the metal wire bond MWB. The redistribution layer RDL is configured to transmit the signal to the under-bump metallization layer UBM, and then to the solder joint SLD. Optionally, the solder joint SLD is an output terminal of the sensor chip.

[0187] In some embodiments, the solder joint SLD is configured to transmit an input signal to the redistribution layer RDL through the under bump metallization layer UBM. The redistribution layer RDL is configured to transmit an input signal to the resistor lead RL and the varistor PR through the metal wire bond MWB. Optionally, the solder joint SLD is an input terminal of the sensor chip.

[0188] The under bump metallization layer UBM serves as an electrical connection structure of the sensor chip to transmit electrical signals from the redistribution layer RDL to the solder joint SLD, serves as a bonding layer between the redistribution layer RDL and the solder joint SLD, and prevents the solder joint material from diffusing into the redistribution layer RDL.

[0189] The pressure inside the pressure reference chamber PRC is used as a reference pressure for measuring the pressure of the sensor chip. When the external pressure is equal to the pressure inside the pressure reference chamber PRC, the output of the sensor chip is zero. When the external pressure exceeds the pressure inside the pressure reference chamber PRC, the output of the sensor chip is the difference between the external atmospheric pressure and the pressure inside the pressure reference chamber PRC.

[0190] The piezoresistors PR are configured to convert deformation of the pressure sensing layer PSL into electrical signals.

[0191] The pressure sensing layer PSL is configured to convert a pressure signal into a deformation signal.

[0192] Fig.23 FIG. 4 shows a layout of a piezoresistor and resistor leads on a first substrate of a sensor chip according to some embodiments of the present disclosure. Fig.23 In some embodiments, the sensor chip includes piezoresistors R1 and R2, and resistor leads RL1, RL2, RL3, and RL4. The first piezoresistors R1 are connected to the resistor leads RL1 and RL2. The second piezoresistors R2 are connected to the resistor leads RL3 and RL4. The piezoresistors R1 and R2 are variable resistors, and the resistance of the piezoresistors R1 and R2 changes when subjected to external pressure. For example, when subjected to external pressure, the resistance of the first piezoresistors R1 increases, while the resistance of the second piezoresistors R2 decreases.

[0193] Fig.23 The circuit structure depicted in Figure 3 The circuit structure depicted in the figure has been greatly miniaturized. Fig.23 The circuit structure depicted in FIG. 1 on the first substrate BS1 includes only piezoresistors and resistor leads, but not electrodes. The size of the resistor leads is correspondingly reduced, resulting in a significant reduction in the size of the sensor chip.

[0194] Fig.24 The layout of metal wire bonding, fixed resistors and under-bump metallization layers on the second substrate substrate of the sensor chip according to some embodiments of the present disclosure is shown. Fig.24 In some embodiments, the sensor chip includes: metal wire bonds MWB1, MWB2, MWB3, and MWB4; under bump metallization layers UBM1, UBM2, UBM3, and UBM4; and fixed resistors FR1 and FR2. The first metal wire bond MWB1 is connected to the first resistor lead RL1. The second metal wire bond MWB2 is connected to the second resistor lead RL2. The third metal wire bond MWB3 is connected to the third resistor lead RL3. The fourth metal wire bond MWB4 is connected to the fourth resistor lead RL4. The first fixed resistor FR1 is connected to the first under bump metallization layer UBM1 and to the third under bump metallization layer UBM3. The second fixed resistor FR2 is connected to the third under bump metallization layer UBM3 and to the fourth under bump metallization layer UBM4. The resistance of the first fixed resistor FR1 and the second fixed resistor FR2 does not change with external pressure.

[0195] In some embodiments, the first fixed resistor FR1 is electrically connected to the first metal wire bond MWB1 and to the second fixed resistor FR2; the second fixed resistor FR2 is electrically connected to the fourth metal wire bond MWB4 and to the first fixed resistor FR1. In some embodiments, the first under bump metallization layer UBM1 is connected to the first metal wire bond MWB1 and to the first fixed resistor FR1; the second under bump metallization layer UBM2 is connected to the second metal wire bond MWB2 and to the third metal wire bond MWB3; the third under bump metallization layer UBM3 is connected to the first fixed resistor FR1 and to the second fixed resistor FR2; the fourth under bump metallization layer UBM4 is connected to the second fixed resistor FR2 and to the fourth metal wire bond MWB4.

[0196] FIG. 25A to FIG. 25K The process of manufacturing a sensor chip in some embodiments of the present disclosure is shown. Fig.25A, forming a first substrate BS1. In some embodiments, the first substrate BS1 is a silicon-based substrate. In one example, a silicon substrate (e.g., an N(100) silicon substrate) is provided, and silicon nitride is grown on both sides as a mask. After depositing the silicon nitride, the desired shape of the pressure-sensitive film is photolithographically defined on the bottom of the silicon substrate. Wet etching of the silicon substrate is performed using a hot alkaline solution (e.g., potassium hydroxide or tetramethylammonium hydroxide). After etching, the silicon nitride mask layer is removed using a hot phosphoric acid solution.

[0197] Reference Fig.25B , a varistor PR is formed on the first substrate BS1. In some embodiments, the varistor PR is formed using a photolithography process. In one example, a photoresist is formed on the first substrate BS1 as a mask to perform ion implantation. After the ion implantation process, the photoresist is removed, and the first substrate BS1 is annealed. In one example, after annealing, the varistor PR has a resistance value of 100Ω / square to 1000Ω / square.

[0198] Reference Fig.25C , a resistor lead RL is formed on the first substrate BS1. In some embodiments, the resistor lead RL is formed using a photolithography process. In one example, a photoresist is formed on the first substrate BS1 as a mask to perform ion implantation. After the ion implantation process, the photoresist is removed, and the first substrate BS1 is annealed. In one example, the resistor lead RL has a resistance value of 20Ω / square to 100Ω / square after annealing.

[0199] Reference Fig.25D , forming a via v extending through the second substrate BS2. In some embodiments, the second substrate BS2 is a glass-based substrate. In one example, a glass-based substrate (e.g., BF33 or 7740 glass) is provided. The glass substrate is patterned to produce a via v. In one example, the diameter of the via v is in the range of 10 μm to 1000 μm. In another example, laser induced etching technology can be used to form the via v. First, a laser is used to perform laser induced modification on the glass substrate to produce a modified area in the area where the via v is to be formed. Subsequently, wet etching is used to etch the laser modified area into a via v having a specific aspect ratio.

[0200] Reference Fig.25E, forming chamber cb in the second substrate BS2. When the second substrate BS2 and the first substrate BS1 are assembled together, chamber cb becomes a pressure reference chamber. In one example, laser induced etching technology can be used to form chamber cb. Laser induced modification of the glass substrate substrate begins by processing the glass substrate substrate with a laser. The laser is used to scan the area where chamber cb is to be formed, generating a modified area. Subsequently, wet etching is used to etch the laser modified area into a desired shape to form chamber cb.

[0201] Reference Fig.25F , the first substrate substrate BS1 and the second substrate substrate BS2 are assembled together. In one example, the first substrate substrate BS1 and the second substrate substrate BS2 may be bonded together using an anodic bonding technique. During the bonding process, the first substrate substrate BS1 is connected to the positive terminal of a power source, and the second substrate substrate BS2 is connected to the negative terminal of the power source. In one example, a voltage in the range of 200V to 1000V and a temperature in the range of 100°C to 500°C are applied during the bonding process.

[0202] Reference Figure 25G , extending through the via in the second substrate BS2, forming a metal wire bond MWB. In one example, an adhesion layer is first deposited on the inner wall of the via, for example using a physical vapor deposition process or a chemical vapor deposition process. Next, a plating layer is deposited on the inner wall of the via. In another example, the adhesion layer has a thickness of 20nm to 50nm and includes titanium or chromium. In another example, the plating layer is made of copper and fills the via.

[0203] Reference Fig.25H , a redistribution layer RDL is formed on the second substrate BS2. In one example, an adhesion layer is first deposited on the surface of the second substrate BS2; then a plating layer is deposited on the adhesion layer, for example, using a physical vapor deposition process or a chemical vapor deposition process. In another example, the adhesion layer has a thickness of 20nm to 50nm and includes titanium or chromium. In another example, the plating layer has a thickness of 0.2nm to 0.5nm and is made of copper. After the plating process, photolithography is performed to produce a pattern of the redistribution layer RDL.

[0204] Reference Fig.25I, a fixed resistor FR is formed on the second base substrate BS2. In one example, an adhesive material layer and a resistive material layer are deposited on the second base substrate BS2, for example, using a physical vapor deposition process or a chemical vapor deposition process, and then a patterning process is performed to form a fixed resistor FR. Various suitable adhesive materials can be used to form the adhesive material layer. Examples of suitable adhesive materials for forming the adhesive material layer include titanium and chromium. Various suitable resistive materials can be used to form the resistive material layer. Examples of suitable resistive materials include kama alloys. In one example, the thickness of the adhesive material layer is in the range of 20 nanometers to 50 nanometers. In another example, the thickness of the zeroing resistance material layer is in the range of 0.1 micrometers to 1 micrometer.

[0205] Reference Fig.25J , forming an under bump metallization layer UBM on the second substrate BS2. In one example, the under bump metallization layer material is deposited on the second substrate BS2 using a physical vapor deposition process or a chemical vapor deposition process. In one example, the thickness of the under bump metallization layer UBM is in the range of 2 μm to 15 μm. In another example, the under bump metallization layer material includes indium or an alloy material such as copper-tin.

[0206] Reference Figure 25K , forming a solder joint SLD on the under bump metallization layer UBM. In some embodiments, screen printing is used to form the solder joint SLD. In one example, a metal solder paste is applied on the second substrate BS2 by screen printing, and a reflow soldering process is performed to form the solder joint SLD.

[0207] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. A sensor chip, comprising: a first substrate base plate; a varistor, which is located on the first substrate; A second substrate, which is located on a side of the varistor away from the first substrate; a metal wire bond extending through the second substrate substrate; as well as a pressure reference chamber located between the first substrate and the second substrate; The first substrate and the second substrate encapsulate at least a portion of the piezoresistor within the pressure reference chamber.

2. The sensor chip according to claim 1, further comprising a resistor lead located on the first substrate substrate; in, The resistor leads are connected to the varistor and to the metal wire bonds.

3. The sensor chip according to claim 1, further comprising a redistribution layer located on a side of the second substrate substrate away from the first substrate substrate; in, The redistribution layer is connected to the metal wire bonds.

4. The sensor chip according to claim 1, further comprising: an under bump metallization layer, which is located on a side of the second substrate away from the first substrate; as well as A solder joint is located at a side of the under bump metallization layer away from the second substrate and connected to the under bump metallization layer.

5. The sensor chip according to claim 1, further comprising a via extending through the second substrate base; in, The metal wire bond is at least partially located in the via.

6. The sensor chip according to claim 5, wherein: The via hole has a trapezoidal shape, and an angle is formed between a top surface and a side surface of the trapezoidal shape; and The angle is in the range of 80 degrees to 90 degrees.

7. The sensor chip according to any one of claims 1 to 6, comprising a pressure sensing layer, wherein the pressure sensing layer is configured to convert a pressure signal into a deformation signal; in, The pressure sensing layer includes a portion of the first substrate substrate located between two piezoresistors; as well as The piezoresistors are configured to convert the deformation signals into electrical signals.

8. The sensor chip according to claim 7, wherein: A surface of a portion of the first substrate between the two piezoresistors is exposed to the pressure reference chamber.

9. The sensor chip according to any one of claims 1 to 6, further comprising an insulating layer located on the first substrate; in, The varistor is located on a side of the insulating layer away from the first substrate; The pressure reference chamber is located between the insulating layer and the second substrate; as well as The insulating layer and the second substrate encapsulate at least a portion of the piezoresistor within the pressure reference chamber.

10. The sensor chip according to claim 9, comprising a pressure sensing layer, wherein the pressure sensing layer is configured to convert a pressure signal into a deformation signal; in, The pressure sensing layer includes a portion of the first substrate located between the two piezoresistors and a portion of the insulating layer located between the two piezoresistors; as well as The piezoresistors are configured to convert the deformation signals into electrical signals.

11. The sensor chip according to claim 10, wherein: A surface of a portion of the insulating layer located between the two piezoresistors is exposed to the pressure reference chamber. 12 . The sensor chip according to claim 1 , further comprising a thermistor located on a side of the second substrate substrate that is away from the first substrate substrate. 13 . The sensor chip according to claim 1 , further comprising a hygrometer located on a side of the second substrate substrate that is away from the first substrate substrate. 14 . The sensor chip according to claim 1 , further comprising one or more zero adjustment resistors located on a side of the second substrate substrate away from the first substrate substrate.

15. The sensor chip according to claim 14, comprising: A first varistor, which is located on the first substrate; a first metal wire bond located on a side of the second substrate away from the first substrate and electrically connected to the first varistor; At least one of a first under bump metallization layer, a second under bump metallization layer, or a third under bump metallization layer, which is located on a side of the second substrate away from the first substrate; as well as At least one of a first zeroing resistor, a second zeroing resistor, or a third zeroing resistor, wherein the first zeroing resistor is connected to the first metal wire bond and to the first under-bump metallization layer, the second zeroing resistor is connected to the first metal wire bond and to the second under-bump metallization layer, and the third zeroing resistor is connected to the first metal wire bond and to the third under-bump metallization layer.

16. The sensor chip according to claim 15, further comprising: a fourth varistor, which is located on the first substrate; an eighth metal wire bond located on a side of the second substrate substrate away from the first substrate substrate and electrically connected to the fourth varistor; at least one of a fourth under bump metallization layer, a fifth under bump metallization layer or a sixth under bump metallization layer, which is located on a side of the second substrate away from the first substrate; as well as At least one of a fourth zeroing resistor, a fifth zeroing resistor or a sixth zeroing resistor, wherein the fourth zeroing resistor is connected to the eighth metal wire bond and to the fourth under-bump metallization layer, the fifth zeroing resistor is connected to the eighth metal wire bond and to the fifth under-bump metallization layer, and the sixth zeroing resistor is connected to the eighth metal wire bond and to the sixth under-bump metallization layer.

17. The sensor chip according to claim 16, further comprising a second piezoresistor and a third piezoresistor located on the first substrate substrate; in, When no pressure is applied to the sensor chip, the resistance of the second piezoresistor, the resistance of the third piezoresistor, the resistance of the first piezoresistor and one of the first zero-adjusting resistor, the second zero-adjusting resistor or the third zero-adjusting resistor, and the resistance of the fourth piezoresistor and one of the fourth zero-adjusting resistor, the fifth zero-adjusting resistor or the sixth zero-adjusting resistor are substantially the same.

18. The sensor chip according to any one of claims 1 to 13, further comprising one or more fixed resistors located on a side of the second substrate substrate away from the first substrate substrate.

19. The sensor chip according to claim 18, further comprising: A first varistor and a second varistor, which are located on the first substrate; a first fixed resistor and a second fixed resistor, which are located on a side of the second substrate away from the first substrate; a first metal wire bond located on a side of the second substrate away from the first substrate and electrically connected to the first varistor; a second metal wire bond located on a side of the second substrate away from the first substrate and electrically connected to the first varistor; a third metal wire bond located on a side of the second substrate away from the first substrate and electrically connected to the second varistor; as well as a fourth metal wire bond located on a side of the second substrate substrate away from the first substrate substrate and electrically connected to the second varistor; wherein the first fixed resistor is electrically connected to the first metal wire bond and is electrically connected to the second fixed resistor; as well as The second fixed resistor is electrically connected to the fourth metal wire bond, and is electrically connected to the first fixed resistor.

20. The sensor chip according to claim 19, further comprising a first under bump metallization layer, a second under bump metallization layer, a third under bump metallization layer and a fourth under bump metallization layer located on a side of the second substrate substrate away from the first substrate substrate; in, the first under bump metallization layer connected to the first metal wire bond and to the first fixed resistor; the second under bump metallization layer is connected to the second metal wire bond and to the third metal wire bond; The third under bump metallization layer is connected to the first fixed resistor and to the second fixed resistor; as well as The fourth under bump metallization layer is connected to the second fixed resistor and to the fourth metal wire bond.

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