Array substrate and display panel

Abstract

The embodiment of the invention provides an array substrate and a display panel. The array substrate includes: a plurality of first active patterns; a plurality of first metal lines; a plurality of conductive parts; the conductive part comprises a first conductive part and a second conductive part which are distributed along the first direction; wherein the adjacent first metal wires on the two sides of the conductive part comprise first sub-metal wires and second sub-metal wires; wherein the first sub metal wire is electrically connected with the second part; the first part is electrically connected with the first electrode through the conductive part; at least the distance between the orthographic projection of the second conductive part on the substrate and the orthographic projection of the first sub-metal wire on the substrate is larger than the distance between the orthographic projection of the second conductive part on the substrate and the orthographic projection of the second sub-metal wire on the substrate.

Description

Array substrate and display panel

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on August 30, 2023, with application number PCT / CN2023 / 115924 and invention name "Array substrate, display panel and display device"; this application claims the priority of the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on March 22, 2024, with application number PCT / CN2024 / 083398 and invention name "Array substrate, display panel and display device", all contents of which are incorporated by reference in this application.

[0003] The present invention relates to the field of semiconductor technology, and in particular to an array substrate and a display panel.

[0004] Virtual reality technology is a new technology that "seamlessly" integrates real-world information and virtual-world information. Compared with conventional display products, the most obvious feature of virtual reality display products is their ultra-high resolution. The best choice for ultra-high PPI is currently liquid crystal display (LCD) technology, because in the LCD display structure, the pixel area circuit has only one switching transistor (Thin Film Transistor, TFT), which is very conducive to achieving high PPI.

[0005] Summary of the invention

[0006] The present disclosure provides an array substrate and a display panel. The array substrate includes:

[0007] substrate;

[0008] The first active layer is located on one side of the substrate and includes: a plurality of first active patterns; the first active patterns include: a first portion and a second portion distributed along a first direction;

[0009] The first metal layer comprises: a plurality of first metal wires; the second portion overlaps with a portion of the first metal wires projected orthographically on the substrate at a portion of the second portion projected orthographically on the substrate;

[0010] The second metal layer includes: a plurality of second metal lines extending along a second direction;

[0011] The first conductive layer comprises: a plurality of conductive parts; the orthographic projection of at least one of the plurality of conductive parts on the substrate is located between the orthographic projections of adjacent first metal lines on the substrate;

[0012] The second conductive layer includes: a plurality of first electrodes;

[0013] Among them, the first metal wires adjacent to the two sides of the conductive part include: a first sub-metal wire, and a second sub-metal wire; wherein the first sub-metal wire is electrically connected to the second part; the first part is electrically connected to the first electrode through the conductive part; the distance between the conductive part's orthographic projection on the substrate and the first sub-metal wire's orthographic projection on the substrate is greater than the distance between the conductive part and the second sub-metal wire's orthographic projection on the substrate.

[0014] In a possible implementation manner, the conductive parts adjacent to each other on both sides of the first sub-metal line include: a first sub-conductive part, and a second sub-conductive part; wherein the first sub-metal conductive part is electrically connected to the first sub-metal line through a transistor;

[0015] The distance between the orthographic projection of the first sub-metal line on the substrate and the orthographic projection of the first sub-conductive portion on the substrate is greater than the distance between the orthographic projection of the first sub-metal line on the substrate and the orthographic projection of the second sub-conductive portion on the substrate.

[0016] In a possible implementation manner, the conductive portion includes: a first conductive portion and a second conductive portion distributed along the first direction; an orthographic projection of the first conductive portion on the substrate has an overlapping area with an orthographic projection of the first portion on the substrate, and an orthographic projection of the second conductive portion on the substrate has an overlapping area with an orthographic projection of the second portion; the first conductive portion and the second conductive portion have different extension directions;

[0017] At least the distance between the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first sub-metal line on the substrate is greater than the distance between the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the second sub-metal line on the substrate.

[0018] In a possible implementation manner, the second conductive portion has a first outer edge facing the first sub-metal line, and a second outer edge facing the second sub-metal line;

[0019] The distance between the orthographic projection of the first outer edge on the substrate and the orthographic projection of the first sub-metal routing on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal routing on the substrate.

[0020] In a possible implementation manner, the second conductive portion, the first sub-metal line, and the second sub-metal line satisfy the following relationship:

[0021] 0.05μm≤(ab) / 2≤0.15μm; wherein a represents the distance between the orthographic projection of the first outer edge on the substrate 11 and the orthographic projection of the first sub-metal routing on the substrate, and b represents the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal routing on the substrate.

[0022] In a possible implementation manner, the first metal line includes: first sub-metal parts and second sub-metal parts alternately arranged along the first direction; the first sub-metal parts and the second sub-metal parts extend in different directions;

[0023] The first conductive portion extends along an extending direction of the second sub-metal portion, and the second conductive portion extends along the extending direction of the first sub-metal portion.

[0024] In a possible implementation manner, the second conductive portion has a first outer edge facing the first sub-metal line, and a second outer edge facing the second sub-metal line; an extension line of the first outer edge intersects an extension line of the second outer edge;

[0025] The distance between the orthographic projection of the first outer edge on the substrate and the orthographic projection of the first sub-metal routing on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal routing on the substrate.

[0026] In a possible implementation manner, the first metal line includes: first sub-metal parts and second sub-metal parts alternately arranged along the first direction; the first sub-metal parts and the second sub-metal parts extend in different directions;

[0027] The first outer edge extends along the first direction; the extending direction of the second outer edge is the same as the extending direction of the first sub-metal portion.

[0028] In a possible implementation manner, the second conductive portion has a first outer edge facing the first sub-metal line, and a second outer edge facing the second sub-metal line;

[0029] The first outer edge includes: a first sub-edge portion and a second sub-edge portion; the second sub-edge portion is located on a side of the first sub-edge portion away from the first conductive portion, and the second sub-edge portion is located on a side of an extension line of the first sub-edge portion toward the first sub-metal wiring;

[0030] The distance between the orthographic projection of the second sub-edge on the substrate and the orthographic projection of the first sub-metal routing on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal routing on the substrate.

[0031] In a possible implementation manner, the first metal line includes: first sub-metal parts and second sub-metal parts alternately arranged along the first direction; the first sub-metal parts and the second sub-metal parts extend in different directions;

[0032] The second sub-edge extends along an extending direction of the first sub-metal portion.

[0033] In a possible implementation manner, the first sub-edge extends along an extension direction of the second sub-metal portion; and the second outer edge extends along the extension direction of the first sub-metal portion.

[0034] In a possible implementation manner, a first bending portion is provided between the first sub-metal portion and the second sub-metal portion; and the first outer edge has a second bending portion;

[0035] The orthographic projection of the second bending portion on the substrate is located in a region between the orthographic projection of the first metal edge on the substrate and the orthographic projection of the first connecting line on the substrate, wherein the first metal edge is the outer edge of the second metal wire facing the first conductive portion, and the first connecting line is a connecting line of the first bending portions of two adjacent first metal wires.

[0036] In a possible implementation, the array substrate further includes: a third metal layer located on the side of the first active layer facing the substrate; the third metal layer includes: a plurality of third metal wires extending along the second direction; the orthographic projection of the third metal wire on the substrate covers the orthographic projection of the second metal wire on the substrate;

[0037] The orthographic projection of the second bending portion on the substrate is located in a region between the orthographic projection of the first metal edge on the substrate and the orthographic projection of the second metal edge on the substrate, and the second metal edge is the outer edge of the third metal wire facing the first conductive portion.

[0038] In a possible implementation manner, the first outer edge has a second bending portion;

[0039] The orthographic projection of the second bent portion on the substrate overlaps with the orthographic projection of the first metal edge on the substrate, and the first metal edge is the outer edge of the second metal wire facing the first conductive portion.

[0040] In a possible implementation manner, a distance between two ends of the first sub-metal portion in the second direction is equal to a distance between two ends of the second sub-metal portion in the second direction; and the second direction is perpendicular to the first direction.

[0041] In a possible implementation, the first conductive portion is located between two adjacent first sub-metal portions in the second direction; the second conductive portion is located between two adjacent second sub-metal portions in the second direction; and an extension direction of the first conductive portion is the same as an extension direction of the first sub-metal portion.

[0042] In a possible implementation, the first electrode includes: a first electrode portion and a second electrode portion distributed along the first direction; an extension direction of the first electrode portion is the same as an extension direction of the first sub-metal portion, and an extension direction of the second electrode portion is the same as an extension direction of the second sub-metal portion.

[0043] In a possible implementation manner, an orthographic projection of the first electrode portion on the substrate and an orthographic projection of the second conductive portion on the substrate have an overlapping area, and are electrically connected at the overlapping position.

[0044] In a possible implementation manner, the first conductive portion has a third outer edge facing the first sub-metal line, and a fourth outer edge facing the second sub-metal line; the third edge is parallel to the fourth outer edge.

[0045] In a possible implementation, the distance between the orthographic projection of the third outer edge on the substrate and the orthographic projection of the first sub-metal routing on the substrate is greater than the distance between the orthographic projection of the fourth outer edge on the substrate and the orthographic projection of the second sub-metal routing on the substrate.

[0046] In a possible implementation, the distance between the orthographic projection of the third outer edge on the substrate and the orthographic projection of the first sub-metal routing on the substrate is equal to the distance between the orthographic projection of the fourth outer edge on the substrate and the orthographic projection of the second sub-metal routing on the substrate.

[0047] In a possible implementation manner, the first outer edge, the second outer edge, and the third outer edge satisfy the following relationship:

[0048] a>c>b, wherein c represents the distance between the orthographic projection of the third outer edge on the substrate and the orthographic projection of the first sub-metal wiring on the substrate.

[0049] In a possible implementation manner, the second conductive portion has a fifth outer edge extending along the second direction, and the fifth outer edge is located on a side of the second metal wire away from the first conductive portion.

[0050] In a possible implementation manner, the second conductive portion has a fifth outer edge extending along the second direction, and the orthographic projection of the second metal line on the substrate covers the orthographic projection of the fifth outer edge on the substrate.

[0051] In a possible implementation manner, the second metal wire has a sixth outer edge extending along the second direction;

[0052] The orthographic projection of a portion of the sixth outer edge on the substrate coincides with the orthographic projection of the fifth outer edge on the substrate.

[0053] In a possible implementation manner, the second portion includes: a first sub-portion and a second sub-portion; the first sub-portion extends along the second direction, and an orthographic projection of the first sub-portion on the substrate overlaps an orthographic projection of the first metal line on the substrate; the second sub-portion connects the first sub-portion and the first portion;

[0054] The plurality of first active patterns include: a first active pattern row and a second active pattern row; the first active pattern row and the second active pattern row extend along a second direction and are arranged overlappingly along the first direction;

[0055] The first active pattern row and the second active pattern row both include a plurality of first active patterns; and in the first active pattern row, the second sub-portion extends along a third direction; in the second active pattern row, the second sub-portion extends along a fourth direction, and the third direction intersects the fourth direction.

[0056] In a possible implementation manner, in the first active pattern row, the first sub-portion and the first portion are located on different sides of the second sub-portion; in the second active pattern row, the first sub-portion and the first portion are located on the same side of the second sub-portion.

[0057] In a possible implementation manner, the first metal line includes: a first sub-metal portion, a second sub-metal portion, and a third sub-metal portion alternately arranged along the first direction;

[0058] The second sub-metal portion extends along the first direction; the first sub-metal portion is located on one side of an extension line of the second sub-metal portion, and the third sub-metal portion is located on the other side of the extension line of the second sub-metal portion.

[0059] In a possible implementation manner, a distance between two ends of the first sub-metal portion in the second direction is equal to a distance between two ends of the third sub-metal portion in the second direction.

[0060] In a possible implementation, the plurality of first active patterns include: a third active pattern row and a fourth active pattern row; the third active pattern row and the fourth active pattern row extend along the second direction and are arranged overlappingly along the first direction;

[0061] The third active pattern row and the fourth active pattern row both include a plurality of first active patterns; in the same third active pattern row, each of the first active patterns is electrically connected to the first metal line on the same side; in the same fourth active pattern row, each of the first active patterns is electrically connected to the first metal line on the same side; between two adjacent first metal lines, the first active pattern of the third active pattern row and the first active pattern of the fourth active pattern row are electrically connected to different first metal lines.

[0062] In a possible implementation manner, the first portion extends along the first direction, and the second portion is located on one side of an extension line of the first portion;

[0063] In the third active pattern row, the first portion and the second portion intersect to form an opening of a first angle, and the first sub-metal portion and the second sub-metal portion intersect to form an opening of a second angle are opposite to each other; in the fourth active pattern row, the first portion and the second portion intersect to form an opening of a first angle, and the third sub-metal portion and the next second sub-metal portion in the first direction intersect to form an opening of a third angle.

[0064] In a possible implementation manner, the first portion extends along the first direction, and the second portion is located on one side of an extension line of the first portion;

[0065] In the third active pattern row, the opening at the first angle formed by the intersection of the first portion and the second portion and the opening at the second angle formed by the intersection of the first sub-metal portion and the second sub-metal portion are oriented to the same side; in the fourth active pattern row, the opening at the first angle formed by the intersection of the first portion and the second portion and the opening at the third angle formed by the intersection of the third sub-metal portion and the next second sub-metal portion in the first direction are oriented to the same side.

[0066] In a possible implementation manner, the plurality of first active patterns include: a plurality of active pattern rows; the active pattern rows include: a plurality of first active patterns sequentially arranged along the second direction;

[0067] In the same active pattern row, each of the first active patterns is electrically connected to the first metal line on the same side; between two adjacent first metal lines, the first active patterns in the active pattern row are electrically connected to the same first metal line.

[0068] In a possible implementation, the array substrate includes: a first via hole, a second via hole, and a third via hole; the first active pattern is electrically connected to the conductive portion through the first via hole; the conductive portion is electrically connected to the first electrode through the second via hole; the first active pattern is electrically connected to the first metal wire through the third via hole;

[0069] The second conductive layer includes: a plurality of first electrode rows extending along the second direction and arranged in sequence along the first direction; the first electrode rows include: a plurality of first electrodes arranged in sequence along the first direction;

[0070] The orthographic projection of the first active pattern electrically connected to the first electrodes in the Mth row through the first via holes and the second via holes on the substrate overlaps with the orthographic projection of the first electrodes in the M-1th row on the substrate.

[0071] In a possible implementation, a portion of the first electrode extends in the same direction as the second sub-metal portion; and another portion of the first electrode extends in the same direction as the third sub-metal portion.

[0072] In a possible implementation manner, the first metal wire extends along a first direction, the first portion extends along the first direction, and the conductive portion extends along the first direction;

[0073] The distance between the orthographic projection of all the conductive parts on the substrate and the orthographic projection of the first sub-metal line on the substrate is greater than the distance between the orthographic projection of all the conductive parts on the substrate and the orthographic projection of the second sub-metal line on the substrate.

[0074] In a possible implementation manner, the conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship:

[0075] 15%≤i2 / i1≤75%, wherein i1 represents the minimum distance between the orthographic projection of the conductive portion on the substrate and the orthographic projection of the first sub-metal line on the substrate, and i2 represents the minimum distance between the orthographic projection of the conductive portion on the substrate and the orthographic projection of the second sub-metal line on the substrate.

[0076] In a possible implementation manner, the conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship:

[0077] 3%≤(i1-i2) / i3≤15%, wherein i3 represents the minimum distance between adjacent first sub-metal lines and second sub-metal lines.

[0078] In a possible implementation manner, the conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship:

[0079] 60%≤i4 / i3≤95%, wherein i4 represents the length of the conductive portion in a direction perpendicular to the first direction.

[0080] In a possible implementation, one end of the conductive portion is electrically connected to the first portion, and the other end extends toward the second metal line and exceeds the second metal line to form a protrusion, and the protrusion overlaps the orthographic projection of the first active pattern on the substrate.

[0081] In a possible implementation manner, the first conductive layer is located on a side of the first active layer away from the substrate; the first electrode is located on a side of the first conductive layer away from the substrate; the array substrate further comprises: a first insulating layer located between the first active layer and the first conductive layer, and a first via hole penetrating the first insulating layer, the conductive portion being electrically connected to the first portion through the first via hole;

[0082] The array substrate further includes: a second insulating layer located between the first conductive layer and the first electrode, and a second via hole penetrating the second insulating layer; the first electrode is electrically connected to the conductive portion through the second via hole;

[0083] In a direction perpendicular to the first direction, at least two adjacent second via holes are an integrated connected structure.

[0084] In a possible implementation, the second via has two side walls extending perpendicular to the first direction; at least one of the side walls has a protruding structure, and the protruding structure is located in a region between the orthographic projections of two adjacent first electrodes on the substrate in the second direction.

[0085] In a possible embodiment, the array substrate further includes: a color resist layer located between the second insulating layer and the second conductive layer; the color resist layer includes: a plurality of color resist portions; and at least part of the color resist portions overlap with the orthographic projection of the first metal line on the substrate.

[0086] In a possible implementation, the array substrate has a display area and a non-display area located outside the display area; and further includes located in the non-display area: a second active layer located on a side of the first active layer facing the substrate, a driving source and drain located on a side of the second active layer away from the substrate, and a driving gate;

[0087] The second active layer is located between the third metal layer and the substrate; the driving gate is located in the third metal layer; the driving source and drain are located in the first metal layer; the second active layer is located between the third metal layer and the first active layer; the driving source and drain are located in the second metal layer; the driving gate is located in the third metal layer;

[0088] The material of the first active layer includes: metal oxide; the material of the second active layer includes: low temperature polysilicon.

[0089] The embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure.

[0090] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure.

[0091] FIG. 1A is a schematic diagram showing a crosstalk problem in a display panel;

[0092] FIG. 1B is a second schematic diagram of a display panel having crosstalk failure;

[0093] FIG. 1C is a third schematic diagram of a display panel having a crosstalk problem;

[0094] FIG. 1D is a fourth schematic diagram of a display panel having a crosstalk problem;

[0095] FIG2A is a schematic top view of an array substrate according to an embodiment of the present disclosure;

[0096] FIG2B is a schematic diagram of a single film layer of the third metal layer in FIG2A ;

[0097] FIG2C is a schematic diagram of a single film layer of the first active layer in FIG2A ;

[0098] FIG2D is a schematic diagram of a single film layer of the second metal layer in FIG2A ;

[0099] FIG2E is a schematic diagram of a single film layer of the first metal layer in FIG2A ;

[0100] FIG2F is a schematic diagram of a single film layer of the first conductive layer in FIG2A ;

[0101] FIG2G is a schematic diagram of a single film layer of the second conductive layer in FIG2A ;

[0102] FIG3 is a schematic cross-sectional view of the dashed line A1A2 in FIG2A ;

[0103] FIG4A is a schematic diagram of a pixel electrode and associated structures provided by an embodiment of the present disclosure;

[0104] FIG4B is a schematic diagram of a first metal line M11 and associated structures provided in an embodiment of the present disclosure;

[0105] FIG4C is a schematic diagram of adjacent pixel electrodes and associated structures provided by an embodiment of the present disclosure;

[0106] FIG. 4D is a diagram of the first coupling capacitor C corresponding to FIG. 4A dp1 Schematic diagram of the composition;

[0107] FIG. 4E is a diagram of the second coupling capacitor C corresponding to FIG. 4A dp2 Schematic diagram of the composition;

[0108] FIG5 is a second schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0109] FIG6A is a third schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0110] FIG6B is a schematic diagram of a single film layer of the first conductive layer in FIG6A ;

[0111] FIG6C is a fourth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0112] FIG. 7 is a fifth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0113] FIG8A is a sixth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0114] FIG8B is a schematic diagram of a single film layer where the data line is located in FIG8A;

[0115] FIG9A is a seventh schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0116] FIG9B is an eighth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0117] FIG9C is a ninth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0118] FIG9D is a schematic diagram of a single film layer of the first conductive layer in FIG9C ;

[0119] FIG9E is a schematic diagram of a single film layer of the first metal layer in FIG9C ;

[0120] FIG9F is a tenth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0121] FIG9G is a schematic diagram of an eleventh array substrate provided in an embodiment of the present disclosure;

[0122] FIG9H is a twelfth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0123] FIG9I is a thirteenth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0124] FIG10A is a schematic diagram of a fourteenth array substrate provided in an embodiment of the present disclosure;

[0125] FIG10B is a schematic diagram of a fifteenth array substrate provided in an embodiment of the present disclosure;

[0126] FIG10C is a sixteenth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0127] FIG10D is a seventeenth schematic diagram of an array substrate provided in an embodiment of the present disclosure;

[0128] FIG10E is a schematic cross-sectional view along the dotted line A0 in FIG10D ;

[0129] FIG11 is a schematic cross-sectional view of an array substrate provided in an embodiment of the present disclosure;

[0130] FIG12A is a schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0131] FIG12B is a schematic diagram of a single film layer of the third metal layer in FIG12A;

[0132] FIG12C is a schematic diagram of a single film layer of the first active layer in FIG12A;

[0133] FIG12D is a schematic diagram of a single film layer of the second metal layer in FIG12A;

[0134] FIG12E is a schematic diagram of a single film layer of the first metal layer in FIG12A;

[0135] FIG12F is a schematic diagram of a single film layer of the first conductive layer in FIG12A ;

[0136] FIG12G is a schematic diagram of a single film layer of the second conductive layer in FIG12A;

[0137] FIG12H is a schematic diagram of an eighteenth array substrate provided in an embodiment of the present disclosure;

[0138] FIG13 is a schematic cross-sectional view of the dashed line A1A2 in FIG12A ;

[0139] FIG14A is a schematic diagram of only a portion of the film layer in FIG12A;

[0140] FIG14B is a second schematic diagram of only a portion of the film layer in FIG12A;

[0141] FIG15A is a schematic diagram of a pixel electrode and associated structures provided by an embodiment of the present disclosure;

[0142] FIG15B is a schematic diagram of a first metal line M11 and associated structures provided in an embodiment of the present disclosure;

[0143] FIG15C is a schematic diagram of adjacent pixel electrodes and associated structures provided in an embodiment of the present disclosure;

[0144] FIG. 15D is a diagram showing a first coupling capacitor C corresponding to FIG. 15A. dp1 Schematic diagram of the composition;

[0145] FIG. 15E is a diagram of the second coupling capacitor C corresponding to FIG. 15A dp2 Schematic diagram of the composition;

[0146] FIG16 is a second schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0147] FIG17A is a third schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0148] FIG. 17B is a diagram showing a first coupling capacitor C corresponding to FIG. 17A. dp1 Schematic diagram of the composition;

[0149] FIG. 17C is a diagram showing a second coupling capacitor C corresponding to FIG. 17B dp2 Schematic diagram of the composition;

[0150] FIG18 is a schematic diagram of a stack of only a portion of the film layers in FIG17A;

[0151] FIG19 is a fourth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0152] FIG20A is a fifth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0153] FIG. 20B may be a single-film layer schematic diagram of the third metal line M31 in FIG. 20A ;

[0154] FIG20C is a schematic diagram of a larger scope of FIG20B ;

[0155] FIG21 is a cross-sectional view of an array substrate according to an embodiment of the present disclosure;

[0156] FIG22 is a second cross-sectional schematic diagram of the array substrate provided in an embodiment of the present disclosure;

[0157] FIG23A is a sixth schematic top view of an array substrate provided in an embodiment of the present disclosure;

[0158] FIG23B is a schematic diagram of a single film layer of the third conductive layer in FIG23A;

[0159] FIG23C is a schematic diagram of a larger area of ​​FIG23B;

[0160] FIG. 24 is a schematic diagram of the display panel structure provided in an embodiment of the present disclosure.

[0161] A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0162] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0163] The ordinal numbers such as "first", "second", "third" and the like in this specification are provided to avoid confusion of constituent elements, rather than to limit the quantity. The "plurality" in this disclosure may include two or more.

[0164] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0165] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0166] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0167] In this specification, a transistor refers to an element including at least three terminals: a gate electrode (gate), a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, a channel region refers to a region where current mainly flows.

[0168] In addition, the gate of a transistor may be referred to as a control electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0169] In this specification, "parallel" means that the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle may be greater than -5° and less than 5°. In addition, "perpendicular" means that the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle may be greater than 85° and less than 95°.

[0170] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0171] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0172] In this specification, "about" or "substantially" means that the limit is not strictly defined and the process and measurement errors are allowed. In this specification, "substantially the same" may refer to the situation where the numerical value differs by less than 10%.

[0173] In the virtual reality (VR) head-mounted display product of the related art, the coupling capacitance Cdp1 between the data line and the electrically connected pixel is 1.322Ff; the coupling capacitance Cdp2 between the data line and the adjacent pixel is 1.173Ff; the coupling capacitance difference between Cdp1 and Cdp2 (i.e., |Cdp1-Cdp2| / Cdp1) is 11.27%, and the difference between the two is relatively large. In the column inversion structure, the coupling capacitance of the pixel electrode affected by the two adjacent data lines (with opposite polarities of the loaded data signals) is relatively different, and the voltage of the pixel electrode is easily deviated from the level, so that crosstalk is easily caused in the vertical direction.

[0174] Specifically, as shown in FIG. 1A , there is a first coupling capacitor C between the data line and its own pixel electrode (the own pixel electrode can be understood as a pixel electrode electrically connected to the data line) inside the pixel. dp1 , and a second coupling capacitor C with an adjacent pixel electrode (a pixel electrode not electrically connected to the data line) dp2 , when C dp1 >C dp2When the difference is large, there will be a conventional crosstalk problem. For example, when displaying the image with white in the middle and black at the edges as shown in FIG1B, the image will be bright at the top and dark at the bottom with the middle as the boundary, as shown in FIG1C. Specifically, in combination with FIG1B, FIG1C and FIG1D, pixel A1 and pixel A2 are two pixels at different positions on the same data line, pixel B1 and pixel B2 are two pixels at different positions on the same data line, pixel B1 and pixel A1 are two pixels in the same row on adjacent data lines, and pixel B2 and pixel A2 are two pixels in the same row on adjacent data lines; when the pixel self-coupling effect (the first coupling capacitor C dp1 ) and mutual coupling effect (second coupling capacitor C dp2 ) are inconsistent, the charging voltage of pixel A1 is the positive voltage of L127, which will be pulled up by the voltage of L255 in the middle of the screen, thereby increasing the voltage difference between pixel A1 and the common electrode voltage (Vcom), and displaying as bright; the charging voltage of pixel A2 is still the negative voltage of the previous frame, which will be pulled up by the voltage of L255 in the middle of the screen, thereby decreasing the voltage difference between pixel A2 and the common electrode voltage (Vcom), and displaying as dark, that is, the undesirable phenomenon of Crosstalk screen being bright on the top and dark on the bottom occurs.

[0175] In view of this, referring to FIGS. 2A-2G, 3, and 9A, wherein FIG. 2B is a schematic diagram of a single film layer of the third metal layer in FIG. 2A, FIG. 2C is a schematic diagram of a single film layer of the first active layer in FIG. 2A, FIG. 2D is a schematic diagram of a single film layer of the second metal layer in FIG. 2A, FIG. 2E is a schematic diagram of a single film layer of the first metal layer in FIG. 2A, FIG. 2F is a schematic diagram of a single film layer of the first conductive layer in FIG. 2A, FIG. 2G is a schematic diagram of a single film layer of the second conductive layer in FIG. 2A, FIG. 3 is a schematic diagram of a cross-section at a dotted line A1A2 in FIG. 2A, and FIG. 4A is a schematic diagram of only a portion of the film layers in FIG. 2A. An embodiment of the present disclosure provides an array substrate, which includes:

[0176] Substrate 11;

[0177] The first active layer C1 is located on one side of the substrate 11, and includes: a plurality of first active patterns C11; the first active pattern C11 includes: a first portion CA and a second portion CB distributed along a first direction X, and the second portion CB and the first portion CA have different extension directions; wherein, different extension directions can be understood as the extension directions are not on the same straight line;

[0178] The first metal layer M1 includes: a plurality of first metal lines M11; an orthographic projection of a first portion CA on a substrate 11 is located between orthographic projections of adjacent first metal lines M11 on the substrate 11; a portion of an orthographic projection of a second portion CB on the substrate 11 overlaps with a portion of an orthographic projection of the first metal line M11 on the substrate 11; specifically, the first metal line M11 may be a data line; specifically, the display area AA may have a plurality of first transistors, and a position where the second portion CB overlaps with the first metal line M11 may serve as a first electrode of the first transistor; and the second portion CB may be turned on at a position where it overlaps with the first metal line M11 to achieve electrical connection between the first transistor and the data line;

[0179] The second metal layer M2 includes: a plurality of second metal wires M21 extending along a second direction Y;

[0180] The first conductive layer D1 includes: a plurality of conductive parts D11 located in the display area AA; the orthographic projection of at least one of the plurality of conductive parts D11 on the substrate 11 is located between the orthographic projections of adjacent first metal lines M11 on the substrate 11; the conductive part D11 includes: a first conductive part DA and a second conductive part DB distributed along the first direction X; the orthographic projection of the first conductive part DA on the substrate 11 has an overlapping area with the orthographic projection of the first part CA on the substrate 11, and the second conductive part DB has an overlapping area with the orthographic projection of the second part CB on the substrate 11; the first conductive part DA and the second conductive part DB have different extension directions; specifically, the first conductive layer D1 may be a transparent conductive layer, and the conductive part D11 may serve as the second electrode of the first transistor to conduct the first active pattern C11 with the first electrode D21; specifically, the orthographic projection shape of the conductive part D11 on the substrate 11 may be bent, and the maximum length of the conductive part D11 in the first direction X may be greater than the length in the second direction Y;

[0181] The second conductive layer D2 includes: a plurality of first electrodes D21 located in the display area AA; specifically, the second conductive layer D2 may be a transparent conductive layer, and the material of the second conductive layer D2 may be the same as the material of the first conductive layer D1; specifically, the first electrode D21 may be a pixel electrode; specifically, the orthographic projection of the first electrode D21 on the substrate 11 may be located between the orthographic projections of adjacent first metal lines M11 on the substrate 11; specifically, the orthographic projection shape of the first electrode D21 on the substrate 11 may be bent; the length of the first electrode D21 in the first direction X may be greater than the length in the second direction Y;

[0182] Among them, the first metal wire M11 adjacent to the two sides of the conductive part D11 includes: a first sub-metal wire MA, and a second sub-metal wire MB; wherein the first sub-metal wire MA is electrically connected to the second part CB, that is, the first metal wire M11 electrically connected to the second part CB is used as the first sub-metal wire MA, and the other first metal wire M11 is used as the second sub-metal wire MB; the first part CA is electrically connected to the first electrode D21 through the conductive part D11; at least the distance a between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 is greater than the distance b between the orthographic projection of the second sub-metal wire MB on the substrate 11.

[0183] In the embodiment of the present disclosure, at least the spacing a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 is greater than the spacing b between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11. This can increase the spacing between the second conductive portion DB and the first sub-metal line MA, thereby reducing the capacitance between the second conductive portion DB and the first sub-metal line MA, and increase the capacitance between the second sub-metal line MB, thereby reducing the difference between the two, thereby improving poor vertical crosstalk.

[0184] The first metal line M11 and the associated structure can form a first coupling capacitor Cdp1 with its own pixel electrode and the associated structure; the first metal line M11 and the associated structure can form a second coupling capacitor Cdp2 with the adjacent pixel electrode and the associated structure; wherein the own pixel electrode and the associated structure can be the area shown in the dotted box in FIG. 4A, and can specifically include: a first electrode D21 (as shown in the dotted box S1 in FIG. 4A), and a conductive portion D11 connected to the first electrode D21 through the second via hole K2 (as shown in the dotted box S2 in FIG. 4A), and the conductive portion D11 through the first via hole K The first active pattern C11 connected to the second metal line M21 is located at a portion of the second metal line M21 on a side away from the second metal line M21 in the first direction X (as shown in the dotted box S3 in FIG. 4A , that is, the portion of the first active pattern C11 located at the lower side of the second metal line M21. Since the time for each row of pixels to be turned on is very short during a frame of display, it can be considered that the gate of the first transistor in the pixel is turned off for most of the time, and the portion of the first active pattern C11 covered by the second metal line M21 can be considered as an insulator); the first metal line M11 and the associated structure can be shown in the dotted box in FIG. 4B The region may specifically include: the first metal line M11 (as shown in the dotted frame S4 ​​in FIG. 4B ), and the portion of the first active pattern C11 electrically connected to the first metal line M11 through the third via K3 and located on the side of the second metal line M21 close to the second metal line M21 in the first direction X (as shown in the dotted frame S5 in FIG. 4B , that is, the portion of the first active pattern C11 located on the upper side of the second metal line M21); the adjacent pixel electrode and the associated structure may be as shown in the dotted frame in FIG. 4C , and specifically include: the adjacent first electrode D21 (as shown in the dotted frame S6 in FIG. 4C ), And the adjacent conductive portion D11 to which the adjacent first electrode D21 is connected through the second via K2 (as shown in the dotted box S7 in Figure 4C), and the adjacent first active pattern C11 to which the adjacent conductive portion D11 is connected through the first via K1 is located on the side of the second metal line M21 away from the second metal line M21 in the first direction X (as shown in the dotted box S8 in Figure 4C, that is, the portion of the first active pattern C11 located on the lower side of the second metal line M21); the composition of the first coupling capacitor Cdp1 can be as shown in Figure 4D, and the composition of the second coupling capacitor Cdp2 can be as shown in Figure 4E.

[0185] According to the research conducted by the inventors of the present application, the main reason for the difference between the first coupling capacitor Cdp1 and the second coupling capacitor Cdp2 is the asymmetry of the design of the first active pattern C11. In addition, since the film layer between the first active layer C1 and the first conductive layer D1 is relatively thin, and the first active pattern C11 and the conductive portion D11 in the first coupling capacitor Cdp1 overlap up and down (as shown in the area of ​​the thick solid frame S in FIG. 4D ), the capacitance facing each other is relatively large, while there is no such overlap in the second coupling capacitor Cdp2, thereby forming a difference between the first coupling capacitor Cdp1 and the second coupling capacitor Cdp2. (In addition, although the overlapping area between the first active pattern C11 and the first electrode D21 in the first coupling capacitor Cdp1 is larger than the overlapping area between the first active pattern C11 and the conductive portion D11, due to the presence of a thicker film layer between the first active pattern C11 and the first electrode D21, the overlapping capacitance is very small and the difference can be ignored); and since there is only one film layer between the first metal wire M11 and the conductive portion D11, the lateral capacitance formed by the first metal wire M11 and the conductive portion D11 dominates the second coupling capacitor Cdp2.

[0186] In the embodiment of the present disclosure, by making the spacing a between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 greater than the spacing b between the orthographic projection of the second sub-metal line MB on the substrate 11, the lateral capacitance between the first metal line M11 and the second conductive part DB can be increased, thereby increasing the second coupling capacitance Cdp2. Since the overlapping capacitance of the first active pattern C11 and the conductive part D11 (the area shown by the thick solid line frame S in Figure 4D) accounts for the majority of the first coupling capacitance Cdp1, the reduced spacing between the conductive part D11 and the second sub-metal line MB will not have a significant impact on the first coupling capacitance Cdp1, thereby reducing the difference between the second coupling capacitance Cdp2 and the first coupling capacitance Cdp1, thereby improving poor vertical crosstalk.

[0187] It should be noted that the spacing a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 may be the minimum spacing a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11; when the outer edge of the orthographic projection of the second conductive portion DB on the substrate 11 is partially uneven due to the manufacturing process, the spacing a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 may be the average spacing between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11; similarly, in the second conductive portion DB When the outer edge of the orthographic projection of the substrate 11 is a straight line, the spacing b between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11 may be the minimum spacing b between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11; when the outer edge of the orthographic projection of the second conductive part DB on the substrate 11 is partially uneven due to the process, the spacing b between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11 may be the average spacing between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11. The spacing a between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11, and the spacing b between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11 may be a comparison of the spacings between the second conductive part DB and the first sub-metal line MA and the second sub-metal line MB on the same straight line parallel to the second direction Y.

[0188] It should be noted that the first sub-metal line MA is electrically connected to the second part CB, which can be understood as the first sub-metal line MA is electrically connected to the second part CB through the first transistor.

[0189] In a possible embodiment, referring to FIG. 2A and FIG. 9A , the second conductive portion DB has a first outer edge w1 facing the first sub-metal wire MA, and a second outer edge w2 facing the second sub-metal wire MB; a distance a between the orthographic projection of the first outer edge w1 on the substrate 11 and the orthographic projection of the first sub-metal wiring MA on the substrate 11 is greater than a distance b between the orthographic projection of the second outer edge w2 on the substrate 11 and the orthographic projection of the second sub-metal wiring MB on the substrate 11.

[0190] In a possible embodiment, referring to FIG. 2A , the first metal wire M11 includes: a first sub-metal portion M1a and a second sub-metal portion M1b alternately arranged along a first direction X; the first sub-metal portion M1a and the second sub-metal portion M1b have different extension directions; the first conductive portion DA extends along the extension direction of the second sub-metal portion M1b, and the second conductive portion DB extends along the extension direction of the first sub-metal portion M1a; specifically, the extension direction of the first conductive portion DA is the same as the extension direction of the second sub-metal portion M1b, and the extension direction of the second conductive portion DB is the same as the extension direction of the first sub-metal portion M1a.

[0191] In a possible implementation, as shown in FIG2A and FIG9A, the first outer edge w1 is parallel to the second outer edge w2. In the disclosed embodiment, the conductive portion D11 can be shifted rightward as a whole, so as to achieve that the distance a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 is greater than the distance b between the orthographic projection of the second sub-metal wire MB on the substrate 11.

[0192] In a possible implementation manner, the second conductive portion DB, and the first sub-metal line MA, the second sub-metal line MB can satisfy the relationship: 0.05μm≤(ab) / 2≤0.15μm; in a possible implementation manner, the second conductive portion DB, and the first sub-metal line MA, the second sub-metal line MB can satisfy the relationship: 0.05μm≤(ab) / 2≤0.2μm; in a possible implementation manner, the second conductive portion DB, and the first sub-metal line MA, the second sub-metal line MB can satisfy the relationship: 0.1μm≤(ab) / 2≤0.15μm; specifically, the second conductive portion DB, and the first sub-metal line MA, the second sub-metal line MB can satisfy the relationship: 0.06μm≤(ab) / 2≤0.14μm; specifically, the second conductive portion DB, and the first sub-metal line MA, the second sub-metal line MB can satisfy the relationship: 0.07μm≤(ab) / 2≤0.13μm; specifically, the second conductive portion DB , and the first sub-metal line MA and the second sub-metal line MB can satisfy the relationship: 0.08μm≤(ab) / 2≤0.12μm; specifically, the second conductive part DB, and the first sub-metal line MA and the second sub-metal line MB can satisfy the relationship: 0.09μm≤(ab) / 2≤0.11μm; specifically, the second conductive part DB, and the first sub-metal line MA and the second sub-metal line MB can satisfy the relationship: (ab) / 2=0.1μm; in the embodiment of the present disclosure, after the second conductive part DB is shifted right by 0.1μm, the first coupling capacitance Cdp1 between the first metal line M11 and the connected pixel is 1.253Ff; the second coupling capacitance Cdp2 between the first metal line M11 and the adjacent pixel is 1.264Ff; the coupling capacitance difference between the first coupling capacitance Cdp1 and the second coupling capacitance Cdp2 is 0.87%, which can greatly reduce the coupling effect of the coupling capacitance on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0193] In a possible embodiment, the distance a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 can be in the range of 0.65μm to 0.08μm; in a possible embodiment, the distance a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 can be in the range of 0.7μm to 0.75μm.

[0194] In a possible embodiment, the spacing b between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11 may be in the range of 0.4 μm to 0.55 μm; in a possible embodiment, the spacing b between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11 may be in the range of 0.45 μm to 0.5 μm.

[0195] In a possible embodiment, the spacing range between the first sub-metal line MA and the second sub-metal line MB may be 3μm to 6μm; in a possible embodiment, the spacing range between the first sub-metal line MA and the second sub-metal line MB may be 4μm to 5μm; in a possible embodiment, the spacing range between the first sub-metal line MA and the second sub-metal line MB may be 4μμm, 4.1μμm, 4.2μμm, 4.3μμm, 4.4μμm, 4.5μμm, 4.6μμm, 4.7μμm, 4.8μμm, 4.9μμm, or 5μm.

[0196] In a possible implementation, referring to FIG. 2A and FIG. 9A , the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy the following relationship:

[0197] 15%≤i2(b) / i1(a)≤75%, wherein i1(a) represents the minimum distance between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11, and i2(b) represents the minimum distance between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11.

[0198] It should be noted that, referring to Figures 2A and 9A, when the conductive part D11 is shifted to the right as a whole, the minimum spacing i1 between the conductive part D11 and the first sub-metal wire MA is equal to the spacing a between the second conductive part DB and the first sub-metal wire MA, that is, i1=a; similarly, when the conductive part D11 is shifted to the right as a whole, the minimum spacing i2 between the conductive part D11 and the second sub-metal wire MA is equal to the spacing b between the second conductive part DB and the first sub-metal wire MA, that is, i2=b.

[0199] In a possible implementation, referring to FIG. 2A and FIG. 9A , the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy the following relationship:

[0200] 3%≤(i1-i2) / i3≤15%, wherein i3 represents the minimum distance between adjacent first sub-metal lines MA and second sub-metal lines MB.

[0201] Specifically, referring to FIG. 2A and FIG. 9A , the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be the spacing between the right edge of the first sub-metal wire MA and the left edge of the second sub-metal wire MB.

[0202] In a possible implementation, referring to FIG. 2A and FIG. 9A , the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy the following relationship:

[0203] 60%≤i4 / i3≤95%, wherein i4 represents the length of the conductive portion D11 in a direction perpendicular to the first direction X.

[0204] In a possible embodiment, referring to FIG. 2A and FIG. 9A , the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: 70% ≤ i4 / i3 ≤ 90%; in a possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: 75% ≤ i4 / i3 ≤ 85%; in a possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: 78% ≤ i4 / i3 ≤ 85%; in a possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy : i4 / i3=78%; in a possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy i4 / i3=79%; in a possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: i4 / i3=79.64%; in a possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: i4 / i3=80%; in a possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: i4 / i3=81%.

[0205] In a possible implementation, referring to FIG. 2A and FIG. 9A , the minimum spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 may be 0.35 μm to 1.15 μm; the minimum spacing i2 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 may be 0.05 μm to 0.85 μm.

[0206] In a possible implementation, referring to FIG. 2A and FIG. 9A , the minimum spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 may be 0.3 μm to 1.5 μm; the minimum spacing i2 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 may be 0.2 μm to 1 μm.

[0207] In a possible embodiment, referring to FIG. 2A and FIG. 9A , the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 2 μm to 10 μm; in a possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 4 μm to 8 μm; in a possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5 μm to 6 μm; in a possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5.1 μm, 5.2 μm, 5.3 μm, 5.4 μm, 5.5 μm, 5.6 μm, 5.7 μm, 5.8 μm, 5.8 μm or 6.0 μm; in a possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5.65 μm.

[0208] In a possible embodiment, referring to FIG. 2A and FIG. 9A , the length i4 of the conductive portion D11 in the direction perpendicular to the first direction X may be 2 μm to 8 μm; in a possible embodiment, the length i4 of the conductive portion D11 in the direction perpendicular to the first direction X may be 3 μm to 6 μm; in a possible embodiment, the length i4 of the conductive portion D11 in the direction perpendicular to the first direction X may be 4 μm to 5 μm; in a possible embodiment, the length i4 of the conductive portion D11 in the direction perpendicular to the first direction X may be 4.1 μm, 4.2 μm, 4.3 μm, 4.4 μm, 4.5 μm, 4.6 μm, 4.7 μm, 4.8 μm, 4.9 μm or 5.0 μm.

[0209] In a possible implementation, referring to FIG. 2A and FIG. 9A , the length i4 of the conductive portion D11 in the direction perpendicular to the first direction X may be 4.5 μm; and the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5.65 μm.

[0210] In a possible embodiment, referring to FIG. 5 and FIG. 9B , the second conductive portion DB has a first outer edge w1 facing the first sub-metal wire MA, and a second outer edge w2 facing the second sub-metal wire MB; an extension line of the first outer edge w1 intersects with an extension line of the second outer edge w2; a distance a between an orthographic projection of the first outer edge w1 on the substrate 11 and an orthographic projection of the first sub-metal wiring MA on the substrate 11 is greater than a distance b between an orthographic projection of the second outer edge w2 on the substrate 11 and an orthographic projection of the second sub-metal wiring MB on the substrate 11. In the disclosed embodiment, the upper end of the conductive portion D11 can be straightened, so that the distance a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 is greater than the distance b between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11; specifically, after the upper end of the conductive portion D11 is straightened, the first coupling capacitance Cdp1 between the first metal line M11 and the connected pixel is 1.187Ff; the second coupling capacitance Cdp2 between the first metal line M11 and the adjacent pixel is 1.176Ff; the coupling capacitance difference between the first coupling capacitance Cdp1 and the second coupling capacitance Cdp2 is 0.93%, which can greatly reduce the coupling effect of the coupling capacitance on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0211] In a possible embodiment, referring to FIG. 5 , the first metal wire M11 includes: a first sub-metal portion M1a and a second sub-metal portion M1b arranged alternately along a first direction; the first sub-metal portion M1a and the second sub-metal portion M1b have different extension directions; the first outer edge w1 extends along the first direction X; the second outer edge w2 extends along the extension direction of the first sub-metal portion M1a, specifically, the extension direction of the second outer edge w2 is the same as the extension direction of the first sub-metal portion M1a.

[0212] In a possible embodiment, in combination with Figures 6A, 6B, 9C, and 9D, the second conductive portion DB has a first outer edge w1 facing the first sub-metal wire MA, and a second outer edge w2 facing the second sub-metal wire MB; the first outer edge w1 includes: a first sub-edge portion w11, and a second sub-edge portion w12; the second sub-edge portion w12 is located on a side of the first sub-edge portion w11 away from the first conductive portion DA, and the second sub-edge portion w12 is located on a side of the extension line of the first sub-edge portion w11 facing the first sub-metal routing MA; a spacing a between the orthographic projection of the second sub-edge w12 on the substrate 11 and the orthographic projection of the first sub-metal routing MA on the substrate 11 is greater than a spacing b between the orthographic projection of the second outer edge w2 on the substrate 11 and the orthographic projection of the second sub-metal routing MB on the substrate. In the disclosed embodiment, the upper end of the conductive portion D11 can be retracted, thereby achieving a distance a between the orthographic projection of the second sub-edge w12 on the substrate 11 and the orthographic projection of the first sub-metal trace MA on the substrate 11, which is greater than the distance b between the orthographic projection of the second outer edge w2 on the substrate 11 and the orthographic projection of the second sub-metal trace MB on the substrate.

[0213] In a possible implementation manner, as shown in FIG. 6A and FIG. 6B , the second conductive portion DB, and the first sub-metal wire MA and the second sub-metal wire MB may satisfy the relationship: 0.3 μm ≤ ab ≤ 0.9 μm; specifically, the second conductive portion DB, and the first sub-metal wire MA and the second sub-metal wire MB may satisfy the relationship: 0.4 μm ≤ ab ≤ 0.8 μm; specifically, the second conductive portion DB, and the first sub-metal wire MA and the second sub-metal wire MB may satisfy the relationship: 0.5 μm ≤ ab ≤ 0.7 μm; specifically, the second conductive portion DB, and the first sub-metal wire MA and the second sub-metal wire MB may satisfy the relationship: 0.5 μm ≤ ab ≤ 0.7 μm; specifically, the second conductive portion DB, and the first sub-metal wire MA and the second sub-metal line MB can satisfy the relationship: ab=0.6μm; in the disclosed embodiment, after the upper end of the conductive part D11 shrinks by 0.6um, the first coupling capacitor Cdp1 between the first metal line M11 and the connected pixel is 1.185Ff; the second coupling capacitor Cdp2 between the first metal line M11 and the adjacent pixel is 1.175Ff; the coupling capacitance difference between the first coupling capacitor Cdp1 and the second coupling capacitor Cdp2 is 0.84%, which can greatly reduce the coupling effect of the coupling capacitor on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0214] In a possible embodiment, in combination with Figures 6A and 6B, the first metal line M11 includes: a first sub-metal portion M1a and a second sub-metal portion M1b arranged alternately along a first direction X; the first sub-metal portion M1a and the second sub-metal portion M1b have different extension directions; the second sub-edge w12 extends along the extension direction of the first sub-metal portion M1a, specifically, the extension direction of the second sub-edge w12 is the same as the extension direction of the first sub-metal portion M1a.

[0215] In a possible embodiment, in combination with Figures 6A and 6B, the first sub-edge w11 extends along the extension direction of the second sub-metal portion M1b; the second outer edge w21 extends along the extension direction of the first sub-metal portion M1a; specifically, the extension direction of the first sub-edge w11 is the same as the extension direction of the outer edge of the first conductive portion DA toward the first sub-metal wire MA, that is, the extension line of the outer edge of the first conductive portion DA toward the first sub-metal wire MA can be used as the first sub-edge w11; the extension direction of the second sub-edge w12 is parallel to the extension direction of the second outer edge w2.

[0216] In a possible embodiment, in combination with what is shown in FIG6C , there is a first bending portion O between the first sub-metal portion M1a and the second sub-metal portion M1b; the first outer edge w1 has a second bending portion Q; the orthographic projection of the second bending portion Q on the substrate 11 is located in the area between the orthographic projection of the first metal edge f1 on the substrate 11 and the orthographic projection of the first connecting line OO on the substrate 11, wherein the first metal edge f1 is the outer edge of the second metal wire M21 facing the first conductive portion DA, that is, the lower edge of the second metal wire M21; the first connecting line OO is the first bending portion O connecting line of two adjacent first metal wires M11.

[0217] In a possible embodiment, referring to FIG. 9C , the first metal wire M11 includes: a first sub-metal portion M1a, a second sub-metal portion M1b, and a third sub-metal portion M1c arranged alternately along a first direction X; the second sub-metal portion M1b extends along the first direction X; the first sub-metal portion M1a is located on one side of an extension line of the second sub-metal portion M1b, and the third sub-metal portion M1c is located on the other side of the extension line of the second sub-metal portion M1b; a fourth bending portion R is provided between the second sub-metal portion M1b and the third sub-metal portion M1c; the first outer edge w1 has a second bending portion Q; the orthographic projection of the second bending portion Q on the substrate 11 is located in an area between the orthographic projection of the first metal edge f1 on the substrate 11 and the orthographic projection of the second connecting line RR on the substrate 11, wherein the first metal edge f1 is the outer edge of the second metal wire M21 facing the first conductive portion DA, that is, the lower edge of the second metal wire M21; the second connecting line RR is a connecting line of the fourth bending portions R of two adjacent first metal wires M11.

[0218] In a possible embodiment, in combination with Figures 6C and 9C, the array substrate also includes: a third metal layer M3 located on the side of the first active layer C1 facing the substrate 11; the third metal layer M3 includes: a plurality of third metal wires M31 extending along the second direction Y; the orthographic projection of the third metal wire M31 on the substrate 11 covers the orthographic projection of the second metal wire M21 on the substrate; the orthographic projection of the second bend portion Q on the substrate 11 is located in the area between the orthographic projection of the first metal edge f1 on the substrate 11 and the orthographic projection of the second metal edge f2 on the substrate 11, and the second metal edge f2 is the outer edge of the third metal wire M31 on the side facing the first conductive portion DA.

[0219] In a possible implementation, as shown in combination with FIG. 6A and FIG. 6B , the first outer edge w1 has a second bend Q; the orthographic projection of the second bend Q on the substrate 11 overlaps with the orthographic projection of the first metal edge f1 on the layer substrate 11, wherein the first metal edge f1 is the outer edge of the second metal wire M21 facing the first conductive portion DA. In the disclosed embodiment, the orthographic projection of the second bend Q on the substrate 11 overlaps with the orthographic projection of the first metal edge f1 on the layer substrate 11, so that the second conductive portion DB and the first sub-metal wire MA have a large spacing, while ensuring the conductive effect of the second via K2 (conductive portion D11 and first electrode D21), and avoiding the improper position of the second bend Q, which may affect the conductive effect of the second via K2 that is conductive to the conductive portion D11 and the first electrode D21.

[0220] In a possible implementation, in combination with FIGS. 6A , 6B, 9C, and 9D, the second outer edge w2 includes a third bend portion P, and the orthographic projection of the third bend portion P on the substrate 11 may overlap with the orthographic projection of the first connecting line OO on the substrate 11 .

[0221] In a possible implementation, as shown in FIG. 2A , FIG. 5 or FIG. 6A , the first conductive portion DA is located between two adjacent first sub-metal portions M1a in the second direction Y; the second conductive portion DB is located between two adjacent second sub-metal portions M1b in the second direction Y; the extension direction of the first conductive portion DA is the same as the extension direction of the first sub-metal portion M1a. That is, in the conductive portion D11, the bending trend of the first conductive portion DA and the second conductive portion DB is consistent with the bending trend of the first metal wire M11, and the conductive portion D11 is bent accordingly at the position where the first metal wire M11 is bent.

[0222] In a possible embodiment, referring to FIG. 2A , the first electrode D21 includes: a first electrode portion DC and a second electrode portion DD distributed along a first direction X; an extension direction of the first electrode portion DC is the same as an extension direction of the first sub-metal portion M1a, and an extension direction of the second electrode portion DD is the same as an extension direction of the second sub-metal portion M1b.

[0223] It should be noted that, in FIG2A, only a portion of the second electrode portion DD is shown, and the second electrode portion DD may have more portions, but the extension direction of the remaining portions of the second electrode portion DD that are not shown may be consistent with the extension direction of the second electrode portion DD shown in the figure, and is only extended in the extension direction, which can be specifically combined with that shown in FIG8A, and the embodiments of the present disclosure are not limited to this.

[0224] In a possible implementation, as shown in FIG. 2A , the orthographic projection of the first electrode portion DC on the substrate 11 and the orthographic projection of the second conductive portion DB on the substrate 11 have an overlapping area and are electrically connected at the overlapping position.

[0225] In a possible implementation, as shown in FIG. 2A , the first conductive portion DA has a third outer edge w3 facing the first sub-metal wire MA, and a fourth outer edge w4 facing the second sub-metal wire MB; the third edge w3 is parallel to the fourth outer edge w4.

[0226] In a possible implementation, as shown in FIG. 2A , the distance c between the orthographic projection of the third outer edge w3 on the substrate 11 and the orthographic projection of the first sub-metal wiring MA on the substrate 11 is greater than the distance d between the orthographic projection of the fourth outer edge w4 on the substrate 11 and the orthographic projection of the second sub-metal wiring MB on the substrate 11. That is, the conductive portion D11 can be shifted right as a whole to achieve a distance a between the second conductive portion DB and the first sub-metal wiring MA that is greater than the distance b between the second conductive portion DB and the second sub-metal wiring MB.

[0227] In a possible implementation, as shown in FIG6A , the spacing c between the orthographic projection of the third outer edge w3 on the substrate 11 and the orthographic projection of the first sub-metal routing MA on the substrate 11 is equal to the spacing d between the orthographic projection of the fourth outer edge w4 on the substrate 11 and the orthographic projection of the second sub-metal routing MB on the substrate 11.

[0228] In a possible implementation, as shown in FIG. 6A , the first outer edge w1 , the second outer edge w2 , and the third outer edge w4 satisfy the following relationship:

[0229] a>c>b, where c represents the distance between the orthographic projection of the third outer edge w3 on the substrate and the orthographic projection of the first sub-metal line MA on the substrate. That is, based on the overall offset, the bending point Q moves upward, further increasing the distance between the first sub-metal line MA and the conductive portion D11.

[0230] In a possible implementation, as shown in FIG. 2A , the second conductive portion DB has a fifth outer edge w5 extending along the second direction Y, and the fifth outer edge w5 is located on a side of the second metal line M21 away from the first conductive portion DA.

[0231] In a possible implementation, as shown in FIG. 7 , the second conductive portion DB has a fifth outer edge w5 extending along the second direction Y, and the orthographic projection of the second metal line M21 on the substrate covers the orthographic projection of the fifth outer edge w5 on the substrate. In the disclosed embodiment, by making the upper end of the second conductive portion DB retracted to the second metal line M21, the positive capacitance generated by the upper and lower overlap of the first active pattern C11 and the conductive portion D11 in the first coupling capacitor Cdp1 (such as the area shown by the thick solid line frame S in FIG. 4D ) can be reduced or eliminated, thereby reducing the first coupling capacitor Cdp1, reducing the coupling capacitance difference between the first coupling capacitor Cdp1 and the second coupling capacitor Cdp2, and reducing the coupling effect of the coupling capacitor on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0232] In the disclosed embodiment, after the upper end of the second conductive portion DB is retracted into the second metal line M21, the first coupling capacitor Cdp1 between the first metal line M11 and the connected pixel is 1.259Ff; the second coupling capacitor Cdp2 between the first metal line M11 and the adjacent pixel is 1.136Ff; the coupling capacitance difference between the first coupling capacitor Cdp1 and the second coupling capacitor Cdp2 is 9.77%, which can greatly reduce the coupling effect of the coupling capacitor on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0233] In a possible implementation, as shown in FIG. 7 , the second metal line M21 has a sixth outer edge w6 extending along the second direction Y; the orthographic projection of a portion of the sixth outer edge w6 on the substrate 11 coincides with the orthographic projection of the fifth outer edge w5 on the substrate 11 .

[0234] In a possible implementation, as shown in FIG. 8A , the second portion CB includes: a first sub-portion CB1 and a second sub-portion CB2; the first sub-portion CB1 extends along the second direction Y, and the orthographic projection of the first sub-portion CB1 on the substrate 11 overlaps with the orthographic projection of the first metal line M11 on the substrate 11; the second sub-portion CB2 connects the first sub-portion CB1 and the first portion CA; the plurality of first active patterns C11 include: a first active pattern row C100 and a second active pattern row C200; the first active pattern row C100 and the second active pattern row C200 extend along the second direction Y and are arranged in an overlapping manner along the first direction X;

[0235] The first active pattern row C100 and the second active pattern row C200 both include a plurality of first active patterns C11; and in the first active pattern row C100, the second sub-portion CB2 extends along the third direction Z1; in the second active pattern row C200, the second sub-portion CB2 extends along the fourth direction Z2, and the third direction Z1 intersects the fourth direction Z2. Specifically, in the two adjacent first sub-metal lines MA and the second sub-metal line MB on both sides of the conductive portion D11, the second sub-portion CB2 of the first active pattern row C100 may be located in the first direction X and biased toward one side of the first sub-metal line MA, and the second sub-portion CB2 of the second active pattern row C200 may be located in the first direction X and biased toward one side of the second sub-metal line MB.

[0236] In the embodiment implemented in FIG8A, by making the first active pattern C11 of adjacent rows a structure of mirror design of upper and lower rows, dark pixel rows and bright pixel rows can be alternately distributed. If the pixels in the odd-numbered rows are bright, the pixels in the even-numbered rows are dark. The brightness difference between the upper and lower rows of pixels is neutralized, and the coupling effect of the coupling capacitor on the first metal line M11 is reduced, thereby avoiding the occurrence of vertical crosstalk. Specifically, in the odd-numbered pixel rows, the first coupling capacitor Cdp1 between the first metal line M11 and the connected pixels is 1.192Ff, and in the odd-numbered pixel rows, the first metal line M11 is 0.192Ff. The second coupling capacitance Cdp2 between M11 and the adjacent pixel is 1.301Ff; in the even pixel rows, the first coupling capacitance Cdp1 between the first metal line M11 and the connected pixel is 1.312Ff, and in the even pixel rows, the second coupling capacitance Cdp2 between the first metal line M11 and the adjacent pixel is 1.177Ff; in the odd rows, the pixel second coupling capacitance Cdp2> the first coupling capacitance Cdp1, and in the even pixel rows, the first coupling capacitance Cdp1> the second coupling capacitance Cdp2, and the brightness difference between the upper and lower rows of pixels is neutralized.

[0237] In a possible implementation manner, the third direction Z1 and the fourth direction Z2 are located on different sides of the first direction X.

[0238] In a possible implementation manner, the angle formed between the third direction Z1 and the first direction X is in a range of 10° to 80°; in a possible implementation manner, the angle formed between the third direction Z1 and the first direction X is in a range of 20° to 70°; in a possible implementation manner, the angle formed between the third direction Z1 and the first direction X is in a range of 30° to 60°; in a possible implementation manner, the angle formed between the third direction Z1 and the first direction X is in a range of 40° to 50°.

[0239] In a possible implementation manner, the angle formed between the fourth direction Z2 and the first direction X is in a range of 10° to 80°; in a possible implementation manner, the angle formed between the fourth direction Z2 and the first direction X is in a range of 20° to 70°; in a possible implementation manner, the angle formed between the fourth direction Z2 and the first direction X is in a range of 30° to 60°; in a possible implementation manner, the angle formed between the fourth direction Z2 and the first direction X is in a range of 40° to 50°.

[0240] In a possible implementation, as shown in FIG. 8A , in the first active pattern row C100 , the first sub-portion CB1 and the first portion CA are located on different sides of the second sub-portion CB2 ; in the second active pattern row C200 , the first sub-portion CB1 and the first portion CA are located on the same side of the second sub-portion CB2 .

[0241] In a possible implementation, in combination with Figures 2A and 3, the first conductive layer D1 is located on the side of the first active layer C1 away from the substrate 11; the array substrate also includes: a first insulating layer F1 located between the first active layer C1 and the first conductive layer D1, and a first via hole K1 penetrating the first insulating layer F1, and the conductive portion D11 is electrically connected to the first portion CA through the first via hole K1.

[0242] In a possible embodiment, in combination with Figures 2A and 3, the first electrode D21 is located on the side of the first conductive layer D1 away from the substrate 11; the array substrate also includes: a second insulating layer F2 located between the first conductive layer D1 and the first electrode D21, and a second via K2 penetrating the second insulating layer F2; the first electrode D21 is electrically connected to the K2 conductive portion D11 through the second via hole.

[0243] In a possible implementation manner, the first insulating layer F1 includes one or a combination of the following:

[0244] A first gate insulating layer 15;

[0245] A first interlayer dielectric layer 16;

[0246] The second interlayer dielectric layer 17 .

[0247] Specifically, as shown in FIG. 3 , the first interlayer dielectric layer 16 may be located on a side of the first gate insulating layer 15 away from the substrate 11 ; the second interlayer dielectric layer 17 may be located on a side of the first interlayer dielectric layer 16 away from the substrate 11 .

[0248] In a possible implementation, as shown in FIG. 3 , the first insulating layer F1 includes: a first gate insulating layer 15 , a first interlayer dielectric layer 16 , and a second interlayer dielectric layer 17 .

[0249] In a possible implementation, in combination with FIG. 2A and FIG. 3 , the array substrate further includes: a third via hole K3 penetrating the first interlayer dielectric layer 16 and the second interlayer dielectric layer 17 , and the first metal line M11 is electrically connected to the second portion CB of the first active pattern C11 through the third via hole K3 .

[0250] In a possible implementation, as shown in FIG. 2A , the orthographic projection of the third metal wire M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11; specifically, the orthographic projection of the second metal wire M21 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11. In a possible implementation, the orthographic projection of the second via K2 on the substrate 11 is located at the overlapping region of the first electrode D21 and the conductive portion D11 on the substrate 11, so that the first electrode D21 is electrically connected to the conductive portion D11 at the overlapping region through the second via K2.

[0251] The orthographic projection of the first metal wire M11 on the substrate 11 covers the orthographic projection of the third via K3 on the substrate 11. In a possible implementation, the orthographic projection of the first via K1 on the substrate 11 is located at an overlapping region of the orthographic projections of the first portion CA of the first active pattern C11 and the conductive portion D11 on the substrate 11, so that the first portion CA is electrically connected to the conductive portion D11 at the overlapping region through the first via K1.

[0252] In a possible implementation, the orthographic projection of the first metal line M11 on the substrate 11 covers the orthographic projection of the third via K3 on the substrate 11. Specifically, the orthographic projection of the third via K3 on the substrate 11 is located at the overlapping region of the orthographic projections of the first metal line M11 and the second portion CB of the first active pattern C11 on the substrate 11, so that the first metal line M11 is electrically connected to the second portion CB of the first active pattern C11 through the third via K3.

[0253] In a possible implementation manner, the orthographic projections of the first via K1 and the second via K2 on the substrate 11 are both located between the orthographic projections of the first sub-metal wire MA and the second sub-metal wire MB on the substrate 11. In a possible implementation manner, the orthographic projections of the first via K1 and the second via K2 on the substrate 11 have a gap in the first direction X.

[0254] In a specific implementation, the thickness of the first insulating layer F1 between the first active layer C1 and the first conductive layer D1 can be adjusted by adjusting at least one or a combination of the first gate insulating layer 15, the first interlayer dielectric layer 16, and the second interlayer dielectric layer 17, and the conductive portion D11 can be moved rightward and / or the second metal trace M21 can be moved upward, so as to achieve accurate capacitance difference control and reduce the second coupling capacitor C dp2 With the first coupling capacitor C dp1 difference.

[0255] In a possible implementation manner, as shown in FIG. 3 , the thickness of at least one of the first gate insulating layer 15 , the first interlayer dielectric layer 16 , and the second interlayer dielectric layer 17 is greater than

[0256] In a possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0257] In a possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0258] In a possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2With the first coupling capacitor C dp1 difference.

[0259] In a possible implementation, the third metal line M31 may be used to shield at least a portion of the first active pattern C11 of the first transistor to prevent the first active pattern C11 from being illuminated by ambient light and affecting the characteristics of the first transistor.

[0260] In a possible implementation, as shown in FIG2A , the orthographic projection of the third metal wire M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11. In the disclosed embodiment, the orthographic projection of the third metal wire M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11, that is, the third metal wire M31 of the array substrate is used to cover the second via K2, which can reduce the risk of light leakage from the second via K2 on the array substrate.

[0261] In a possible implementation, as shown in FIG. 8B , the distance g1 between the two ends of the first sub-metal portion M1a in the second direction Y is equal to the distance g2 between the two ends of the second sub-metal portion M1b in the second direction Y; the second direction Y is perpendicular to the first direction X. That is, the offset amount of the two ends of the first sub-metal portion M1a to the right in the second direction Y is equal to the offset amount of the two ends of the second sub-metal portion M1b to the left in the second direction Y, so that the first metal line M11 generally maintains extension along the first direction Y in the first direction X.

[0262] In a possible implementation, referring to FIG. 9A-FIG 9C, the first metal line M11 includes: a first sub-metal portion M1a, a second sub-metal portion M1b, and a third sub-metal portion M1c arranged alternately along a first direction X; the second sub-metal portion M1b extends along the first direction X; the first sub-metal portion M1a is located on one side of an extension line of the second sub-metal portion M1b, and the third sub-metal portion M1c is located on the other side of the extension line of the second sub-metal portion M1b. In the disclosed embodiment, for a 2P2D pixel structure, the first metal line M11 is bent (the extension directions of the first metal line M11 portions corresponding to the upper and lower rows of pixel electrodes intersect), and the offsets of the first metal line M11 portions corresponding to the upper and lower rows of pixel electrodes are equal (the offsets of the first metal line M11 in the second direction Y are offset), and the middle portion (the second sub-metal portion M1b) is vertical to avoid the occurrence of an oblique channel in the first active pattern.

[0263] In a possible implementation, as shown in FIG. 9E , a distance g3 between two ends of the first sub-metal portion M1a in the second direction Y is equal to a distance g4 between two ends of the third sub-metal portion M1c in the second direction Y.

[0264] In a possible implementation, referring to FIG. 9A , the first active layer C1 includes: a third active pattern row C300, and a fourth active pattern row C400; the third active pattern row C300 and the fourth active pattern row C400 extend along the second direction Y and are arranged overlappingly along the first direction X; the third active pattern row C300 and the fourth active pattern row C400 each include a plurality of first active patterns C11; in the same third active pattern row C300, each first active pattern C11 is electrically connected to the first metal line M11 on the same side; in the same fourth active pattern row C400, each first active pattern C11 is electrically connected to the first metal line M11 on the same side; between two adjacent first metal lines M11, the first active pattern C11 of the third active pattern row C300 and the first active pattern C11 of the fourth active pattern row C400 are electrically connected to different first metal lines M11.

[0265] In a possible embodiment, referring to FIG. 9A , the first portion CA extends along the first direction X, and the second portion CB is located on one side of the extension line of the first portion CA; in the third active pattern row C300, the first portion CA and the second portion CB intersect to form an opening at a first angle α1, and the first sub-metal portion M1a and the second sub-metal portion M1b intersect to form an opening at a second angle α2, that is, the deflection direction of the second portion CB relative to the first portion CA is opposite to the deflection direction of the first sub-metal portion M1a relative to the second sub-metal portion M1b; in the fourth active pattern row C400, the first portion CA and the second portion CB intersect to form an opening at a first angle α1, and the third sub-metal portion M1c and the next second sub-metal portion M1b in the first direction X intersect to form an opening at a third angle α3, that is, the deflection direction of the second portion CB relative to the first portion CA is opposite to the deflection direction of the third sub-metal portion M1a relative to the next second sub-metal portion M1b in the first direction X. That is, in combination with what is shown in FIG. 9A , for example, in the third active pattern row C300, the second portion CB is deflected to the left relative to the first portion CA, and the first sub-metal portion M1a is deflected to the right relative to the second sub-metal portion M1b, and the two deflection directions are opposite; in the fourth active pattern row C400, the second portion CB is deflected to the right relative to the first portion CA, and the third sub-metal portion M1c is deflected to the left relative to the next second sub-metal portion M1b in the first direction X, and the two deflection directions are opposite.

[0266] In a possible implementation, referring to FIG. 9A to FIG. 9C , since between two adjacent first metal lines M11, the first active pattern C11 of the third active pattern row C300 and the first active pattern C11 of the fourth active pattern row C400 are electrically connected to different first metal lines M11, the same first metal line M11 can be used as the first sub-metal line MA in the area where the third active pattern row C300 is located, and can be used as the second sub-metal line MB in the area where the fourth active pattern row C400 is located. Accordingly, for FIG. 9A , the second conductive part DB is realized by moving the conductive part D11. When the spacing a between the orthographic projection of the first sub-metal line MA on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 is greater than the spacing b between the orthographic projection of the second sub-metal line MB on the substrate 11, corresponding to the entire display panel, all the conductive parts D11 in one conductive part row may move in one direction as a whole, while all the conductive parts D11 in the adjacent conductive part row may move in another direction as a whole. For example, as shown in FIG9A , the conductive parts D11 in the first conductive part row from top to bottom all move to the right, while the conductive parts D11 in the second conductive part row all move to the left. Similarly, in combination with FIG9B , by straightening the upper end of the conductive part D11, the orthographic projection of the second conductive part DB on the substrate 11 is achieved. When the spacing a between the orthographic projection of the first sub-metal line MA on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11 is greater than the spacing b between the orthographic projection of the second sub-metal line MB on the substrate 11, corresponding to the entire display panel, all the conductive parts D11 in one conductive part row may move in one direction as a whole. 9B , the conductive portions D11 in the first conductive portion row from top to bottom are all straightened on the left side, while the conductive portions D11 in the second conductive portion row are all straightened on the right side; similarly, in combination with FIG9C , by retracting one end of the conductive portion D11, it is achieved that the spacing a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 is greater than the spacing b between the orthographic projection of the second sub-metal wire MB on the substrate 11, then, corresponding to the entire display panel, all the conductive portions D11 in one conductive portion row may be retracted on the same side, while all the conductive portions D11 in adjacent conductive portion rows may be retracted on the other side, for example, as shown in FIG9C , the conductive portions D11 in the first conductive portion row from top to bottom are all retracted on the left side, while the conductive portions D11 in the second conductive portion row are all retracted on the right side.

[0267] In a possible implementation, referring to FIG. 9F , the first portion CA extends along the first direction X, and the second portion CB is located on one side of the extension line of the first portion CA; in the third active pattern row C300, the first portion CA and the second portion CB intersect to form an opening with a first angle α1, and the first sub-metal portion M1a and the second sub-metal portion M1b intersect to form an opening with a second angle α2 facing the same side; in the fourth active pattern row C400, the first portion CA and the second portion CB intersect to form an opening with a first angle α1, and the first sub-metal portion M1a and the second sub-metal portion M1b intersect to form an opening with a second angle α2 facing the same side. The openings of the third angle α3 formed by the intersection of the part M1c and the next second sub-metal part M1b in the first direction X are facing the same side, that is, in the third active pattern row C300, the deflection direction of the second part CB relative to the first part CA is the same as the deflection direction of the first sub-metal part M1a relative to the second sub-metal part M1b; in the fourth active pattern row C400, the deflection direction of the second part CB relative to the first part CA is the same as the deflection direction of the third sub-metal part M1a relative to the next second sub-metal part M1b in the first direction X. That is, in combination with what is shown in FIG. 9F , for example, in the third active pattern row C300, the second portion CB is deflected to the right relative to the first portion CA, and the first sub-metal portion M1a is deflected to the right relative to the second sub-metal portion M1b, and the two have the same deflection direction; in the fourth active pattern row C400, the second portion CB is deflected to the left relative to the first portion CA, and the third sub-metal portion M1c is deflected to the left relative to the next second sub-metal portion M1b in the first direction X, and the two have the same deflection direction.

[0268] In a possible embodiment, referring to FIG. 9G and FIG. 9H , the plurality of first active patterns C11 include: a plurality of active pattern rows CA0; the active pattern row CA0 includes: a plurality of first active patterns C11 arranged sequentially along the second direction Y; in the same active pattern row CA0, each first active pattern C11 is electrically connected to the first metal line M11 on the same side; between two adjacent first metal lines M11, the first active patterns C11 of the active pattern row CA0 are electrically connected to the same first metal line M11.

[0269] In a possible embodiment, referring to FIG. 9I , the array substrate includes: a first via K1, a second via K2, and a third via K3; the first active pattern C11 is electrically connected to the conductive portion D11 through the first via K1; the conductive portion D11 is electrically connected to the first electrode D21 through the second via K2; the first active pattern C11 is electrically connected to the first metal wire M11 through the third via K3; the second conductive layer D2 includes: a plurality of first electrode rows D200 extending along the second direction Y and arranged sequentially along the first direction X; the first electrode row D200 includes: a plurality of first electrodes D21 arranged sequentially along the first direction X; the orthographic projection of the first active pattern C11 electrically connected to the first electrode D21 of the Mth row through the first via K1 and the second via K2 on the substrate 1 overlaps with the orthographic projection of the first electrode D21 of the M-1th row on the substrate 1. That is, in the embodiment of the present disclosure, the first active pattern C11 electrically connected to the first electrode D21 in the Mth row may be the first electrode row 200 located in the M-1th row.

[0270] In a possible implementation, as shown in FIG9I , the extension direction of a portion of the first electrode D21 is the same as the extension direction of the second sub-metal portion M1b, and the extension direction of another portion of the first electrode D21 is the same as the extension direction of the third sub-metal portion M1c. That is, the first electrode D21 is bent corresponding to the bending direction of the first metal wire M11.

[0271] In a possible implementation, referring to FIGS. 9A to 9H , the orthographic projection of the first active pattern C11 electrically connected to the first electrode D21 of the Mth row through the first via K1 and the second via K2 on the substrate 1 may also overlap with the orthographic projection of the first electrode D21 of the Mth row on the substrate 1. That is, the first active pattern C11 electrically connected to the first electrode D21 of the Mth row may also be in the first electrode row D200.

[0272] In a possible implementation, in combination with Figures 2A, 3, and 11, the array substrate also includes: a second insulating layer F2 located between the first conductive layer D1 and the second conductive layer D2; the second insulating layer F2 has a second via hole K2; and the first electrode D21 is electrically connected to the conductive portion D11 through the second via hole K2.

[0273] In a possible implementation, as shown in FIG. 10A , at least two adjacent second via holes K2 are an integrated connected structure in a direction perpendicular to the first direction X. In the disclosed embodiment, because the second insulating layer F2 is thicker, in order to ensure that the first electrode D21 is well electrically connected to the conductive portion D11, the second via hole K2 of the second insulating layer F can be changed to a groove, that is, at least two adjacent second via holes K2 are an integrated connected structure.

[0274] In one possible implementation, the second via holes K2 of three sub-pixels may be an integrated connected structure; in another possible implementation, all second via holes K2 perpendicular to the second direction X may be an integrated connected structure, that is, the second via holes K2 corresponding to a row of sub-pixels may be an integrated connected structure.

[0275] In a possible implementation, the second via hole K2 has two side walls extending perpendicular to the first direction X; at least one side wall is wavy or sawtooth-shaped. In the disclosed embodiment, on the basis of trenching, the side wall of the groove is set to be wavy or sawtooth-shaped to avoid photoresist residue in the groove, resulting in short circuit of the first electrode D21 of adjacent sub-pixels. The wavy / sawtooth-shaped protruding edge can be set on the side facing the first electrode D21, or on both sides of the groove.

[0276] In a possible implementation, in combination with Figures 10B, 10C, 10D, 10E, and 12H, Figure 10E may be a cross-sectional schematic diagram at the dotted line A0 in Figure 10D, when the second via K2 is an integrally connected structure, that is, a plurality of second vias K2 are connected in the second direction Y to form a groove, and the second via K2 has two side walls extending perpendicular to the first direction X; at least one side wall has a protruding structure K20, and the orthographic projection of the protruding structure K20 on the substrate is located in the area between the orthographic projections of two adjacent first electrodes D21 on the substrate in the second direction Y; the orthographic projection of the protruding structure K20 on the first plane overlaps with the orthographic projection of the first electrode D21 on the first plane, and the first plane is parallel to the first direction X and perpendicular to the substrate. It can be understood that compared with the side walls of other areas, the side walls of the protruding structure K20 have a longer slope, which separates the first electrodes D21 on the adjacent two sides, thereby avoiding the problem of short-circuiting the first electrode D21 due to photoresist residue during the exposure process of preparing the first electrode D21.

[0277] In a possible implementation, in combination with Figures 10B and 10C, a side wall of the second via K2 may have a protruding structure K20. For example, the first electrode D21 in Figure 10B extends toward the third via K3 (that is, the first electrode D21 is in the row where the third via K3 is located), so the protruding structure K20 is arranged on the side of the side wall of the second via K2 close to the third via K3; for another example, the first electrode D21 in Figure 10C extends toward the first via K1 (that is, the first electrode D21 is in the next row of the third via K3), so the protruding structure K20 is arranged on the side wall of the second via K2 close to K1; in a possible implementation, in combination with Figures 10D and 12H, both side walls of the second via K2 may have a protruding structure K20, and the first electrode D21 extends to the side walls on both sides.

[0278] In one possible embodiment, the protruding structure K20 may be a structure that is recessed toward one side of the inside of the second via hole K2; in another possible embodiment, the protruding structure K20 may also be a structure that is protruding toward the outside of K2; in one possible embodiment, the orthographic projection shape of the protruding structure K20 on the substrate may be a triangle, a trapezoid, a semicircle, or an ellipse.

[0279] In a possible implementation, as shown in FIG. 11 , the array substrate further includes: a color resist layer located between the second insulating layer F2 and the second conductive layer D2; the color resist layer includes: a plurality of color resist portions 102; the orthographic projection of at least part of the color resist portion 102 on the substrate 1 overlaps with the orthographic projection of the first metal line M11 on the substrate 1. In the embodiment of the present disclosure, when the array substrate is provided with a color resist layer, because there is an additional layer of the color resist layer, the distance between the first electrode D21 and the first metal line M11 increases, that is, in Cdp, the capacitance of the first electrode D21 facing and the side of the first metal line M11 will be further reduced; if the conductive portion D11 exceeds the second metal line M21 (gate line) and overlaps with the source conductor portion of the first active pattern C11, the Cdp1 caused by this portion will be more obviously larger, so it is more necessary to balance the coupling capacitance by offsetting the transfer electrode and other methods provided in the embodiment of the present disclosure. Moreover, when the array substrate is provided with a color resist layer, the film thickness between the first electrode D21 and the first metal wire M11 increases, and at least two adjacent second via holes K2 are an integrated connected structure, so that the first electrode D21 and the conductive portion D11 can be well electrically connected.

[0280] In a possible embodiment, referring to FIG. 11 , the array substrate further includes: the first electrode D21 may include a first sub-electrode D211 and a second sub-electrode D212; the first sub-electrode D211 is partially located at the bottom of the second via hole K2, partially located at the side wall of the second via hole K2, and partially extended to the surface of the second insulating layer F2 facing away from the substrate 1; the second sub-electrode D212 is located at the side of the first sub-electrode D211 facing away from the substrate 1, and is in direct contact with the portion of the first sub-electrode D211 extended to the surface of the second insulating layer F2 facing away from the substrate 1.

[0281] In a possible implementation, as shown in FIG. 11 , the array substrate further includes: a filling portion 101 filled in the second via hole K2 to achieve planarization at the first electrode D21 .

[0282] In a possible embodiment, referring to FIG. 11 , the array substrate further includes: a passivation layer 19 located on the side of the second conductive layer D2 facing away from the substrate 1, a fourth metal layer M4 located on the side of the passivation layer 19 facing away from the substrate 1, and a third conductive layer D3 located on the side of the fourth metal layer M4 facing away from the substrate 1, wherein the fourth metal layer M4 may include a plurality of light-shielding portions M40, and the third conductive layer D3 may be a common electrode layer; the third conductive layer may be in direct contact with the fourth metal layer M4 to reduce the resistance of the common electrode layer through the fourth metal layer M4.

[0283] In a possible implementation manner, as shown in FIG. 11 , the array substrate further includes: a first spacer PS on a side of the passivation layer 19 facing away from the substrate 1 .

[0284] 12A-12G, 13 and 14A, wherein FIG. 12B is a schematic diagram of a single film layer of the third metal layer in FIG. 12A, FIG. 12C is a schematic diagram of a single film layer of the first active layer in FIG. 12A, FIG. 12D is a schematic diagram of a single film layer of the second metal layer in FIG. 12A, FIG. 12E is a schematic diagram of a single film layer of the first metal layer in FIG. 12A, FIG. 12F is a schematic diagram of a single film layer of the first conductive layer in FIG. 12A, FIG. 12G is a schematic diagram of a single film layer of the second conductive layer in FIG. 12A, FIG. 13 is a schematic diagram of a cross-section at a dotted line A1A2 in FIG. 12A, and FIG. 14A is a schematic diagram of only a portion of the film layers in FIG. 12A. An embodiment of the present disclosure provides an array substrate having a display area AA, and a non-display area BB located outside the display area AA, wherein the array substrate comprises:

[0285] Substrate 11;

[0286] The first active layer C1 is located on one side of the substrate 11 and includes: a plurality of first active patterns C11 located in the display area AA; the first active pattern C11 includes: a first portion CA extending along the first direction X, and a second portion CB extending from one end of the first portion CA;

[0287] The first metal layer M1 includes: a plurality of first metal lines M11 extending along a first direction X; an orthographic projection of a first portion CA on a substrate 11 is located between orthographic projections of adjacent first metal lines M11 on the substrate; a portion of an orthographic projection of a second portion CB on the substrate 11 overlaps with a portion of an orthographic projection of the first metal line M11 on the substrate 11; specifically, the first metal line M11 may be a data line; specifically, the display area AA may have a plurality of first transistors, and a position where the second portion CB overlaps with the first metal line M11 may serve as a first electrode of the first transistor; and the second portion CB may be turned on at a position where it overlaps with the first metal line M11 to achieve electrical connection between the first transistor and the data line;

[0288] The first conductive layer D1 includes: a plurality of conductive parts D11 located in the display area AA; the orthographic projection of at least one of the plurality of conductive parts D11 on the substrate 11 is located between the orthographic projections of adjacent first metal lines M11 on the substrate 11; specifically, the first conductive layer D1 may be a transparent conductive layer, and the conductive part D11 may serve as the second electrode of the first transistor to conduct the first active pattern C11 with the first electrode D21; specifically, the orthographic projection shape of the conductive part D11 on the substrate 11 may be a rectangle, and the length of the conductive part D11 in the first direction X may be greater than the length in the second direction Y; specifically, the length of the conductive part D11 in the first direction X may also be equal to the length in the second direction Y;

[0289] The second conductive layer D2 includes: a plurality of first electrodes D21 located in the display area AA; specifically, the second conductive layer D2 may be a transparent conductive layer, and the material of the second conductive layer D2 may be the same as the material of the first conductive layer D1; specifically, the first electrode D21 may be a pixel electrode; specifically, the orthographic projection of the first electrode D21 on the substrate 11 may be located between the orthographic projections of adjacent first metal lines M11 on the substrate 11; specifically, the orthographic projection shape of the first electrode D21 on the substrate 11 may be a rectangle; the length of the first electrode D21 in the first direction X is greater than the length in the second direction Y;

[0290] Among them, the first metal wire M11 on the two adjacent sides of the conductive part D11 includes: a first sub-metal wire MA, and a second sub-metal wire MB; wherein the first sub-metal wire MA is electrically connected to the second part CB, that is, the first metal wire M11 electrically connected to the second part CB is used as the first type of metal wire MA; the first part CA is electrically connected to the first electrode D21 through the conductive part D11; the orthographic projection of the conductive part D11 on the substrate 11, and the spacing i1 between the orthographic projection of the first sub-metal wire MA on the substrate 11 are greater than the spacing i2 between the orthographic projection of the second sub-metal wire MB on the substrate 11.

[0291] The first metal line M11 and its associated structure, together with its own pixel electrode and its associated structure, can form a first coupling capacitor C dp1 The first metal line M11 and its associated structure can form a second coupling capacitor C with the adjacent pixel electrode and its associated structure. dp2; Wherein, the pixel electrode itself and the associated structure may be the area shown in the dotted box in FIG. 15A, and may specifically include: the first electrode D21 (as shown in the dotted box S1 in FIG. 15A), and the conductive portion D11 connected to the first electrode D21 through the second via K2 (as shown in the dotted box S2 in FIG. 15A), and the portion of the first active pattern C11 connected to the conductive portion D11 through the first via K1, which is located on the side of the second metal line M21 away from the second metal line M21 in the first direction X (as shown in the dotted box S3 in FIG. 15A, that is, the portion of the first active pattern C11 located on the lower side of the second metal line M21. Since the time when each row of pixels is turned on is very short within one frame of display, it can be considered that the gate of the first transistor in the pixel is closed for most of the time, and the portion of the first active pattern C11 covered by the second metal line M21 can be considered as an insulator); the first metal line M11 and the associated structure may be the area shown in the dotted box in FIG. 15B, and may specifically include: the first metal line M11 (as shown in FIG. 1 15B), and a portion of the first active pattern C11 electrically connected to the first metal line M11 through the third via K3, located on the side of the second metal line M21 close to the second metal line M21 in the first direction X (as shown in the dotted frame S5 in FIG. 15B, that is, the portion of the first active pattern C11 located on the upper side of the second metal line M21); the adjacent pixel electrodes and associated structures may be the area shown in the dotted frame in FIG. 15C, and may specifically include: an adjacent first electrode D21 (as shown in the dotted frame S6 in FIG. 15C), and an adjacent conductive portion D11 connected to the adjacent first electrode D21 through the second via K2 (as shown in the dotted frame S7 in FIG. 15C), and a portion of the adjacent first active pattern C11 connected to the adjacent conductive portion D11 through the first via K1, located on the side of the second metal line M21 away from the second metal line M21 in the first direction X (as shown in the dotted frame S8 in FIG. 15C, that is, the portion of the first active pattern C11 located on the lower side of the second metal line M21); the first coupling capacitor C dp1 The structure can be shown in FIG. 15D, where the second coupling capacitor C dp2 The composition may be as shown in FIG. 15E ;

[0292] After research by the inventor of this application, the first coupling capacitor C dp1 The second coupling capacitor C dp2 The main reason for the difference is the asymmetry of the design of the first active pattern C11, and the thin film between the first active layer C1 and the first conductive layer D1, and the first coupling capacitor C dp1 The first active pattern C11 in the conductive portion D11 overlaps with the conductive portion D11 (as shown in the area of ​​the thick solid frame S in FIG. 15D ), and the positive capacitance is larger, while the second coupling capacitor C dp2 There is no overlap in the first coupling capacitor C dp1 The second coupling capacitor Cdp2 The main part of the difference (in addition, although the first coupling capacitor C dp1 In the figure, the overlapping area of ​​the first active pattern C11 and the first electrode D21 is larger than the overlapping area of ​​the first active pattern C11 and the conductive portion D11, but since there is a thicker film layer between the first active pattern C11 and the first electrode D21, the overlapping capacitance is very small and the difference can be ignored); and since there is only one film layer between the first metal wire M11 and the conductive portion D11, the lateral capacitance formed by the first metal wire M11 and the conductive portion D11 is greater than the second coupling capacitor C dp2 Dominant in the middle.

[0293] In the embodiment of the present disclosure, the distance i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 is greater than the distance i2 between the orthographic projection of the second sub-metal line MB on the substrate 11, which can increase the lateral capacitance between the first metal line M11 and the conductive portion D11, thereby increasing the second coupling capacitance C dp2 , and due to the first coupling capacitor C dp1 In the embodiment, the overlap capacitance between the first active pattern C11 and the conductive portion D11 (the area shown by the thick solid frame S in FIG. 15D ) accounts for the main part, and the distance between the conductive portion D11 and the second sub-metal line MB is reduced, which will not affect the first coupling capacitor C dp1 This has a significant impact, thereby reducing the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference, thereby improving the vertical crosstalk problem.

[0294] It should be noted that, when the outer edge of the orthographic projection of the conductive portion D11 on the substrate 11 is linear, the spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 may be the minimum spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11; when the outer edge of the orthographic projection of the conductive portion D11 on the substrate 11 is non-linear (for example, due to process manufacturing, the edge has some unevenness) or when the orthographic projection of the conductive portion D11 on the substrate 11 is non-rectangular, the spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 may be the average spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11. similarly, when the outer edge of the orthographic projection of the conductive portion D11 on the substrate 11 is linear, the spacing i2 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 may be the minimum spacing i2 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11; when the outer edge of the orthographic projection of the conductive portion D11 on the substrate 11 is non-linear (for example, due to process manufacturing, the edge has some unevenness) or when the orthographic projection of the conductive portion D11 on the substrate 11 is non-rectangular, the spacing i2 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 may be the average spacing between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11.

[0295] It should be noted that the first sub-metal wire MA is electrically connected to the second part CB, which can be understood as the first sub-metal wire MA is electrically connected to the second part CB through the first transistor; when the orthographic projection shape of the conductive part D11 on the substrate 11 is a rectangle, the minimum spacing i1 between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 can be the spacing between the left edge of the conductive part D11 and the right edge of the first sub-metal wire MA; the minimum spacing i2 between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 can be the spacing between the right edge of the conductive part D11 and the left edge of the second sub-metal wire MB.

[0296] In a possible implementation, in combination with FIG. 12A or FIG. 14A , the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy the following relationship:

[0297] 15%≤i2 / i1≤75%, wherein i1 represents the minimum distance between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11, and i2 represents the minimum distance between the orthographic projection of the conductive part D11 on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11.

[0298] In a possible implementation, in combination with FIG. 12A or FIG. 14A , the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy the following relationship:

[0299] 3%≤(i1-i2) / i3≤15%, wherein i3 represents the minimum distance between adjacent first sub-metal lines MA and second sub-metal lines MB.

[0300] Specifically, as shown in FIG. 14A , the minimum spacing i3 between adjacent first sub-metal lines MA and second sub-metal lines MB may be the spacing between the right edge of the first sub-metal line MA and the left edge of the second sub-metal line MB.

[0301] In a possible implementation, in combination with FIG. 12A or FIG. 14A , the conductive portion D11 , the first sub-metal wire MA, and the second sub-metal wire MB satisfy the following relationship:

[0302] 60%≤i4 / i3≤95%, wherein i4 represents the length of the conductive portion D11 in a direction perpendicular to the first direction X.

[0303] In a possible implementation manner, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: 70%≤i4 / i3≤90%; in a possible implementation manner, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: 75%≤i4 / i3≤85%; in a possible implementation manner, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: 78%≤i4 / i3≤85%; in a possible implementation manner, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: i4 / i3 =78%; in a possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy i4 / i3=79%; in a possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: i4 / i3=79.64%; in a possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: i4 / i3=80%; in a possible embodiment, the conductive portion D11, the first sub-metal wire MA, and the second sub-metal wire MB satisfy: i4 / i3=81%.

[0304] In a possible implementation, the minimum spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 can be 0.35 μm to 1.15 μm; the minimum spacing i2 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11 can be 0.05 μm to 0.85 μm.

[0305] In a possible implementation, the minimum spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal wire MA on the substrate 11 may be 0.3 μm to 1.5 μm; the minimum spacing i2 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the second sub-metal wire MB on the substrate 11 may be 0.2 μm to 1 μm.

[0306] In a possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 2μm to 10μm; in a possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 4μm to 8μm; in a possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5μm to 6μm; in a possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5.1μm, 5.2μm, 5.3μm, 5.4μm, 5.5μm, 5.6μm, 5.7μm, 5.8μm, 5.8μm or 6.0μm; in a possible embodiment, the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB may be 5.65μm.

[0307] In a possible embodiment, the length i4 of the conductive portion D11 perpendicular to the first direction X may be 2μm to 8μm; in a possible embodiment, the length i4 of the conductive portion D11 perpendicular to the first direction X may be 3μm to 6μm; in a possible embodiment, the length i4 of the conductive portion D11 perpendicular to the first direction X may be 4μm to 5μm; in a possible embodiment, the length i4 of the conductive portion D11 perpendicular to the first direction X may be 4.1μm, 4.2μm, 4.3μm, 4.4μm, 4.5μm, 4.6μm, 4.7μm, 4.8μm, 4.9μm or 5.0μm.

[0308] In a possible implementation, a length i4 of the conductive portion D11 in a direction perpendicular to the first direction X may be 4.5 μm; and a minimum interval i3 between adjacent first sub-metal lines MA and second sub-metal lines MB may be 5.65 μm.

[0309] In a possible embodiment, in combination with Figures 12A, 12C and 12F, the first portion CA has a first symmetry axis e1 extending along the first direction X, and the first portion CA is symmetrical about the first symmetry axis e1; the conductive portion D11 has a second symmetry axis e2 extending along the first direction X, and the conductive portion D11 is symmetrical about the second symmetry axis e2; the second symmetry axis e2 is located on the side of the first symmetry axis e1 away from the first sub-metal wire MA.

[0310] In a possible implementation, in combination with Figures 12A, 12F and 12G, the first electrode D21 has a seventh outer edge j1 extending along the first direction X; between two adjacent first metal wires M11, the portion of the seventh outer edge j1 that is projected directly onto the substrate 11 is located on the side of the first portion CA that is projected directly onto the substrate 11 away from the first sub-metal wire MA; specifically, as shown in Figure 12F, the seventh outer edge j1 may be the right edge of the first electrode D21; the conductive portion D11 has an eighth outer edge j2 extending along the first direction X; between two adjacent first metal wires M11, the portion of the eighth outer edge j2 that is projected directly onto the substrate 11 is located on the side of the first portion CA that is projected directly onto the substrate 11 away from the first sub-metal wire MA; specifically, as shown in Figure 12G, the eighth outer edge j2 may be the right edge of the conductive portion D11; between two adjacent first metal wires M11, the portion of the eighth outer edge j2 that is projected directly onto the substrate 11 is located on the side of the seventh outer edge j1 that is away from the first sub-metal wire MA.

[0311] In a possible implementation, in combination with Figures 12A, 12F and 12G, the first electrode D21 has a ninth outer edge j3 extending along the first direction X; between two adjacent first metal wires M11, the ninth outer edge j3 is located at the part of the positive projection of the substrate 11, and is located on the side of the positive projection of the first portion CA on the substrate 11 close to the first sub-metal wire MA; specifically, as shown in Figure 12F, the ninth outer edge j3 may be the left edge of the first electrode D21; the conductive portion D11 has a tenth outer edge j4 extending along the first direction X; between two adjacent first metal wires M11, the tenth outer edge j4 is located at the part of the positive projection of the substrate 11, and is located on the side of the positive projection of the first portion CA on the substrate 11 close to the first sub-metal wire MA; specifically, as shown in Figure 12G, the tenth outer edge j4 may be the left edge of the conductive portion D11; between two adjacent first metal wires M11, the tenth outer edge j4 is located at the part of the positive projection of the substrate 11, and is located on the side of the positive projection of the ninth outer edge j3 on the substrate 11 away from the first sub-metal wire MA. In the embodiment of the present disclosure, the conductive portion D11 is moved away from the first sub-metal line MA to increase the second coupling capacitor C dp2 , thereby reducing the second coupling capacitance C dp2 With the first coupling capacitor C dp1difference, thereby improving the vertical crosstalk problem.

[0312] In a specific implementation, as shown in FIG. 12A , the conductive portion D11 may be moved to a side away from the first sub-metal line MA, thereby increasing the second coupling capacitor C dp2 In another possible implementation, as shown in FIG. 16 , the conductive portion D11 may not be moved, but the edge of the conductive portion D11 away from the first sub-metal line MA may be moved toward the side away from the first sub-metal line MA, that is, the width of D11 along the second direction Y is increased, and the orthographic projection of the conductive portion D11 on the substrate 11 is reduced, and the minimum spacing i2 between the orthographic projection of the conductive portion D11 and the second sub-metal line MB on the substrate 11 is reduced, which can also achieve the purpose of increasing the second coupling capacitor C. dp2 .

[0313] Specifically, as shown in FIG16 , the first electrode D21 has a ninth outer edge j3 extending along the first direction X; between two adjacent first metal wires M11, the portion of the ninth outer edge j3 at the orthographic projection of the substrate 11 is located on the side of the orthographic projection of the first portion CA at the substrate 11 close to the first sub-metal wire MA; specifically, as shown in FIG16 , the ninth outer edge j3 may be the left edge of the first electrode D21; the conductive portion D11 has a tenth outer edge j4 extending along the first direction X; between two adjacent first metal wires M11, the portion of the tenth outer edge j4 at the orthographic projection of the substrate 11 is located on the side of the orthographic projection of the first portion CA at the substrate 11 close to the first sub-metal wire MA; specifically, as shown in FIG16 , the tenth outer edge j4 may be the left edge of the conductive portion D11; between two adjacent first metal wires M11, the portion of the ninth outer edge j3 at the orthographic projection of the substrate 11 coincides with the portion of the orthographic projection of the tenth outer edge j4 at the substrate 11. In the embodiment of the present disclosure, the second coupling capacitor C is increased by moving the conductive portion D11 away from the edge of the first sub-metal line MA and away from the first sub-metal line MA. dp2 , thereby reducing the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference, thereby improving the vertical crosstalk problem.

[0314] It should be noted that, in order to clearly illustrate the positional relationship of the various structures of the embodiments of the present disclosure, Figures 12A to 19 are used to mark and illustrate the edges and positional relationship between the first electrode D21 of the second row and the conductive part D11, the first active pattern C11, the first sub-metal line MA, and the second sub-metal line MB. In a specific implementation, the first electrode D21 of each row and the conductive part D11, the first active pattern C11, the first sub-metal line MA, and the second sub-metal line MB corresponding to the current row also satisfy the relevant edge and positional relationships, but the embodiments of the present disclosure are not limited to this.

[0315] In addition, it should be noted that, for example, in FIG. 12G , the second row of first electrodes D21 from top to bottom only illustrates part of the complete first electrode D21 due to the limitation of the illustration range, and the complete pattern of the first electrode D21 can be as shown in the first row of first electrodes D21 from top to bottom, and the embodiments of the present disclosure are not limited to this.

[0316] In a possible embodiment, in combination with Figures 2A and 14B, one end of the conductive portion D11 is electrically connected to the first portion CA, and the other end extends toward the side of the second metal line M21 and exceeds the second metal line M21 to form a protrusion S, and the orthographic projection of the protrusion S on the substrate overlaps with the orthographic projection of the first active pattern C11 on the substrate.

[0317] In a possible implementation, as shown in FIG. 12C and FIG. 14B , the array substrate further includes: a second metal layer M2 located between the first active layer C1 and the first conductive layer D1 , the second metal layer M2 including: a plurality of second metal wires M21 extending along the second direction Y;

[0318] The first portion CA includes: a first sub-portion CA1, a second sub-portion CA2, and a third sub-portion CA3 sequentially distributed along the first direction X; wherein the orthographic projection of the second sub-portion CA2 on the substrate overlaps with the orthographic projection of the second metal line M21 on the substrate 11; the first sub-portion CA1 is located on the side of the second sub-portion CA2 facing the second portion CB, and the third sub-portion CA3 is located on the side of the second sub-portion CA2 away from the second portion CB; that is, the portion of the first portion CA overlapping with the projection of the second metal line M21 is taken as the second sub-portion CA2;

[0319] The orthographic projection of the first sub-portion CA1 on the substrate 11 has an overlapping area with the orthographic projection of the conductive portion D11 on the substrate 11. Specifically, the orthographic projection of the first sub-portion CA1 on the substrate 11 has an overlapping area with the orthographic projection of the conductive portion D11 on the substrate 11, as shown in the thick solid line frame S in FIG. 14B.

[0320] In a possible implementation, in combination with FIG. 12A, FIG. 13, FIG. 17A and FIG. 18, wherein FIG. 18 is a schematic diagram of the stacking of some film layers in FIG. 17A, the array substrate further includes: a second metal layer M2 located between the first active layer C1 and the first conductive layer D1, the second metal layer M2 including: a plurality of second metal wires M21 extending along the second direction Y; the second portion CB including: a fourth sub-portion CB1 connected to the first portion CA and extending along the third direction, and a fifth sub-portion CB2 connected to the fourth sub-portion CB1, the first metal wire M11 being electrically connected to the fifth sub-portion CB2; the second direction Y intersects the first direction X, and the third direction Z intersects with the first direction X; the conductive portion D11 includes: an eleventh outer edge j5 extending along the second direction Y and toward the fifth sub-portion CB2, specifically, as shown in FIG17A, the eleventh outer edge j5 can be the upper edge of the conductive portion D11; the second metal wire M21 has a twelfth outer edge j6 extending along the second direction Y and toward the fifth sub-portion CB2, specifically, as shown in FIG17A, the twelfth outer edge j6 can be the upper edge of the second metal wire M21; the orthographic projection of the twelfth outer edge j6 on the substrate 11 is located on the side of the orthographic projection of the eleventh outer edge j5 on the substrate 11 facing the orthographic projection of the fifth sub-portion CB2 on the substrate 11.

[0321] In the embodiment of the present disclosure, the second metal line M21 has a twelfth outer edge j6 extending along the second direction Y and toward the fifth sub-portion CB2, that is, the second metal line M21 is moved up (after the second metal line M21 is moved up, the first coupling capacitor C dp1 The structure can be shown in FIG. 17B, where the second coupling capacitor C dp2 The structure can be as shown in FIG. 17C ), the second metal line M21 can shield the overlap capacitance between the first active pattern C11 and the conductive portion D11 (that is, it can shield the capacitance of the area shown by the thick solid line frame S in FIG. 15D ), thereby reducing the first coupling capacitance C dp1 The overlap capacitance accounts for a large proportion in the first coupling capacitance C dp1 The second metal line M21 moves upward, and the lateral capacitance between the first metal line M11 and the conductive portion D11 (constituting the second coupling capacitor C dp2 The main part of the second coupling capacitor C dp2 With the first coupling capacitor C dp1 The difference can be reduced to improve the vertical crosstalk problem.

[0322] Specifically, the second metal line M21 may be a gate line.

[0323] Specifically, the second direction Y may be perpendicular to the first direction X; the angle formed by the third direction Z and the first direction X may be 0 to 90°; specifically, the angle formed by the third direction Z and the first direction X may be 30 to 60°; specifically, the angle formed by the third direction Z and the first direction X may be 45°.

[0324] In a possible implementation, as shown in FIG. 12A , FIG. 12C , FIG. 12F , and FIG. 12G , the length g1 of the orthographic projection of the first electrode D21 on the substrate 11 along the second direction Y may be equal to the length g2 of the orthographic projection of the conductive portion D11 on the substrate 11 along the second direction Y. The length g1 of the orthographic projection of the first electrode D21 on the substrate 11 along the second direction Y may be less than the minimum spacing i3 between adjacent first sub-metal wires MA and second sub-metal wires MB. In a possible implementation, as shown in FIG. 12A , FIG. 12C , FIG. 12F , and FIG. 12G , the length g4 of the orthographic projection of the first electrode D21 on the substrate 11 along the first direction X may be greater than the length g5 of the orthographic projection of the conductive portion D11 on the substrate 11 along the first direction X. In a possible embodiment, in combination with Figures 12A, 12C, 12F and 12G, the length g5 of the orthographic projection of the conductive portion D11 on the substrate 11 along the first direction X may be one-fifth to four-fifths of the length g4 of the orthographic projection of the first electrode D21 on the substrate 11 along the first direction X; in a possible embodiment, the length g5 of the orthographic projection of the conductive portion D11 on the substrate 11 along the first direction X may be one-half of the length g4 of the orthographic projection of the first electrode D21 on the substrate 11 along the first direction X.

[0325] In a possible implementation, as shown in FIG. 12A , the orthographic projection of the conductive portion D11 on the substrate 11 may cover the orthographic projection of the gap between two adjacent first electrodes D21 on the substrate 11 in the first direction X. In a possible implementation, as shown in FIG. 12A , the overlapping area of ​​the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first electrode D21 on the substrate 11 may account for one-fifth to four-fifths of the orthographic projection area of ​​the conductive portion D11 on the substrate 11; in a possible implementation, as shown in FIG. 12A , the overlapping area of ​​the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first electrode D21 on the substrate 11 may account for one-third of the orthographic projection area of ​​the conductive portion D11 on the substrate 11.

[0326] In a possible implementation, in combination with Figures 12A, 12C, 12F and 12G, the distance g6 between two adjacent first electrodes D21 in the first direction X may be one-fifth to four-fifths of the length g5 of the orthographic projection of the conductive portion D11 on the substrate 11 in the first direction X; in a possible implementation, in combination with Figures 12A, 12C, 12F and 12G, the distance g6 between two adjacent first electrodes D21 in the first direction X may be one-third of the length g5 of the orthographic projection of the conductive portion D11 on the substrate 11 in the first direction X.

[0327] In a possible embodiment, as shown in Figures 12A, 12C, 12F and 12G, the maximum length g3 of the orthographic projection of the first portion CA1 of the first active pattern C11 on the substrate 11 along the second direction Y may be smaller than the length g2 of the orthographic projection of the conductive portion D11 on the substrate 11 along the second direction Y.

[0328] In a possible embodiment, in combination with FIG. 12C , the maximum length g7 of the orthographic projection of the first portion CA1 of the first active pattern C11 on the substrate 11 along the first direction X may be one third to three thirds of the maximum length g8 of the orthographic projection of the first portion CA1 of the first active pattern C11 on the substrate 11 along the first direction X; in a possible embodiment, in combination with FIG. 12C , the maximum length g7 of the orthographic projection of the first portion CA1 of the first active pattern C11 on the substrate 11 along the first direction X may be one half of the maximum length g8 of the orthographic projection of the first portion CA1 of the first active pattern C11 on the substrate 11 along the first direction X.

[0329] In a possible implementation, in combination with FIG. 12C , a maximum length g9 of the orthographic projection of the fourth sub-portion CB1 of the first active pattern C11 on the substrate 11 along the first direction X may be one-third to three-thirds of a maximum length g10 of the orthographic projection of the second portion CB of the first active pattern C11 on the substrate 11 along the first direction X; in a possible implementation, in combination with FIG. 12C , a maximum length g9 of the orthographic projection of the fourth sub-portion CB1 of the first active pattern C11 on the substrate 11 along the first direction X may be one-half of a maximum length g10 of the orthographic projection of the second portion CB of the first active pattern C11 on the substrate 11 along the first direction X; a maximum length g11 of the orthographic projection of the fifth sub-portion CB2 of the first active pattern C11 on the substrate 11 along the first direction X may be one-half of a maximum length g10 of the orthographic projection of the second portion CB of the first active pattern C11 on the substrate 11 along the first direction X.

[0330] In a possible embodiment, in combination with FIG. 12C , a maximum length g12 of the orthographic projection of the fifth sub-portion CB2 of the first active pattern C11 on the substrate 11 along the second direction Y may be equal to a maximum length g3 of the orthographic projection of the first portion CA of the first active pattern C11 on the substrate 11 along the second direction Y; in a possible embodiment, in combination with FIG. 12C , a maximum length g12 of the orthographic projection of the fifth sub-portion CB2 of the first active pattern C11 on the substrate 11 along the second direction Y may be greater than a length g13 of the orthographic projection of the fourth sub-portion CB1 of the first active pattern C11 on the substrate 11 along the second direction Y.

[0331] In a possible embodiment, in combination with Figures 17A and 18, the spacing d1 between the orthographic projection of the twelfth outer edge j6 on the substrate 11 and the orthographic projection of the eleventh outer edge j5 on the substrate 11 in the first direction X is one-fifth to four-fifths of the length d2 of the orthographic projection of the second metal wire M21 on the substrate 11 in the first direction X.

[0332] In a possible implementation, as shown in FIG17A and FIG18 , the orthographic projection of the second metal line M21 on the substrate 11 covers the orthographic projection of the eleventh outer edge j5 on the substrate 11. That is, the maximum upward movement of the second metal line M21 does not exceed the upper edge of the conductive portion D11.

[0333] In a possible implementation manner, a distance d1 between an orthographic projection of the twelfth outer edge j6 on the substrate 11 and an orthographic projection of the eleventh outer edge j5 on the substrate 11 in the first direction X is 1 μm to 3 μm. In a possible implementation manner, a distance d1 between an orthographic projection of the twelfth outer edge j6 on the substrate 11 and an orthographic projection of the eleventh outer edge j5 on the substrate 11 in the first direction X is 1.5 μm.

[0334] In a specific implementation, as shown in FIG. 12A , the second coupling capacitor C may be reduced by only making the minimum spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 greater than the minimum spacing i2 between the orthographic projection of the conductive portion D11 and the second sub-metal line MB on the substrate 11 (i.e., the conductive portion D11 is shifted to the right). dp2 With the first coupling capacitor C dp1 17A and 18, the second coupling capacitance C can be reduced by only making the positive projection of the twelfth outer edge j6 on the substrate 11 located on the side where the positive projection of the eleventh outer edge j5 on the substrate 11 faces the positive projection of the fifth sub-portion CB2 on the substrate 11 (that is, moving the second metal line M21 upward). dp2 With the first coupling capacitor C dp119, the orthographic projection of the conductive portion D11 on the substrate 11 and the minimum spacing i1 of the orthographic projection of the first sub-metal wire MA on the substrate 11 are made greater than the minimum spacing i2 of the orthographic projection of the second sub-metal wire MB on the substrate 11 (that is, the conductive portion D11 is moved to the right), and at the same time, the orthographic projection of the twelfth outer edge j6 on the substrate 11 is located on the side of the orthographic projection of the eleventh outer edge j5 on the substrate 11 toward the orthographic projection of the fifth sub-portion CB2 on the substrate 11 (that is, the second metal wire M21 is moved up), so as to reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0335] In a possible implementation, as shown in FIG. 12A and FIG. 13 , the first conductive layer D1 is located on the side of the first active layer C1 away from the substrate 11; the array substrate further includes: a first insulating layer F1 located between the first active layer C1 and the first conductive layer D1, and a first via K1 penetrating the first insulating layer F1, the conductive portion D11 is electrically connected to the first portion CA through the first via K1; between two adjacent first metal wires M11, the first via K1 is at the center O1 of the orthographic projection of the substrate 11, and the minimum spacing d3 between the first via K1 and the first sub-metal wire MA on the orthographic projection of the substrate 11 is greater than the minimum spacing d4 between the first via K1 and the second sub-metal wire MB on the orthographic projection of the substrate 11. In the embodiment of the present disclosure, when the conductive portion D11 is moved to the right, the first via K1 that conducts the conductive portion D11 and the first active pattern C11 is also moved to the right, so as to avoid affecting the conduction effect between the conductive portion D11 and the first active pattern C11 when the conductive portion D11 is moved to the right but the first via K1 is not moved to the right.

[0336] In a possible implementation, as shown in FIG. 12A and FIG. 13 , the first electrode D21 is located on a side of the first conductive layer D1 away from the substrate 11; the array substrate further includes: a second insulating layer F2 located between the first conductive layer D1 and the first electrode D21, and a second via K2 penetrating the second insulating layer F2; the first electrode D21 is electrically connected to the K2 conductive portion D11 through the second via; between two adjacent first metal wires M11, the second via K2 is at the center O2 of the orthographic projection of the substrate 11, and the minimum spacing d5 between the second via K2 and the first sub-metal wire MA on the orthographic projection of the substrate 11 is greater than the minimum spacing d6 between the second sub-metal wire MB on the orthographic projection of the substrate 11. In the disclosed embodiment, when the conductive portion D11 is moved to the right, the second via K2 that conducts the first electrode D21 and the conductive portion D11 is also moved to the right, so as to avoid affecting the conduction effect between the first electrode D21 and the conductive portion D11 when the conductive portion D11 is moved to the right but the second via K2 is not moved to the right.

[0337] In a possible implementation, at least a portion of the orthographic projection of the first via K1 on the substrate 11 does not overlap with at least a portion of the orthographic projection of the second via K2 on the substrate 11. In a possible implementation, in combination with FIG. 12A and FIG. 13 , the entire orthographic projection of the first via K1 on the substrate 11 does not overlap with the entire orthographic projection of the second via K2 on the substrate 11.

[0338] In a possible implementation manner, the first insulating layer F1 includes one or a combination of the following:

[0339] A first gate insulating layer 15;

[0340] A first interlayer dielectric layer 16;

[0341] The second interlayer dielectric layer 17 .

[0342] Specifically, as shown in FIG. 13 , the first interlayer dielectric layer 16 may be located on a side of the first gate insulating layer 15 away from the substrate 11 ; the second interlayer dielectric layer 17 may be located on a side of the first interlayer dielectric layer 16 away from the substrate 11 .

[0343] In a possible implementation, as shown in FIG. 13 , the first insulating layer F1 includes: a first gate insulating layer 15 , a first interlayer dielectric layer 16 , and a second interlayer dielectric layer 17 .

[0344] In a possible implementation, in combination with FIG. 2A and FIG. 13 , the array substrate further includes: a third via hole K3 penetrating the first interlayer dielectric layer 16 and the second interlayer dielectric layer 17 , and the first metal line M11 is electrically connected to the second portion CB of the first active pattern C11 through the third via hole K3 .

[0345] In a possible implementation, as shown in FIG. 12A , the orthographic projection of the third metal wire M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11; specifically, the orthographic projection of the second metal wire M21 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11. In a possible implementation, the orthographic projection of the second via K2 on the substrate 11 is located at the overlapping region of the first electrode D21 and the conductive portion D11 on the substrate 11, so that the first electrode D21 is electrically connected to the conductive portion D11 at the overlapping region through the second via K2.

[0346] In a possible implementation, the orthographic projection of the third metal line M31 on the substrate 11 covers the orthographic projection of the first via K1 on the substrate 11. The orthographic projection of the first metal line M11 on the substrate 11 covers the orthographic projection of the third via K3 on the substrate 11. In a possible implementation, the orthographic projection of the first via K1 on the substrate 11 is located at the overlapping region of the orthographic projection of the first portion CA of the first active pattern C11 and the conductive portion D11 on the substrate 11, so as to realize the electrical connection of the first portion CA and the conductive portion D11 at the overlapping region through the first via K1.

[0347] In a possible implementation, the orthographic projection of the first metal line M11 on the substrate 11 covers the orthographic projection of the third via K3 on the substrate 11. Specifically, the orthographic projection of the third via K3 on the substrate 11 is located at the overlapping area of ​​the orthographic projections of the first metal line M11 and the second portion CB of the first active pattern C11 on the substrate 11, so that the first metal line M11 is electrically connected to the second portion CB of the first active pattern C11 through the third via K3.

[0348] In a possible implementation, the orthographic projections of the first via K1 and the second via K2 on the substrate 11 are both located between the orthographic projections of the first sub-metal wire MA and the second sub-metal wire MB on the substrate 11. In a possible implementation, the orthographic projections of the first via K1 and the second via K2 on the substrate 11 have a gap in the first direction X. Specifically, the length of the gap between the first via K1 and the second via K2 in the first direction X may be one quarter to three quarters of the length of the conductive portion D11 in the first direction X.

[0349] In a possible embodiment, the third via K3 has a third via symmetry axis e3 extending along the second direction Y; the first electrode D21 has a first electrode outer edge j7 extending along the second direction Y and facing the side of the electrically connected conductive portion D11; the distance between the third via symmetry axis e3 and the first electrode outer edge j7 in the first direction X may be one quarter to three quarters of the length of the first electrode D21 along the first direction X; in a possible embodiment, the distance between the third via symmetry axis e3 and the first electrode outer edge j7 in the first direction X may be one half of the length of the first electrode D21 along the first direction X, and the third via symmetry axis e3 is located at a position where the length of the first electrode D21 along the first direction X is half.

[0350] In a specific implementation, the thickness of the first insulating layer F1 between the first active layer C1 and the first conductive layer D1 can be adjusted by adjusting at least one or a combination of the first gate insulating layer 15, the first interlayer dielectric layer 16, and the second interlayer dielectric layer 17, and the conductive portion D11 can be moved rightward and / or the second metal trace M21 can be moved upward, so as to achieve accurate capacitance difference control and reduce the second coupling capacitor C dp2 With the first coupling capacitor C dp1 difference.

[0351] In a possible implementation manner, as shown in FIG. 13 , the thickness of at least one of the first gate insulating layer 15 , the first interlayer dielectric layer 16 , and the second interlayer dielectric layer 17 is greater than

[0352] In a possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0353] In a possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0354] In a possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference.

[0355] In a possible implementation, as shown in FIG13, the array substrate further includes: a third metal layer M3 located on the side of the first active layer C1 facing the substrate 11; the third metal layer M3 includes: a plurality of third metal wires M31 extending along the second direction Y, and the orthographic projection of the third metal wires M31 on the substrate 11 covers the orthographic projection of the second metal wires M21 on the substrate 11. Specifically, the third metal wires M31 can be used to shield at least part of the first active pattern C11 of the first transistor to prevent the external ambient light from affecting the illumination of the first active pattern C11 and affecting the characteristics of the first transistor.

[0356] In a possible implementation, as shown in FIG. 12A , the orthographic projection of the third metal line M31 on the substrate 11 may cover the orthographic projection of the gap between two adjacent first electrodes D21 in the first direction X on the substrate 11. In a possible implementation, as shown in FIG. 12A , the orthographic projection of the third metal line M31 on the substrate 11 may cover the orthographic projection of the first portion CA of the first active pattern C11 on the substrate 11, and the orthographic projection of the fourth sub-portion CB1 of the first active pattern C11 on the substrate 11. The orthographic projection of the third metal line M31 on the substrate 11 may cover the orthographic projection of the conductive portion D11 on the substrate 11.

[0357] In a possible implementation, as shown in FIG. 12A , the orthographic projection of the third metal wire M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11. In the disclosed embodiment, the orthographic projection of the third metal wire M31 on the substrate 11 covers the orthographic projection of the second via K2 on the substrate 11, that is, the third metal wire M31 of the array substrate is used to cover the second via K2, which can reduce the risk of light leakage from the second via K2 on the array substrate.

[0358] Since virtual reality (VR) headsets are near-eye displays, and the images displayed on the LCD screen need to be magnified many times by the imaging system before they can enter the human eye, even if the current VR display resolution has reached more than 1000PPI, the screen door effect caused by the shading structure can still be seen in the display of the entire device. In view of this, in a possible implementation, referring to FIG. 20A, FIG. 20B and FIG. 20C, wherein FIG. 20B may be a single film layer schematic diagram of the third metal wire M31 in FIG. 20A, FIG. 20B may also be a local schematic diagram at the dotted frame J1 in FIG. 20C, and FIG. 20C may be a schematic diagram of a larger range of FIG. 20B, the array substrate includes: a plurality of pixel light-transmitting areas P, the plurality of pixel light-transmitting areas P include: a plurality of pixel light-transmitting area rows H extending along a first direction X and arranged along a second direction Y; at least one pixel light-transmitting area row H of the plurality of pixel light-transmitting area rows H includes: a first pixel light-transmitting area P1, a second pixel light-transmitting area P2, and a third pixel light-transmitting area P3; the light band range emitted by the third pixel light-transmitting area P3 is smaller than the light band range emitted by the first pixel light-transmitting area P1 , and a light band range smaller than that of the second pixel light-transmitting area P2; specifically, the first pixel light-transmitting area P1 can be a pixel light-transmitting area emitting red light, the second pixel light-transmitting area P2 can be a pixel light-transmitting area emitting green light, and the third pixel light-transmitting area P3 can be a pixel light-transmitting area emitting blue light; the third metal wire M31 includes: a third metal wire main portion M310 extending along the second direction Y, and a first shielding structure Z1 connected to the third metal wire main portion M310; the maximum length h1 of the first shielding structure Z1 in the first direction X is greater than the maximum length h3 of the third metal wire main portion M310 in the first direction X; the orthographic projection of the first shielding structure Z1 on the substrate 11 is located in the gap between the orthographic projections of at least partially adjacent two third pixel light-transmitting areas P3 on the substrate 11 in the first direction X.

[0359] Specifically, the array substrate further includes: a spacer (not shown in the figure, and specifically, the orthographic projection shape and position on the substrate 11 can be as shown in FIG. 20C, that is, the orthographic projection shape of the spacer on the substrate 11 can be an octagon, and can be located in the gap between the orthographic projections of at least two adjacent third pixel light-transmitting areas P3 on the substrate 11 in the first direction X); the orthographic projection of the first shielding structure Z1 on the substrate 11 covers the orthographic projection of the spacer on the substrate 11. That is, the orthographic projection of the spacer on the substrate 11 is located in the gap between the orthographic projections of at least two adjacent third pixel light-transmitting areas P3 on the substrate 11 in the first direction X.

[0360] In the disclosed embodiment, spacers are placed in the gaps between light-transmitting areas of adjacent blue pixels, which effectively reduces the human eye's sensitivity to compensation of obstructions (such as a black matrix) at the position of the spacers (blue pixels have lower brightness than green and red pixels, so placing spacers in the gaps between light-transmitting areas of adjacent blue pixels will give the human eye a smaller visual difference in light and dark than placing them on green and red pixels).

[0361] In a possible embodiment, referring to Figures 20A, 20B and 20C, the third metal wire M31 also includes: a second shielding structure Z2 connected to the third metal wire main portion M310; the maximum length h2 of the second shielding structure Z2 in the first direction X is greater than the maximum length h3 of the third metal wire main portion M310 in the first direction X, and less than the maximum length h1 of the first shielding structure Z1 in the first direction X; the orthographic projection of the second shielding structure Z1 on the substrate 11 is located in the gap between the orthographic projections of two adjacent third pixel light-transmitting areas P3 on the substrate 11 in the second direction Y, and the orthographic projection of the second shielding structure Z2 on the substrate 11 does not overlap with the orthographic projection of the first shielding structure Z1 on the substrate 11.

[0362] In the disclosed embodiment, the orthographic projection of the second shielding structure Z1 on the substrate 11 is located in the gap between the orthographic projections of two adjacent third pixel light-transmitting areas P3 on the substrate 11 in the second direction Y, and the orthographic projection of the second shielding structure Z2 on the substrate 11 does not overlap with the orthographic projection of the first shielding structure Z1 on the substrate 11, that is, the second shielding structure Z1 can be set at a position without spacers between adjacent blue pixels, which reduces the brightness difference between the positions of the blue pixels with spacers and without spacers, and makes the brightness more evenly distributed in the entire pixel area, thereby reducing the screen window effect and improving the visual effect.

[0363] In a possible implementation, a length m3 of the third pixel light-transmitting area P3 in the first direction X is smaller than a length m1 of the first pixel light-transmitting area P1 in the first direction X, and smaller than a length m2 of the second pixel light-transmitting area P2 in the first direction X.

[0364] Specifically, the pixel light-transmitting area P can be understood as the effective display area of ​​the pixel, which can be an area in the pixel area that is not blocked by a blocking structure (such as a shading layer, a gate line, a data line, a black matrix, etc.). Specifically, in a possible implementation, as shown in FIG. 20C , the pixel light-transmitting area P can be a white area.

[0365] In a possible implementation, the length m1 of the first pixel light-transmitting area P1 in the first direction X is equal to the length m2 of the second pixel light-transmitting area P2 in the first direction X. In the disclosed embodiment, the second shielding structure Z2 is set by setting the length m3 of the third pixel light-transmitting area P3 in the first direction X to be shorter, and the third pixel light-transmitting area P3 with a smaller light-emitting band range has a lower brightness than the first pixel light-transmitting area P1 and the second pixel light-transmitting area P2 with a longer light-emitting band range, which can effectively reduce the sensitivity of the human eye to the second shielding structure Z2, and can reduce the brightness difference between the position with spacers and the position without spacers between the third pixel light-transmitting area P3, so that the brightness is more evenly distributed in the entire pixel area, thereby reducing the screen window effect and improving the visual effect.

[0366] In the disclosed embodiment, the spacers can be placed at the gap between the light-transmitting areas of adjacent blue pixels, which effectively reduces the human eye's sensitivity to compensation of the shielding objects (such as black matrix) at the spacer position (the blue pixel has lower brightness than the green pixel and the red pixel, so placing the spacers at the gap between the light-transmitting areas of adjacent blue pixels will bring a smaller visual difference of light and dark to the human eye than placing them on the green pixel and the red pixel). In addition, the second shielding structure Z2 can be set at the position without spacers between adjacent blue pixels, which reduces the brightness difference between the position with spacers and the position without spacers of the blue pixels, making the brightness distribution in the entire pixel area more uniform, thereby reducing the screen door effect and improving the visual effect.

[0367] In a possible implementation, the wavelength range of light emitted by the third pixel light-transmitting area P3 may also be greater than the wavelength range of light emitted by the first pixel light-transmitting area P1, and greater than the wavelength range of light emitted by the second pixel light-transmitting area P2. Specifically, the third pixel light-transmitting area P3 may be a red pixel light-transmitting area, the first pixel light-transmitting area P1 may be a blue pixel light-transmitting area, and the second pixel light-transmitting area P2 may be a green pixel light-transmitting area. That is, the second shielding structure Z2 may be provided in at least part of the gap between two adjacent red pixel light-transmitting areas, and a spacer may be placed in the gap between two adjacent red pixel light-transmitting areas.

[0368] In a possible implementation, as shown in FIG20C , the orthographic projections of the first shielding structure Z1 and the second shielding structure Z2 on the substrate 11 are alternately distributed along the first direction X. Specifically, the first shielding structure Z1 and the second shielding structure Z2 may be located in the same column upward, such as both located in the column where the third pixel light-transmitting area P3 is located.

[0369] In a possible embodiment, the orthographic projection shape of the first shielding structure Z1 on the substrate 11 may be the same as the orthographic projection shape of the spacer on the substrate 11. For example, the orthographic projection shape of the spacer on the substrate 11 may be a hexagon, an octagon, a circle, or an ellipse; the orthographic projection shape of the first shielding structure Z1 on the substrate 11 may also be a hexagon, an octagon, a circle, or an ellipse.

[0370] Specifically, the orthographic projection shape of the second shielding structure Z2 on the substrate 11 may be a rectangle. The maximum length of the second shielding structure Z2 in the first direction X may be greater than the maximum length in the second direction Y.

[0371] Specifically, the ratio of the maximum length h2 of the second shielding structure Z2 in the first direction X to the maximum length h1 of the first shielding structure Z1 in the first direction X is greater than or equal to 0.78.

[0372] Specifically, the orthographic projection shape of the second shielding structure Z2 on the substrate 11 is a rectangle, and the maximum length h2 of the second shielding structure Z2 in the first direction X may be the length of the vertical side of the rectangle along the first direction X; the orthographic projection shape of the first shielding structure Z1 on the substrate 11 is an octagon, and the maximum length h1 of the first shielding structure Z1 in the first direction X may be the distance between two opposite sides of the octagon parallel to the second direction Y.

[0373] In a possible implementation, referring to FIG. 20C , in the pixel light-transmitting area row H, the first pixel light-transmitting area P1, the second pixel light-transmitting area P2, and the third pixel light-transmitting area P3 are arranged in sequence along the second direction Y; the pixel light-transmitting areas P with the same output light wavelength band range are located in the same first direction X, that is, the first pixel light-transmitting area P1 is located in the same column, the second pixel light-transmitting area P2 is located in the same column, and the third pixel light-transmitting area P3 is located in the same column.

[0374] In a possible embodiment, the maximum length h2 of the second shielding structure Z2 in the first direction X may be in the range of 8μm to 12μm, specifically, for example, 8μm, 9μm, 10μm, 10.5μm, 11μm, 12μm; the maximum length h1 of the first shielding structure Z1 in the first direction X may be in the range of 10μm to 15μm, specifically, for example, 10μm, 11μm, 12μm, 13μm, 13.5μm, 14μm, 15μm; the maximum length h3 of the third metal wire main portion M310 in the first direction X may be in the range of 5μm to 10μm, specifically, for example, 5μm, 6μm, 7μm, 7.5μm, 8μm, 9μm, 10μm.

[0375] In a possible implementation, as shown in FIG. 21 and FIG. 22, the array substrate further includes: a second active layer C2 located on the side of the first active layer C1 facing the substrate 11, a driving source drain (including a driving source MQ2 and a driving drain MQ3) located on the side of the second active layer C2 away from the substrate 11, and a driving gate MQ1. Specifically, the array substrate may include a gate driving circuit in the non-display area BB, and the gate driving circuit board includes: a plurality of second transistors, and the second transistor may include: a second active layer C2, a driving source drain (including a driving source MQ2 and a driving drain MQ3), and a driving gate MQ1. In the disclosed embodiment, the array substrate uses LTPO (Low Temperature Polycrystalline Oxide) technology, integrating two TFTs (Thin Film Transistor, Thin Film Field Effect Transistor) of LTPS (Low Temperature Poly-Silicon) and Oxide (oxide), which can enable AR and VR products to have high resolution (PPI, Pixel Per Inch), high aperture ratio and high transmittance.

[0376] In a possible implementation, referring to FIG. 21 and FIG. 22, the array substrate further includes: a first drive electrode MD1, a second drive electrode MD2, a third drive electrode MD3, and a fourth drive electrode MD4 located in the non-display area BB, wherein the first drive electrode MD1 is electrically connected to the second drive electrode MD2, and the third drive electrode MD3 is electrically connected to the fourth drive electrode MD4. Specifically, the first drive electrode MD1 can be used as a first signal line, and the third drive electrode MD3 can be used as a second signal line. The first signal line may include a signal line electrically connected to a gate drive circuit, and / or a signal line electrically connected to a multiplexer; the second signal line may include a signal line electrically connected to a gate drive circuit, and / or a signal line electrically connected to a multiplexer. The first signal line may include: an initial signal line, a clock signal line, a reset signal line, or a light-emitting control line. The second signal line may include: an initial signal line, a clock signal line, a reset signal line, or a light-emitting control line.

[0377] In a possible implementation, as shown in FIG. 21 , the second active layer C2 is located between the third metal layer M3 and the substrate 11; the driving gate MQ1 is located in the third metal layer M3; and the driving source and drain (including the driving source MQ2 and the driving drain MQ3) are located in the first metal layer M1. In the disclosed embodiment, the driving gate MQ1 is located in the third metal layer M3; and the driving source and drain are located in the first metal layer M1. The driving gate MQ1 and the driving source and drain corresponding to the non-display area can be formed while the third metal layer M3 and the first metal layer M1 are formed in the display area AA, thereby simplifying the manufacturing process of the display panel.

[0378] In a possible implementation, referring to FIG. 21 , the first driving electrode MD1 and the third driving electrode MD3 may be located in the first metal layer M1; the second driving electrode MD2 may be located in the third metal layer M3, and the fourth driving electrode MD4 may be located in the second metal layer M2; and thus, while forming the first metal layer M1 in the display area AA, the first driving electrode MD1 and the third driving electrode MD3 corresponding to the non-display area may be formed; while forming the second metal layer M2 in the display area AA, the fourth driving electrode MD4 corresponding to the non-display area may be formed; and while forming the third metal layer M3 in the display area AA, the second driving electrode MD2 corresponding to the non-display area may be formed, thereby simplifying the manufacturing process of the display panel.

[0379] In one possible implementation, at least part of the routing of the second metal layer M2 and at least part of the routing of the third metal layer M3 can be electrically connected by jumping layers in the non-display area BB. For example, the second metal line M21 and the third metal line M31 can be electrically connected in the non-display area BB to enable the transistors in the display area AA to form a dual-gate structure.

[0380] In a possible implementation, as shown in FIG. 22, the second active layer C2 is located between the third metal layer M3 and the first active layer C1; the driving source and drain (including the driving source MQ2 and the driving drain MQ3) are located in the second metal layer M2; and the driving gate MQ1 is located in the third metal layer M3. In the disclosed embodiment, the driving source and drain are located in the second metal layer M2; the driving gate MQ1 is located in the third metal layer M3, and the corresponding driving gate MQ1 and driving source and drain in the non-display area can be formed while forming the third metal layer M3 and the second metal layer M2 in the display area AA, which can simplify the manufacturing process of the display panel.

[0381] In a possible implementation, referring to FIG. 22 , the first driving electrode MD1 may be located in the first metal layer M1; the second driving electrode MD2 may be located in the second metal layer M2, and the third driving electrode MD3 may be located in the third metal layer M3; and thus, while forming the first metal layer M1 in the display area AA, the first driving electrode MD1 corresponding to the non-display area may be formed; while forming the second metal layer M2 in the display area AA, the second driving electrode MD2 corresponding to the non-display area may be formed; and while forming the third metal layer M3 in the display area AA, the third driving electrode MD3 corresponding to the non-display area may be formed, thereby simplifying the manufacturing process of the display panel.

[0382] In a possible implementation, in combination with FIG. 21, FIG. 23A-FIG. 23C, where FIG. 23B is a pattern of the third conductive layer corresponding to FIG. 23A, and FIG. 23B may also be a partial schematic diagram of the dotted frame in FIG. 23C, that is, FIG. 23C is a schematic diagram of a larger range of FIG. 23B, the array substrate further includes: a third conductive layer D3 located on the side of the second conductive layer D2 away from the substrate, the third conductive layer D3 includes a plurality of hollows L, and the portion of the hollow L projected on the substrate 11 overlaps with the portion of the first electrode D21 on the substrate 11. In the disclosed embodiment, the array substrate further includes a third conductive layer D3, the third conductive layer D3 includes a plurality of hollows L, and the portion of the hollow L projected on the substrate 11 overlaps with the portion of the first electrode D21 on the substrate 11, so that the first electrode D21 and the third conductive layer D3 can form a fringe electric field at the hollow L, thereby driving the liquid crystal to deflect. In the disclosed embodiment, the driving mode of the display panel may be a novel Fringe Field Switching (FFS) mode, or an Advanced Super Dimension Switch (ADS) mode.

[0383] It should be noted that, in order to clearly illustrate the various film layers, Figure 23A only illustrates the hollow L shape of the third conductive layer D3. The complete pattern of the third conductive layer D3 can be shown in Figure 23B, and the pattern of a larger area of ​​Figure 23B can be shown in Figure 23C.

[0384] Specifically, the third conductive layer D3 may be a common electrode layer, which forms an electric field with the first electrode D21 to drive the liquid crystal molecules between the array substrate and the opposite substrate.

[0385] In a possible implementation, the third conductive layer D3 may include: a plurality of hollow rows extending along the first direction X and arranged along the second direction Y; the hollow rows include: a plurality of hollows L sequentially arranged along the first direction X. In a possible implementation, as shown in FIG. 23A to FIG. 23C , the hollows L may correspond one-to-one to the first electrodes D21 .

[0386] In a possible embodiment, the portion of the hollow L projected on the substrate 11 overlaps with the portion of the first metal wire M11 projected on the substrate 11; in a possible embodiment, the portion of the hollow L projected on the substrate 11 overlaps with the portion of the third metal wire M31 projected on the substrate 11; in a possible embodiment, the portion of the hollow L projected on the substrate 11 overlaps with the portion of the third metal wire M31 projected on the substrate 11.

[0387] In a possible implementation manner, the orthographic projection of the second metal wire M21 on the substrate 11 covers the orthographic projection of the gap between two adjacent hollow rows on the substrate 11 .

[0388] In a possible embodiment, referring to FIG. 21 and FIG. 22 , the array substrate further includes: a fourth metal layer M4 located on the side of the third conductive layer D3 facing the substrate 11 and in contact with the third conductive layer D3; the fourth metal layer M4 includes: a plurality of fourth metal wires M41 extending along the first direction X, the orthographic projection of the fourth metal wires M41 on the substrate 11 covers the orthographic projection of the first metal wires M11 on the substrate 11.

[0389] Specifically, the conductivity of the fourth metal layer M4 may be better than that of the third conductive layer D3. The plurality of fourth metal wires M41 disposed on the array substrate and in contact with the third conductive layer D3 may reduce the resistance of the third conductive layer D3.

[0390] In a possible implementation, as shown in FIG. 21 , the display panel may further include at least one of the following:

[0391] A buffer layer 12 located between the substrate 11 and the second active layer C2;

[0392] A second gate insulating layer 13 located between the second active layer C2 and the third metal layer M3;

[0393] A third interlayer dielectric layer 14 located between the third metal layer M3 and the first active layer C1;

[0394] A first gate insulating layer 15 located between the first active layer C1 and the second metal layer M2;

[0395] A first interlayer dielectric layer 16 located between the second metal layer M2 and the first metal layer M1;

[0396] A second interlayer dielectric layer 17 located between the first metal layer M1 and the first conductive layer D1;

[0397] A first planar layer 18 located between the first conductive layer D1 and the second conductive layer D2;

[0398] The second planar layer 19 is located between the second conductive layer D2 and the fourth metal layer M4.

[0399] In some examples, at least one of the buffer layer 12, the second gate insulating layer 13, the third interlayer dielectric layer 14, the first gate insulating layer 15, the first interlayer dielectric layer 16, the second interlayer dielectric layer 17, the first planarizing layer 18, and the second planarizing layer 19 may be an inorganic insulating layer, for example, any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON) may be used, and may be a single layer, a multilayer, or a composite layer.

[0400] In a possible implementation, the material of the first active layer C1 includes: metal oxide doped with rare earth elements. Specifically, the material of the first active layer C1 is a metal oxide semiconductor material, and the metal oxide semiconductor material may include: any one or more of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), and rare earth element doped metal oxide (RE-OS), wherein the rare earth element doped metal oxide may include lanthanide doped metal oxide (Ln-OS); the crystal state of the active layer material may be amorphous, partially crystalline or polycrystalline. In the embodiment of the present disclosure, the material of the first active layer C1 is a metal oxide doped with rare earth elements, and the first active layer C1 may have stable performance even when exposed to light, and thus, no light shielding layer may be provided in the light-transmitting area P, which may further improve the aperture ratio of the display panel. In the embodiment of the present disclosure, the first active layer C1 of the display region transistor may be an oxide active layer, that is, the thin film transistor of the oxide active layer has advantages such as low leakage current.

[0401] In a possible implementation, the material of the second active layer C2 includes: low temperature polysilicon. That is, considering that the current high-transition oxide gate drive circuit design is not mature enough, the transistor size in the gate drive circuit will be larger, resulting in an excessively large frame. In the disclosed embodiment, the gate drive circuit of the non-display area can adopt a low temperature polysilicon transistor design.

[0402] In the embodiment of the present disclosure, the first active layer C1 of the first transistor in the display area can be an oxide active layer, and the second active layer C2 of the second transistor in the non-display area can be a polysilicon active layer. Since the oxide thin film transistor has the advantages of low leakage current, and the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, the low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display panel to form a low-temperature polycrystalline oxide display panel. By utilizing the advantages of both, high resolution (Pixel Per Inch, PPI) and low-frequency driving can be achieved, which can reduce power consumption and improve display quality. For example, the array substrate provided in the embodiment of the present disclosure combines the technical effects of high mobility and narrow frame of the second transistor of the second active layer C2 made of polysilicon material, and the display effect of high transmittance of the first transistor of the first active layer C1 made of metal oxide semiconductor material. When the array substrate is used in a display panel, the display effect of virtual reality can be further improved.

[0403] In a possible implementation, the first active layer C1 and the second active layer C2 may also be the same layer and the same material; specifically, the first active layer C1 and the second active layer C2 may both be oxide active layers. Specifically, for example, the materials of the first active layer C1 and the second active layer C2 may include: amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), or indium zinc tin oxide (IZTO). In the disclosed embodiment, when the active layers of the transistors in the display area and the non-display area are both oxide active layers, the second transistor in the non-display area and the first transistor in the display area may both adopt an oxide double-gate structure, and the bottom gate size of the second transistor in the non-display area is larger than the top gate size (the single-side package size may be 0.5μm to 2μm), which can effectively improve the on-state current and device stability of the second transistor in the non-display area; for the first transistor in the display area, the bottom gate size may be smaller than the top gate size (the bottom gate is 0.3μm to 0.6μm smaller than the top gate on one side), which can avoid affecting the aperture ratio.

[0404] In a possible implementation, the material of the first conductive layer D1 may include: metal oxide (eg, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide.

[0405] In a possible implementation, the material of the second conductive layer D2 may include: metal oxide (eg, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide.

[0406] In a possible implementation, the material of the third conductive layer D3 may include: metal oxide (for example, indium tin oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), indium-doped cadmium oxide.

[0407] In a possible implementation, at least two of the first conductive layer D1, the second conductive layer D2, and the third conductive layer D3 are made of the same material. In a possible implementation, the first conductive layer D1, the second conductive layer D2, and the third conductive layer D3 may also be made of different materials.

[0408] In a possible embodiment, the material of at least one of the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 may include: any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0409] In a possible implementation, at least two of the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 are made of the same material. In a possible implementation, the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 may also be made of different materials.

[0410] In some examples, the substrate 11 may be a flexible substrate, or may be a rigid substrate. For example, the rigid substrate may include a glass substrate. The flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the material of the semiconductor layer may be amorphous silicon (a-Si). However, the embodiments of the present disclosure are not limited to this.

[0411] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes an array substrate as provided in the embodiment of the present disclosure, and also includes an opposite substrate arranged opposite to the array substrate.

[0412] In a possible implementation, the opposing substrate may include an opposing substrate, a black matrix located on one side of the opposing substrate, and an optical adhesive layer located on a side of the black rectangle away from the opposing substrate.

[0413] In a possible implementation, the display panel further includes: a color filter layer; the color filter layer may be located on the opposite substrate, or the color filter layer may be located on the array substrate.

[0414] FIG24 is a schematic diagram of the structure of a display panel of at least one embodiment of the present disclosure. In some examples, as shown in FIG24, the display panel may include: a timing controller 20, a data driver 40, a gate drive circuit, and a sub-pixel array 10. The gate drive circuit may include at least one driver, for example, a scan driver 30. The timing controller 20, the data driver 40, and the gate drive circuit may be located in a non-display area outside the display area of ​​the display panel. The sub-pixel array 10 located in the display area may include a plurality of sub-pixels PX arranged in a regular pattern. The scan driver 30 may be configured to provide a scan signal to the sub-pixel PX along a scan line; the data driver 40 may be configured to provide a data signal to the sub-pixel PX along a data line; and the timing controller 20 may be configured to control the scan driver 30 and the data driver 40.

[0415] In some examples, the timing controller 20 may provide the data driver 40 with a grayscale value and a control signal suitable for the specifications of the data driver 40; the timing controller 20 may provide the scan driver 30 with a clock signal, an initial signal, etc. suitable for the specifications of the scan driver 30. The data driver 40 may generate a data voltage to be provided to the data lines D1 to Dn using the grayscale value and the control signal received from the timing controller 20. For example, the data driver 40 may sample the grayscale value using the clock signal, and apply the data signal corresponding to the grayscale value to the data lines D1 to Dn in units of sub-pixel rows. The scan driver 30 may generate a scan signal to be provided to the scan lines G1 to Gm using the clock signal, the initial signal, etc. received from the timing controller 20. For example, the scan driver 30 may sequentially provide a scan signal having an on-level pulse to the scan line. In some examples, the scan driver 30 may include a shift register, and may sequentially transmit the scan initial signal provided in the form of an on-level pulse to the next level circuit under the control of the clock signal to generate a scan signal. Wherein, n and m are both natural numbers.

[0416] In some examples, the gate driver circuit can be directly disposed on the substrate. For example, the gate driver can be disposed in the peripheral areas on the left and right sides of the display area. In some examples, the gate driver can be formed together with the sub-pixel in the process of forming the sub-pixel. However, the present embodiment does not limit the position or formation method of the gate driver. In some examples, the gate driver can be disposed on a separate chip or printed circuit board to connect to a pad or pad formed on the substrate substrate.

[0417] In some examples, the data driver 40 may be disposed on a separate chip or printed circuit board to be connected to the sub-pixel PX through a signal access pin disposed on the substrate. For example, the data driver 40 may be formed by a chip on glass, a chip on plastic, a chip on a film, etc. to be connected to a signal access pin on the substrate. The timing controller 20 may be disposed separately from the data driver 40 or integrally with the data driver 40. However, this embodiment is not limited thereto.

[0418] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel provided by the embodiment of the present disclosure.

[0419] In the embodiment of the present disclosure, the minimum spacing i1 between the orthographic projection of the conductive portion D11 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 is greater than the minimum spacing i2 between the orthographic projection of the second sub-metal line MB on the substrate 11, which can increase the lateral capacitance between the first metal line M11 and the conductive portion D11, thereby increasing the second coupling capacitance C dp2 , and due to the first coupling capacitor C dp1 In the embodiment, the overlap capacitance between the first active pattern C11 and the conductive portion D11 (the area shown by the thick solid frame S in FIG. 15D ) accounts for the main part, and the distance between the conductive portion D11 and the second sub-metal line MB is reduced, which will not affect the first coupling capacitor C dp1 This has a significant impact, thereby reducing the second coupling capacitance C dp2 With the first coupling capacitor C dp1 difference, thereby improving the vertical crosstalk problem.

[0420] It should be noted that in the present disclosure, "same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for making a specific pattern, and then using the same mask plate through a single patterning process. That is, one patterning process corresponds to a mask plate (mask, also called a photomask). Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0421] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0422] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

An array substrate, wherein: include: substrate; The first active layer is located on one side of the substrate, and includes: a plurality of first active patterns; the first active pattern includes: a first part and a second part distributed along a first direction; the first metal layer includes: a plurality of first metal wires; the part of the second part on the orthographic projection of the substrate overlaps with the part of the first metal wire on the orthographic projection of the substrate; the second metal layer includes: a plurality of second metal wires extending along the second direction; the first conductive layer includes: a plurality of conductive parts; the orthographic projection of at least one of the plurality of conductive parts on the substrate is located between the orthographic projections of adjacent first metal wires on the substrate; the second conductive layer includes: a plurality of first electrodes; wherein the first metal wires adjacent to the two sides of the conductive part include: a first sub-metal wire and a second sub-metal wire; wherein the first sub-metal wire is electrically connected to the second part; the first part is electrically connected to the first electrode through the conductive part; the orthographic projection of the conductive part on the substrate is spaced apart from the orthographic projection of the first sub-metal wire on the substrate, which is greater than the space between the orthographic projection of the conductive part and the orthographic projection of the second sub-metal wire on the substrate. The array substrate according to claim 1, wherein: The conductive parts adjacent to the first sub-metal wire on both sides include: a first sub-conductive part, and a second sub-conductive part; wherein, the first sub-metal conductive part is electrically connected to the first sub-metal wire through a transistor; the distance between the orthographic projection of the first sub-conductive part on the substrate and the orthographic projection of the first sub-conductive part on the substrate is greater than the distance between the orthographic projection of the first sub-conductive part on the substrate and the orthographic projection of the second sub-conductive part on the substrate. The array substrate according to claim 1 or 2, wherein: The conductive part includes: a first conductive part and a second conductive part distributed along the first direction; the orthographic projection of the first conductive part on the substrate has an overlapping area with the orthographic projection of the first part on the substrate, and the second conductive part has an overlapping area with the orthographic projection of the second part on the substrate; the first conductive part and the second conductive part have different extension directions; at least the orthographic projection of the second conductive part on the substrate is spaced apart from the orthographic projection of the first sub-metal wire on the substrate by a greater distance than the orthographic projection of the second sub-metal wire on the substrate. The array substrate according to claim 3, wherein: The second conductive portion has a first outer edge facing the first sub-metal wire, and a second outer edge facing the second sub-metal wire; the distance between the first outer edge and the first sub-metal wire's projection on the substrate is greater than the distance between the second outer edge and the second sub-metal wire's projection on the substrate. The array substrate according to claim 4, wherein: The second conductive portion and the first sub-metal wire and the second sub-metal wire satisfy the following relationship: 0.05μm≤(ab) / 2≤0.15μm; wherein a represents the distance between the orthographic projection of the first outer edge on the substrate 11 and the orthographic projection of the first sub-metal routing on the substrate, and b represents the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal routing on the substrate. The array substrate according to claim 4 or 5, wherein: The first metal wire includes: a first sub-metal portion and a second sub-metal portion arranged alternately along the first direction; the first sub-metal portion and the second sub-metal portion have different extension directions; the first conductive portion extends along the extension direction of the second sub-metal portion, and the second conductive portion extends along the extension direction of the first sub-metal portion. The array substrate according to claim 3, wherein: The second conductive portion has a first outer edge facing the first sub-metal wire, and a second outer edge facing the second sub-metal wire; the extension line of the first outer edge intersects with the extension line of the second outer edge; the distance between the orthographic projection of the first outer edge on the substrate and the orthographic projection of the first sub-metal routing on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal routing on the substrate. The array substrate according to claim 7, wherein: The first metal wire includes: a first sub-metal portion and a second sub-metal portion arranged alternately along the first direction; the first sub-metal portion and the second sub-metal portion have different extension directions; the first outer edge extends along the first direction; and the extension direction of the second outer edge is the same as the extension direction of the first sub-metal portion. The array substrate according to claim 3, wherein: The second conductive portion has a first outer edge facing the first sub-metal line, and a second outer edge facing the second sub-metal line; The first outer edge includes: a first sub-edge portion, and a second sub-edge portion; the second sub-edge portion is located on a side of the first sub-edge portion away from the first conductive portion, and the second sub-edge portion is located on a side of an extension line of the first sub-edge portion toward the first sub-metal routing; a distance between an orthographic projection of the second sub-edge on the substrate and an orthographic projection of the first sub-metal routing on the substrate is greater than a distance between an orthographic projection of the second outer edge on the substrate and an orthographic projection of the second sub-metal routing on the substrate. The array substrate according to claim 9, wherein: The first metal line includes: first sub-metal parts and second sub-metal parts alternately arranged along the first direction; the first sub-metal parts and the second sub-metal parts have different extending directions; and the second sub-edges extend along the extending direction of the first sub-metal parts. The array substrate according to claim 10, wherein: The first sub-edge extends along an extension direction of the second sub-metal portion; and the second outer edge extends along the extension direction of the first sub-metal portion. The array substrate according to claim 10, wherein: There is a first bending portion between the first sub-metal portion and the second sub-metal portion; the first outer edge has a second bending portion; the second bending portion is located in the area between the orthographic projection of the first metal edge on the substrate and the orthographic projection of the first connecting line on the substrate, wherein the first metal edge is the outer edge of the second metal wire facing the first conductive portion, and the first connecting line is the connecting line of the first bending portions of two adjacent first metal wires. The array substrate according to claim 12, wherein: The array substrate also includes: a third metal layer located on the side of the first active layer facing the substrate; the third metal layer includes: a plurality of third metal wires extending along the second direction; the orthographic projection of the third metal wire on the substrate covers the orthographic projection of the second metal wire on the substrate; the orthographic projection of the second bent portion on the substrate is located in the area between the orthographic projection of the first metal edge on the substrate and the orthographic projection of the second metal edge on the substrate, and the second metal edge is the outer edge of the third metal wire on the side facing the first conductive portion. The array substrate according to claim 9, wherein: The first outer edge has a second bending portion; the orthographic projection of the second bending portion on the substrate overlaps with the orthographic projection of the first metal edge on the substrate, and the first metal edge is the outer edge of the second metal wire facing the first conductive portion. The array substrate according to any one of claims 6, 8, 11-14, wherein: The distance between two ends of the first sub-metal portion in the second direction is equal to the distance between two ends of the second sub-metal portion in the second direction; and the second direction is perpendicular to the first direction. The array substrate according to any one of claims 6, 8, 11-15, wherein: The first conductive portion is located between two adjacent first sub-metal portions in the second direction; the second conductive portion is located between two adjacent second sub-metal portions in the second direction; and an extending direction of the first conductive portion is the same as an extending direction of the first sub-metal portion. The array substrate according to any one of claims 6, 8, 11-15, wherein: The first electrode includes: a first electrode portion and a second electrode portion distributed along the first direction; an extending direction of the first electrode portion is the same as an extending direction of the first sub-metal portion, and an extending direction of the second electrode portion is the same as an extending direction of the second sub-metal portion. The array substrate according to claim 17, wherein: The orthographic projection of the first electrode portion on the substrate has an overlapping area with the orthographic projection of the second conductive portion on the substrate, and the first electrode portion and the second conductive portion are electrically connected at the overlapping position. The array substrate according to any one of claims 5 to 18, wherein: The first conductive portion has a third outer edge facing the first sub-metal line and a fourth outer edge facing the second sub-metal line; the third edge is parallel to the fourth outer edge. The array substrate according to claim 19, wherein: The distance between the orthographic projection of the third outer edge on the substrate and the orthographic projection of the first sub-metal routing on the substrate is greater than the distance between the orthographic projection of the fourth outer edge on the substrate and the orthographic projection of the second sub-metal routing on the substrate. The array substrate according to claim 20, wherein: The distance between the orthographic projection of the third outer edge on the substrate and the orthographic projection of the first sub-metal routing on the substrate is equal to the distance between the orthographic projection of the fourth outer edge on the substrate and the orthographic projection of the second sub-metal routing on the substrate. The array substrate according to any one of claims 19 to 21, wherein: The first outer edge, the second outer edge, and the third outer edge satisfy the following relationship: a>c>b, wherein c represents the distance between the orthographic projection of the third outer edge on the substrate and the orthographic projection of the first sub-metal routing on the substrate. The array substrate according to any one of claims 1 to 22, wherein: The second conductive portion has a fifth outer edge extending along the second direction, and the fifth outer edge is located at a side of the second metal line away from the first conductive portion. The array substrate according to any one of claims 1 to 23, wherein: The second conductive portion has a fifth outer edge extending along the second direction, and the orthographic projection of the second metal line on the substrate covers the orthographic projection of the fifth outer edge on the substrate. The array substrate according to claim 24, wherein: The second metal line has a sixth outer edge extending along the second direction; an orthographic projection of a portion of the sixth outer edge on the substrate coincides with an orthographic projection of the fifth outer edge on the substrate. The array substrate according to any one of claims 1 to 25, wherein: The second portion includes: a first sub-portion and a second sub-portion; the first sub-portion extends along the second direction, and the orthographic projection of the first sub-portion on the substrate overlaps with the orthographic projection of the first metal line on the substrate; the second sub-portion connects the first sub-portion and the first portion; the multiple first active patterns include: a first active pattern row and a second active pattern row; the first active pattern row and the second active pattern row extend along the second direction and are arranged overlappingly along the first direction; the first active pattern row and the second active pattern row each include multiple first active patterns; and in the first active pattern row, the second sub-portion extends along a third direction; in the second active pattern row, the second sub-portion extends along a fourth direction, and the third direction intersects with the fourth direction. The array substrate according to claim 26, wherein: In the first active pattern row, the first sub-portion and the first portion are located on different sides of the second sub-portion; in the second active pattern row, the first sub-portion and the first portion are located on the same side of the second sub-portion. The array substrate according to claim 4, 7, or 9, wherein: The first metal line includes: a first sub-metal portion, a second sub-metal portion, and a third sub-metal portion arranged alternately along the first direction; the second sub-metal portion extends along the first direction; the first sub-metal portion is located on one side of an extension line of the second sub-metal portion, and the third sub-metal portion is located on the other side of the extension line of the second sub-metal portion. The array substrate according to claim 28, wherein: The distance between two ends of the first sub-metal portion in the second direction is equal to the distance between two ends of the third sub-metal portion in the second direction. The array substrate according to claim 28 or 29, wherein: The multiple first active patterns include: a third active pattern row, and a fourth active pattern row; the third active pattern row and the fourth active pattern row extend along the second direction and are arranged overlappingly along the first direction; the third active pattern row and the fourth active pattern row each include multiple first active patterns; in the same third active pattern row, each of the first active patterns is electrically connected to the first metal line on the same side; in the same fourth active pattern row, each of the first active patterns is electrically connected to the first metal line on the same side; between two adjacent first metal lines, the first active pattern of the third active pattern row and the first active pattern of the fourth active pattern row are electrically connected to different first metal lines. The array substrate according to claim 30, wherein: The first portion extends along the first direction, and the second portion is located on one side of the extension line of the first portion; in the third active pattern row, the first portion and the second portion intersect to form an opening of a first angle, and the first sub-metal portion and the second sub-metal portion intersect to form an opening of a second angle are opposite to each other; in the fourth active pattern row, the first portion and the second portion intersect to form an opening of a first angle, and the third sub-metal portion and the next second sub-metal portion in the first direction intersect to form an opening of a third angle. The array substrate according to claim 30, wherein: The first portion extends along the first direction, and the second portion is located on one side of the extension line of the first portion; in the third active pattern row, the first portion and the second portion intersect to form an opening of a first angle, and the first sub-metal portion and the second sub-metal portion intersect to form an opening of a second angle, facing the same side; in the fourth active pattern row, the first portion and the second portion intersect to form an opening of a first angle, and the third sub-metal portion and the next second sub-metal portion in the first direction intersect to form an opening of a third angle, facing the same side. The array substrate according to claim 28 or 29, wherein: The multiple first active patterns include: multiple active pattern rows; the active pattern row includes: multiple first active patterns arranged in sequence along the second direction; in the same active pattern row, each first active pattern is electrically connected to the first metal line on the same side; between two adjacent first metal lines, the first active patterns in the active pattern row are electrically connected to the same first metal line. The array substrate according to any one of claims 28 to 33, wherein: The array substrate includes: a first via hole, a second via hole, and a third via hole; the first active pattern is electrically connected to the conductive part through the first via hole; the conductive part is electrically connected to the first electrode through the second via hole; the first active pattern is electrically connected to the first metal wire through the third via hole; the second conductive layer includes: a plurality of first electrode rows extending along the second direction and arranged in sequence along the first direction; the first electrode row includes: a plurality of first electrodes arranged in sequence along the first direction; the orthographic projection of the first active pattern electrically connected to the first electrode of the Mth row through the first via hole and the second via hole on the substrate overlaps with the orthographic projection of the first electrode of the M-1th row on the substrate. The array substrate as claimed in claim 34, wherein: An extension direction of a portion of the first electrode is the same as an extension direction of the second sub-metal portion; an extension direction of another portion of the first electrode is the same as an extension direction of the third sub-metal portion. The array substrate according to claim 1, wherein: The first metal line extends along a first direction, the first portion extends along the first direction, and the conductive portion extends along the first direction; the distance between the orthographic projection of all the conductive portions on the substrate and the orthographic projection of the first sub-metal line on the substrate is greater than the distance between the orthographic projection of all the conductive portions on the substrate and the orthographic projection of the second sub-metal line on the substrate. The array substrate according to any one of claims 1 to 3, wherein: The conductive part, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship: 15%≤i2 / i1≤75%, wherein i1 represents the minimum distance between the orthographic projection of the conductive part on the substrate and the orthographic projection of the first sub-metal wire on the substrate, and i2 represents the minimum distance between the orthographic projection of the conductive part on the substrate and the orthographic projection of the second sub-metal wire on the substrate. The array substrate according to claim 37, wherein: The conductive portion, the first sub-metal line, and the second sub-metal line satisfy the following relationship: 3%≤(i1-i2) / i3≤15%, wherein i3 represents the minimum spacing between adjacent first sub-metal lines and second sub-metal lines. The array substrate as claimed in claim 38, wherein: The conductive portion, the first sub-metal wire, and the second sub-metal wire satisfy the following relationship: 60%≤i4 / i3≤95%, wherein i4 represents the length of the conductive portion in a direction perpendicular to the first direction. The array substrate according to any one of claims 1 to 3, wherein: One end of the conductive portion is electrically connected to the first portion, and the other end extends toward the second metal line and exceeds the second metal line to form a protrusion, and the orthographic projection of the protrusion on the substrate overlaps with the orthographic projection of the first active pattern on the substrate. The array substrate according to any one of claims 1 to 40, wherein: The first conductive layer is located on a side of the first active layer away from the substrate; The first electrode is located on a side of the first conductive layer facing away from the substrate; The array substrate also includes: a first insulating layer located between the first active layer and the first conductive layer, and a first via hole penetrating the first insulating layer, and the conductive part is electrically connected to the first part through the first via hole; the array substrate also includes: a second insulating layer located between the first conductive layer and the first electrode, and a second via hole penetrating the second insulating layer; the first electrode is electrically connected to the conductive part through the second via hole; in a direction perpendicular to the first direction, at least two adjacent second via holes are an integrated connected structure. The array substrate according to claim 41, wherein: The second via hole has two side walls extending perpendicular to the first direction; at least one of the side walls has a protruding structure, and the orthographic projection of the protruding structure on the substrate is located in a region between the orthographic projections of two adjacent first electrodes on the substrate in the second direction. The array substrate according to claim 41 or 42, wherein: The array substrate further includes: a color resist layer located between the second insulating layer and the second conductive layer; the color resist layer includes: a plurality of color resist portions; an orthographic projection of at least part of the color resist portions on the substrate overlaps with an orthographic projection of the first metal line on the substrate. The array substrate according to any one of claims 1 to 43, wherein: The array substrate has a display area and a non-display area located outside the display area; further comprising: a second active layer located on a side of the first active layer facing the substrate, a driving source and drain located on a side of the second active layer away from the substrate, and a driving gate located in the non-display area; The second active layer is located between the third metal layer and the substrate; The driving gate is located at the third metal layer; The driving source and drain are located in the first metal layer; The second active layer is located between the third metal layer and the first active layer; The driving source and drain are located in the second metal layer; The driving gate is located at the third metal layer; The material of the first active layer includes: metal oxide; the material of the second active layer includes: low temperature polysilicon. A display panel, wherein Comprising an array substrate as described in any one of claims 1-44.

Images