Method and system for dynamically improving low task storage depth latency in solid state drive devices

Abstract

Systems and methods for dynamically changing an operating clock frequency of a circuit are provided. The control circuit determines a first workload value of a circuit operating at a first clock frequency. The control circuit then detects a second workload value of the circuit that is less than the first workload value. When the control circuit detects a second workload value, the control circuit calculates a second clock frequency greater than the first clock frequency. The control circuit then causes the circuit to operate at a second clock frequency.

Description

Technical Field

[0001] The present disclosure relates to a memory device system and method for dynamically changing an operating clock frequency of a circuit, and more particularly, to determining an operating clock frequency based on a low queue workload in the circuit. Summary of the invention

[0002] According to the present disclosure, systems and methods are provided to improve the operational quality of a circuit (e.g., improve the latency of a circuit when the workload of a task storage device of the circuit is low). In some embodiments, a circuit (e.g., a circuit of a hardware accelerator of a storage device) has at least one pipeline processor having a task storage device for commands executed by at least one processor. In some embodiments, the circuit can be any other suitable circuit.

[0003] In some embodiments, the method may include determining a first workload value of a circuit operating at a first clock frequency by using a control circuit. The method also includes detecting a second workload value of the circuit using the control circuit, the second workload value being less than the first workload value. When the control circuit detects the second workload value, the control circuit calculates a second clock frequency greater than the first clock frequency. Then, the control circuit causes the circuit to operate at the second clock frequency.

[0004] In some embodiments, the control circuit further determines a third workload value for the circuit operating at a third clock frequency. The control circuit further detects a fourth workload value greater than the third workload value. In this example, in response to the control circuit detecting the fourth workload value greater than the third workload value, the control circuit calculates a fourth clock frequency less than the third clock frequency. When the fourth clock frequency is calculated, the control circuit causes the circuit to operate at the fourth clock frequency. In some embodiments, the circuit can be a solid state drive (SSD) pipeline accelerator or a network controller pipeline hardware accelerator.

[0005] In some embodiments, the first and second workload values ​​are measured by the number of instructions that the circuit is scheduled to execute. In some embodiments, the workload value is measured by the number of commands that the circuit is scheduled to execute. In some embodiments, the instructions or commands are stored in a task storage device that is communicatively coupled to the circuit. In some embodiments, the instructions or commands can be stored in a task storage device (e.g., a buffer, a stack, a queue) before being executed by the circuit.

[0006] In some embodiments, the control circuit can calculate the second clock frequency by using a linear function. For example, the linear function can be the relationship between the operating clock frequency of the circuit and the workload value. In some embodiments, the use of the linear function to calculate the second clock frequency is also based on the minimum operating clock frequency of the circuit, the maximum operating clock frequency of the circuit, and the ratio of the second workload value to the maximum workload capacity of the task storage device. In some embodiments, calculating the second clock frequency includes comparing the second workload value with a reference workload value. If the control circuit determines that the second workload value is less than the reference workload value, the control circuit causes the circuit to operate at a third clock frequency. If the control circuit determines that the second workload value is greater than the reference workload value, the control circuit causes the circuit to operate at a fourth clock frequency lower than the third clock frequency. In some embodiments, calculating the second clock frequency includes determining a range corresponding to the second workload value from a plurality of workload value ranges. In this embodiment, each range in the plurality of workload value ranges corresponds to a corresponding clock frequency. When the range of the workload value is determined, the control circuit selects the clock frequency as the second clock frequency.

[0007] In some embodiments, the control circuit causes the circuit to operate at the second clock frequency by coupling the circuit to one of the plurality of voltage rails based on the second clock frequency. In some embodiments, causing the circuit to operate at the second clock frequency includes changing a voltage of the circuit using a power management integrated circuit (PMIC) coupled to the circuit.

[0008] In some embodiments, a solid state drive (SSD) storage system is provided, which has an SSD pipeline accelerator, and a storage controller communicatively coupled to the SSD pipeline accelerator. In some embodiments, the storage controller is configured to determine a first workload value of a circuit operating at a first clock frequency, and detect a second workload value of the circuit that is less than the first workload value. If the storage controller detects the second workload value of the circuit, the storage controller calculates a second clock frequency of the circuit that is greater than the first clock frequency, and causes the circuit to operate at the second clock frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The following description includes a discussion of the accompanying drawings, which have diagrams given as examples of implementations of embodiments of the present invention. The accompanying drawings should be understood as examples, not as limitations. As used herein, references to one or more "embodiments" should be understood to describe specific features, structures and / or characteristics included in at least one implementation of the present invention. Therefore, phrases such as "in one embodiment" or "in an alternative embodiment" appearing here describe various embodiments and implementations of the present invention, and do not necessarily all refer to the same embodiment. However, they are not necessarily mutually exclusive.

[0010] Figure 1 An illustrative diagram showing a control circuit for dynamically changing clock control of a circuit based on a workload value according to some embodiments of the present disclosure;

[0011] Figure 2 An illustrative diagram showing a system for dynamically changing the clock frequency of a circuit according to some embodiments of the present disclosure;

[0012] Figure 3A shows an illustrative graph providing an exemplary relationship between workload values ​​and operating frequency according to some embodiments of the present disclosure;

[0013] Figure 3B shows an alternative illustrative graph providing another exemplary relationship between workload value and operating frequency according to some embodiments of the present disclosure;

[0014] Figure 3C shows another illustrative graph providing another exemplary relationship between workload value and operating frequency according to some embodiments of the present disclosure;

[0015] Figure 4 A flowchart showing determining and setting a clock frequency based on a workload value according to some embodiments of the present disclosure; and

[0016] Figure 5 Another flow chart for determining and setting a clock frequency based on a workload value according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0017] According to the present disclosure, systems and methods are provided to improve the operational quality of a circuit (e.g., to improve the latency when an instruction task storage device has a low number of commands). In some embodiments, the task storage device may be an instruction buffer, an instruction stack, or an instruction queue of a circuit. A circuit (e.g., a hardware accelerator of a storage device or a network device) may have a pipeline processor having a task storage device for commands executed by at least one processor. In some embodiments, the pipeline processor may concurrently operate on multiple instructions from the task storage device, for example, by dividing each processor core into multiple stages (e.g., based on roles and available resources). For example, each processor core may be divided into four stages: fetch, decode, execute, write back. Each of these stages may perform one or more instruction operations in each clock cycle in parallel. However, in general, for each instruction, the operation still must be run sequentially relative to the clock cycle. The decoding operation of the instruction may not necessarily start before the fetch operation of the instruction is completed. Therefore, the pipeline processor of the present embodiment is capable of executing 4 different instructions during a single clock cycle. In some alternative embodiments, the pipeline may have more stages or more complex systems or features to reorder, prioritize, or predict the results of certain instructions that are buffered for execution. A pipelined processor can also start processing the next command before the previous command has completed its work through the stages.

[0018] In one approach, when a task store for commands or instructions has a low number of commands (e.g., less than a certain percentage of the total task store size), the pipeline processor can execute commands or instructions while operating at a normal or reduced frequency (e.g., at the same or lower frequency when there are a larger number of commands in the task store). However, in this approach, the latency of the circuit is increased because there are not enough commands or instructions to fill the pipeline.

[0019] To address this problem, the operation of the circuit may be adjusted to increase the frequency of the circuit when the number of commands or instructions in the task store decreases. In this way, the latency of the circuit is reduced when the number of commands or instructions in the task store is low.

[0020] In some embodiments, the pipeline processor can be a highly parallelized processor that can quickly handle high-bandwidth instructions (e.g., by starting simultaneous processing of new instructions before completing previous instructions). In one example, multiple instances of a task can be completed in parallel so that each task of the same type will have the same delay. That is, by exploiting parallelism, if the processor is given more tasks, such a processor can obtain processing tasks at a higher rate. However, when there are fewer tasks (e.g., commands or instructions) in the task storage device, the parallelized pipeline processor may not be able to fully utilize this parallel processing (e.g., because there may not be enough new commands to start processing while previous commands are being processed). As explained above and below, when this happens, the frequency of the processor can be increased to reduce the delay in task execution, thereby alleviating the lack of parallelism.

[0021] In some embodiments, the systems and methods of the present disclosure may refer to a solid-state drive (SSD) storage system that includes an SSD pipeline accelerator and a storage controller or a pipeline processor and a network controller for a transport layer protocol (eg, PCIe).

[0022] A solid-state drive (SSD) is a data storage device that uses integrated circuit components as memory to permanently store data. SSDs have no moving mechanical parts, and this feature distinguishes SSDs from traditional electromechanical disks, such as hard disk drives (HDDs) or floppy disks, which contain rotating platters and movable read / write heads. Compared to electromechanical disks, SSDs are generally more resistant to physical shock, operate quietly, have faster access times, and experience less latency.

[0023] Many types of SSDs use NAND-based flash memory, which retains data without power and includes a non-volatile storage technology. The quality of service (QoS) of an SSD may be related to predictability of low latency and consistency of high input / output operations per second (IOPS) when servicing read / write input / output (I / O) workloads. This means that latency, or I / O command completion time, needs to be within a specified range without unexpected outliers. Throughput, or I / O rate, may also need to be tightly regulated to avoid sudden drops in performance levels.

[0024] refer to Figure 1-5 The subject matter of the present disclosure may be better understood.

[0025] Figure 1An illustrative diagram of a control circuit 100 for dynamically changing a circuit clock based on a workload value 104 of the circuit by a circuit clock control section 116 of the circuit (e.g., a hardware accelerator of an SSD drive or a network card) is shown. In some embodiments, the control circuit 100 includes a load detector 102 that determines a workload value 104 of a task storage device for commands or instructions of the circuit. In some embodiments, the task storage device may be an instruction buffer, an instruction stack, or an instruction queue of the circuit. For example, the circuit (e.g., a solid-state drive) has a processor and a task storage device for instructions executed by the processor. In this example, the control circuit 100 may be located within a storage device, or may be located outside the storage device. The load detector 102 receives task storage device information from the task storage device and outputs a workload value 104. In some embodiments, the workload value 104 is used by a clock adjuster 106, which determines an adjusted clock frequency 114 for the storage device. In some embodiments, the adjusted clock frequency 114 is also based on the minimum operating clock frequency 110 and the maximum operating clock frequency 112 of the circuit, which may be set as circuit-specific or adjustable variables that may be requested by the control circuit 100 for the clock adjuster 106. In some embodiments, the adjusted clock frequency 114 is received by a clock control section 116, which selects the circuit to which the new circuit clock signal 118 is set to the adjusted clock frequency 114. In some embodiments, when the control circuit 100 provides dynamic clock frequency changes to multiple circuits, the clock control section 116 may use the selection bits to determine to which circuit clock signal the new circuit clock signal is sent.

[0026] Any one of the load detector 102, the clock regulator 106, and the clock control section 116 may include a processor and a memory. In some embodiments, the processor of any one of the load detector 102, the clock regulator 106, and the clock control section 116 may include a hardware processor, a software processor, or any combination thereof. In some embodiments, any one of the load detector 102, the clock regulator 106, and the clock control section 116 may be a hardwired circuit, a software module (e.g., a logic block) that simulates hardware, or a combination thereof. In some embodiments, the control circuit 100 may include a single software processor (e.g., a processor simulated using a virtual machine). Each processor may include a hardware processor, a software processor, or any combination thereof. In some embodiments, the combination of the processor and the memory may be referred to as the control circuit 100. In some embodiments, the processor may be referred to as the control circuit 100 alone. The memory of the control circuit 100 may include hardware elements for non-transitory storage of commands or instructions, a history of the workload value 104, and a minimum operating clock frequency 110 and a maximum operating clock frequency 112. In some embodiments, the control circuit 100 may dynamically change the clock frequencies of multiple circuits, wherein each corresponding circuit has a task storage device and a processor running at a corresponding clock frequency. For example, if the workload value decreases, the load detector 102 detects the decrease and determines a smaller workload value 104, which is sent to the clock adjuster 106. The clock adjuster 106 then determines an adjusted clock frequency 114 based on the workload value 104, the minimum operating circuit clock frequency 110, and the maximum operating circuit clock frequency 112. The adjusted clock frequency 114 is then sent to the clock control section 116, which sets the frequency of the clock signal 118 of the circuit to the adjusted clock frequency 114. The adjusted clock frequency 114 can be adjusted by using the respective Figure 3A , Figure 3B and Figure 3B The method may be determined based on the techniques and relationships shown in one or more of graphs 300 , 310 , or 320 .

[0027] Figure 2 An illustrative diagram of a system for dynamically changing the clock frequency of a circuit is shown, according to some embodiments of the present disclosure. Figure 2 An illustrative diagram of a system 200 for dynamically changing the operating frequency of a pipeline processor 212 (e.g., a processor of an SSD drive or a network card) according to some embodiments of the present disclosure is shown. In some embodiments, the system 200 includes a control circuit 202 that determines and sets a new circuit clock frequency 210 for a circuit 204. In some embodiments, the control circuit 202 may be Figure 11. The same control circuit 100 as shown. In some embodiments, the control circuit 202 can perform the functions of the load detector 102, the clock regulator 106, and / or the clock regulator 116 by software, hardware, or a combination thereof. The circuit 204 includes a circuit clock input 206, a task storage device 208 for temporarily storing commands or instructions, and a pipeline processor 212. In some embodiments, the task storage device 208 can be an instruction buffer, an instruction stack, or an instruction queue of the circuit 204. In some embodiments, the circuit 204 can include a memory 216, which can be located inside or outside the circuit 204. In some embodiments, the pipeline processor 212 is communicatively coupled to the task storage device 208 (e.g., a buffer, stack, or queue), the clock signal 206, and the memory 216. In addition, the pipeline processor 212 is communicatively coupled to the circuit output 214. In some embodiments, the pipeline processor 212 can write to or read from the task storage device 208, which temporarily stores the commands or instructions scheduled for execution. The capacity of the task storage device 208 is defined by the maximum number of commands or instructions that can be stored in the task storage device 208. In general, the task storage device size refers to the number of commands or instructions currently stored in the task storage device 208. In some embodiments, the state data of the task storage device 208 (e.g., the task storage device size and the task storage device capacity) is received by the control circuit 202 to determine the adjusted operating clock frequency 210, which is set as the new clock signal 206 of the circuit 204. For example, the control circuit 202 determines a workload value of the circuit 204 operating at a first clock frequency. The first workload value is determined by receiving the task storage device size data from the task storage device 208 of the circuit 204. A load detector of the control circuit 202 determines the first workload value when the circuit 204 operates at the first clock frequency. When determining the first workload value, the control circuit 202 determines whether the workload value has changed. In some embodiments, there may be multiple circuits electrically coupled to the control circuit 202. In these embodiments, the control circuit 202 may perform multiple determinations in parallel and output new clock signals for multiple circuits of the multiple circuits.

[0028] In some embodiments, the control circuit 202 determines the adjusted operating clock frequency 210 by an equation or formula. For example, the control circuit 202 may use the following equation to calculate the adjusted operating frequency f:

[0029]

[0030] Where q is a workload value, Q is a maximum load or task storage device 208 capacity, M[h] is a maximum clock frequency of circuit h, and N[h] is a minimum clock frequency of circuit h. In some embodiments, the workload value q corresponds to a task storage device size of task storage device 208. In one example, circuit h has a task storage device 208 with a task storage device capacity Q of 8 kilobytes (KB), a maximum clock frequency M[h] of 80 megahertz (MHz), and a minimum clock frequency N[h] of 12 MHz. When the workload value q is 4 KB (q1), the control circuit 202 sets the operating frequency f[h](q1) of circuit h at the workload value q1 to 46 MHz. If the control circuit 202 detects that the workload value q increases to 7 KB (q2), the control circuit 202 determines that the adjusted operating frequency f[h](q2) of circuit h at the workload value q2 is 20.5 MHz. In some embodiments, the control circuit 202 sets the clock frequency of the circuit to the adjusted clock operating frequency f[h](q2).

[0031] For example, the same equation seen in the previous paragraph can be used to calculate the adjusted operating frequency of a circuit with an internal circuit delay of 12 microseconds. The internal circuit delay is the time it takes for the circuit to process an instruction. In addition (for example, for a read instruction), there may be an additional delay from the worst-case delay of 50 microseconds due to the need to access the memory device (for example, to read 4KB of data). Therefore, in this example, the approximate total worst-case delay of the read command for 4KB read data is approximately 62 microseconds (12us+50us). Therefore, in this example, the maximum frequency of the clock signal is approximately 16.1 kilohertz (1 / 62 microseconds) in order to process instructions with the worst-case delay. In this example, the control circuit 202 determines a first workload value for a 4KB read command in a task storage device for a circuit operating at a first clock frequency (lower than the maximum frequency of 16.1 kilohertz). If the control circuit 202 determines that the number of 4KB read commands in the task storage device of the circuit has dropped to a second workload value, the control circuit 202 calculates a second clock frequency that is greater than the first clock frequency but less than the maximum frequency (e.g., a maximum frequency of 16.1 kHz). The control circuit 202 then causes the circuit to operate at the second clock frequency.

[0032] The control circuit 202 is configured to increase the clock frequency of the circuit as the workload value decreases, and to decrease the clock frequency of the circuit as the workload value increases. The circuit 204 has a worst-case delay that includes network delays between components, task storage device 208 read delays, memory read delays, and processor 212 delays. In some embodiments, the worst-case delay will correspond to a minimum operating circuit clock frequency. The minimum operating circuit clock frequency ensures a minimum throughput, even at high workload values. When the workload value decreases, the clock frequency can be increased to achieve higher throughput while the workload value continues to decrease.

[0033] Figure 3A , 3B 3C shows illustrative graphs 300, 310, and 320 according to some embodiments of the present disclosure, providing different relationships between workload values ​​and operating frequencies. For each graph 300, 310, and 320, workload independent variables 304, 314, and 324 may also be referred to as Figure 1 In some embodiments, the control circuit (e.g., control circuit 202) may use the formulas or relationships shown in graphs 300, 310, 320 to determine operating clock frequencies 302, 312, 322 based on workload values ​​304, 314, 324 of a task storage device (e.g., task storage device 208). In some embodiments, the task storage device may be an instruction buffer, instruction stack, or instruction queue of the circuit. In some embodiments, the workload value is the size of the task storage device, or how many commands or instructions are currently stored in the task storage device. In some embodiments, the workload value is a percentage of the task storage memory that contains stored commands or instructions. Operating frequencies 302, 312, and 322 refer to operating clock frequencies that are set as new clock signals for the circuit (e.g., circuit 204). In Figure 3A , graph 300 illustrates a linear inverse relationship between workload 304 and operating frequency 302. For example, operating frequency 302 may be inversely proportional to the ratio of task storage device workload 304 to task storage device capacity. In this example, as the task storage device stores more commands and instructions, workload 304 increases, the task storage device capacity remains constant, and thus the ratio increases. For example, graph 300 may be a portion of a linear relationship between a circuit's operating frequency (f) 302 and a workload value (q) 304, such as:

[0034]

[0035] The size of the task storage device 208 can be, for example, in the range of 256B to 8KB, and is therefore the lower and upper limits for the linear relationship portion of the circuit. For example, the control circuit determines that at a first workload value q1 of 5KB (e.g., the current task storage device size), the first clock frequency f(q1) is 12.5kHz. If the control circuit determines that the second workload value q2 is reduced to 2KB, the control circuit determines that the second clock frequency f(q2) is 14kHz and causes the circuit to operate at the second clock frequency. By increasing the clock frequency from 12.5kHz to 14kHz, the processor in the circuit executes a greater number of instructions in the same amount of time. Although in Figure 3A This linear relationship is shown for the control circuit in , but the control circuit may use any other suitable decreasing linear function (eg, a linear function with a negative slope) to calculate the adjusted operating frequency.

[0036] Figure 3B A graph 310 having an alternative relationship is shown, where the change in operating frequency 312 becomes smaller for each incremental increase in task store workload 314. Furthermore, when task store workload 314 reaches a certain value, the relationship begins to become more linear. Figure 3B This hyperbolic relationship is shown for the control circuit in , but the control circuit may use any other suitable decreasing hyperbolic function (eg, a hyperbolic function with a decreasing negative slope) to calculate the adjusted operating frequency.

[0037] Figure 3C A graph 320 is shown in which an operating frequency 322 determined by a control circuit is determined by a step function of a task storage device workload 324. There is a range of workload 324 values ​​corresponding to a single operating frequency 322. In this graphical example 320, there are five different workload 324 ranges, and five corresponding operating frequencies 322 are shown. For example, a circuit having an 8KB capacity task storage device can have the circuit's control circuit determine the circuit's operating frequency 322, as shown in the graph 320. For a range of workload values ​​324 of 256B to 1KB, the operating frequency 322 is 80MHz. The ranges of workload values ​​324 are 1KB to 3KB and 3KB to 5KB, and the corresponding operating frequencies 322 are 70MHz and 55MHz, respectively. Finally, the ranges of workload values ​​324 of 5KB to 7.5KB and 7.5KB to 8KB correspond to operating frequencies 322 of 40MHz and 32MHz, respectively. For a given range of workload values ​​324, the control circuit can determine the step size in the operating frequency 322 to be the most efficient operating frequency 322 without frequently changing the operating frequency 322. Figure 3CThis step function is shown for the control circuit in , but the control circuit may use any other suitable decreasing step function to calculate the adjusted operating frequency.

[0038] In some embodiments, portions of each of these graphs may be used within a particular range of workload 304, 314, 324 values. For example, within a first range of workload values, the relationship between the task storage device workload and the operating frequency is linear, whereas within a second range of workload values, the relationship between the task storage device workload and the operating frequency is hyperbolic. This example shows multiple relationship configurations of workload 304, 314, and 324 to operating frequency 302, 312, 322 that may be used for a circuit. In some embodiments, if the workload value is at the task storage device capacity and a greater frequency is needed to avoid a bottleneck in throughput, the operating frequency 302, 312, 322 may be increased. In addition, for each circuit, there is a maximum operating circuit frequency and a minimum operating circuit frequency, which may be viewed as the endpoints of each relationship of graphs 300, 310, and 320.

[0039] Figure 4 A flowchart 400 is shown for determining and setting a clock frequency based on a workload value according to some embodiments of the present disclosure. The flowchart shows a method performed by a control circuit, which may be Figure 2 4. In some embodiments, the steps described in flowchart 400 may be modified by, for example, rearranging, changing, adding, and / or removing steps.

[0040] In step 402, a control circuit (eg, Figure 2 The control circuit 202 of the embodiment of the present invention determines the operating load value of the circuit operating at the first clock frequency. By Figure 2 The circuit 204) has a task storage device (e.g., Figure 2 The task storage device 208 of the control circuit receives the task storage device size data to determine the first workload value. In some embodiments, the task storage device can be an instruction buffer, an instruction stack, or an instruction queue of the circuit. The load detector of the control circuit determines the first workload value when the circuit operates at the first clock frequency. When determining the first workload value, the control circuit determines whether the workload value has changed.

[0041] At step 404, the control circuit determines whether the load detector detects a decrease in the workload value of the circuit. After determining the first workload value, the load detector detects whether the task storage device size has decreased to a second workload value since determining the first workload value. If the control circuit detects a decrease in the workload value, then at step 406, the control circuit determines a second clock frequency. However, if a decrease in the workload value is not detected, then at step 410, the control circuit causes the circuit to operate at a clock frequency that is equal to or less than the first clock frequency.

[0042] At step 406, the control circuit determines a second clock frequency for the circuit. The control circuit determines the second clock frequency based on the second workload value. The clock regulator of the control circuit determines the second clock frequency by using a configured relationship between the operating clock frequency of the circuit and the workload value of the task storage device 208 (e.g., Figure 1 14). As previously described, the relationship between the operating clock frequency of the circuit and the workload value of the circuit task storage device 208 can be a linear relationship, a hyperbolic relationship, based on a step function, or any other suitable relationship. In some embodiments, the relationship between the operating clock frequency of the circuit and the workload value of the task storage device can vary. For example, within a first range of workload values, the relationship between the task storage device workload and the operating frequency is one relationship, and within a second range of workload values, the relationship between the task storage device workload and the operating frequency is another relationship, and so on.

[0043] In step 408, the control circuit causes the circuit to operate at a second clock frequency, wherein the second clock frequency is greater than the first clock frequency. The clock control of the control circuit sets the second clock frequency as a new clock signal for the circuit. As previously discussed, the workload value is reduced, so the second clock frequency is greater than the first clock frequency, so that a smaller number of commands or instructions are executed in a short burst, which can result in, for example, reducing latency (e.g., increasing the number of commands or instructions executed) by utilizing the available circuit power budget. In addition, when the control circuit sets the new clock signal frequency, the control circuit should then follow the closed-loop method 400 by determining the new workload value of the circuit at the new first clock frequency, wherein the new first clock frequency is the previous second clock frequency. In some embodiments, the control circuit causes the circuit to operate at the second clock frequency, including coupling the circuit to a voltage rail selected based on the second clock frequency in a plurality of voltage rails. In some embodiments, each of the plurality of voltage rails corresponds to a different clock frequency. In some embodiments, coupling the circuit to the voltage rail may include causing a current to flow through the circuit from the selected voltage rail. In some embodiments, the control circuit may cause the circuit to operate at the second clock frequency by changing the voltage of the circuit using a power management integrated circuit (PMIC) coupled to the circuit. In some embodiments, the PMIC uses adaptive voltage scaling (AVS), which gradually steps up or down the voltage without significantly affecting the performance of the circuit. Typically, as the voltage increases, the clock frequency also increases, and conversely, if the voltage decreases, the clock frequency decreases.

[0044] At step 410, the control circuit causes the circuit to operate at a clock frequency that is equal to or less than the first clock frequency. In some embodiments, the second workload value is the same as the first workload value, so the control circuit maintains the circuit clock frequency the same. However, as shown below Figure 5 As described in more detail in the description of , when the workload value increases, the control circuit causes the circuit to operate at a clock frequency that is less than the first clock frequency. In addition, when the control circuit causes the circuit to operate at the new clock signal frequency, the control circuit should then follow the closed-loop method 400 by determining a new workload value for the circuit at the new first clock frequency.

[0045] Figure 5 Another flow chart for determining and setting a clock frequency based on a workload value according to some embodiments of the present disclosure is shown. Flowchart 500 shows a method performed by a control circuit, which may be Figure 2 5. In some embodiments, the steps described in flowchart 500 may be modified by, for example, rearranging, changing, adding, and / or removing steps.

[0046] At step 502, the control circuit determines a workload value of the circuit operating at a third clock frequency. The third workload value is determined by receiving task storage size data from a task storage device (e.g., task storage device 208) of a circuit (e.g., circuit 204). In some embodiments, the task storage device may be an instruction buffer, an instruction stack, or an instruction queue of the circuit. A load detector of the control circuit determines a third workload value when the circuit operates at the third clock frequency. When determining the third workload value, the control circuit determines whether the workload value has changed.

[0047] At step 504, the control circuit determines whether an increase in the workload value of the circuit is detected. After determining the third workload value, the load detector detects whether the task storage device size has increased to a fourth workload value since determining the third workload value. If the control circuit detects an increase in the workload value, then at step 506, the control circuit determines a fourth clock frequency. However, if an increase in the workload value is not detected, then at step 510, the control circuit causes the circuit to operate at a clock frequency equal to or greater than the third clock frequency.

[0048] At step 506, the control circuit determines a fourth clock frequency for the circuit. The control circuit determines the fourth clock frequency based on the fourth workload value. The clock regulator of the control circuit determines the fourth clock frequency by using a configured relationship between the operating clock frequency of the circuit and the workload value of the task storage device (e.g., Figure 1 114). As previously described, the relationship between the operating clock frequency of the circuit and the workload value of the task storage device can be a linear relationship, a hyperbolic relationship, based on a step function, or any other suitable relationship. In some embodiments, the relationship between the operating clock frequency of the circuit and the workload value of the task storage device can vary. For example, within a first range of workload values, the relationship between the task storage device workload and the operating frequency is one relationship, and within a second range of workload values, the relationship between the task storage device workload and the operating frequency is another relationship, and so on.

[0049] In step 508, the control circuit causes the circuit to operate at a fourth clock frequency, wherein the fourth clock frequency is less than the third clock frequency. The clock control of the control circuit sets the fourth clock frequency as a new clock signal for the circuit. As previously discussed, the workload value increases, and therefore the fourth clock frequency is less than the third clock frequency, so as to execute a greater number of commands or instructions with less circuit power consumption while maintaining at least a minimum operating circuit clock frequency, which can improve circuit power consumption efficiency. In addition, when the control circuit sets the new clock signal frequency, the control circuit should then follow the closed-loop method 500 by determining a new workload value for the circuit at the new third clock frequency, wherein the new third clock frequency is the previous fourth clock frequency.

[0050] At step 510, the control circuit causes the circuit to operate at a clock frequency that is equal to or greater than the third clock frequency. In some embodiments, the fourth workload value is the same as the third workload value, so the control circuit keeps the circuit clock frequency the same. However, when the workload value decreases, as seen in method 400, the control circuit causes the circuit to operate at a clock frequency that is greater than the third clock frequency. In addition, when the control circuit causes the circuit to operate at the new clock signal frequency, the control circuit should then follow the closed-loop method 500 by determining the new workload value for the circuit at the new third clock frequency.

[0051] Although Figure 5 The description of FIG. 1 refers to the third and fourth clock frequencies, but it should be noted that for the operation of the circuit, the third and fourth clock frequencies do not necessarily follow each other in time. Figure 4 In one embodiment, the circuit operates in accordance with Figure 4 In another embodiment, the circuit is operated at a first clock frequency, then at a second clock frequency, then at a third clock frequency after a period of time, and finally at a fourth clock frequency (in one example, the second and third clock frequencies may be the same). Figure 4 Method 400 performs Figure 5 In this embodiment, the circuit initially operates at a third clock frequency and then operates at a fourth clock frequency. In yet another embodiment, Figure 4 Method 400 is executed before Figure 5 Method 500, in which case the circuit first operates at the third clock frequency, and then operates at the fourth clock frequency, then operates at the first clock frequency, and then operates at the second clock frequency (eg, in this example, the fourth and second clock frequencies may be the same).

[0052] In some embodiments of flowchart 400 or 500, there may be multiple circuits electrically coupled to the control circuit. In these embodiments, the control circuit may perform different steps of the method in parallel for several of the multiple circuits.

[0053] The terms "an embodiment," "embodiments," "multiple embodiments," "described embodiment," "described multiple embodiments," "one or more embodiments," "some embodiments," and "one embodiment" mean "one or more (but not all) embodiments" unless expressly stated otherwise.

[0054] The terms "including," "comprising," "having" and variations thereof mean "including but not limited to," unless expressly stated otherwise.

[0055] The enumerated listing of items does not imply that any or all of the items are mutually exclusive unless expressly stated otherwise.

[0056] The terms "a", "an" and "the" mean "one or more" unless expressly stated otherwise.

[0057] Devices that are in communication with each other need not be in constant communication with each other unless expressly specified otherwise. In addition, devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries.

[0058] The description of the embodiment with several mutually communicating parts does not mean that all such parts are needed. On the contrary, various optional parts are described to illustrate various possible embodiments. In addition, although process steps, method steps, algorithms etc. can be described in order, these processes, methods and algorithms can be configured to work in alternating order. In other words, any order or sequence of the steps that may be described does not necessarily indicate the requirement to perform these steps in this order. The steps of the process described here can be performed in any actual order. In addition, some steps can be performed simultaneously.

[0059] When a single device or article is described herein, it will be readily apparent that more than one device / article (whether or not they collaborate) may be used in place of a single device / article. Similarly, where more than one device or article is described herein (whether or not they collaborate), it will be readily apparent that a single device / article may be used in place of more than one device or article, or a different number of devices / articles may be used in place of the number of devices or programs shown. The functions and / or features of a device may be alternately embodied by one or more other devices that are not explicitly described as having such functions / features. Therefore, other embodiments need not include the device itself.

[0060] At least some of the operations that may have been shown in the accompanying drawings illustrate certain events that occur in a certain order. In alternative embodiments, certain operations may be performed, modified, or removed in a different order. In addition, steps may be added to the above logic and still conform to the described embodiments. Further, the operations described herein may occur in sequence, or certain operations may be processed in parallel. Further, operations may be performed by a single processing unit or a distributed processing unit.

[0061] The foregoing description of various embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or limited to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings.

Claims

1. A method comprising: determining, using the control circuit, a first workload value for the circuit operating at a first clock frequency; detecting, using the control circuit, a second workload value of the circuit that is less than the first workload value; as well as In response to detecting a second operating load value of the circuit, performing the following operations: calculating, using the control circuit, a second clock frequency that is greater than the first clock frequency of the circuit, and The control circuit is used to cause the circuit to operate at a second clock frequency.

2. The method of claim 1, wherein the circuit is one of a solid state drive (SSD) pipeline hardware accelerator or a network controller pipeline hardware accelerator. 3 . The method of claim 1 , wherein the first workload value and the second workload value measure a number of instructions scheduled for execution by the circuit.

4. The method of claim 3, wherein the instructions are stored in a task storage device communicatively coupled to the circuit. The method of claim 1 , wherein calculating the second clock frequency comprises calculating the second clock frequency based on the second workload value using a linear function.

6. The method of claim 5, wherein using a linear function to calculate the second clock frequency is further based on: The minimum operating clock frequency of the circuit; the maximum operating clock frequency of the circuit; and A ratio of the second workload value to the maximum workload capacity of the circuit.

7. The method of claim 1 , wherein calculating the second clock frequency comprises: comparing the second workload value to a reference workload value; In response to determining that the second workload value is less than the reference workload value, selecting the third clock frequency as the second clock frequency; as well as In response to determining that the second workload value is greater than the reference workload value, a fourth clock frequency that is lower than the third clock frequency is selected as the second clock frequency.

8. The method of claim 1 , wherein calculating the second clock frequency comprises: determining a range corresponding to the second workload value from a plurality of workload value ranges, wherein each range in the plurality of workload value ranges corresponds to a corresponding clock frequency; as well as A clock frequency corresponding to the determined range is selected as the second clock frequency.

9. The method according to claim 1, further comprising: determining a third workload value for the circuit operating at a third clock frequency; detecting a fourth workload value of the circuit that is greater than the third workload value; as well as In response to detecting a fourth operating load value of the circuit, performing the following operations: a fourth clock frequency of the computing circuit that is less than the third clock frequency, and The circuit is caused to operate at a fourth clock frequency.

10. The method of claim 1 , wherein causing the circuit to operate at the second clock frequency comprises: The circuit is coupled to a voltage rail of the plurality of voltage rails selected based on the second clock frequency.

11. The method of claim 1 , wherein causing the circuit to operate at the second clock frequency comprises: The voltage of the circuit is varied using a power management integrated circuit (PMIC) coupled to the circuit.

12. A system comprising: Circuit; as well as A control circuit is communicatively coupled to the circuit, the control circuit being configured to: determining a first workload value for a circuit operating at a first clock frequency; detecting a second operating load value of the circuit that is less than the first operating load value; and In response to detecting a second operating load value of the circuit, performing the following operations: a second clock frequency of the computing circuit that is greater than the first clock frequency, and The circuit is caused to operate at a second clock frequency.

13. The system of claim 12, wherein the first workload value and the second workload value measure a number of instructions scheduled for execution by the circuit.

14. The system of claim 13, wherein the instructions are stored in a task storage device communicatively coupled to the circuit.

15. The system of claim 12, wherein the control circuit is to calculate the second clock frequency of the circuit by calculating the second clock frequency based on the second workload value using a linear function.

16. The system of claim 15, wherein the linear function is further based on: The minimum operating clock frequency of the circuit; the maximum operating clock frequency of the circuit; and The ratio of the reduced workload value to the maximum workload capacity of the circuit.

17. The system of claim 12, wherein the control circuit further determines the second clock frequency by: comparing the second workload value to a reference workload value; In response to determining that the second workload value is less than the reference workload value, operating the circuit at a third clock frequency; and In response to determining that the second workload value is greater than the reference workload value, the circuit is operated at a fourth clock frequency that is lower than the third clock frequency.

18. The system of claim 12, wherein the control circuit further determines the second clock frequency by: determining a range corresponding to the second workload value from a plurality of workload value ranges, wherein each range in the plurality of workload value ranges corresponds to a corresponding clock frequency; and A clock frequency corresponding to the determined range is selected as the second clock frequency.

19. The system of claim 12, wherein the control circuit further causes the circuit to operate at the second clock frequency by coupling the circuit to a voltage rail among the plurality of voltage rails selected based on the second clock frequency.

20. The system of claim 12, wherein the control circuit is further configured to cause the circuit to operate at the second clock frequency by varying a voltage of the circuit using a power management integrated circuit (PMIC) coupled to the circuit.

21. A solid state drive (SSD) storage system comprising: SSD pipeline accelerator: A storage controller is communicatively coupled to the SSD pipeline accelerator, the storage controller being configured to perform the following operations: determining a first workload value for a circuit operating at a first clock frequency; detecting a second operating load value of the circuit that is less than the first operating load value; and In response to detecting a second operating load value of the circuit, performing the following operations: a second clock frequency of the computing circuit that is greater than the first clock frequency; The circuit is caused to operate at a second clock frequency.

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