Multiprocessor interconnection system, processor group and processors

Abstract

The invention relates to the technical field of chip design, in particular to a multiprocessor interconnection system, a processor group and processors, the system comprises N groups of processors, and each group comprises M processors; wherein the jth processor Pij of the ith group comprises a first type of intergroup interfaces and a second type of intergroup interfaces; the first class of intergroup interfaces of the Pij are connected with the second class of intergroup interfaces of the PNext (i) Nmap (i, j), and the Nmap (i, j) is a mapping function of a processor interconnected with the Pij in the Next (i); the second class of inter-group interfaces of the Pij are connected with the first class of inter-group interfaces of Pmap (i, j) of the Prev (i), and the Pmap (i, j) is a mapping function of a processor interconnected with the Pij in the Prev (i). According to the method, the purposes of expanding the computing power of the system, realizing concurrency to the maximum extent and balancing the communication pressure are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a multi-processor interconnection system, a processor group and a processor. Background Art

[0002] In the field of chip design, multi-processor interconnection is one of the core strategies for expanding the computing power of the system. Multi-processor interconnection can not only improve the computing power and throughput of the system, but also increase the flexibility of the system, so that the chip can cope with more complex and changeable computing tasks. At present, common multi-processor interconnection topologies include full interconnection topology and ring topology. When the computing power of the system is insufficient, the interconnection topologies in multiple servers can be connected in sequence through a single cable, so as to achieve the purpose of expanding the computing power. The technology of interconnecting the interconnection topologies in the server using cables can refer to the patent with publication number CN110461111A. Further, considering that the increase in the number of hops will directly affect the communication efficiency and system performance, in order to solve this problem, the interconnection system provided by patent publication number CN112416850A includes multiple groups of processors, the processors in each group are interconnected in pairs, and the different processors in any two groups are connected one-to-one. When exchanging data, the system can first complete the data exchange within the group, and then complete the data exchange between groups through one hop, so as to achieve the purpose of reducing the number of communication hops between processors. The system provided by patent publication number CN106776014B includes a cube topology with multiple corresponding vertices interconnected, each vertex in the cube topology is a computing unit, when exchanging data, first synchronize the node data in the same plane in the cube topology, then synchronize the node data in the opposite plane in the same cube, and finally synchronize the node data in different cubes; in this system, for each additional cube topology, the number of hops increases by 1, and the number of control hops reaches log2N. In order to reduce the number of communication hops during AllReduce collective communication, the system provided by patent publication number CN115129655A includes multiple groups, each processing unit in each group is connected to another processing unit in the same group through two communication links and connected to a processing unit in other groups through one communication link. When AllReduce collective communication is performed based on this system, each processing unit first collects data from all other processing units in the same group through one hop, and then each processing unit exchanges data with other groups through one hop, and finally each processing unit broadcasts the obtained data to other processors in the group, completing AllReduce collective communication, reducing the number of communication hops.

[0003] The above expansion solutions are all for reducing the number of hops in data exchange. However, when facing large model scenarios, since large models involve a large number of parameter updates and gradient synchronization, which require frequent communication, their traffic characteristics are explosive large traffic. When expanding the computing power of the system, it is necessary to consider concurrency. The above solutions cannot meet the needs of large model scenarios for high concurrency and high computing power. Summary of the invention

[0004] In view of the above technical problems, the technical solution adopted by the present invention is:

[0005] In a first aspect, the present invention provides a multi-processor interconnection system, the system comprising N groups of processors, each group comprising M processors, N>2, M>1; wherein the jth processor P of the i-th group ij Including the first type of inter-group interface and the second type of inter-group interface, 1≤i≤N, 1≤j≤M; P ij The first type of inter-group interface and P Next(i)Nmap(i,j) The second type of inter-group interface has a bandwidth of B1 ij connection; where P Next(i)Nmap(i,j) is the Nmap(i,j)th processor of the Next(i)th group, the function value of Next(i) is the next group of the i-th group; Nmap(i,j) is the processor in Next(i) that is connected to P ij The mapping function of the interconnected processors; P ij The second type of inter-group interface and P Prev(i)Pmap(i,j) The first type of inter-group interface has a bandwidth of B2 ij connection; where P Prev(i)Pmap(i,j) is the Pmap(i,j)th processor of the Prev(i)th group, the function value of Prev(i) is the previous group of the i-th group; Pmap(i,j) is the processor in Prev(i) that is consistent with Pmap(i,j) ij The mapping function of the interconnected processors; where B1 ij and B2 ij match.

[0006] In a second aspect, the present invention provides a processor group, the processor group includes M processors, M>1; wherein the jth processor P j Including the first type of inter-group interface and the second type of inter-group interface, 1≤j≤M; P j The first type of inter-group interface is used with bandwidth B1 j Connect to the Nmap(i,j)th processor of the Next(i)th group, where i is P j The number of the processor group where it is located, the function value of Next(i) is P j The next group of processors in which Nmap(i,j) is located; Nmap(i,j) is the next group of processors in Next(i) jThe mapping function of the interconnected processors; P j The second type of inter-group interface is used for bandwidth B2 j Connect the Pmap(i,j)th processor of the Prev(i)th group, where the function value of the Prev(i)th group is P j The previous group of processors in which the processor is located; the Pmap(i,j) is the same as P in Prev(i) j Mapping function of interconnected processors; where B1 and B2 match, B1 = ∑ j＝1 M B1 j , B2=∑ j＝1 M B2 j .

[0007] In a third aspect, the present invention provides a processor, comprising a first type of inter-group interface and a second type of inter-group interface; the first type of inter-group interface is used to connect to the second type of inter-group interface of the Nmap(i,j)th processor of the Next(i)th group with a bandwidth of BW1, wherein i is the number of the processor group to which the current processor belongs, and the function value of Next(i) is the next group of the processor group to which the current processor belongs; Nmap(i,j) is a mapping function of the processors interconnected with the current processor in Next(i); the second type of inter-group interface is used to connect to the first type of inter-group interface of the Pmap(i,j)th processor of the Prev(i)th group with a bandwidth of BW2, wherein the function value of Prev(i) is the previous group of the processor group to which the current processor belongs; Pmap(i,j) is a mapping function of the processors interconnected with the current processor in Prev(i); wherein BW1 and BW2 match.

[0008] The present invention has at least the following beneficial effects:

[0009] The embodiment of the present invention provides a multi-processor interconnection system, a processor group and a processor, which use a first-type inter-group interface to connect the processors of the next group, and use a second-type inter-group interface to connect the first-type inter-group interface of the previous group, which not only expands the computing power of the system, maximizes concurrency, and balances communication pressure; and each processor in the system is connected to the upper and lower groups through only two interfaces, which is not limited by the number of the processor's own interconnection interfaces, and realizes unlimited expansion. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 A schematic diagram of the structure of a multi-processor interconnection system when the mapping function provided in the first embodiment of the present invention is single-valued;

[0012] Figure 2 A schematic diagram of the topological structure of a 16-card interconnection system provided in Embodiment 1 of the present invention;

[0013] Figure 3 A schematic diagram of the topological structure of a 32-card interconnection system provided in Embodiment 1 of the present invention;

[0014] Figure 4 A schematic diagram of the topological structure of a 32-card interconnection system when the mapping function provided in the first embodiment of the present invention is a vector;

[0015] Figure 5 The topological structure diagram of the OAM protocol supporting up to 8 processors interconnected;

[0016] Figure 6 A schematic diagram of a first interconnection system provided in Embodiment 2 of the present invention;

[0017] Figure 7 A schematic diagram of a second interconnection system provided in Embodiment 2 of the present invention;

[0018] Figure 8 A schematic diagram of a third interconnection system provided in Embodiment 2 of the present invention;

[0019] Fig. 9 This is a schematic diagram of a fourth interconnection system provided in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0021] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meanings as commonly understood by those skilled in the art.

[0022] Embodiment 1

[0023] Embodiment 1 of the present invention provides a multi-processor interconnection system, which includes N groups of processors, each group includes M processors, N>2, M>1.

[0024] In one embodiment, the processor is a graphics processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), or a general purpose computing on GPU (GPGPU). Other types of processors also fall within the scope of protection of the present invention.

[0025] In another embodiment, the processor is a module or expansion card that complies with a specified standard.

[0026] In one embodiment, the processor is an OAM module, which is a modular accelerator that complies with the OAM (Optical Accelerator Module) standard, and the OAM module includes a processor, such as a GPU or an NPU. Processors of other standard module types also fall within the scope of protection of the present invention. Among them, the OAM module can have different names, for example, when the OAM module includes a GPU, it can also be called an OAM GPU module. Of course, in future communication systems, the OAM module can also have different names, which are not limited here. When the processor is an OAM module, the OAM module supports 7 interconnection interfaces (Serializer / Deserializer, serdes) for interconnection or expansion interfaces between OAMs. Among them, each interface can be flexibly configured to a different number of channels. For example, each interface is configured as a group of 16 high-speed serial channels, or configured as two groups and each group is 8 high-speed serial channels, or configured as four groups and each group is 4 high-speed serial channels, or configured as 16 groups and each group is 1 high-speed serial channel; other configuration modes of the configuration interface also fall within the scope of protection of the present invention.

[0027] In one embodiment, the protocol supported by the interface is NVLink (NVIDIA Link), MetaXLink (MetaXLink), UCIe standard (Universal Chiplet Interconnect Express) or PCIe (Peripheral Component Interconnect Express), and other interface protocols for achieving high-speed interconnection between processors also fall within the scope of protection of the present invention.

[0028] In one embodiment, the processor is an expansion card that complies with the PCIe (Peripheral Component Interconnect Express) standard, and the expansion card includes a processor, such as a GPU or an NPU. Expansion cards that comply with other standards also fall within the protection scope of the present invention.

[0029] In one embodiment, each group of processors in the system is integrated into the same board or server. Alternatively, each basic group is integrated into the same board or server, and each basic group includes N1 bound, indivisible processor groups, where N1≤N. For example, N1=2, that is, two unit groups are a basic group, which are integrated into the same board, and the physical distance between processors integrated into the same board is short, and the communication delay is low. The interconnected system obtained by configuring the processor in other types of devices or configuring it with other configuration strategies also falls within the protection scope of the present invention.

[0030] Furthermore, the jth processor P of the i-th group ij Including the first type of inter-group interface and the second type of inter-group interface, 1≤i≤N, 1≤j≤M; P ij The first type of inter-group interface and P Next(i)Nmap(i,j) The second type of inter-group interface connection; where P Next(i)Nmap(i,j) is the Nmap(i,j)th processor of the Next(i)th group, the function value of Next(i) is the next group of the i-th group; Nmap(i,j) is the processor in Next(i) that is connected to P ij The mapping function of the interconnected processors; P ij The second type of inter-group interface and P Prev(i)Pmap(i,j) The first type of inter-group interface connection; where P Prev(i)Pmap(i,j) is the Pmap(i,j)th processor of the Prev(i)th group, the function value of Prev(i) is the previous group of the i-th group; Pmap(i,j) is the processor in Prev(i) that is consistent with Pmap(i,j) ij Mapping functions of interconnected processors.

[0031] Among them, the "first category" in the first category of inter-group interfaces and the "second category" in the second category of inter-group interfaces do not indicate order or weight. For the convenience of understanding and description, "first category" is used to distinguish the interfaces used to connect to the previous group of processors, and "second category" is used to distinguish the interfaces used to connect to the next group of processors. Similarly, for the convenience of understanding and description, "inter-group" is used to distinguish that the processor connected to the interface is another processor of a different group, and "intra-group" is used to distinguish that the processor connected to the interface is another processor of the same group. Similarly, the processor group number and the processor number are not built-in numbers of the processor group or the processor itself. For the convenience of understanding and description, the processor group number is only used to distinguish different processor groups, and the processor number is only used to distinguish different processors.

[0032] In one embodiment, the connection between the first type of inter-group interface and the second type of inter-group interface is an electrical connection line or an optical fiber connection line. Other types of connection lines for interconnection interfaces for connecting two processors across groups fall within the protection scope of the present invention.

[0033] In one embodiment, when the distance between groups is short, the connection between the first type of group interface and the second type of group interface is an electrical connection line. When the distance between groups is long or high bandwidth and low latency, the connection between the first type of group interface and the second type of group interface is an optical fiber connection line.

[0034] Other types of connections or other types of connection media between the first type inter-group interface and the second type inter-group interface also fall within the protection scope of the present invention.

[0035] In one implementation, the connection between the first type inter-group interface and the second type inter-group interface supports bidirectional transmission and also supports unidirectional transmission.

[0036] Among them, considering each group as a node, the N nodes corresponding to the N groups of processors form a chain topology or a ring topology.

[0037] In one embodiment, when the topology formed by the interconnected system is a ring topology with each group as one node, Next(i) and Prev(i) respectively satisfy: if i=N, then Next(i)=1; otherwise, Next(i)=i+1. If i=0, then Prev(i)=N; otherwise, Prev(i)=i-1.

[0038] In one embodiment, when the topology formed by the interconnection system is a chain topology with each group as one node, Next(i) and Prev(i) respectively satisfy: if i=N, then Next(i)=NULL, where NULL is empty; otherwise, Next(i)=i+1. If i=0, then Prev(i)=NULL; otherwise, Prev(i)=i-1.

[0039] In order to adapt to different computing scenarios, other types of interconnection topologies formed by adjusting the relationship satisfied by Next(i) and Prev(i) also fall within the protection scope of the present invention.

[0040] In one embodiment, the P ij The first type of inter-group interface and P Next(i)Nmap(i,j) The second type of inter-group interface has a bandwidth of B1 ij connection; the P ij The second type of inter-group interface and P Prev(i)Pmap(i,j) The first type of inter-group interface has a bandwidth of B2 ij Connection; among them, B1 i and B2 i Match, B1 i =∑ j＝1 M B1 ij , B2 i =∑ j＝1 M B2 ij .

[0041] Among them, for each group of processors, the total bandwidth B1 of each group of processors connected to the next group i and the total bandwidth B2 of the previous group i Matching. It should be noted that bandwidth matching refers to bandwidth equality, but not strict bandwidth equality. When the error between the two bandwidths is within an acceptable range, the bandwidth is considered to be matched. The total bandwidth matching between each group of processors and the connected upper and lower groups can enable data to be transmitted efficiently between groups, reduce data transmission delays and system bottlenecks, and improve the overall system operation efficiency.

[0042] In one embodiment, B1 ij and B2 ij Matching. That is, the bandwidth matching of each processor connecting the upper and lower groups. This bandwidth matching strategy enables each processor to fully utilize its allocated bandwidth resources, so that data can flow smoothly between processors connected in sequence through the inter-group interface. The insufficient bandwidth of a processor will not become a bottleneck for the interconnection between groups. At the same time, it avoids bandwidth waste and ensures smooth and efficient data transmission. When more processors need to be added, it is only necessary to ensure that the bandwidth between the newly added processors and the existing processors matches, so that the system can be more easily expanded to larger-scale parallel computing.

[0043] In one embodiment, the kth processor P of the i-th group ik The first type of inter-group interface and P Next(i)Nmap(i,k) The second type of inter-group interface has a bandwidth of B1 ikConnect the B1 ik and B1 ij The relationship between them satisfies: B1 ik =B1 ij , where the value of Nmap(i,k) is the value of Next(i) that matches P ik For interconnected processors, 1≤k≤M and k≠j. That is, on the basis of bandwidth matching between a single processor and the upper and lower groups, the bandwidths of different processors in the same group are further made the same. When designing a data transmission path, there is no need to consider the bandwidth matching problem, which simplifies the design logic of the data transmission path. The bandwidths of all data transmission paths in the interconnected system are the same, so that data can flow smoothly throughout the system, and the bandwidth problem of a certain processor will not become a bottleneck for the entire system, thereby improving transmission efficiency. This bandwidth matching strategy can be more efficient when performing data synchronization and collective communication, allowing processors to work together efficiently to complete complex parallel computing tasks.

[0044] The value of the mapping function indicates the number of the processor in the previous group or the next group to which the current processor is connected. The mapping functions Nmap(i,j) and Pmap(i,j) have the same function properties. Nmap(i,j) is used as an example to illustrate the properties of the mapping function. For each pair of different input parameters (i,j), the mapping function Nmap(i,j) will return a unique output value; and when the value of Nmap(i,j) is determined, the value of (i,j) is unique. That is, there is a one-to-one mapping relationship between the value of the mapping function Nmap(i,j) and the input parameter (i,j). The advantages of each processor in each processor group being connected to the corresponding processor in the upper and lower groups through a mapping function include: first, each processor in the same group has the ability to independently send data to the corresponding processor in the upper and lower groups connected to it, and multiple data transmission operations can be performed almost simultaneously in the same time period without waiting for each other. This data transmission method logically constitutes concurrency and improves the overall processing power and throughput of the system; second, each processor can directly transmit data to the corresponding processor in the upper and lower groups, reducing the number of data transmission hops and potential delays, while also facilitating data transmission between processors, helping to achieve more efficient load balancing; third, the number of inter-group interfaces occupied by each processor in the system is fixed and will not increase with the increase in the number of processors, and can be expanded infinitely.

[0045] Among them, when the conditions satisfied by Nmap(i,j) and Pmap(i,j) are different, different interconnection topologies will be formed. When the function values ​​of Nmap(i,j) and Pmap(i,j) are single values, each processor is connected to a processor in the upper and lower groups respectively; the connection structure of this scheme is simple, easy to implement and maintain, and easy to expand to a larger scale when more processors need to be added. When the function values ​​of Nmap(i,j) and Pmap(i,j) are vectors, each processor is connected to multiple processors in the upper and lower groups. When the values ​​of Nmap(i,j) and Pmap(i,j) are a value, there are also many different connection methods.

[0046] In one embodiment, when the function values ​​of Nmap(i,j) and Pmap(i,j) are single values, Nmap(i,j) and Pmap(i,j) satisfy: Nmap(i,j)=Pmap(i,j)=Nmap(j), and when j1≠j2, Nmap(j1)≠Nmap(j2), that is, each processor is connected to a processor in the upper and lower groups, and the numbers of the connected processors are the same. Since the connection relationship is only related to the processor number and has no direct correlation with the group number in the system, the complexity of system design and the logic of task allocation are simplified. In addition, when the system is expanded or reconfigured, it is only necessary to maintain the consistency of the processor number without considering the boundaries between groups.

[0047] In one implementation, Nmap(j)=Pmap(j)=j, where j is the logical number of the processor. That is, each processor in the system is connected to a processor in the upper and lower groups with the same number as itself. The framework is more intuitive and easy to understand, which not only facilitates resource management and task allocation, but also reduces the complexity of development and maintenance.

[0048] Adjusting the value of the mapping function so that the processor can be connected to other interconnection systems with different numbers also falls within the protection scope of the present invention.

[0049] For ease of understanding, the multi-processor interconnection system is described by taking Nmap(j)=Pmap(j)=j and the topology formed by the interconnection system as an example of a ring topology with each group as one node. Figure 1 , Figure 1 A schematic diagram of a multi-processor interconnection system is shown, the system includes N groups of processors {G1, G2, ..., G i-1 ,G i ,G i+1 ,…,G N}, G i is the i-th group, and the value of i ranges from 1 to N. G i It includes M processors {P i1 ,Pi2 ,…,P ij ,…P iM}, P ij G i The jth processor of G, the value of j ranges from 1 to M. i Each processor and G i+1 The topological connection formed by each processor, G i and G i+1 M links are formed between i1 ,Nlink i2 ,…,Nlink ij ,…,Nlink iM}, where Nlink ij P ij The first group interface and G i+1 The jth processor P (i+1)j The connection between the second group of interconnection interfaces. That is, Nlink i1 P i1 The first type of inter-group interface and G i+1 The first processor P (i+1)1 The connection between the second type of inter-group interfaces, Nlink i2 P i2 The first group interface and G i+1 The second processor P (i+2)2 The second group of interconnection interfaces are connected, and so on. iM P iM The first group interface and G i+1 The Mth processor P (i+1)M The connection between the second group of interconnection interfaces. i+1 The M lines connected make each processor in each group connected to G i+1 The corresponding processors in G i and G i-1 M lines are formed between {Plink i1 ,Plink i2 ,…,Plink ij ,…,Plink iM}, where Plink ij P ij The first group interface and G i-1 The jth processor P (i+1)j By analogy, N groups of processors are interconnected to form a ring topology.

[0050] In one embodiment, M = 4. In another embodiment, M = 2 or M = 6. Other values ​​of M greater than 1 also fall within the protection scope of the present invention.

[0051] In one embodiment, M=4, and N is a multiple of 2. When M=4 and N=4, it is a system with 16 interconnected cards. When M=4 and N=6, it is a system with 24 interconnected cards. When M=4 and N=8, it is a system with 32 interconnected cards. When M=4 and N=10, it is a system with 40 interconnected cards, and so on. The scale of the multi-processor interconnection system can be expanded according to demand.

[0052] As an example, for ease of understanding, Figure 1 Based on N=M=4, please refer to Figure 2 , which shows a schematic diagram of the topology of a 16-card interconnection system, in which there are 4 groups of processors: G1-G4. Each group includes 4 processors. Each processor includes a first-type inter-group interface and a second-type inter-group interface. Each group is connected to the upper and lower groups by 4 lines. Taking the second group G2 as an example, there are 4 first lines connected between G2 and G3: G2's P 21 Connect G3's P 31 , G2's P 22 Connect G3's P 32 , G2's P 23 Connect G3's P 33 , G2's P 24 Connect G3's P 34 There are also four second lines connecting G2 and G1: 21 Connect G1's P 11 , G2's P 22 Connect G1's P 12 , G2's P 23 Connect G1's P 13 , G2's P 24 Connect G1's P 14 Similarly, four groups of processors are interconnected to form a ring topology.

[0053] As another example, for ease of understanding, in Figure 2 Based on N=8 and M=4, please refer to Figure 3 , which shows a schematic diagram of the topology of a 32-card interconnection system, which includes 8 groups of processors: G1-G8. Figure 2The same topology is provided in that each group includes 4 processors. The 8 groups of processors are connected in sequence. Similarly, each group of processors is connected to the next group of processors through 4 lines through the first type of inter-group interconnection interface, and is connected to the previous group of processors through 4 lines through the second type of inter-group interface. It can be seen that when the scale of the interconnection system is doubled, each processor still occupies two interfaces to achieve interconnection. In other words, expanding the scale of the interconnection system does not consume the number of processor interfaces, so in theory the interconnection system can be infinitely expanded. And the connection strategy of the added processor group is the same as the connection strategy of the processor group that already exists in the interconnection system, and it only needs to comply with the corresponding mapping function. The expansion logic is simple and easy to expand.

[0054] In one implementation, Nmap(i,j) and Pmap(i,j) are both vectors containing L elements, each element is the number value of a processor, and the values ​​of the L elements are different, where 1<L≤M. That is, each processor is connected to the L processors of the upper and lower groups, and compared with the interconnection system solution in which each processor occupies two inter-group interfaces, the inter-group bandwidth is increased by L times, and the transmission rate is increased by L times.

[0055] As an example, for ease of understanding, take N=8, M=4 and L=2 as an example, see Figure 4 , Figure 4 is Figure 3 On the basis of each processor, two inter-group interfaces are added, that is, each processor includes two first-type inter-group interfaces and two second-type inter-group interfaces. Figure 4 The second processor P of the second group G2 22 and the third processor P 23 As an example, the interconnection relationship between two first-class inter-group interfaces and two different processors in the next group is explained. 22 Through two first-class inter-group interfaces, they are connected to G3's P 32 and the G3's fourth processor P 34 Connection; G2 P 23 Through two first-class inter-group interfaces, they are connected to G3's P 33 and P 31 Connect. Then use P in G2 22 and P 23 As an example, the interconnection relationship between two first-class inter-group interfaces and two different processors in the next group is explained. 22 Through two second-type inter-group interfaces, they are respectively connected to the P 12 and P 14 Connect. G2 P 23 Through two second-type inter-group interfaces, they are connected to G1's P 13 and P 11Connection. That is, P of G2 22 and P 23 The corresponding inter-group interfaces are used to connect different processors in the previous group and the next group. Similarly, the first processor P of G2 21 and the fourth processor P 24 The remaining different processors in one group and the next group are connected respectively. That is, each processor occupies 4 inter-group interfaces, of which two inter-group interfaces are connected to the next group, and two inter-group interfaces are connected to the previous group, so there are 8 lines between two adjacent groups. On the basis of occupying two inter-group interfaces to achieve infinite expansion, two more inter-group interfaces are occupied to connect the processors in the previous group and the next group respectively, that is, occupying four interconnection interfaces of each processor. On the basis of achieving infinite interconnection, compared with the interconnection system occupying two interconnection interfaces, the bandwidth can be doubled and the transmission rate can be doubled.

[0056] In one embodiment, N>2 and N≠4.

[0057] In one embodiment, P ij The first type of inter-group interface is only with P Next(i)Nmap(i,j) The second type of inter-group interface connection; P ij The second type of inter-group interface is only with P Prev(i)Pmap(i,j) The first type of inter-group interface connection. That is, for P ij For example, its first-type inter-group interface is only used to connect to the second-type inter-group interface of the next group, and its second-type inter-group interface is only used to connect to the second-type inter-group interface of the previous group.

[0058] In one embodiment, P ij It also includes M-1 intra-group interfaces, among which P ij The fth intra-group interface PI ij,f The hth intra-group interface PI with the rth processor of the ith group ir,h Connect, 1≤r≤M and j≠r, 1≤r≤M-1.

[0059] In one implementation, the topology formed by interconnecting the M processors of the i-th group through the intra-group interface is a ring topology, a full interconnection topology or a tree topology, and other topologies also fall within the protection scope of the present invention.

[0060] In one embodiment, data may be exchanged more frequently within a group than between groups, so P ij The total bandwidth of all interfaces within the group is greater than the total bandwidth of all interfaces between groups. The total bandwidth of all interfaces between groups is the bandwidth B1 of the first interface between groups. ij Bandwidth B2 of the interface between the second group ij sum.

[0061] A multi-processor interconnection system provided by the first embodiment of the present invention, in which each processor is directly connected to the corresponding processors in the upper and lower groups, and the number of processors in each group is the same, and this design helps to achieve load balancing. In collective communication, each processor can process data and communicate with other processors at the same time, improving the overall concurrency capability. When more processors need to be added to improve system performance, new processor groups can be simply added. This design makes the system have good scalability, thereby meeting the needs for high computing power and high concurrency.

[0062] It should be noted that the embodiments of the present invention, in addition to being applicable to collective communication, also support other types of communication modes, such as point-to-point communication, broadcast communication, etc. Other types of communication modes also fall within the protection scope of the present invention.

[0063] Embodiment 2

[0064] Based on the same inventive concept as the first embodiment, the second embodiment of the present invention provides a multi-processor interconnection system, which can solve the problem of how to expand the number of processor interconnections while complying with the original protocol. Since the OAM protocol supports a maximum of 8 processor interconnection topologies, please refer to Figure 5 ,exist Figure 5 There are a total of 8 processors including OAM0-OAM7. Any two processors can be directly interconnected, that is, point-to-point interconnection. The interconnection protocol is the OAM protocol. In the OAM protocol, when the addresses of the source processor and the destination processor are determined, the route between the two will also be uniquely determined, because the route between the source processor and the destination processor is fixed in the hardware and cannot be changed. The route is {source processor address, source processor interface index number, destination processor address, destination processor interface index number}. However, in the training and reasoning of large models, point-to-point full interconnection between processors is not required. It is only necessary to support collective communication (collectives) modes such as Allreduce and Alltoall. Among them, the allreduce mode refers to collecting and aggregating data from each graphics card, and then distributing the aggregated results to each graphics card. The alltoall mode means that the data of each node will be distributed to each graphics card, and the data of each graphics card will also be collected. Therefore, the processors can be interconnected point-to-point or through forwarding by other processors. The following will Figure 5The topology in is called the original topology, and it will not be stated below. In order to solve the problem of how to expand the number of processor interconnections while complying with the original protocol, the values ​​of Nmap(i,j) and Pmap(i,j) in the topology formed by the interconnection system are single-valued, and the topology formed by the M processors of the i-th group through the intra-group interface interconnection is an interconnection system formed by a fully interconnected topology. That is, the system includes N groups of processors, each group includes M processors, and the positions of the processors in each group are distributed in the same way. Each group of processors includes two layers of interconnection structure: intra-group interconnection structure and inter-group interconnection structure. The point-to-point full connection between the M processors in the intra-group interconnection structure forms a fully interconnected topology. The inter-group interconnection structure includes M ring connection structures, and each processor connected in the ring connection structure has the same distribution position in each group of processors, that is, each processor is connected to a processor in the previous group and to another processor in the next group.

[0065] As a preferred embodiment, the software address remapping table is searched to obtain the remapping address of each processor address in the interconnection system, and the route corresponding to the remapping address is obtained. The software address remapping table includes each processor address and its remapping address. When the processor address is less than 7, that is, any one of S0-S7, the remapping address of the processor address is itself. When the processor address is greater than 7, the remapping address of the processor address is the modulo of the processor address. The software address remapping table is searched according to the addresses of the source processor and the destination processor to obtain the remapping address of each processor. All processor addresses of N groups of processors are remapped to S0-S7 through the software address remapping table, so that the processor addresses during data transmission conform to the interconnection routes fixed in the hardware. In compliance with the original protocol, the number of processor interconnections is expanded.

[0066] See also Figure 6 , Figure 7 , Figure 8 and Fig. 9 ,in, Figure 6-8 Three types of interconnection topologies are provided, and the difference lies in the different interface numbers occupied by each processor interconnection. Fig. 9 Provides a 32-card interconnection topology. It should be noted that: Figure 6 , Figure 7 , Figure 8 and Fig. 9 In the provided interconnection system, the j-th processor of the i-th group is connected to the processor numbers of the upper and lower groups satisfying Nmap(i,j) and Pmap(i,j), and the values ​​of Nmap(i,j) and Pmap(i,j) are single values, that is, each processor is connected to a processor of the upper and lower groups respectively.

[0067] Please refer to the attached Figure 6, which shows the first type of interconnect topology. Figure 6 The interconnection system includes 4 groups, each with 4 processors, and the entire interconnection system has a total of 16 processors. The first group G1 includes P 11 , P 12 , P 13 and P 14 , the second group G2 includes P 21 , P 22 , P 23 and P 24 , the third group G3 includes P 31 , P 32 , P 33 and P 34 , the fourth group G4 includes P 41 , P 42 , P 43 and P 44 Each processor includes 7 interfaces. Each interface in each processor corresponds to a unique index number. The index numbers of different processors are independent, that is, the index numbers of interfaces in different processors are all from the first interface index number inf1 to the seventh interface index number inf7. Figure 6 In the interconnection topology of 16 processors, each processor occupies a total of 5 interfaces. In each group of processors, the same three interfaces are used as intra-group interfaces to achieve full interconnection. Figure 6 In the example, the full interconnection within the group is realized through the intra-group interfaces inf1, inf2 and inf3 to form a fully interconnected topology. Inter-group interconnection is achieved by using two interfaces of the remaining interfaces of the interconnected processors as the first-type inter-group interface and the second-type inter-group interface, respectively. The processors of the next group are connected through the first-type inter-group interface, and the processors of the previous group are connected through the second-type inter-group interface to form a ring structure.

[0068] Among them, P 11 , P 21 , P 31 and P 41 The distribution positions in each group of processors are the same, and P 11 , P 21 , P 31 and P 41 In the interconnection structure formed by interconnection, the connection between the index numbers of the interfaces is as follows: 11 inf7 connection P 21 inf7,P 21 inf4 connection P 31 inf4,P 31 inf7 connection P 41 inf7,P 41 inf6 connection P 11inf6, connected end to end to form a ring structure. 12 , P 22 , P 32 and P 42 The distribution positions in each group of processors are the same, and P 12 , P 22 , P 32 and P 42 In the interconnection structure formed by interconnection, the connection between the index numbers of the interfaces is as follows: 12 inf7 connection P 22 inf7,P 22 inf4 connection P 32 inf4,P 32 inf7 connection P 42 inf7,P 42 inf6 connection P 12 inf6, connected end to end to form a ring structure. 14 , P 24 , P 34 and P 44 The distribution positions in each group of processors are the same, and P 14 , P 24 , P 34 and P 44 The interconnection forms an interconnection structure, and the connection between the index numbers of the interfaces is as follows: 14 inf7 connection P 24 inf7,P 24 inf6 connection P 34 inf6,P 34 inf7 connection P 44 inf7,P 44 inf4 connection P 14 inf4, connected end to end to form a ring structure. 13 , P 23 , P 33 and P 43 The distribution positions in each group of processors are the same, and P 13 , P 23 , P 33 and P 43 The interconnection forms an interconnection structure, and the connection between the index numbers of the interfaces is as follows: 13 inf7 connection P 23 inf7,P 23 inf6 connection P 33 inf6,P 33 inf7 connection P 43 inf7,P 43inf4 connection P 14 inf4, connected end to end to form a ring structure.

[0069] exist Figure 6 Based on the software address remapping table, P 11 -P 44 These 16-bit processor addresses are remapped to P 11 -P 24 The 8-bit processor address. Figure 6 The interconnection routing between any two processors in Figure 1 The interconnection routes of the original 8 processors are the same. That is, the expansion of interconnected processors is achieved without changing the fixed routes in the hardware.

[0070] It should be noted that Figure 6 The index numbers of the interfaces forming the ring-type group interconnection structure are inf7, inf6 and inf4. According to the order of the ring structure, the index numbers of the interconnection interfaces are inf7, inf6, inf7 and inf4 or inf7, inf4, inf7 and inf6. Optionally, the equivalent implementation of the index number of the interconnection interface can also be inf6, inf7, inf6 and inf4 or inf6, inf4, inf6 and inf7. It can also be to use Inf5 to replace the index number of any interface in the ring structure. For example, the index number of the interconnection structure does not use inf7 but uses inf5, then the index numbers of the interfaces are inf5, inf6, and inf4.

[0071] Please see attached Figure 7 , which shows a second type of interconnect topology, also including 4 groups of processors. Figure 7 The 16 processors in the interconnection topology occupy a total of 5 interfaces. The processors in each group of processors are fully interconnected within the group. Inter-group interconnection is to form a ring structure through the remaining interfaces between the processors in the same distribution position in each group of processors. The 4 groups of processors are: The first group G1 includes P 11 , P 12 , P 13 and P 14 , the second group G2 includes P 21 , P 22 , P 23 and P 24 , the third group G3 includes P 31 , P 32 , P 33 and P 34 , the fourth group G4 includes P 41 , P 42 , P 43 and P 44In each group of processors, full interconnection is achieved through inf3, inf4, inf5 and inf6. Inter-group interconnection is formed by jumping between the remaining interfaces of the interconnected processors to form a ring structure. 11 , P 21 , P 31 and P 41 The interconnection forms a ring structure, and the connection between the index numbers of the interfaces is as follows: 11 inf7 connection P 21 inf7,P 21 inf6 connection P 31 inf6,P 31 inf7 connection P 41 inf7,P 41 inf5 connection P 11 The inf5 of each processor is connected end to end to form a ring structure. 12 , P 22 , P 32 and P 42 The interconnection forms a ring structure, and the connection between the index numbers of the interfaces is as follows: 12 inf7 connection P 22 inf7,P 22 inf4 connection P 32 inf4,P 32 inf7 connection P 42 inf7,P 42 inf5 connection P 12 The inf5 of each processor is connected end to end to form a ring structure. 14 , P 24 , P 34 and P 44 The interconnection forms a ring structure, and the connection between the index numbers of the interfaces is as follows: 14 inf7 connection P 24 inf7,P 24 inf5 connection P 34 inf5,P 34 inf7 connection P 44 inf7,P 44 inf6 connection P 14 The inf6 of each processor is connected end to end to form a ring structure. 13 , P 23 , P 33 and P 43The interconnection forms a ring structure, and the connection between the index numbers of the interfaces is as follows: 13 inf7 connection P 23 inf7,P 23 inf5 connection P 33 inf5,P 33 inf7 connection P 43 inf7,P 43 inf4 connection P 13 inf4, connected end to end to form a ring structure.

[0072] exist Figure 7 Based on the software address remapping table, P 11 -P 44 These 16-bit processor addresses are remapped to P 11 -P 24 The 8-bit processor address achieves the purpose of expanding the interconnected processors without changing the fixed routing in the hardware.

[0073] Please refer to the attached Figure 8 , which shows a third type of interconnect topology, also including 4 groups of processors. Figure 8 The 16 processors in the interconnection topology occupy a total of 6 interfaces. The processors in each group of processors are fully interconnected within the group. Inter-group interconnection is to form a ring structure through the remaining interfaces between the processors with the same distribution position in each group of processors. The four groups of processors are: the first group G1 includes P 11 , P 12 , P 13 and P 14 , the second group G2 includes P 21 , P 22 , P 23 and P 24 , the third group G3 includes P 31 , P 32 , P 33 and P 34 , the fourth group G4 includes P 41 , P 42 , P 43 and P 44 In each group of processors, full interconnection is achieved through inf2, inf6, inf7, and inf4. Inter-group interconnection is formed by forming a ring structure between the remaining interfaces of the interconnected processors. 11 , P 21 , P 31 and P 41 The interconnection forms a ring structure, and the interconnection interfaces are as follows: The connection between the interface index numbers is as follows:11 inf4 connection P 21 inf6,P 21 The inf1 connection P 31 inf1,P 31 inf5 connection P 41 inf5,P 41 The inf1 connection P 11 The inf1 of each group of processors is connected end to end to form a ring structure. 12 , P 22 , P 32 and P 42 The interconnection forms a ring structure, and the connection between the interfaces is as follows: 12 The inf1 connection P 22 inf1,P 22 inf4 connection P 32 inf6,P 32 The inf1 connection P 42 inf5,P 42 inf5 connection P 12 The inf5 of each processor is connected end to end to form a ring structure. 14 , P 24 , P 34 and P 44 The interconnection forms a ring structure, and the connection between the index numbers of the interfaces is as follows: 14 The inf1 connection P 24 inf1,P 24 inf5 connection P 34 inf5,P 34 The inf1 connection P 44 inf1,P 44 inf4 connection P 14 The inf6 of each processor is connected end to end to form a ring structure. 13 , P 23 , P 33 and P 43 The interconnection forms a ring structure, and the connection between the index numbers of the interfaces is as follows: 13 inf5 connection P 23 inf5,P 23 The inf1 connection P 33 inf1,P 33 inf4 connection P 43 inf6,P 43 The inf1 connection P 13inf1, connected end to end to form a ring structure.

[0074] Attached Figure 8 The extended topology system provided by the 16 processors also needs to remap the P 11 -P 44 The address is remapped to P 11 -P 24 In this way, the purpose of expanding the interconnected processors is achieved without changing the fixed routing in the hardware.

[0075] Among them, Figure 6 , 7 The equivalent topology system of the extended topology system provided by the 16 processors provided by 8 also includes: an interconnection structure formed after the positional relationship between the groups of processors in the exchange extended topology system. The extended topology system that changes the index number so that the final result is the same as the hardware fixed route determined by the OAM protocol falls within the protection scope of the present invention.

[0076] Please refer to the attached Fig. 9 , which shows a fourth type of interconnection topology, which is attached Figure 7 The interconnection topology provided is further expanded to realize the interconnection of 32 processors, which is equivalent to the interconnection between 4 groups of original interconnection topology structures. The interconnection of 32 processors includes 8 groups of interconnection structures, each of which is fully interconnected, and the processors in the same position are interconnected in turn to form a ring interconnection structure. Address remapping and attachment Figure 7 The software address remapping table used is the same.

[0077] As a preferred embodiment, Figure 6 and attached Figure 8 The extended topology system provided can refer to the attached Fig. 9 The extended topology system provided can be expanded again. Figure 6 , Attachment Figure 7 and attached Figure 8 It can be expanded multiple times in the manner of full interconnection within the group and interconnection of processors at the same position between groups to form a ring structure, thereby realizing the interconnection of M*N processors.

[0078] As a preferred embodiment, when the source processor performs hardware address remapping to make it conform to the verification rule of the destination processor, or the destination address performs hardware address remapping, hardware address remapping is added to the hardware path between the source processor and the destination processor. 11 Expectation and P 41 The inf3 interconnection communication, but in fact P 11 With P 41The inf6 interconnection communication can be realized by remapping the mapping address to remap the interconnection inf6 to inf3.

[0079] As a preferred embodiment, when 16 processors are interconnected, P 11 -P 24 After the address is remapped to itself, P 31 -P 44 The address after remapping is the current processor address minus 8.

[0080] In summary, the interconnection system provided in the second embodiment of the present invention includes N groups of processors, each group of processors includes M processors, the positions of each group of processors are distributed in the same manner, and each group of processors includes two layers of interconnection structures: an intra-group interconnection structure and an inter-group interconnection structure, so that the obtained extended topology system can achieve the expansion of the number of processor interconnections while complying with the original protocol.

[0081] Embodiment 3

[0082] Based on the same inventive concept as a multi-processor interconnection system, the second embodiment of the present invention further provides a processor group. The processor group includes M processors, M>1; wherein the jth processor P j Including the first type of inter-group interface and the second type of inter-group interface, 1≤j≤M; P j The first type of inter-group interface is used with bandwidth B1 j Connect to the Nmap(i,j)th processor of the Next(i)th group, where i is P j The number of the processor group where it is located, the function value of Next(i) is P j The next group of processors in which Nmap(i,j) is located; Nmap(i,j) is the next group of processors in Next(i) j The mapping function of the interconnected processors; P j The second type of inter-group interface is used for bandwidth B2 j Connect the Pmap(i,j)th processor of the Prev(i)th group, where the function value of the Prev(i)th group is Pmap(i,j) j The previous group of processor groups where the processor group is located; the Pmap(i,j) is the same as P in Prev(i) j Mapping function of interconnected processors; where B1 and B2 match, B1 = ∑ j＝1 M B1 j , B2=∑ j＝1 M B2 j .

[0083] Among them, when P j When the processor group is the i-th group, Pj The representation form can also be recorded as P ij , P ij The same as in the first embodiment, no further description is given. j When the processor group is the i-th group, B1 j It can also be written as B1 ij , B2 j Can also be written as B2 ij , no more details.

[0084] It should be noted that the relevant technical features of the processor group are the same as those of the multi-processor interconnection system provided in the first embodiment, and will not be described in detail.

[0085] Embodiment 4

[0086] Based on the same inventive concept as a multi-processor interconnection system, embodiment three of the present invention also provides a processor, which includes a first type of inter-group interface and a second type of inter-group interface; the first type of inter-group interface is used to connect to the second type of inter-group interface of the Nmap(i,j)th processor of the Next(i)th group with a bandwidth of BW1, wherein i is the number of the processor group where the current processor is located, and the function value of Next(i) is the next group of the processor group where the current processor is located; Nmap(i,j) is the mapping function of the processor interconnected with the current processor in Next(i); the second type of inter-group interface is used to connect to the first type of inter-group interface of the Pmap(i,j)th processor of the Prev(i)th group with a bandwidth of BW2, wherein the function value of Prev(i) is the previous group of the processor group where the current processor is located; Pmap(i,j) is the mapping function of the processor interconnected with the current processor in Prev(i); wherein BW1 and BW2 match.

[0087] If the current processor is the jth processor of the i-th group, BW1 can also be recorded as B1 ij , BW2 can also be written as B2 ij , no more details.

[0088] It should be noted that the relevant technical features in the processor are the same as those of the multi-processor interconnection system provided in Example 1 and will not be described in detail.

[0089] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0090] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A multi-processor interconnection system, characterized in that: The system includes N groups of processors, each group includes M processors, N>2, M>1; Among them, the jth processor P of the i-th group ij Including the first type of inter-group interface and the second type of inter-group interface, 1≤i≤N, 1≤j≤M; P ij The first type of inter-group interface and P Next(i)Nmap(i,j) The second type of inter-group interface connection; where P Next(i)Nmap(i,j) is the Nmap(i,j)th processor of the Next(i)th group, the function value of Next(i) is the next group of the i-th group; Nmap(i,j) is the processor in Next(i) that is connected to P ij mapping functions of interconnected processors; P ij The second type of inter-group interface and P Prev(i)Pmap(i,j) The first type of inter-group interface connection; where P Prev(i)Pmap(i,j) is the Pmap(i,j)th processor of the Prev(i)th group, the function value of Prev(i) is the previous group of the i-th group; Pmap(i,j) is the processor in Prev(i) that is consistent with Pmap(i,j) ij Mapping functions of interconnected processors.

2. The system according to claim 1, characterized in that The Next(i) and Prev(i) respectively satisfy: If i=N, then Next(i)=1; otherwise, Next(i)=i+1; If i=0, then Prev(i)=N; Otherwise, Prev(i)=i-1.

3. The system according to claim 1 or 2, characterized in that: The function values ​​of Nmap(i, j) and Pmap(i, j) are single values ​​respectively.

4. The system according to claim 3, characterized in that The Nmap(i,j) and Pmap(i,j) satisfy: Nmap(i,j)=Pmap(i,j)=Nmap(j).

5. The system according to claim 4, characterized in that The Nmap(j)=Pmap(j)=j.

6. The system according to claim 5, characterized in that N≠4。 7. The system according to claim 6, characterized in that The M processors in the i-th group form a ring topology, a fully interconnected topology, or a tree topology.

8. The system according to claim 7, characterized in that The P ij It also includes M-1 intra-group interfaces, among which P ij The fth intra-group interface PI ij,f The hth intra-group interface PI with the rth processor of the ith group ir,h Connect, 1≤r≤M and j≠r, 1≤r≤M-1.

9. The system according to claim 1, characterized in that The Nmap(i,j) and Pmap(i,j) are both vectors containing L elements, each element is the number value of a processor, and the values ​​of the L elements are different, wherein 1<L≤M.

10. The system according to claim 1, characterized in that in: The P ij The first type of inter-group interface and P Next(i)Nmap(i,j) The second type of inter-group interface has a bandwidth of B1 ij connect; The P ij The second type of inter-group interface and P Prev(i)Pmap(i,j) The first type of inter-group interface has a bandwidth of B2 ij connect; Among them, B1 i and B2 i Match, B1 i =∑ j＝1 M B1 ij , B2 i =∑ j＝1 M B2 ij .

11. The system according to claim 10, characterized in that The Next(i) and Prev(i) respectively satisfy: If i=N, then Next(i)=1; otherwise, Next(i)=i+1; If i=0, then Prev(i)=N; otherwise, Prev(i)=i-1; And the B1 ij and B2 ij match.

12. The system according to claim 11, characterized in that The kth processor P of the i-th group ik The first type of inter-group interface and P Next(i)Nmap(i,k) The second type of inter-group interface has a bandwidth of B1 ik Connect the B1 ik and B1 ij The relationship between them satisfies: B1 ik =B1 ij , where the value of Nmap(i,k) is the value of Next(i) that matches P ik Interconnected processors, 1≤k≤M and k≠j.

13. The system according to claim 1, characterized in that The Next(i) and Prev(i) respectively satisfy: If i=N, Next(i)=NULL, where NULL is empty; otherwise, Next(i)=i+1; If i=0, Prev(i)=NULL; otherwise, Prev(i)=i-1.

14. The system according to claim 1, characterized in that in: P ij The first type of inter-group interface is only with P Next(i)Nmap(i,j) The second type of inter-group interface connection; P ij The second type of inter-group interface is only with P Prev(i)Pmap(i,j) The first type of inter-group interface connection.

15. A processor group, characterized in that: The processor group includes M processors, M>1; Among them, the jth processor P j Including the first type of inter-group interface and the second type of inter-group interface, 1≤j≤M; P j The first type of inter-group interface is used with bandwidth B1 j Connect to the Nmap(i,j)th processor of the Next(i)th group, where i is P j The number of the processor group where it is located, the function value of Next(i) is P j The next group of processors in which Nmap(i,j) is located; Nmap(i,j) is the next group of processors in Next(i) j mapping functions of interconnected processors; P j The second type of inter-group interface is used for bandwidth B2 j Connect the Pmap(i,j)th processor of the Prev(i)th group, where the function value of the Prev(i)th group is Pmap(i,j) j The previous group of processor groups where the processor group is located; the Pmap(i,j) is the same as P in Prev(i) j mapping functions of interconnected processors; Among them, B1 and B2 match, B1 = ∑ j＝1 M B1 j , B2=∑ j＝1 M B2 j .

16. A processor, characterized in that: The processor includes a first type of inter-group interface and a second type of inter-group interface; The first type of inter-group interface is used to connect the second type of inter-group interface of the Nmap(i,j)th processor of the Next(i)th group with a bandwidth of BW1, wherein i is the number of the processor group where the current processor is located, the function value of Next(i) is the next group of the processor group where the current processor is located; and Nmap(i,j) is a mapping function of the processors interconnected with the current processor in Next(i); The second type of inter-group interface is used to connect the first type of inter-group interface of the Pmap(i,j)th processor of the Prev(i)th group with a bandwidth of BW2, wherein the function value of Prev(i) is the previous group of the processor group where the current processor is located; and Pmap(i,j) is a mapping function of the processors interconnected with the current processor in Prev(i); Among them, BW1 and BW2 match.

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