Operation method of memory system, memory system and storage medium

Abstract

An operation method of a memory system, a memory system and a storage medium, comprising: providing a logical block management table, the logical block management table comprising a first sequence of identifiers corresponding to M first logical blocks, the identifiers of the M first logical blocks being constructed as a ring queue and managing allocation states of the M first logical blocks through the logical block management table, m is an integer greater than or equal to 2 (S502); and according to the sequence of the identifiers of the M first logic blocks in the annular queue, allocating a certain first logic block of which the allocation state is a first state which is not allocated to a certain second logic block in N second logic blocks, N being an integer greater than M, and updating the allocation state of the first logical block from the first state to a second state indicating that the first logical block has been allocated in the logical block management table (S504).

Description

Operation method of memory system, memory system and storage medium

[0001] The present disclosure relates to the field of storage technology, and in particular to an operating method of a memory system, a memory system, and a storage medium.

[0002] The memory system can perform mapping from logical addresses associated with data that are recognizable by the host to physical addresses storing data in the storage space, and the mapping between logical addresses and physical addresses (L2P mapping) can constitute an L2P (Logical to Physical) mapping table; the memory controller of the memory system can manage and allocate logical block resources that divide the storage space, and recommend appropriate logical block resources to the host, and cache the L2P mapping relationship corresponding to the appropriate logical block resources on the host side, thereby improving the performance of the memory system. It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0003]

[0004] The purpose of the present disclosure is to provide an operating method of a memory system, a memory system and a storage medium.

[0005] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0006] An embodiment of the present disclosure provides an operation method of a memory system, including: providing a logic block management table, the logic block management table including a first sequence of identifiers corresponding to M first logic blocks, the identifiers of the M first logic blocks being constructed as a circular queue and managing the allocation states of the M first logic blocks through the logic block management table, where M is an integer greater than or equal to 2; and allocating a first logic block whose allocation state is a first state indicating unallocated to a second logic block among N second logic blocks, where N is an integer greater than M, in the order of the identifiers of the M first logic blocks in the circular queue, and updating the allocation state of a first logic block from the first state to the second state indicating allocated in the logic block management table.

[0007] In some exemplary embodiments of the present disclosure, M represents the number of logic blocks supported by the memory controller of the memory system in the HPB mode, and the N second logic blocks cover all physical addresses of the memory devices of the memory system.

[0008] In some exemplary embodiments of the present disclosure, the above method also includes: when there is no first logic block with a corresponding allocation state of the first state in the circular queue, de-allocating the second logic block corresponding to the first logic block that was first updated to the second state, and updating the allocation state corresponding to the first logic block that was first identified as the second state to the first state.

[0009] In some exemplary embodiments of the present disclosure, the circular queue includes a pointer, which is configured to point to one of the M first logic blocks in sequence according to the order of the identification of the M first logic blocks in the circular queue; the above method also includes: in response to the allocation state of the first logic block pointed to by the pointer being the second state, allocating the second logic block corresponding to the first logic block that was first updated to the second state, and updating the allocation state corresponding to the first logic block that was first identified as the second state to the first state.

[0010] In some exemplary embodiments of the present disclosure, the method further includes: allocating the first logic block pointed to by the pointer to a second logic block among the N second logic blocks, and pointing the pointer to the next first logic block in the order.

[0011] In some exemplary embodiments of the present disclosure, the above method also includes: allocating Y first logic blocks with an allocation status of the first state to Y second logic blocks among N second logic blocks, where Y is an integer greater than 1 and less than M, and updating the allocation status of the Y first logic blocks from the first state to a third state indicating that they have been allocated and fixed in the logic block management table.

[0012] In some exemplary embodiments of the present disclosure, Y first logic blocks whose allocation status is a first state are allocated to Y second logic blocks among N second logic blocks, including: allocating Y consecutive first logic blocks whose allocation status is the first state in the circular queue to Y second logic blocks.

[0013] In some exemplary embodiments of the present disclosure, the first logic block whose allocation state is the third state is skipped according to the order of the identifiers of the M first logic blocks in the circular queue.

[0014] In some exemplary embodiments of the present disclosure, the logic block management table further includes a second sequence of identifiers corresponding to N second logic blocks; the method further includes: updating the identifier of a first logic block or an identifier of a second logic block in the logic block management table.

[0015] In some exemplary embodiments of the present disclosure, the number of elements of the circular queue is the same as the number of first logic blocks, and each element stores an identifier of a corresponding first logic block and an allocation status of the first logic block.

[0016] In some exemplary embodiments of the present disclosure, a size of the first logic block is the same as a size of the second logic block.

[0017] In some exemplary embodiments of the present disclosure, the method further includes: sending the updated logic block management table to the host.

[0018] In some exemplary embodiments of the present disclosure, the method further includes: sending a corresponding L2P mapping table in a second logic block to a host.

[0019] The present disclosure provides a memory system, comprising: a memory device, and a memory controller coupled to the memory device and used to control the memory device to perform data storage operations; the memory controller comprises an interface coupled to a host for communication; the interface is configured to sequentially send at least part of mapping information in a first logic block management table and a second logic block management table to the host; wherein the first logic block management table and the second logic block management table each represent a mapping relationship between a first logic block and a second logic block at different times, the first logic block management table and the second logic block management table both comprise a first sequence of identifiers corresponding to M first logic blocks, the identifiers of the M first logic blocks are constructed as a circular queue and the M first logic blocks are managed through the logic block management table The allocation status of the first logic block, M is an integer greater than or equal to 2; the first logic block management table and the second logic block management table each include identifiers of K first logic blocks whose allocation status at different times is a second status indicating that they have been allocated, and identifiers of K second logic blocks among the N second logic blocks to which the K first logic blocks are allocated, K is an integer greater than 1 and less than or equal to M, and N is an integer greater than M; a first logic block that is first allocated among the K first logic blocks corresponding to the first logic block management table is updated in the second logic block management table and allocated to a second logic block of the K second logic blocks, so as to reflect the update of the mapping relationship of the second logic block management table relative to the mapping relationship of the first logic block management table.

[0020] In some exemplary embodiments of the present disclosure, M represents the number of logic blocks supported by the memory controller of the memory system in the HPB mode, and the N second logic blocks cover all physical addresses of the memory devices of the memory system.

[0021] In some exemplary embodiments of the present disclosure, the first logic block management table and the second logic block management table both include identifiers of Y first logic blocks whose allocation status is a third status indicating allocated and fixed, and identifiers of Y second logic blocks to which the Y first logic blocks are allocated, Y is an integer greater than 1, and the sum of Y and K is less than or equal to M; the interface is configured to send K mapping information in the first logic block management table and K mapping information in the second logic block management table to the host in sequence.

[0022] In some exemplary embodiments of the present disclosure, the interface is further configured to send a corresponding L2P mapping table in a second logic block to the host.

[0023] The present disclosure provides a memory system, comprising: a memory device, and a memory controller coupled to the memory device and controlling the memory device to perform data storage operations; the memory controller comprises an interface coupled to a host for communication; the interface is configured to sequentially send a first mapping relationship and a second mapping relationship to the host after two adjacent logic block management table updates are triggered; wherein the first mapping relationship comprises K pieces of mapping information of a first logic block and a second logic block, the K pieces of mapping information being included in a first logic block management table, the second mapping relationship comprises L pieces of mapping information of the first logic block and the second logic block, the L pieces of mapping information being included in a second logic block management table, The first logic block management table and the second logic block management table both include a first sequence of identifiers corresponding to M first logic blocks, the identifiers of the M first logic blocks are constructed as a circular queue and the allocation status of the M first logic blocks is managed by the logic block management table, M is an integer greater than or equal to 2, K and L are both integers greater than or equal to 1 and less than or equal to M; a first logic block that is first allocated among the M first logic blocks corresponding to the first logic block management table is updated and allocated to a second logic block of the L second logic blocks in the second logic block management table to reflect the update of the mapping relationship in the second logic block management table relative to the mapping relationship in the first logic block management table.

[0024] In some exemplary embodiments of the present disclosure, M represents the number of logical blocks supported by the memory controller of the memory system in HPB mode, there are N second logical blocks, N is an integer greater than M, and the N second logical blocks cover all physical addresses of the memory devices of the memory system.

[0025] In some exemplary embodiments of the present disclosure, the interface is further configured to send an L2P mapping table corresponding to the certain second logic block to the host.

[0026] An embodiment of the present disclosure provides a non-transitory computer-readable storage medium having computer instructions stored thereon, wherein the computer instructions execute any of the above-mentioned memory system operation methods when executed.

[0027] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

[0028] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0029] FIG. 1 illustrates a block diagram of an example system having a memory device according to some aspects of the present disclosure.

[0030] FIG. 2 a shows a schematic diagram of a memory card integrating a memory controller and a memory device according to some aspects of the present disclosure.

[0031] FIG. 2 b shows a schematic diagram of an SSD with integrated memory controller and memory devices according to some aspects of the present disclosure.

[0032] FIG. 3 shows a schematic diagram of a system including a host and a memory system according to an embodiment.

[0033] FIG. 4 is a schematic diagram showing management when the memory system selectively provides a portion of the L2P mapping table to the host.

[0034] FIG5 is a schematic flow chart showing an operation method of a memory system according to an embodiment of the present disclosure.

[0035] FIG6 shows a schematic diagram of a ring queue in an embodiment of the present disclosure.

[0036] FIG. 7 shows a schematic diagram of a ring queue in an embodiment of the present disclosure.

[0037] FIG8 shows a schematic diagram of a ring queue in an embodiment of the present disclosure.

[0038] FIG. 9 shows a schematic diagram of a ring queue in an embodiment of the present disclosure.

[0039] FIG. 10 shows a schematic diagram of a ring queue in an embodiment of the present disclosure.

[0040] FIG. 11 is a schematic diagram showing a logic block management table in an embodiment of the present disclosure.

[0041] FIG. 12 is a schematic diagram showing a logic block management table in an embodiment of the present disclosure.

[0042] FIG. 13 is a schematic diagram showing a logic block management table in an embodiment of the present disclosure.

[0043] FIG. 14 is a schematic diagram showing a logic block management table in an embodiment of the present disclosure.

[0044] FIG. 15 is a schematic diagram showing a logic block management table in an embodiment of the present disclosure.

[0045] FIG. 16 is a schematic diagram showing another logic block management table in an embodiment of the present disclosure.

[0046] FIG. 17 is a schematic diagram showing another logic block management table in an embodiment of the present disclosure.

[0047] FIG. 18 is a schematic diagram showing another logic block management table in an embodiment of the present disclosure.

[0048] FIG. 19 is a schematic diagram showing another logic block management table in an embodiment of the present disclosure.

[0049] FIG. 20 is a schematic diagram showing another logic block management table in an embodiment of the present disclosure.

[0050] FIG. 21 is a flow chart showing another method for operating a memory system according to an embodiment of the present disclosure.

[0051] FIG. 22 is a flow chart showing another method for operating a memory system according to an embodiment of the present disclosure.

[0052] FIG. 23 shows a schematic diagram of the interaction between a host and a memory system in an embodiment of the present disclosure.

[0053] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0054] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0055] In addition, in the description of the present disclosure, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. The terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0056] FIG1 shows a block diagram of an exemplary system 100 with a memory device according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG1 , the system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to or receive data from the memory device 104.

[0057] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0058] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0059] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. In one example as shown in FIG. 2a, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG. 1). In another example as shown in FIG. 2b, the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. SSD 206 may also include an SSD connector 208 that couples SSD 206 to a host (eg, host 108 in FIG. 1 ). In some implementations, the storage capacity and / or operating speed of SSD 206 is greater than the storage capacity and / or operating speed of memory card 202 .

[0060] 3 shows a diagram of a system 300 including a host 310 and a memory system 320 according to an embodiment, wherein the system 300 in FIG. 3 may correspond to the system 100 described above with reference to FIG. 1 , the host 310 in FIG. 3 may correspond to the host 108 described above with reference to FIG. 1 , and the memory system 320 in FIG. 3 may correspond to the memory system 102 described above with reference to FIG. 1 .

[0061] The memory system 320 may include a memory controller 330 and a memory device 340. The memory controller 330 may include a host interface 332, a processor 334, a cache 336, and a memory device interface 338. The memory controller 330 may receive commands from the host 310 through the host interface 332, and may control the operation of the memory device 340 based on the received commands through the processor 334. The memory controller 330 may communicate with the memory device 340 through the memory device interface 338 to control the operation of the memory device 340. The commands received by the memory controller 330 through the host interface 332 and the data involved in the commands may be temporarily stored in the cache 336. The cache 336 may also be configured to temporarily store data read out by the memory device 340 to be transmitted to the host 310. In some embodiments, the cache 336 may also be configured to cache other related information involved in the memory system 320.

[0062] In some embodiments, the memory controller 330 may receive a write command, a read command, etc. of data from the host 310 through the host interface 332, and may generate a command for controlling the operation of the memory device 340 based on the received command through the processor 334, and transmit the command to the memory device 340 through the memory device interface 338. The memory device 340 is configured to receive a command and an address from the memory controller 330, and access an area selected by the address in the memory cell array of the memory controller 330. That is, the memory device 340 performs an internal operation corresponding to the command on the area selected by the address. For example, the memory device 340 may perform a programming operation, a reading operation, and an erasing operation. During a programming operation, the memory device 340 may program data to an area selected by an address. During a reading operation, the memory device 340 may read data from an area selected by an address. During an erasing operation, the memory device 340 may erase data stored in an area selected by an address. In some embodiments, the memory device 340 may include one or more memory arrays of any type of memory cell (e.g., a nonvolatile memory cell, a volatile memory cell, or any combination thereof). The memory device 340 may perform a write operation and a read operation in units of pages, and may perform an erase operation in units of blocks.

[0063] In some embodiments, the memory system 320 may have a flash translation layer (Flash Translation Layer, FTL) in the memory controller 330, and one or more command operations, internal operations, etc. may be performed through the FTL. For example, the memory controller 330 may control the memory device 340 in response to a request from the host 310. At the same time, the memory controller 330 may perform internal operations (e.g., garbage collection operations, read recovery operations, and wear leveling operations) regardless of the request from the host 310. For example, the memory controller 330 may perform the above operations by running the FTL using software. The FTL may be run by a processor 334 of the memory controller 330. Therefore, the various operations of the FTL may be performed by the processor 334.

[0064] An important operation of FTL includes completing the mapping of the logical address space of the host 310 to the physical address space of the memory device 340. Every time the memory system 320 writes a piece of user data into the memory device 340, it records the mapping of the logical address of the user data to the physical address of the data in the memory device 340. When the host 310 reads the data, the memory system 320 will read the data from the memory device 340 according to this mapping and then return it to the host 310.

[0065] In some embodiments, the operations performed by the commands and the internal operations may be performed by the FTL, and the logical address (LA) provided from the host 310 may be converted or converted into the physical address (PA) of the memory device 340. The L2P mapping information may be provided in a logical-to-physical mapping table (i.e., L2P mapping table) including the logical address to physical address mapping data. As the memory system 320 expands, the size of the L2P mapping table inevitably increases. Therefore, the time spent by the memory system 320 searching the L2P mapping table increases, which may reduce the operating speed of the memory system 320, especially the memory system 320 that is not configured with DRAM.

[0066] In some embodiments, the system 300 including the host 310 and the memory system 320 may have a host memory 312 in the host 310, and synchronize at least part of the L2P mapping table in the memory system 320 to the host memory 312, so that the address mapping operation can be preferentially performed in the host 310 to improve the performance of the memory system 320. For example, the host 310 transmits the L2P mapping information searched from the host memory 312 together with the read command to the memory system 320, the host interface 332 receives the read command and the L2P mapping information, and the processor 334 transmits the read command for reading user data and the physical address corresponding to the read command to the memory device 340. The memory device 340 reads the user data corresponding to the received read command. The read user data may be transmitted to the memory controller 330 and may be transmitted from the memory controller 330 to the host 310.

[0067] In order to synchronize at least part of the L2P mapping information in the memory system 320 to the host memory 312, the host 310 and the memory system 320 need to be configured to support the operation, which may be a HPB (Host Performance Booster) operation or a HMB (Host Memory Buffer) operation. When the memory system 320 provides all the L2P mapping tables stored in the memory system 320 to the host 310, the ability of the memory system 320 to support the corresponding operation may be limited, or the host 310 may have difficulty in assigning storage space in the host memory 312 to store all the L2P mapping information, or, due to other functions, the memory system 320 may selectively provide part of the L2P mapping tables to the host 310 instead of providing all the L2P mapping tables to the host 310.

[0068] FIG4 shows a schematic diagram of the management when the memory system 320 selectively provides a portion of the L2P mapping table to the host 310. The memory controller 330 can perform corresponding coverage expression on the physical address space of the memory device 340, which is divided into a plurality of logical blocks. Referring to FIG4, the logical address space can cover all physical addresses of the memory device 340, and the logical address space can be evenly divided into a plurality of second logical blocks 121 in a manner that each logical block has the same size. The plurality of second logical blocks 121 are compiled into a second logical block table 120 (Region table). The size of each second logical block 121 can be set according to actual needs, and the number of second logical blocks 121 is determined according to the size of the memory device 340 and the size of each second logical block 121. For example, referring to FIG4, the size of the memory device 340 is 512G, the size of the second logical block 121 is 16M, the number of the second logical blocks 121 is 32K, and the length of the second logical block table 120 is 32K.

[0069] When the memory system 320 selectively provides a portion of the L2P mapping table to the host 310, it is necessary to select a portion of the second logical blocks 121 from the plurality of second logical blocks 121, and send the L2P mapping table corresponding to the selected portion of the second logical blocks 121 to the host 310 for storage in the host memory 312, so that the host 310 can call it when making a read request. The memory system 320 can be configured with a logical space that supports the aforementioned operation, and divide the logical space into a plurality of first logical blocks, wherein the number of first logical blocks is less than the number of second logical blocks. Referring to FIG. 4 , a plurality of first logical blocks 111 can be compiled into a first logical block table (Sub-region table). The size of the first logical block 111 can be set according to actual needs, for example, the size of the first logical block 111 can be the same as the size of the second logical block 121. For example, referring to FIG. 4 , the size of the first logical block 111 may be 16M, and the memory system 320 may be configured with a logical space of 128G to support the aforementioned operation. Then, the number of first logical blocks 111 is 8K, and the length of the first logical table 110 is 8K. The memory system 320 may be configured with a logical space to support the aforementioned operation and may only recommend to the host 310 the L2P mapping table corresponding to the 128G physical address space in the memory device 340.

[0070] When the memory system 320 selectively provides a partial L2P mapping table to the host 310, it can select at least one second logical block 121 that meets the recommended criteria from the second logical block table 120, map it with at least one first logical block 111 in the first logical block table 110, and recommend the mapping relationship between the first logical block 111 and the second logical block 121 to the host 310. After the host 310 receives the mapping relationship between the first logical block 111 and the second logical block 121, it requests the L2P mapping table corresponding to the second logical block 121 from the memory system 320. In response to the request, the memory system 320 sends the L2P mapping table corresponding to the second logical block 121 to the host 310 for storage in the host memory 312.

[0071] When it is necessary to update the memory system 320 to selectively provide part of the L2P mapping table to the host 310, refer to FIG4. Before the update, the 1st to 8K second logic blocks 121 are selected as 8K second logic blocks 121 that meet the recommended standard, and are mapped one-to-one with the 8K first logic blocks 111 in the first logic block table 110 to form a mapping relationship 110A between the 8K first logic blocks 111 and the second logic blocks 121. The mapping relationship 110A between the first logic block 111 and the second logic block 121 is recommended to the host 310, and the L2P mapping tables corresponding to the 1st to 8K second logic blocks 121 are stored in the host memory 312; when a new second logic block 121 meets the recommended standard, Standard, for example, the 8K+1 and 8K+2 second logic blocks 121 in FIG4 , it is necessary to search the first logic block 111 in the first logic block table 110 for mapping with the new second logic block 121 that meets the recommended standard. For example, referring to FIG4 , the first first logic block 111 is mapped with the 8K+1 second logic block 121, and the second first logic block 111 is mapped with the 8K+2 second logic block 121, thereby forming a new mapping relationship 110B between the 8K first logic blocks 111 and the second logic blocks 121. The mapping relationship 110B between the first logic block 111 and the second logic block 121 is recommended to the host 310, and the L2P mapping table stored in the host memory 312 is updated.

[0072] When the memory system 320 selectively provides a partial L2P mapping table to the host 310, when searching the first logical block 111 in the first logical block table 110 for mapping with the second logical block 121 that meets the recommended standard, the management of the mapping relationship is relatively complicated. Some embodiments of the present disclosure provide a method for quickly updating the mapping relationship between the first logical block 111 and the second logical block 121 to improve resource management efficiency.

[0073] In the disclosed embodiment, a memory controller 320 in the memory system 310 stores a logic block management table of a first logic block (e.g., Sub-Region) and a second logic block (e.g., Region). The memory controller 320 can manage and allocate multiple first logic blocks through the logic block management table. In some embodiments, when a second logic block among multiple second logic blocks meets the recommended standard, a first logic block among the multiple first logic blocks is allocated to the second logic block, and the corresponding relationship is sent to the host 310; after the host 310 receives the corresponding relationship, the L2P mapping table corresponding to the second logic block stored in the memory system 320 can be obtained, thereby updating the part of the L2P mapping table to the host 310, thereby improving data reading efficiency and system performance.

[0074] FIG5 is a flow chart showing a method for operating a memory system in an embodiment of the present disclosure. The execution subject of the method may be a memory controller 330 in a memory system 320. As shown in FIG5 , the method for operating a memory system provided in an embodiment of the present disclosure may include the following steps.

[0075] In step S502, a logic block management table is provided, which includes a first sequence of identifiers corresponding to M first logic blocks. The identifiers of the M first logic blocks are constructed as a circular queue and the allocation status of the M first logic blocks is managed by the logic block management table, where M is an integer greater than or equal to 2.

[0076] In the embodiment of the present disclosure, the logic block management table includes a mapping relationship between a first logic block and a second logic block, and there may be M first logic blocks. Wherein, M may represent the number of logic blocks supported by the memory controller 330 in the memory system 320 in the HPB mode; M may also represent the number of logic blocks supported by the memory controller 330 in the memory system 320 in the HMB mode. M first logic blocks may cover part of the physical address space of the memory device 340 in the memory system 320. There may be N second logic blocks, and these N second logic blocks may cover part or all of the physical addresses of the memory device 340 of the memory system 320. It should be noted that M is an integer greater than or equal to 1, which can be specifically configured in the memory controller 330, N is an integer greater than M, and the physical address space of the memory device 340 in the memory system 320 covered by the M first logic blocks is less than the physical address space of the memory device 340 in the memory system 320 covered by the N second logic blocks.

[0077] For example, for a 512G memory system 320, the physical address space of the memory device 340 is 512G, the storage space corresponding to the entire physical address space of the memory device 340 that can be covered by N second logical blocks can be 512G, and the partial physical address space of the memory device 340 that can be covered by M first logical blocks, for example, the corresponding storage space can be 128G.

[0078] In the embodiment of the present disclosure, the size of the first logic block and the size of the second logic block may be the same, for example, both are 16 M. In some embodiments, the size of the first logic block and the size of the second logic block may also be different.

[0079] In the embodiment of the present disclosure, the logic block management table may include a first sequence of identifiers corresponding to M first logic blocks, the identifier of the first logic block may be the ID (Identity Document) of the first logic block, and each first logic block has an identifier corresponding to it; the first sequence may be a column in the logic block management table, such as the first column in the logic block management table A as shown in Figures 11 to 15, or the second column in the logic block management table B as shown in Figures 16 to 20; the logic block management table may also include a second sequence of identifiers for representing second logic blocks, the identifier of the second logic block may be the ID of the second logic block, and each second logic block has an identifier corresponding to it; wherein the second sequence includes the identifier of the second logic block to which each first logic block is assigned (when the first logic block is not assigned, the identifier of the corresponding second logic block in the second sequence may be an initial value or a preset value, such as 0), and the logic block management table may also include a third sequence, and the third sequence includes the allocation status of each first logic block.

[0080] Specifically, the allocation status of the first logic block may include but is not limited to a first state, a second state and a third state, wherein the first state may represent an "unassigned" state, the second state may represent an "allocated" state, and the third state may represent an "allocated and fixed" state; the "allocated" state may refer to a state in which the first logic block has been allocated to an available second logic block (e.g., a second logic block that meets the recommended standard), and the "allocated and fixed" state may refer to a state in which the first logic block has been fixedly allocated to a second logic block, and the second logic block allocated to the first logic block will basically not change.

[0081] In the disclosed embodiment, a circular queue can be constructed according to the number of first logic blocks, and the number of elements in the circular queue is the same as the number of first logic blocks; for example, a FIFO (First Input First Output) circular queue 600 with a depth of M is initialized to manage the resources of the first logic blocks, as shown in Figures 6 to 10; each element in the circular queue 600 can store the identifier of the corresponding first logic block and the allocation status of the first logic block, for example, the first element of the circular queue 600 stores the identifier of the first first logic block (ID=1), the second element stores the identifier of the second first logic block (ID=2), ..., the Mth element stores the identifier of the Mth first logic block (ID=M), and the initial allocation status of each first logic block can be set to the first state of "unassigned".

[0082] In some embodiments, the circular queue 600 may include a pointer 601. In an initial state, the pointer 601 points to the first first logic block in the circular queue 600. For example, as shown in FIG. 6, in an initial state, the pointer 601 points to the first logic block corresponding to the identifier 1.

[0083] In step S504, according to the order of the identifiers of the M first logic blocks in the circular queue, a first logic block whose allocation state is the first state indicating "unassigned" is allocated to a second logic block among the N second logic blocks, where N is an integer greater than M, and the allocation state of the first logic block is updated from the first state to the second state indicating "allocated" in the logic block management table.

[0084] In the embodiment of the present disclosure, one of the first logic blocks with an allocation status of the first state can be allocated to one of the N second logic blocks in sequence according to the order of the identifiers of the M first logic blocks in the circular queue, that is, according to the order of the M elements in the circular queue (for example, the first one is identifier 1 (corresponding to the first first logic block), the second one is identifier 2 (corresponding to the second first logic block), ..., the Mth one is identifier M (corresponding to the Mth first logic block)), and the allocation status of the first logic block can be updated from the first state to the second state in the logic block management table.

[0085] In some embodiments, when one of the N second logic blocks reaches the recommended standard, the first logic block with the first allocation state pointed to by the pointer of the circular queue can be allocated to the second logic block that reaches the recommended standard (the L2P mapping table corresponding to the second logic block is activated after being stored in the host memory 312, and can also be called an active second logic block). The pointer of the circular queue can point to the first logic block with the first allocation state in the order of the identifiers of the M first logic blocks in the circular queue.

[0086] In an exemplary embodiment, M first logic blocks may establish mapping relationships with corresponding M second logic blocks respectively, that is, all first logic blocks in the logic block management table have been allocated, and at this time there is no corresponding first logic block with an allocation status of the first state in the circular queue. The above method may also include: de-allocating the second logic block corresponding to the first logic block that was first updated to the second state in the circular queue, and updating the allocation status corresponding to the first logic block that was first identified as the second state to the first state.

[0087] In some embodiments, there may be no first logic block in the circular queue whose corresponding allocation state is the first state, that is, the corresponding first logic blocks in the circular queue are all in the second state or the third state, that is, the first logic blocks have all been allocated to the second logic block that meets the recommended standard or the fixed second logic block. At this time, the first logic block that is first updated to the second state is first determined, that is, the first logic block that is first allocated to the second logic block that meets the recommended standard, and the second logic block corresponding to the first logic block is de-allocated (also called deactivated), that is, the mapping relationship between the first logic block and its corresponding second logic block is released, and the allocation state of the first logic block in the logic block management table is updated from the second state to the first state, so as to facilitate the reallocation of the first logic block to other second logic blocks that meet the recommended standard.

[0088] In some embodiments, when there is no first logic block with a corresponding allocation status of the first state in the circular queue, the first logic block allocated first can be determined according to the order of the identifiers of the M first logic blocks in the circular queue; for example, referring to Figure 9, the circular queue 600 includes M identifiers, and the allocation status of the M first logic blocks corresponding to these M identifiers are not the first state; wherein the first identifier is identifier 1, and the first logic block corresponding to identifier 1 is the first first logic block, so the first first logic block is the first first logic block allocated.

[0089] FIG21 is a flow chart showing another method for operating a memory system according to an embodiment of the present disclosure. As shown in FIG21 , the method for operating a memory system provided in an embodiment of the present disclosure may include the following steps.

[0090] In step S2102, a second logic block that meets the recommended standard is determined.

[0091] In some embodiments, when it is determined that there is a second logic block that meets the recommended standard, the following step S2104 may be executed.

[0092] In step S2104, it is determined whether there is a first logic block in the circular queue whose corresponding allocation state is the first state.

[0093] In some embodiments, if there is a first logic block with a corresponding allocation state of the first state in the circular queue, the following step S2106 is executed; if there is no first logic block with a corresponding allocation state of the first state in the circular queue, the following step S2108 is executed.

[0094] In step S2106, according to the order of the identifiers of the M first logic blocks in the circular queue, the first first logic block whose allocation state is the first state is allocated to the second logic block that meets the recommended standard.

[0095] In step S2108, the second logic block corresponding to the first logic block first updated to the second state is de-allocated, and the allocation state corresponding to the first logic block first identified as the second state is updated to the first state; and the first logic block is allocated to the second logic block that meets the recommended standard.

[0096] In step S2110, the allocation state of the first logic block allocated to the second logic block that meets the recommendation standard is updated from the first state to the second state.

[0097] For other contents of the embodiment of Figure 21, please refer to the text description of the above method embodiment, and the repeated parts will not be repeated.

[0098] In an exemplary embodiment, the circular queue includes a pointer, and the pointer is configured to point to one of the M first logic blocks in sequence according to the order of the identifiers of the M first logic blocks in the circular queue.

[0099] For example, in the initial state, referring to Figure 6, pointer 601 points to the first first logic block in the circular queue 600, that is, the first logic block corresponding to identifier 1; after the first first logic block is allocated, referring to Figure 7, pointer 601 points to the second first logic block in the circular queue 600, that is, the first logic block corresponding to identifier 2; and so on, after the current first logic block pointed to by pointer 601 is allocated, it points to the next first logic block of the current first logic block in sequence.

[0100] In an exemplary embodiment, in response to the allocation state corresponding to the first logic block pointed to by the pointer being the first state, the first logic block pointed to by the pointer is allocated to a second logic block, and the pointer is pointed to the next first logic block in sequence.

[0101] In some embodiments, when the allocation state corresponding to the first logic block pointed to by the pointer is the first state, it means that the first logic block is allocatable, and the first logic block can be directly allocated to the second logic block that currently meets the recommended criteria, and the pointer can be pointed to the next first logic block in sequence.

[0102] In an exemplary embodiment, the method may further include: in response to the allocation state of the first logic block pointed to by the pointer being the second state, de-allocating the second logic block corresponding to the first logic block that was first updated to the second state, and updating the allocation state corresponding to the first logic block that was first identified as the second state to the first state.

[0103] In some embodiments, when the allocation state of the first logic block pointed to by the pointer is the second state, the first logic block pointed to by the pointer is the first logic block updated to the second state first, and the second logic block corresponding to the first logic block pointed to by the pointer can be de-allocated; thus, the first logic block to be allocated can be quickly located through the pointer.

[0104] In an exemplary embodiment, the method may further include: allocating the first logic block pointed to by the pointer to a second logic block among the N second logic blocks, and pointing the pointer to the next first logic block in sequence.

[0105] For example, when the first logical block pointed to by the pointer is the first first logical block corresponding to identifier 1 and the allocation status of the first first logical block is the second status, it is necessary to first de-allocate the second logical block to which the first first logical block has been allocated, update the allocation status of the first first logical block to the first status, and then allocate the first first logical block to the second logical block that currently meets the recommended criteria (not the same second logical block as the previously allocated second logical block), update the allocation status of the first first logical block to the second status, and point the pointer to the second first logical block corresponding to identifier 2.

[0106] FIG22 is a flow chart showing another method for operating a memory system according to an embodiment of the present disclosure. As shown in FIG22 , the method for operating a memory system provided in an embodiment of the present disclosure may include the following steps.

[0107] In step S2202, a second logic block that meets the recommended standard is determined.

[0108] In some embodiments, when it is determined that there is a second logic block that meets the recommended standard, the following step S2204 may be executed.

[0109] In step S2204, it is determined whether the allocation state of the first logic block currently pointed to by the pointer is the first state.

[0110] In some embodiments, if the allocation state of the first logic block currently pointed to by the pointer is the first state, the following step S2206 is executed; if the allocation state of the first logic block currently pointed to by the pointer is not the first state, the following step S2208 is executed.

[0111] In step S2206, the first logical block currently pointed to by the pointer is allocated to the second logical block that meets the recommended standard.

[0112] In step S2208, the second logic block corresponding to the first logic block currently pointed to by the pointer is allocated, and the allocation state corresponding to the first logic block currently pointed to by the pointer is updated to the first state; and the first logic block currently pointed to by the pointer is allocated to the second logic block that meets the recommended standard.

[0113] In step S2210, the allocation state of the first logic block currently pointed to by the pointer is updated from the first state to the second state.

[0114] In step S2212, according to the order of the identifiers of the M first logic blocks in the circular queue, the pointer is pointed to the next first logic block.

[0115] For other contents of the embodiment of Figure 22, please refer to the text description of the above method embodiment, and the repeated parts will not be repeated.

[0116] In an exemplary embodiment, the above method also includes: allocating Y first logic blocks with an allocation status of the first state to Y second logic blocks among N second logic blocks, Y is an integer greater than 1 and less than M, and updating the allocation status of the Y first logic blocks from the first state to a third state indicating "allocated and fixed" in the logic block management table.

[0117] In some embodiments, when the system is initialized, Y second logic blocks out of N second logic blocks are used to store relevant configuration information, that is, these Y second logic blocks are logic blocks for storing configuration information (also referred to as Pinned Regions), and after initialization, the information stored in these Y second logic blocks (Pinned Regions) will basically not change.

[0118] In some embodiments, for the Y second logical blocks (Pinned Regions), Y first logical blocks in the first state are allocated to them, and the allocation state of the Y first logical blocks in the logical block management table is updated to the third state. After the Y first logical blocks are allocated to the Y second logical blocks (Pinned Regions), the allocation state corresponding to the Y first logical blocks basically does not change. The mapping relationship between the Y first logical blocks and the Y second logical blocks (Pinned Regions) is sent to the host 310, and the host 310 requests the L2P mapping tables corresponding to the Y second logical blocks (Pinned Regions) according to the mapping relationship between the Y first logical blocks and the Y second logical blocks (Pinned Regions), and the memory system 320 sends the L2P mapping tables corresponding to the Y second logical blocks (Pinned Regions) to the host 310 for storage in the host memory 312. The mapping relationship between the Y first logical blocks and the Y second logical blocks (Pinned Region) will basically not change after initialization. Therefore, when the mapping relationship between the first logical blocks and the second logical blocks is subsequently updated, the mapping relationship between the Y first logical blocks and the Y second logical blocks (Pinned Region) does not need to be repeatedly sent to the host 310.

[0119] In an exemplary embodiment, Y consecutive first logic blocks in the ring queue whose allocation state is the first state may be fixedly allocated to Y second logic blocks (Pinned Region).

[0120] In some embodiments, Y consecutive first logic blocks with an allocation status of the first state at the head of the circular queue may be fixedly allocated to Y second logic blocks (Pinned Region), Y consecutive first logic blocks with an allocation status of the first state at the tail of the circular queue may be fixedly allocated to Y second logic blocks (Pinned Region), or Y consecutive first logic blocks with an allocation status of the first state at the middle of the circular queue may be fixedly allocated to Y second logic blocks (Pinned Region).

[0121] For example, referring to FIG7 , the Y consecutive first logic blocks 602 corresponding to the identifiers of the (M-Y+1)th to the Mth first logic blocks in the circular queue are allocated to the Y second logic blocks (Pinned Region); for another example, the Y first logic blocks corresponding to the identifiers of the 1st to the Yth consecutive first logic blocks in the circular queue may also be allocated to the Y second logic blocks (Pinned Region). In other alternative embodiments, the Y first logic blocks fixedly allocated to the Y second logic blocks (Pinned Region) may be pre-determined randomly in the circular queue.

[0122] In an exemplary embodiment, when allocating a first logic block to a second logic block that meets the recommendation standard, the first logic block in the third state may be skipped according to the order of the identifiers of the M first logic blocks in the circular queue.

[0123] In some embodiments, after determining that Y first logic blocks have an allocation status of the third state, the identifiers of these Y first logic blocks can be recorded; when the first logic blocks corresponding to the identifiers of these Y first logic blocks are allocated in the order of the identifiers of the M first logic blocks in the circular queue, these Y first logic blocks are skipped.

[0124] For example, referring to Figure 7, the (M-Y+1)th to Mth first logic blocks 602 in the circular queue 600 are first logic blocks in the third state. After the (MY)th first logic block is assigned to the corresponding second logic block, the (M-Y+1)th to Mth first logic blocks are skipped, and the 1st first logic block is assigned to the corresponding second logic block.

[0125] In some embodiments, the circular queue includes a pointer, and the pointer can be used to skip the first logical block whose allocation state is the third state.

[0126] For example, after Y consecutive first logical blocks corresponding to the identifiers of the (M-Y+1)th to the Mth first logical blocks in the circular queue are allocated to Y second logical blocks, when a certain first logical block belongs to the 1st to (MY-1)th first logical blocks, the pointer is pointed to the next first logical block of the certain first logical block.

[0127] For example, referring to Figure 7, when the first logic block pointed to by pointer 601 is the first first logic block and the allocation status of the first first logic block is the first status, the first first logic block can be directly allocated to the second logic block that currently meets the recommended criteria, and the allocation status of the first first logic block is updated to the second status, and the pointer 601 points to the second first logic block, as shown in Figure 8; for another example, when the first logic block pointed to by pointer 601 is the second first logic block, the second first logic block can be directly allocated to the second logic block that currently meets the recommended criteria, and the allocation status of the second first logic block is updated to the second status, and the pointer 601 points to the third first logic block, and so on.

[0128] In some embodiments, when a certain first logical block is in the (MY)th first logical block, the pointer is pointed to the 1st first logical block.

[0129] For example, referring to Figure 9, when the first logic block pointed to by pointer 601 is the (MY)th first logic block and the allocation status of the (MY)th first logic block is the first state, the (MY)th first logic block can be directly allocated to the second logic block that currently meets the recommended criteria, and the allocation status of the (MY)th first logic block can be updated to the second state, and the pointer 601 points to the first first logic block. At this time, the pointer skips the (M-Y+1)th to Mth first logic blocks 602 in the circular queue whose allocation status is the third state.

[0130] Referring to Figures 9 and 10, when the first logic block pointed to by pointer 601 is the first first logic block and the allocation status of the first first logic block is the second status, it is necessary to first de-allocate the second logic block to which the first first logic block has been allocated, update the allocation status of the first first logic block to the first status, and then allocate the first first logic block to the second logic block that currently meets the recommended criteria (not the same second logic block as the previously allocated second logic block), update the allocation status of the first first logic block to the second status, and point pointer 601 to the second first logic block, thereby enabling rapid management and allocation of logic block resources to be achieved through a circular queue.

[0131] In an exemplary embodiment, the method further includes: updating an identifier of a first logic block or an identifier of a second logic block in the logic block management table.

[0132] The logic block management table in the embodiment of the present disclosure may be a logic block management table A as shown in FIGS. 11 to 15 , or a logic block management table B as shown in FIGS. 16 to 20 , where M may be 8K and N may be 32K.

[0133] The following describes updating the identifier of the second logic block in the logic block management table by taking the logic block management table A shown in FIGS. 11 to 15 as an example.

[0134] With reference to Figures 6 and 11, the first column in the logic block management table A is the identifier of the first logic block, the second column is the identifier of the second logic block to which the first logic block is allocated, and the third column is the allocation status of the first logic block; in the initial stage, the first column is the identifier 1 to M of the first logic block. At this time, the first logic block is not allocated, so the identifier of the second logic block in the second column is the initial value, for example, all are 0, and the allocation status in the third column is the first state, that is, the unallocated state.

[0135] In combination with reference Figures 7 and 12, the Y first logic blocks 602 corresponding to the identifiers of the (M-Y+1)th to the Mth first logic blocks in the circular queue 600 are allocated to Y second logic blocks (Pinned Region); the identifiers of the second logic blocks corresponding to the identifiers of the (M-Y+1)th to Mth first logic blocks in the logic block management table A are updated to X~Z, and the allocation status corresponding to the identifiers of the (M-Y+1)th to Mth first logic blocks in the logic block management table A is updated to the third status.

[0136] In conjunction with reference to Figures 7, 8 and 13, for example, the second logical block that currently meets the recommended standard is the second logical block identified as 1; when the first logical block pointed to by pointer 601 is the first first logical block and the allocation state of the first first logical block is the first state, the first first logical block can be directly allocated to the second logical block identified as 1; the identifier of the second logical block corresponding to the identifier of the first first logical block in the logical block management table A is updated to 1, the allocation state corresponding to the identifier of the first first logical block in the logical block management table A is updated to the second state, and the pointer 601 points to the second first logical block, and so on, ..., in conjunction with reference to Figures 9 and 14, for example, the second logical block that currently meets the recommended standard is the second logical block identified as (MY); when the first logical block pointed to by pointer 601 is the (MY)th first logical block and the allocation state of the (MY)th first logical block is the first state, the (MY)th first logical block can be directly allocated to The second logical block identified as (MY), updates the identifier of the second logical block corresponding to the identifier of the (MY)th first logical block in the logical block management table A to (MY), updates the allocation status of the (MY)th first logical block to the second status, and points the pointer 601 to the first first logical block; in conjunction with reference to Figures 9, 10 and 15, for example, the second logical block that currently meets the recommended standard is the second logical block identified as (M-Y+1); when the first logical block pointed to by the pointer 601 is the first first logical block and the allocation status of the first first logical block is the second status, it is necessary to first de-allocate the second logical block (i.e., the second logical block identified as 1) to which the first first logical block has been allocated, and then allocate the first first logical block to the second logical block identified as (M-Y+1), update the identifier of the second logical block corresponding to the identifier of the first first logical block in the logical block management table A from 1 to (M-Y+1), and point the pointer to the second first logical block.

[0137] The following describes updating the identifier of the first logic block in the logic block management table by taking the logic block management table B shown in FIGS. 16 to 20 as an example.

[0138] With reference to Figures 6 and 16, the first column in the logic block management table B is the identifier of the second logic block, the second column is the identifier of the first logic block to which the second logic block has been allocated, and the third column is the allocation status of the first logic block; in the initial stage, the first column is the identifier 1 to N of the second logic block. At this time, the first logic block is not allocated, so the identifier of the first logic block in the second column is the initial value, for example, all are 0, and the allocation status in the third column is the first state, that is, the unallocated state.

[0139] In combination with reference Figures 7 and 17, the Y first logic blocks corresponding to the identifiers of the (M-Y+1)th to the Mth first logic blocks in the circular queue 600 are allocated to Y second logic blocks (Pinned Region); the identifiers of the first logic blocks corresponding to the identifiers of the Xth to Zth second logic blocks in the logic block management table B are updated to (M-Y+1)~M, and the allocation status corresponding to the identifiers of the (M-Y+1)th to Mth first logic blocks in the logic block management table B is updated to the third status.

[0140] In conjunction with reference to Figures 7, 8 and 18, for example, the second logic block that currently meets the recommended criteria is the second logic block identified as 1; when the first logic block pointed to by pointer 601 is the first first logic block and the allocation status of the first first logic block is the first state, the first first logic block can be directly allocated to the second logic block identified as 1; the identifier of the first logic block corresponding to the identifier of the first second logic block in the logic block management table B is updated to 1, and the allocation status corresponding to the first logic block identified as 1 in the logic block management table B is updated to the first state. The pointer 601 is in the second state, and points to the second first logic block, and so on, ..., with reference to Figures 9 and 19, for example, the second logic block that currently meets the recommended standard is the second logic block identified as 0X5999; when the first logic block pointed to by the pointer 601 is the (MY)th first logic block and the allocation state of the (MY)th first logic block is in the first state, the (MY)th first logic block can be directly allocated to the second logic block identified as 0X5999, and the second logic block identified as 0X5999 in the logic block management table B can be allocated to the second logic block identified as 0X5999. The identifier of the first logic block corresponding to the logic block is updated to (MY), and the allocation state of the (MY)th first logic block is updated to the second state, and the pointer 601 points to the first first logic block; in combination with reference to Figures 9, 10 and 20, for example, the second logic block that currently meets the recommended standard is the second logic block identified as 0X6E2D; in the case that the first logic block pointed to by the pointer 601 is the first first logic block and the allocation state of the first first logic block is the second state, it is necessary to first de-allocate the second logic block (i.e., the second logic block identified as 1) to which the first first logic block has been allocated, and update the identifier of the first logic block corresponding to the second logic block identified as 1 in the logic block management table B to an invalid value (for example, it can be 0X7FFF), and update the state corresponding to the first logic block identified as an invalid value to the first state; then allocate the first first logic block to the second logic block identified as 0X6E2D, update the identifier of the first logic block corresponding to the second logic block identified as 0X6E2D in the logic block management table B to 1, and point the pointer to the second first logic block.

[0141] In an exemplary embodiment, the method may further include: sending the updated logical block management table to the host, and sending a logical address-physical address mapping table (L2P mapping table) corresponding to a second logical block in the logical block management table to the host.

[0142] In the disclosed embodiment, the memory controller 330 may send a logic block management table to the host 310 at preset time intervals, or may allocate a first logic block to a new second logic block that meets the recommended criteria each time a new second logic block that meets the recommended criteria appears, obtain an updated logic block management table, and send the updated logic block management table to the host 310; after receiving the recommended second logic block and the mapping relationship between the first logic block and the second logic block, the host 310 may obtain the logical address-physical address mapping table (i.e., L2P mapping table) corresponding to the recommended second logic block from the memory system 320, and store the L2P mapping table in the host memory 312.

[0143] The operating method of the memory system provided by the embodiment of the present disclosure can, on the one hand, dynamically manage the allocation status of the first logic block and the allocation relationship between the first logic block and the second logic block through the logic block management table; on the other hand, through a circular queue constructed according to the identifiers of M first logic blocks, quickly and efficiently search for the first logic block, and quickly allocate the corresponding first logic block to the second logic block that meets the recommended standard among the N second logic blocks, thereby improving resource allocation efficiency, random read performance, and system performance.

[0144] In some embodiments, when there is no first logic block with an allocation status of the first state, the earliest allocated first logic block can be located quickly and efficiently through the circular queue, so as to quickly allocate the corresponding first logic block to the second logic blocks that meet the recommended criteria among the N second logic blocks.

[0145] 3 , an embodiment of the present disclosure provides a memory system 320, comprising: a memory device 340, and a memory controller 330 coupled to the memory device 340 and controlling the memory device 340 to perform data storage operations; the memory controller 330 comprises an interface coupled to communicate with a host 310 (i.e., a host interface 332); the host interface 332 coupled to communicate with the host 310 is configured to send at least part of the mapping information in the first logic block management table and the second logic block management table to the host 310 in sequence.

[0146] Among them, the first logic block management table and the second logic block management table each represent the mapping relationship between the first logic block and the second logic block at different times, and both the first logic block management table and the second logic block management table include a first sequence of identifiers corresponding to M first logic blocks, the identifiers of the M first logic blocks are constructed as a circular queue and the allocation status of the M first logic blocks is managed through the logic block management table, M is an integer greater than or equal to 2; the first logic block management table and the second logic block management table each include identifiers of K first logic blocks whose allocation status at different times is a second status indicating that they have been allocated, and identifiers of K second logic blocks among the N second logic blocks to which the K first logic blocks are allocated, K is an integer greater than 1 and less than or equal to M, and N is an integer greater than M; a first logic block that is first allocated among the K first logic blocks corresponding to the first logic block management table is updated and allocated to a second logic block of the K second logic blocks in the second logic block management table, so as to reflect the update of the mapping relationship of the second logic block management table relative to the mapping relationship of the first logic block management table.

[0147] In the embodiment of the present disclosure, the host interface 332 can send all the mapping information in the first logic block management table and the second logic block management table to the host 310 in sequence, and can also send part of the mapping information in the first logic block management table and the second logic block management table (for example, the mapping information of the second logic block management table that is updated relative to the first logic block management table).

[0148] In one embodiment, the first logic block management table may be the logic block management table shown in FIG. 11 (i.e., the initial state of the logic block management table, in which the allocation states corresponding to the first logic blocks are all unallocated first states), and the second logic block management table may be the logic block management table shown in FIG. 12 or include the bold entries in the logic block management table shown in FIG. 12 (i.e., Y first logic blocks are fixedly allocated to Y second logic blocks (Pinned Region)).

[0149] Taking the first logic block management table as shown in FIG11 and the second logic block management table as shown in FIG12 as an example, when the host interface 332 sends the first logic block management table to the host 310, since the logic block management table shown in FIG11 is the initial state of the logic block management table, the host interface 332 sends all the mapping entries in the logic block management table shown in FIG11 to the host 310; then the host interface 332 sends the second logic block management table to the host 310, at which time the host interface 332 can send all the mapping entries in the logic block management table shown in FIG12 to the host 310, or can send the mapping entries updated in the logic block management table shown in FIG12 relative to the logic block management table shown in FIG11 (i.e., the bold entries in the logic block management table shown in FIG12 (i.e., the mapping entries corresponding to the Y first logic blocks fixedly allocated and the Y second logic blocks (Pinned Region) to which the Y first logic blocks are fixedly allocated)); the allocation state corresponding to the Y first logic blocks basically no longer changes, and the Y first logic blocks are mapped to the Y second logic blocks (Pinned Region). After the mapping relationship of the first logic block and the second logic block is sent to the host 310, when the mapping relationship of the first logic block and the second logic block is subsequently updated, the mapping relationship of the Y first logic blocks and the Y second logic blocks (Pinned Region) does not need to be repeatedly sent to the host 310.

[0150] In one embodiment, the first logic block management table may be the logic block management table shown in FIG. 12 or include the bolded portion of the logic block management table shown in FIG. 12 , and the second logic block management table may be the logic block management table shown in FIG. 13 or include the bolded entries in the logic block management table shown in FIG. 13 (i.e., the first first logic block is assigned to the first second logic block).

[0151] Taking the first logic block management table as shown in FIG12 and the second logic block management table as shown in FIG13 as an example, when the host interface 332 sends the first logic block management table to the host 310, the host interface 332 can send all mapping entries in the logic block management table shown in FIG12 to the host 310, and can also send the mapping entries updated in the logic block management table shown in FIG12 relative to the logic block management table shown in FIG11 (i.e., the bold entries in the logic block management table shown in FIG12 (i.e., the Y first logic blocks are fixed and the Y first logic blocks are fixedly allocated to the Y second logic blocks (Pinned Region) corresponding to the mapping entry); then the host interface 332 sends the second logical block management table to the host 310. At this time, the host interface 332 can send all the mapping entries in the logical block management table shown in Figure 13 to the host 310, and can also send the mapping entries of the logical block management table shown in Figure 13 that are updated relative to the logical block management table shown in Figure 12 (that is, the bold entries in the logical block management table shown in Figure 13 (that is, the mapping entries corresponding to the first logical block identifier 1 and the second logical block identifier 1)).

[0152] In one embodiment, the first logic block management table may be the logic block management table shown in FIG. 13 or include the bolded portion in the logic block management table shown in FIG. 13 , and the second logic block management table may be the logic block management table shown in FIG. 14 or include the mapping entries corresponding to the first logic block identifier 1 to MY in the logic block management table shown in FIG. 14 (i.e., the first to (MY)th first logic blocks are respectively assigned to the first to (MY)th second logic blocks).

[0153] Taking the example that the first logical block management table is the logical block management table shown in Figure 13 and the second logical block management table is the logical block management table shown in Figure 14, when the host interface 332 sends the first logical block management table to the host 310, the host interface 332 can send all the mapping entries in the logical block management table shown in Figure 13 to the host 310, and can also send the mapping entries updated in the logical block management table shown in Figure 13 relative to the logical block management table shown in Figure 12 (that is, the bold entries in the logical block management table shown in Figure 13); then the host interface 332 sends the second logical block management table to the host 310, at which time the host interface 332 can send all the mapping entries in the logical block management table shown in Figure 14 to the host 310, and can also send the mapping entries updated in the logical block management table shown in Figure 14 relative to the logical block management table shown in Figure 13 (that is, the mapping entries corresponding to the first logical block identifier 1~MY in the logical block management table shown in Figure 14).

[0154] In one embodiment, the first logic block management table may be the logic block management table shown in FIG. 14 or include the bolded portion of the logic block management table shown in FIG. 14 , and the second logic block management table may be the logic block management table shown in FIG. 15 or include the bolded entries in the logic block management table shown in FIG. 15 .

[0155] Taking the example that the first logical block management table is the logical block management table shown in Figure 14 and the second logical block management table is the logical block management table shown in Figure 15, when the host interface 332 sends the first logical block management table to the host 310, the host interface 332 can send all the mapping entries in the logical block management table shown in Figure 14 to the host 310, and can also send the mapping entries updated in the logical block management table shown in Figure 14 relative to the logical block management table shown in Figure 13 (that is, the first logical block identifier in the logical block management table shown in Figure 14 is the mapping entry corresponding to 1~MY); then the host interface 332 sends the second logical block management table to the host 310. At this time, the host interface 332 can send all the mapping entries in the logical block management table shown in Figure 15 to the host 310, and can also send the mapping entries updated in the logical block management table shown in Figure 15 relative to the logical block management table shown in Figure 14 (that is, the bold entries in the logical block management table shown in Figure 15).

[0156] Taking the example in which the first logic block management table is the logic block management table shown in Figure 14 and the second logic block management table is the logic block management table shown in Figure 15, the first logic block that is first allocated among the K first logic blocks corresponding to the first logic block management table shown in Figure 14 (i.e., the first logic block corresponding to identifier 1) is updated in the second logic block management table and allocated to a second logic block of the K second logic blocks (i.e., the second logic block corresponding to identifier (M-Y+1)).

[0157] In one embodiment, the first logic block management table may be the logic block management table shown in FIG. 16 , and the second logic block management table may be the logic block management table shown in FIG. 17 or include bold entries in the logic block management table shown in FIG. 17 .

[0158] In one embodiment, the first logic block management table may be the logic block management table shown in FIG. 17 or include the bolded portion of the logic block management table shown in FIG. 17 , and the second logic block management table may be the logic block management table shown in FIG. 18 or include the bolded entries in the logic block management table shown in FIG. 18 .

[0159] In one embodiment, the first logic block management table may be the logic block management table shown in FIG. 18 or include the bolded portion of the logic block management table shown in FIG. 18 , and the second logic block management table may be the logic block management table shown in FIG. 19 or include the bolded entries in the logic block management table shown in FIG. 19 .

[0160] In one embodiment, the first logic block management table may be the logic block management table shown in FIG. 19 or include the bolded portion of the logic block management table shown in FIG. 19 , and the second logic block management table may be the logic block management table shown in FIG. 20 or include the bolded entries in the logic block management table shown in FIG. 20 .

[0161] In some embodiments, the first logic block management table and the second logic block management table may be logic block management tables between two adjacent updated first logic blocks and second logic blocks sent by the host interface 332 to the host 310 . The memory controller 330 can update the logical block management table at every preset time interval, and use the host interface 332 to send the updated logical block management table to the host. In this case, the first logical block management table is the logical block management table sent by the host interface 332 to the host 310 at time T1 to update the L2P mapping table stored in the host memory 312, and the second logical block management table is the logical block management table sent by the host interface 332 to the host 310 at time T2, and the time difference between time T1 and time T2 is the preset time interval; the memory controller 330 can also send the updated logical block management table to the host 310 through the host interface 332 after each logical block management table is updated to update the L2P mapping table stored in the host memory 312; the memory controller 330 can also send the updated logical block management table to the host 310 through the host interface 332 after the mapping relationship between the updated first logical block and the second logical block reaches a certain number to update the L2P mapping table stored in the host memory 312.

[0162] In some embodiments, the first logic block management table includes a first sequence of identifiers corresponding to M first logic blocks, the identifiers of the M first logic blocks are constructed as a circular queue and the allocation status of the M first logic blocks is managed through the logic block management table, the first logic block management table may include identifiers of K first logic blocks whose allocation status at the first moment is a second state indicating that they have been allocated, and identifiers of K second logic blocks among the N second logic blocks to which the K first logic blocks at the first moment are allocated; the second logic block management table includes a first sequence of identifiers corresponding to the M first logic blocks, the identifiers of the M first logic blocks are constructed as a circular queue and the allocation status of the M first logic blocks is managed through the logic block management table. The second logic block management table may include identifiers of K first logic blocks whose allocation status at the second moment is a second status indicating that they have been allocated (the identifiers of the K first logic blocks in the second logic block management table are different from the identifiers of the K first logic blocks in the first logic block management table), and identifiers of K second logic blocks among the N second logic blocks to which the K first logic blocks at the second moment are allocated; a first logic block that is first allocated among the K first logic blocks corresponding to the first logic block management table is updated in the second logic block management table and allocated to a second logic block of the K second logic blocks, so as to reflect the update of the mapping relationship of the second logic block management table relative to the mapping relationship of the first logic block management table.

[0163] In some exemplary embodiments of the present disclosure, M represents the number of logic blocks supported by the memory controller of the memory system in the HPB mode, and the N second logic blocks cover all physical addresses of the memory devices of the memory system.

[0164] In some exemplary embodiments of the present disclosure, both the first logic block management table and the second logic block management table include identifiers of Y first logic blocks whose allocation status is a third status indicating allocated and fixed, and identifiers of Y second logic blocks to which the Y first logic blocks are allocated, where Y is an integer greater than 1, and the sum of Y and K is less than or equal to M; the host interface 332 is configured to send to the host 310 K mapping information updated in the second logic block management table relative to the first logic block management table.

[0165] In the disclosed embodiment, when Y first logical blocks are fixedly allocated to Y second logical blocks (Pinned Region), the allocation status of the Y first logical blocks in the logical block management table is updated to the third status. After the logical block management table is updated, the host interface 332 sends the updated logical block management table to the host 310 (for example, the logical block management table shown in FIG. 12 or including the bold entries in the logical block management table shown in FIG. 12); when the logical block management table is subsequently updated and sent, only the updated entries (for example, the K mapping information that are updated) may be sent, without repeatedly sending the Y mapping information corresponding to the Y first logical blocks in the logical block management table and other entries that are not updated.

[0166] In some exemplary embodiments of the present disclosure, the host interface 332 is further configured to send a logical address-physical address mapping table corresponding to a second logical block to the host 310 .

[0167] FIG. 23 shows a schematic diagram of the interaction between a host and a memory system in an embodiment of the present disclosure.

[0168] In the embodiment of the present disclosure, referring to FIG. 23 , the interaction process between the host 310 and the memory system 320 may include the following steps.

[0169] In step S2301 , the host interface 332 in the memory controller 330 sends a first logical block management table to the host 310 .

[0170] In the embodiment of the present disclosure, the host interface 332 can send the first logic block management table to the host 310, or send part of the mapping information in the first logic block management table to the host 310; the first logic block management table (or part of the mapping information in the first logic block management table) sent by the host interface 332 to the host 310 includes at least one mapping relationship between the first logic block and the second logic block.

[0171] In step S2302 , the host 310 requests the memory system 320 for an L2P mapping table corresponding to the second logical block included in the first logical block management table.

[0172] In the embodiment of the present disclosure, after the host 310 receives the first logical block management table (or partial mapping information in the first logical block management table), it requests the memory system 320 for the L2P mapping table corresponding to the second logical block included in the received first logical block management table (or partial mapping information in the first logical block management table).

[0173] In step S2303 , the host interface 332 in the memory controller 330 sends the L2P mapping table corresponding to the second logical block included in the first logical block management table to the host 310 , and the L2P mapping table corresponding to the second logical block included in the first logical block management table is stored in the host memory 312 in the host 310 .

[0174] In the embodiment of the present disclosure, the memory system 320 responds to a request for the L2P mapping table sent by the host 310, and sends the L2P mapping table corresponding to the second logical block included in the first logical block management table (or partial mapping information in the first logical block management table) to the host 310 for storage in the host memory 312.

[0175] In step S2304 , the host interface 332 in the memory controller 330 sends the second logical block management table to the host 310 .

[0176] In the embodiment of the present disclosure, the memory controller 330 may send a logic block management table to the host 310 at preset time intervals, and the logic block management tables sent sequentially at preset time intervals are the first logic block management table and the second logic block management table.

[0177] In the disclosed embodiment, the memory controller 330 may also allocate a first logic block to a new second logic block that meets the recommended criteria each time a new second logic block that meets the recommended criteria appears, obtain an updated logic block management table, and send the updated logic block management table to the host 310. The logic block management table before each update is the first logic block management table, and the updated logic block management table is the second logic block management table.

[0178] In the embodiment of the present disclosure, the host interface 332 can send a second logic block management table to the host 310, or send part of the mapping information in the second logic block management table to the host 310; the second logic block management table (or part of the mapping information in the second logic block management table) sent by the host interface 332 to the host 310 includes at least one mapping relationship between the first logic block and the second logic block.

[0179] In step S2305 , the host 310 requests the memory system 320 for an L2P mapping table corresponding to the second logical block included in the second logical block management table.

[0180] In the embodiment of the present disclosure, after the host 310 receives the second logical block management table (or partial mapping information in the second logical block management table), it requests the memory system 320 to include the L2P mapping table corresponding to the second logical block included in the received second logical block management table (or partial mapping information in the second logical block management table).

[0181] In step S2306 , the host interface 332 in the memory controller 330 sends the L2P mapping table corresponding to the second logical block included in the second logical block management table to the host 310 , and the L2P mapping table corresponding to the second logical block included in the second logical block management table is stored in the host memory 312 in the host 310 .

[0182] In the embodiment of the present disclosure, the memory system 320 responds to a request for the L2P mapping table sent by the host 310, and sends the L2P mapping table corresponding to the second logical block included in the second logical block management table (or partial mapping information in the second logical block management table) to the host 310 for storage in the host memory 312.

[0183] 3 , an embodiment of the present disclosure provides a memory system 320, comprising: a memory device 340, and a memory controller 330 coupled to the memory device 340 and controlling the memory device 340 to perform data storage operations; the memory controller 330 comprises an interface (i.e., a host interface 332) coupled to communicate with a host 310; the host interface 332 is configured to send a first mapping relationship and a second mapping relationship to the host 310 in sequence after two adjacent logic block management table updates are triggered.

[0184] Among them, the first mapping relationship includes P mapping information of the first logical block and the second logical block, and the P mapping information is included in the first logical block management table. The second mapping relationship includes Q mapping information of the first logical block and the second logical block, and the Q mapping information is included in the second logical block management table. The first logical block management table and the second logical block management table both include a first sequence of identifiers corresponding to M first logical blocks. The identifiers of the M first logical blocks are constructed as a circular queue and the allocation status of the M first logical blocks is managed through the logical block management table. M is an integer greater than or equal to 2, and P and Q are both integers greater than or equal to 1 and less than or equal to M. A first logical block that is first allocated among the M first logical blocks corresponding to the first logical block management table is updated and allocated to a second logical block of the Q second logical blocks in the second logical block management table to reflect the update of the mapping relationship in the second logical block management table relative to the mapping relationship in the first logical block management table.

[0185] In the disclosed embodiment, after a certain update of the logic block management table (the updated logic block management table is referred to as the first logic block management table), the host interface 332 sends the updated mapping information (e.g., P pieces of mapping information) in the first logic block management table to the host 310; after a certain next update (the updated logic block management table is referred to as the second logic block management table), the host interface 332 sends the updated mapping information (e.g., Q pieces of mapping information) in the second logic block management table to the host 310.

[0186] In one embodiment, the first logical block management table obtained in a certain update may be the logical block management table shown in Figure 12, the updated mapping information may be the mapping information marked in bold in Figure 12, and the host interface 332 may send the mapping information marked in bold in Figure 12 to the host 310; the second logical block management table obtained in the next update of a certain time may be the logical block management table shown in Figure 13, the updated mapping information may be the mapping information marked in bold in Figure 13, and the host interface 332 may send the mapping information marked in bold in Figure 13 to the host 310.

[0187] In the disclosed embodiment, when the host interface 332 sends updated mapping information to the host 310, it may be sent to the host 310 one by one in the form of mapping entries, and each mapping entry may include at least an identifier of the first logic block and an identifier of the second logic block.

[0188] Taking the updated mapping information as the mapping information marked in bold in Figure 12 as an example, the host interface 332 can send a mapping entry in which the first logical block in Figure 12 is identified as M-Y+1 and the second logical block is identified as X to the host 310, and then the host interface 332 sends a mapping entry in which the first logical block in Figure 12 is identified as M-Y+2 and the second logical block is identified as X+1 to the host 310, and..., and then the host interface 332 sends a mapping entry in which the first logical block in Figure 12 is identified as M and the second logical block is identified as Z to the host 310.

[0189] Taking the updated mapping information as the mapping information corresponding to the first logical block identified as 1~MY in Figure 14 as an example, the host interface 332 can send the mapping entry with the first logical block identified as 1 and the second logical block identified as 1 in Figure 14 to the host 310, and then the host interface 332 can send the mapping entry with the first logical block identified as 2 and the second logical block identified as 2 in Figure 14 to the host 310, ..., the host interface 332 can send the mapping entry with the first logical block identified as MY and the second logical block identified as MY in Figure 14 to the host 310; that is, the host interface can send the updated mapping information one by one in the form of mapping entries to the host 310.

[0190] In one embodiment, the first logical block management table obtained in a certain update may be the logical block management table shown in Figure 14, the updated mapping information may be the mapping information marked in bold in Figure 14, and the host interface 332 may send the mapping information marked in bold in Figure 14 to the host 310; the second logical block management table obtained in the next update of a certain time may be the logical block management table shown in Figure 15, the updated mapping information may be the mapping information marked in bold in Figure 15, and the host interface 332 may send the mapping information marked in bold in Figure 15 to the host 310.

[0191] Taking the example in which the first logic block management table is the logic block management table shown in Figure 14 and the second logic block management table is the logic block management table shown in Figure 15, the first logic block that is first allocated among the M first logic blocks corresponding to the first logic block management table shown in Figure 14 (that is, the first logic block corresponding to identifier 1) is updated in the second logic block management table and allocated to a second logic block of the Q second logic blocks (that is, the second logic block corresponding to identifier (M-Y+1)).

[0192] In one embodiment, the first logical block management table obtained in a certain update may be the logical block management table shown in Figure 17, the updated mapping information may be the mapping information marked in bold in Figure 17, and the host interface 332 may send the mapping information marked in bold in Figure 17 to the host 310; the second logical block management table obtained in the next update of a certain time may be the logical block management table shown in Figure 18, the updated mapping information may be the mapping information marked in bold in Figure 18, and the host interface 332 may send the mapping information marked in bold in Figure 18 to the host 310.

[0193] Since the principle of solving the problem in the system embodiment is similar to that in the above method embodiment, the implementation of the system embodiment can refer to the implementation of the above method embodiment, and the repeated parts will not be repeated.

[0194] The embodiment of the present disclosure provides a non-temporary computer-readable storage medium, on which computer instructions are stored, wherein the computer instructions execute the operating method of any of the above-mentioned memory systems when they are executed. The computer instructions are suitable for being loaded by the processor and executing the operating method of the memory system provided by each step in any of the above-mentioned embodiments. For details, please refer to the implementation method provided by each step in any of the above-mentioned embodiments, which will not be repeated here. In addition, the description of the beneficial effects of adopting the same method will not be repeated. For technical details not disclosed in the computer-readable storage medium embodiment involved in the present disclosure, please refer to the description of the method embodiment of the present disclosure. As an example, the computer program can be deployed to be executed on one computer device, or on multiple computer devices located at one location, or on multiple computer devices distributed at multiple locations and interconnected by a communication network.

[0195] The present disclosure also provides a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method provided in any of the above-mentioned optional modes.

[0196] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in this description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this disclosure.

[0197] The method and related device provided by the embodiment of the present disclosure are described with reference to the method flow chart and / or structural schematic diagram provided by the embodiment of the present disclosure, and each process and / or box of the method flow chart and / or structural schematic diagram, as well as the combination of the process and / or box in the flow chart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable application display device to produce a machine, so that the instructions executed by the processor of the computer or other programmable application display device produce a device for implementing the function specified in one process or multiple processes of the flow chart and / or one box or multiple boxes of the structural schematic diagram. These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable application display device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the function specified in one process or multiple processes of the flow chart and / or one box or multiple boxes of the structural schematic diagram. These computer program instructions can also be loaded onto a computer or other programmable application display device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the structure diagram.

[0198] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The description and examples are to be regarded as exemplary only, and the true scope of the present disclosure is indicated by the appended claims.

Claims

A method for operating a memory system, comprising: A logic block management table is provided, the logic block management table comprising a first sequence of identifiers corresponding to M first logic blocks, the identifiers of the M first logic blocks being constructed as a circular queue and the allocation status of the M first logic blocks being managed through the logic block management table, where M is an integer greater than or equal to 2; and a first logic block whose allocation status is a first state indicating unallocated is allocated to a second logic block among N second logic blocks, where N is an integer greater than M, according to the order of the identifiers of the M first logic blocks in the circular queue, and the allocation status of the first logic block is updated from the first state to a second state indicating allocated in the logic block management table. The method according to claim 1, wherein M represents the number of logic blocks supported by the memory controller of the memory system in the HPB mode, and the N second logic blocks cover all physical addresses of the memory devices of the memory system. The method according to claim 1, wherein Also includes: If there is no first logic block with the corresponding allocation state as the first state in the circular queue, the second logic block corresponding to the first logic block that is first updated to the second state is allocated, and the allocation state corresponding to the first logic block that is first identified as the second state is updated to the first state. The method according to claim 1, wherein The circular queue includes a pointer, and the pointer is configured to point to one of the M first logic blocks in sequence according to the order of the identifiers of the M first logic blocks in the circular queue; The method also includes: in response to the allocation state of the first logic block pointed to by the pointer being the second state, de-allocating the second logic block corresponding to the first logic block that was first updated to the second state, and updating the allocation state corresponding to the first logic block that was first identified as the second state to the first state. The method according to claim 4, wherein Also includes: The first logic block pointed to by the pointer is allocated to a second logic block among the N second logic blocks, and the pointer is pointed to the next first logic block in the order. The method according to any one of claims 1 to 5, wherein: It also includes: allocating the Y first logic blocks whose allocation status is the first state to Y second logic blocks among N second logic blocks, where Y is an integer greater than 1 and less than M, and updating the allocation status of the Y first logic blocks from the first state to a third state indicating that they have been allocated and fixed in the logic block management table. The method according to claim 6, wherein Allocating the Y first logic blocks whose allocation status is the first state to Y second logic blocks among N second logic blocks includes: allocating Y consecutive first logic blocks whose allocation status is the first state in the circular queue to the Y second logic blocks. The method according to claim 6, wherein According to the order of the identifiers of the M first logic blocks in the circular queue, the first logic block whose allocation state is the third state is skipped. The method according to claim 1, wherein The logic block management table also includes a second sequence of identifiers corresponding to the N second logic blocks; the method also includes: updating the identifier of the first logic block or the identifier of the second logic block in the logic block management table. The method according to claim 1, wherein The number of elements in the circular queue is the same as the number of the first logic blocks, and each of the elements stores an identifier of a corresponding first logic block and an allocation status of the first logic block. The method according to claim 1, wherein The size of the first logical block is the same as the size of the second logical block. The method according to claim 1, wherein Also includes: The updated logic block management table is sent to the host. The method according to claim 12, wherein Also includes: The L2P mapping table corresponding to the second logic block is sent to the host. A memory system, comprising: A memory device, and a memory controller coupled to the memory device and controlling the memory device to perform data storage operations; The memory controller includes an interface coupled to communicate with a host; The interface is configured to send at least part of the mapping information in the first logic block management table and the second logic block management table to the host in sequence; wherein the first logic block management table and the second logic block management table each represent a mapping relationship between the first logic block and the second logic block at different times, and the first logic block management table and the second logic block management table both include a first sequence of identifiers corresponding to M first logic blocks, the identifiers of the M first logic blocks are constructed as a circular queue and the allocation status of the M first logic blocks is managed by the logic block management table, where M is an integer greater than or equal to 2; the first logic block management table and the second logic block management table each represent a mapping relationship between the first logic block and the second logic block at different times, and the first logic block management table and the second logic block management table each include a first sequence of identifiers corresponding to M first logic blocks, the identifiers of the M first logic blocks are constructed as a circular queue and the allocation status of the M first logic blocks is managed by the logic block management table, and M is an integer greater than or equal to 2; The management tables each include identifiers of K first logic blocks whose allocation status at different times is a second status indicating that they have been allocated, and identifiers of K second logic blocks among the N second logic blocks to which the K first logic blocks are allocated, K is an integer greater than 1 and less than or equal to M, and N is an integer greater than M; a first logic block that is first allocated among the K first logic blocks corresponding to the first logic block management table is updated and allocated to a second logic block of the K second logic blocks in the second logic block management table to reflect the update of the mapping relationship of the second logic block management table relative to the mapping relationship of the first logic block management table. The system of claim 14, wherein: M represents the number of logic blocks supported by the memory controller of the memory system in the HPB mode, and the N second logic blocks cover all physical addresses of the memory devices of the memory system. The system of claim 14, wherein: The first logic block management table and the second logic block management table both include identifiers of Y first logic blocks whose allocation status is a third status indicating allocated and fixed, and identifiers of Y second logic blocks to which the Y first logic blocks are allocated, Y is an integer greater than 1, and the sum of Y and K is less than or equal to M; the interface is configured to send to the host K mapping information updated in the second logic block management table relative to the first logic block management table. The system of claim 14, wherein: The interface is further configured to send the L2P mapping table corresponding to the second logic block to the host. A memory system, comprising: A memory device, and a memory controller coupled to the memory device and controlling the memory device to perform data storage operations; The memory controller includes an interface coupled to communicate with a host; The interface is configured to send a first mapping relationship and a second mapping relationship to the host in sequence after two adjacent logic block management table updates are triggered; wherein the first mapping relationship includes P mapping information of the first logic block and the second logic block, the P mapping information is included in the first logic block management table, the second mapping relationship includes Q mapping information of the first logic block and the second logic block, the Q mapping information is included in the second logic block management table, the first logic block management table and the second logic block management table both include a first sequence of identifiers corresponding to M first logic blocks, the identifiers of the M first logic blocks are constructed as a circular queue and the allocation status of the M first logic blocks is managed by the logic block management table, M is an integer greater than or equal to 2, P and Q are both integers greater than or equal to 1 and less than or equal to M; a first logic block that is first allocated among the M first logic blocks corresponding to the first logic block management table is updated and allocated to a second logic block of the Q second logic blocks in the second logic block management table, so as to reflect the update of the mapping relationship in the second logic block management table relative to the mapping relationship in the first logic block management table. The system of claim 18, wherein: M represents the number of logic blocks supported by the memory controller of the memory system in HPB mode, there are N second logic blocks, N is an integer greater than M, and the N second logic blocks cover all physical addresses of the memory devices of the memory system. The system of claim 18, wherein: The interface is further configured to send the L2P mapping table corresponding to the second logic block to the host. A non-transitory computer-readable storage medium having computer instructions stored thereon, wherein: When the computer instructions are executed, the steps of the method according to any one of claims 1 to 13 are executed.

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