Semiconductor structure, forming method thereof and semiconductor device

Abstract

The embodiment of the invention provides a semiconductor structure and a forming method thereof, and a semiconductor device. The semiconductor structure comprises a stacking structure; the semiconductor layer is located on the stacked structure; the channel structure penetrates through the stacking structure and extends into the semiconductor layer; the contact structure extends along the stacking direction of the stacking structure; a first welding structure and a second welding structure; wherein the first welding structure penetrates through the semiconductor layer and is connected with the contact structure, and the second welding structure is connected with the semiconductor layer.

Description

Semiconductor structure and method for forming the same, and semiconductor device

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same, and a semiconductor device.

[0002] Three-dimensional memory is an emerging type of flash memory that solves the limitations of two-dimensional or planar flash memory by vertically stacking multiple layers of data storage units. Three-dimensional memory has excellent precision, supports higher storage capacity in a smaller space, has low cost and low power consumption, and can fully meet many needs.

[0003] However, three-dimensional memory still faces many challenges.

[0004] Summary of the invention

[0005] The present disclosure provides a semiconductor structure and a method for forming the same, as well as a semiconductor device, for solving the problem that the semiconductor structure and the process are relatively complex and the process cost is relatively high due to the special requirements of each conductive through hole structure and each pad on the material in the semiconductor structure.

[0006] To solve the above problems, the technical solution of the present disclosure is implemented as follows:

[0007] The present disclosure provides a semiconductor structure, comprising:

[0008] Stacked structure;

[0009] A semiconductor layer, located on the stacked structure;

[0010] A channel structure, penetrating the stacked structure and extending into the semiconductor layer;

[0011] A contact structure extending along a stacking direction of the stacking structure;

[0012] A first welding structure and a second welding structure; wherein the first welding structure penetrates the semiconductor layer and is connected to the contact structure, and the second welding structure is connected to the semiconductor layer.

[0013] In one embodiment of the present disclosure, the first welding structure and the second welding structure both include a first part and a second part located on the first part; wherein a size of the second part along a first direction is larger than a size of the first part along the first direction, and the first direction is perpendicular to the stacking direction.

[0014] In one embodiment of the present disclosure, the size of the first portion along the first direction is a first size, and the size of the first portion along the stacking direction is a second size; the ratio of the second size to the first size is less than 1:5.

[0015] In an embodiment of the present disclosure, the first portion and the second portion are integrally formed.

[0016] In an embodiment of the present disclosure, a dimension of a portion of the channel structure extending to the semiconductor layer along the stacking direction is less than 200 nm.

[0017] In an embodiment of the present disclosure, a top surface of the semiconductor layer located directly above the channel structure is flush with a top surface of the semiconductor layer located directly above the stacked structure.

[0018] In one embodiment of the present disclosure, a top surface of the semiconductor layer located directly above the channel structure is higher than a top surface of the semiconductor layer located directly above the stacked structure.

[0019] In one embodiment of the present disclosure, the material of the first welding structure and the material of the second welding structure both include aluminum.

[0020] In one embodiment of the present disclosure, the semiconductor structure further includes:

[0021] The isolation structure is at least located between the first welding structure and the semiconductor layer.

[0022] In one embodiment of the present disclosure, the stacking structure includes alternately stacked first material layers and insulating layers, the stacking structure includes a third part and a fourth part arranged in parallel along a direction perpendicular to the stacking direction, the contact structure passes through the third part, the channel structure passes through the fourth part, the first material layer in the third part includes a sacrificial layer, and the first material layer in the fourth part includes a conductive layer.

[0023] In one embodiment of the present disclosure, the channel structure includes a functional layer and a channel layer, the functional layer is located in the stacked structure, the channel layer is located in the stacked structure and extends into the semiconductor layer, and the functional layer covers the sidewall of the channel layer located in the stacked structure.

[0024] To solve the above technical problems, the present disclosure further provides a semiconductor device, including a first semiconductor structure and a semiconductor structure as described in any of the above embodiments;

[0025] The first semiconductor structure is located on one side of the semiconductor structure that is opposite to each other along the stacking direction and is far away from the semiconductor layer. The first semiconductor structure is connected to the semiconductor structure by hybrid bonding.

[0026] In one embodiment of the present disclosure, the first semiconductor structure includes:

[0027] A peripheral circuit is connected to the contact structure in the semiconductor structure.

[0028] In order to solve the above technical problems, the present disclosure further proposes a method for forming a semiconductor structure, comprising:

[0029] Providing a stacking structure, a contact structure, and a channel structure, wherein the channel structure penetrates the stacking structure and protrudes from the stacking structure, and the contact structure extends along a stacking direction of the stacking structure;

[0030] forming a semiconductor layer on the stack structure and the channel structure from a side of the channel structure protruding from the stack structure;

[0031] A first welding structure and a second welding structure are formed, wherein the first welding structure penetrates the semiconductor layer and is connected to the contact structure, and the second welding structure is connected to the semiconductor layer.

[0032] In one embodiment of the present disclosure, forming a semiconductor layer on the stacked structure and the channel structure includes:

[0033] Semiconductor material layers are formed on the stacked structure, the channel structure, and the contact structure; the top surfaces of the semiconductor material layers directly above the channel structure and directly above the contact structure are higher than the top surface of the semiconductor material layer directly above the stacked structure; a portion of the semiconductor material layer is removed to form a first opening and expose the contact structure, and the remaining semiconductor material layer forms the semiconductor layer.

[0034] In one embodiment of the present disclosure, the forming of a semiconductor layer on the stacked structure and the channel structure further includes:

[0035] Before forming the first opening, the semiconductor material layer is planarized so that the top surface of the semiconductor material layer directly above the channel structure is flush with the top surface of the semiconductor material layer directly above the stacked structure.

[0036] In one embodiment of the present disclosure, the method further comprises: forming an isolation layer covering the sidewalls and bottom wall of the first opening and the semiconductor layer;

[0037] At least the isolation layer on the bottom wall of the first opening is removed to expose the contact structure; and part of the isolation layer on the semiconductor layer is removed to form a second opening, wherein the second opening exposes the semiconductor layer; the remaining isolation layer forms an isolation structure.

[0038] In one embodiment of the present disclosure, the forming of the first welding structure and the second welding structure includes:

[0039] After forming the isolation structure, the first welding structure is formed at least in the first opening, and the second welding structure is formed at least in the second opening, wherein the first welding structure and the second welding structure each include a first part and a second part located on the first part, the first part of the first welding structure is located in the first opening, and the second part of the second welding structure is located in the second opening.

[0040] In one embodiment of the present disclosure, the providing of a stack structure, a contact structure, and a channel structure includes:

[0041] A stacking structure, a contact structure, and a channel structure are formed on a base structure; the base structure includes a substrate and a first semiconductor layer between the substrate and the stacking structure, and the channel structure extends into the first semiconductor layer; or the base structure includes a substrate, and the channel structure extends into the substrate;

[0042] The base structure is removed to expose a portion of the channel structure.

[0043] In one embodiment of the present disclosure, the channel structure includes a channel layer and a functional layer surrounding the channel layer, and after removing the base structure, a portion of the functional layer is exposed, and the method further includes:

[0044] After removing the substrate structure, the exposed functional layer is removed to expose a portion of the channel layer.

[0045] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are described in detail below with reference to the accompanying drawings, wherein:

[0046] FIG. 1 is a schematic diagram of a semiconductor structure in some embodiments;

[0047] FIG2A is a schematic diagram 1 of a semiconductor structure along the AA′ cross section and the BB′ cross section provided by an embodiment of the present disclosure;

[0048] FIG2B is a schematic top view of a semiconductor structure provided by an embodiment of the present disclosure;

[0049] 3A and 3B are schematic diagrams of the structures of the first part and the second part provided in an embodiment of the present disclosure;

[0050] FIG4 is a second schematic diagram of a semiconductor structure along the AA′ cross section and the BB′ cross section provided by an embodiment of the present disclosure;

[0051] FIG5 is a third schematic diagram of a semiconductor structure along the AA′ cross section and the BB′ cross section provided by an embodiment of the present disclosure;

[0052] FIG6 is a schematic diagram of a process of forming a semiconductor structure according to an embodiment of the present disclosure;

[0053] 7 to 21 are schematic diagrams of the semiconductor structure formation process along the AA' section and the BB' section provided by the embodiment of the present disclosure;

[0054] 22 and 23 are schematic diagrams of the semiconductor device forming process along the AA′ cross section and the BB′ cross section provided by the embodiment of the present disclosure.

[0055] In order to make the above-mentioned objects, features and advantages of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0056] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein, and therefore the present disclosure is not limited to the specific embodiments disclosed below.

[0057] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0058] When describing the embodiments of the present disclosure in detail, for the sake of convenience, the cross-sectional views showing the device structure will not be partially enlarged according to the general scale, and the schematic views are only examples, which should not limit the scope of protection of the present disclosure. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0059] For ease of description, spatial relationship words such as "under", "below", "below", "below", "above", "on", etc. may be used here to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship words are intended to include other directions of the device in use or operation in addition to the direction depicted in the drawings. For example, if the device in the drawings is turned over, the direction of the element described as being "under" or "under" or "below" other elements or features will be changed to "above" the other elements or features. Thus, the exemplary words "under" and "below" can include both the up and down directions. The device may also have other orientations (rotated 90 degrees or in other orientations), so the spatial relationship descriptors used here should be interpreted accordingly. In addition, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more layers in between.

[0060] In the context of the present application, a structure in which a first feature is described as being "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0061] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of this application.

[0062] The term "three-dimensional memory" as used herein refers to a semiconductor device having a vertically oriented memory cell transistor string (referred to herein as a "memory string", such as a NAND string) on ​​a laterally oriented substrate such that the memory string extends in a vertical direction relative to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to a lateral surface of the substrate.

[0063] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0064] The term "layer" used in this application refers to a material portion including an area with a thickness. The layer can extend over the entire lower or upper structure, or can have a range that is less than the range of the lower or upper structure. In addition, a layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of a continuous structure. For example, a layer can be located between the top surface and the bottom surface of a continuous structure or between any pair of horizontal planes at or at the layer. The layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductors and contact layers (wherein contacts, interconnects and / or through holes are formed) and one or more dielectric layers.

[0065] Flowcharts are used in the present application to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed accurately in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0066] In some embodiments, as shown in FIG. 1 , the channel structure of the semiconductor structure includes a functional layer and a channel layer, and the functional layer covers part of the sidewall of the channel layer. In some embodiments, in the process of forming the channel structure, the depth of the channel structure extending out of the stacked structure is difficult to control within a small range, so that the channel layer not covered by the functional layer formed in the end has a higher height along the Z direction. The semiconductor structure also includes a contact structure and a gate line slit structure (GLS). The top of the channel structure and the gate line slit structure is also covered with a semiconductor layer, and the semiconductor layer is also covered with an isolation layer. In the case where the top height of the contact structure and the top height of the semiconductor layer at the top of the gate line slit structure are both much lower than the top height of the isolation layer, in order to lead out the contact structure and the channel structure, a first conductive via structure penetrating the isolation layer and connected to the contact structure, as well as a second conductive via structure penetrating the isolation layer and connected to the semiconductor layer at the top of the gate line slit structure and / or a third conductive via structure penetrating the isolation layer and connected to the semiconductor layer at the top of the channel structure can be provided. It should be noted that the above-mentioned top refers to the highest point of the semiconductor structure in the Z direction. Furthermore, a first pad may be disposed above the first conductive via structure, a second pad may be disposed above the second conductive via structure, and a third pad may be disposed above the third conductive via structure.

[0067] It is understandable that, since the functional layer not covered by the channel layer in the above-mentioned semiconductor structure has a relatively high height along the Z direction, the thickness of the isolation layer in the Z direction is relatively thick, which further causes the above-mentioned conductive through-hole structures to have a relatively high aspect ratio. In addition, the above-mentioned conductive through-hole structure is filled with conductive material. Since the step coverage of aluminum is relatively poor, it is not suitable for the case where the conductive through-hole structure in Figure 1 has a high aspect ratio. For the filling of through holes with a high aspect ratio, metal tungsten can be considered, but the cost of metal tungsten is relatively high. In addition, since each pad can also be used in the testing stage, it is necessary to select a metal material that is not easily deformed, and the material used for each pad can be metal aluminum. Due to the special requirements of each conductive through-hole structure and each pad on the material in the above-mentioned semiconductor structure, the semiconductor structure and the process are relatively complicated, and the process cost is relatively high.

[0068] To solve one or more of the above problems, referring to FIGS. 2A and 2B , an embodiment of the present disclosure provides a semiconductor structure, including:

[0069] A stacked structure 100; a semiconductor layer 110, located on the stacked structure 100; a channel structure 210, penetrating the stacked structure 100 along the Z direction and extending into the semiconductor layer 110; a contact structure 220, extending along the stacking direction (i.e., the Z direction) of the stacked structure 100; FIG. 2A is a cross-sectional schematic diagram of the semiconductor structure provided by the present disclosure along the AA' and BB' lines shown in FIG. 2B, and FIG. 2B is a schematic diagram of a top view of the semiconductor structure provided by the present disclosure. The numbers of the channel structures 210, the contact structures 220, and the gate line gap structures 230 in FIG. 2B and FIG. 2A are only examples and do not correspond to each other. FIG. 2B also includes a contact area, and the contact area includes a plurality of word line contact structures 221, and the word line contact structures 221 are used to lead out the word lines in the stacked structure 100. FIG. 2B also includes a first welding structure 310 and a second welding structure 320, and the first welding structure 310 is used to lead out the contact structure 220, and the second welding structure 320 is used to lead out the channel structure 210.

[0070] In some embodiments, the channel structure 210 includes a functional layer and a channel layer, the functional layer is located in the stacked structure 100, the channel layer is located in the stacked structure 100 and extends into the semiconductor layer 110, and the functional layer covers the sidewall of the channel layer located in the stacked structure 100. The channel layer extending into the semiconductor layer 110 is not covered by the functional layer. And the height of the channel layer extending into the semiconductor layer 110 in the Z direction is less than the first preset value.

[0071] In some embodiments, the functional layer includes a barrier layer, a trapping layer, and a tunneling layer. The material of the channel layer includes, but is not limited to, polysilicon.

[0072] In some embodiments, the dimension of the portion of the channel structure 210 extending to the semiconductor layer 110 along the stacking direction is less than 200 nm, that is, the first preset value is 200 nm.

[0073] It should be noted that the first preset value given in the above embodiment is only an exemplary demonstration and is not used to limit the specific value of the first preset value in the embodiment of the present disclosure.

[0074] The semiconductor structure shown in FIG2A further includes a first welding structure 310 and a second welding structure 320; the first welding structure 310 penetrates the semiconductor layer 110 and is connected to the contact structure 220, and the second welding structure 320 is connected to the semiconductor layer 110. The first welding structure 310 is used to lead out the contact structure 220, and the second welding structure 320 is used to lead out the channel structure 210. It should be noted that the second welding structure 320 here does not directly lead out the channel structure 210, but indirectly leads out the channel structure 210 through the semiconductor layer 110.

[0075] In some specific examples, the material of the semiconductor layer 110 includes but is not limited to polysilicon. The semiconductor layer 110 can be used as a source layer.

[0076] It can be understood that in the embodiment of the present disclosure, based on the fact that the portion of the channel structure 210 extending to the semiconductor layer 110 is relatively small in size along the stacking direction and the size of the semiconductor layer 110 along the stacking direction is also correspondingly small, the first welding structure 310 is directly in contact with the contact structure 220, and the second welding structure 320 is directly in contact with the semiconductor layer 110. In other words, the contact structure 220 and the channel structure 210 are directly led out through the second welding structure 320 and the first welding structure 310, without having to additionally form a contact structure filled with tungsten between the first welding structure 310 and the contact structure 220 and between the second welding structure 320 and the semiconductor layer 110. This simplifies the semiconductor structure and saves corresponding process steps, thereby reducing process costs.

[0077] In some embodiments, the material of the first welding structure 310 and the material of the second welding structure 320 may both include aluminum, but the materials of the first welding structure 310 and the second welding structure 320 are not limited thereto.

[0078] In some embodiments, as shown in Figures 3A and 3B, the first welding structure 310 and the second welding structure 320 both include a first part 301 and a second part 302 located on the first part 301; wherein the size of the second part 302 along the first direction (i.e., the X direction) is larger than the size of the first part 301 along the first direction, and the first direction is perpendicular to the stacking direction (i.e., the Z direction).

[0079] In some embodiments, the size of the first portion 301 along the first direction is a first size, and the size of the first portion 301 along the stacking direction is a second size; the ratio of the second size to the first size is less than 1:5.

[0080] It should be noted that, as shown in FIG3A , the first portion 301 may be an inverted trapezoid, and for the inverted trapezoid, the first dimensions intercepted at different heights along the Z direction are different, and the first dimension here may be the minimum dimension of the inverted trapezoid along the X direction, that is, the dimension of the bottom of the first portion 301 in FIG3A along the X direction. In some embodiments, as shown in FIG3B , the first portion 301 may be a rectangle, and the first dimensions intercepted at different heights along the Z direction are the same, and the first dimension may be the dimension of the rectangle along the X direction at any height in the Z direction.

[0081] In some embodiments, the first part 301 and the second part 302 are integrally formed, so as to simplify the process flow, save process time and process cost, and reduce the complexity of the lead process.

[0082] In the embodiment of the present disclosure, the conductive material used in the first part 301 and the second part 302 is the same material, including but not limited to aluminum.

[0083] In some embodiments, as shown in FIG. 4 , a top surface of the semiconductor layer 110 located directly above the channel structure 210 is higher than a top surface of the semiconductor layer 110 located directly above the stacked structure 100 .

[0084] In the embodiment of the present disclosure, the topography of the upper surface of the semiconductor layer 110 is irregular and is related to the profile of the portion of the channel structure 210 protruding from the stacked structure 100 .

[0085] Specifically, the semiconductor layer 110 can be formed by depositing semiconductor materials on the side walls and top surfaces of the stacked structure 100 and the channel structure 210 through a deposition process / epitaxial growth process. The semiconductor layer 110 with an irregular upper surface morphology has the same thickness in the Z direction. Since the channel structure 210 protrudes from the stacked structure 100, the top surface of the semiconductor layer 110 located directly above the channel structure 210 is higher than the top surface of the semiconductor layer 110 located directly above the stacked structure 100.

[0086] In some embodiments, as shown in FIG4 , the semiconductor structure further includes a gate line gap structure 230, which penetrates the stacked structure 100 and extends into the semiconductor layer 110. It can be understood that the top surface of the semiconductor layer 110 directly above the gate line gap structure 230 is also higher than the top surface of the semiconductor layer 110 directly above the stacked structure 100.

[0087] In some specific examples, the material of the gate line gap structure 230 may be one or more of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and semiconductor materials such as polysilicon.

[0088] In some embodiments, as shown in FIG. 2A , a top surface of the semiconductor layer 110 located directly above the channel structure 210 is flush with a top surface of the semiconductor layer 110 located directly above the stacked structure 100 .

[0089] Specifically, in the corresponding formation process, the semiconductor layer 110 with an irregular upper surface morphology as shown in FIG. 4 can be formed first, and then the top surface of the semiconductor layer 110 with an irregular upper surface morphology is smoothed by chemical mechanical polishing (CMP), and finally the semiconductor layer 110 with a flat surface in the X direction as shown in FIG. 2A is formed.

[0090] In some embodiments, as shown in FIG2A , the stacked structure 100 includes alternately stacked first material layers 101 and insulating layers 102, and the stacked structure 100 includes a third portion 100b (e.g., a contact region) and a fourth portion 100a (e.g., an array region) arranged in parallel in a direction perpendicular to the stacking direction. The contact structure 220 runs through the third portion 100b, the channel structure 210 runs through the fourth portion 100a, the first material layer 101 in the third portion 100b includes a sacrificial layer, and the first material layer 101 in the fourth portion 100a includes a conductive layer.

[0091] In the embodiment of the present disclosure, the conductive layer in the fourth part 100a can be replaced by a sacrificial layer. During the replacement process, the sacrificial layer in the third part 100b will not be replaced, and the contact structure 220 in the third part 100b can provide support for the stacked structure 100 during the replacement process.

[0092] In some specific examples, the material used for the conductive layer may include one or more of conductive materials such as tungsten, cobalt, copper, aluminum, and metal silicide. The material used for the sacrificial layer may include but is not limited to silicon nitride. The material used for the insulating layer 102 may include but is not limited to silicon oxide.

[0093] In some embodiments, as shown in FIG. 2A , the semiconductor structure further includes:

[0094] The isolation structure 120 is at least located between the first welding structure 310 and the semiconductor layer 110 .

[0095] In the embodiment of the present disclosure, the isolation structure 120 is used to isolate the first welding structure 310 from the semiconductor layer 110, so that the first welding structure 310 and the second welding structure 320 can respectively lead out the contact structure 220 and the channel structure 210. In some specific examples, the material of the isolation structure 120 includes but is not limited to silicon oxide.

[0096] The embodiment of the present disclosure provides a semiconductor device, as shown in FIG5 , comprising a first semiconductor structure 400 and a semiconductor structure as in any of the above embodiments;

[0097] The first semiconductor structure 400 is located on one side of the semiconductor structure that is away from the semiconductor layer 110 and one side of the semiconductor structure that is opposite to each other along the stacking direction. The first semiconductor structure 400 is connected to the semiconductor structure by hybrid bonding.

[0098] In some embodiments, the first semiconductor structure 400 includes:

[0099] Peripheral circuit, the peripheral circuit is connected to the contact structure 220 in the semiconductor structure.

[0100] In some embodiments, the semiconductor structure includes a first bonding layer, which is located on one side of the semiconductor structure that is away from the semiconductor layer 110, of two opposite sides of the semiconductor structure along the Z direction. The first semiconductor structure 400 also includes a second bonding layer. The first bonding layer and the second bonding layer can be bonded by a hybrid bonding process.

[0101] In some embodiments, the first semiconductor structure 400 can be bonded to the semiconductor structure provided by the embodiment of the present disclosure by melt bonding and direct wafer bonding processes, and after the bonding is completed, the side of the substrate away from the stacked structure 100 faces upward.

[0102] It should be noted that the embodiment of the present disclosure takes the example of bonding a storage array wafer including a stacking structure 100 to a first semiconductor structure 400 including a peripheral circuit, and then performing a subsequent back side lead-out process from a side of the substrate away from the stacking structure 100. In other embodiments, after performing the back side lead-out process, the storage array wafer may be bonded to the first semiconductor structure 400 including a peripheral circuit, or only a storage array wafer may be formed and the back side lead-out process may be performed on the storage array wafer.

[0103] In some specific examples, as shown in FIG. 5 , the contact structure 220 can be connected to the peripheral circuit in the first semiconductor structure 400 through the interconnection structure in the interconnection layer 410. The peripheral circuit may include CMOS (Complementary Metal Oxide Semiconductor) and MOS (Metal Oxide Semiconductor) devices. The CMOS devices and MOS devices in the peripheral circuit can be electrically led out through the interconnection structure, the contact structure 220, and the first welding structure 310. The first welding structure 310 can be used to receive a first voltage and transfer the first voltage to the peripheral circuit through the contact structure 220. The second welding structure 320 can be used to receive a second voltage, and the semiconductor layer 110 is used to receive the second voltage and provide it as a source voltage to the multiple channel structures 210. The isolation structure 120 located between the first welding structure 310 and the semiconductor layer 110 prevents the first welding structure 310 and the second welding structure 320 from interfering with each other.

[0104] The present disclosure provides a method for forming a semiconductor structure. FIG6 is a schematic flow chart of the method for forming a semiconductor structure provided by the present disclosure. As shown in FIG6 , the method for forming a semiconductor structure includes:

[0105] Step S10: providing a stacking structure, a contact structure, and a channel structure, wherein the channel structure penetrates the stacking structure and protrudes from the stacking structure, and the contact structure extends along a stacking direction of the stacking structure;

[0106] Step S20: forming a semiconductor layer on the stack structure and the channel structure from a side of the channel structure protruding from the stack structure;

[0107] Step S30: forming a first welding structure and a second welding structure, wherein the first welding structure penetrates the semiconductor layer and is connected to the contact structure, and the second welding structure is connected to the semiconductor layer.

[0108] 7 to 19 are schematic diagrams of the structure of the semiconductor structure forming process provided in the embodiment of the present disclosure. Below, the method for forming the semiconductor structure provided in the embodiment of the present disclosure will be described in detail in conjunction with FIGS. 6 to 19 .

[0109] 7 , step S10 is performed to provide a stack structure 100 , a contact structure 220 , and a channel structure 210 . The channel structure 210 penetrates the stack structure 100 and protrudes from the stack structure 100 , and the contact structure 220 extends along the stacking direction of the stack structure 100 .

[0110] In some embodiments, the stacked structure 100 includes a third portion 100b (e.g., a contact region) and a fourth portion 100a (e.g., an array region) arranged in parallel in a direction perpendicular to the stacking direction. The third portion 100b includes a sacrificial layer 101b and an insulating layer 102 arranged in sequence along the Z direction. The fourth portion 100a includes a conductive layer 101a and an insulating layer 102 arranged in sequence along the Z direction.

[0111] In some specific examples, a substrate structure may be provided first, and the substrate structure may include a first region and a second region arranged in parallel along the X direction. The process of forming the stacked structure 100 includes: firstly, an insulating layer 102 and a sacrificial layer 101b alternately stacked along the Z direction are formed on both the first region and the second region by a deposition process; after forming a gate line slit (GLS), the sacrificial layer 101b on the second region is removed, and the sacrificial layer 101b on the first region is retained; and a conductive layer 101a is deposited at the position where the sacrificial layer 101b is removed on the second region. Thus, a third part 100b of the stacked structure 100 is formed on the first region, and a fourth part 100a of the stacked structure 100 is formed on the second region. In some specific examples, the method further includes filling the gate line slit to form a gate line slit structure 230.

[0112] It should be noted that the number of sacrificial layers 101b, insulating layers 102 and conductive layers 101a in FIG7 is only an example, and the present disclosure does not limit the specific number of sacrificial layers 101b, insulating layers 102 and conductive layers 101a. It is understood that the number of sacrificial layers 101b is the same as the number of conductive layers 101a.

[0113] In the embodiments of the present disclosure, the deposition process includes but is not limited to chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0114] In the embodiment of the present disclosure, the channel structure 210 includes a functional layer and a channel layer, and the functional layer covers part of the sidewall of the channel layer. And the top surface of the functional layer is flush with the top surface of the stacked structure 100, and the channel layer protrudes from the top surface of the stacked structure 100. The channel structure 210 can be formed by etching an initial channel structure, and the initial channel structure includes an initial functional layer and a channel layer, and the initial functional layer covers the sidewall and top of the channel layer. The portion of the initial functional layer higher than the stacked structure 100 is removed to form a functional layer.

[0115] In the embodiment of the present disclosure, the material of the contact structure 220 may be one or more of conductive materials such as tungsten, cobalt, copper, aluminum, and metal silicide.

[0116] For the method of forming the semiconductor layer, the first welding structure, and the second welding structure, the embodiment of the present disclosure provides multiple embodiments, and Figures 8 to 13 are schematic diagrams of a structure of the formation process of the semiconductor layer, the first welding structure, and the second welding structure provided by the present disclosure. Below, the method of forming the semiconductor layer, the first welding structure, and the second welding structure provided by an embodiment of the present disclosure will be described in detail in conjunction with Figures 6, 8 to 13.

[0117] 8 and 9 , step S20 is performed to form a semiconductor layer 110 on the stacked structure 100 and the channel structure 210 from a side of the channel structure 210 protruding from the stacked structure 100. The material of the semiconductor layer 110 includes at least one of the following: polysilicon, polycrystalline germanium, polycrystalline silicon germanium.

[0118] In some embodiments, referring to FIG. 8 and FIG. 9 , forming a semiconductor layer 110 on the stacked structure 100 and the channel structure 210 includes:

[0119] The semiconductor material layer 111 shown in FIG8 is formed on the stacked structure 100, the channel structure 210, and the contact structure 220 through a deposition process; the upper surface of the semiconductor material layer 111 is different in concave and convex, and the semiconductor material layer 111 can be formed conformally according to the channel structure 210 and the contact structure 220, so the thickness of the semiconductor material layer 111 in the Z direction is the same. Since the channel structure 210 and the contact structure 220 protrude from the stacked structure 100, the top surface of the semiconductor material layer 111 located directly above the channel structure 210 and the contact structure 220 is higher than the top surface of the semiconductor material layer 111 located directly above the stacked structure 100; a portion of the semiconductor material layer 111 is removed, and the portion of the semiconductor material layer 111 is located above the contact structure 220. In some embodiments, at least the portion of the contact structure 220 that is higher than the top surface of the stacked structure 100 can also be removed to form a first opening 501 and expose the contact structure 220, and the remaining semiconductor material layer 111 forms the semiconductor layer 110 shown in FIG9.

[0120] 10 , step S30 is performed to form a first welding structure 310 and a second welding structure 320 . The first welding structure 310 penetrates the semiconductor layer 110 and is connected to the contact structure 220 , and the second welding structure 320 is connected to the semiconductor layer 110 .

[0121] The first welding structure 310 is used to lead out the contact structure 220, and the second welding structure 320 is used to lead out the channel structure 210. The conductive material used for the first welding structure 310 and the second welding structure 320 includes but is not limited to aluminum.

[0122] In the embodiment of the present disclosure, a welding layer may be first formed on the semiconductor layer 110, and the welding layer may be subjected to photolithography and etching processes to form a first welding structure 310 and a second welding structure 320. It should be noted that the number of the first welding structure 310 and the second welding structure 320 in FIG. 10 is only an example, and the present disclosure does not limit the specific number of the first welding structure 310 and the second welding structure 320.

[0123] 11 to 13, the method further comprises: forming an isolation layer 121 covering the sidewalls and bottom wall of the first opening 501 and the semiconductor layer 110 by a deposition process as shown in FIG11; the isolation layer 121 completely covers the semiconductor layer 110. The material used for the isolation layer 121 includes but is not limited to silicon oxide.

[0124] The isolation layer 121 at least on the bottom wall of the first opening 501 is removed by an etching process to expose the contact structure 220 ; and part of the isolation layer 121 on the semiconductor layer 110 is removed to form a second opening 502 , which exposes the semiconductor layer 110 ; the remaining isolation layer 121 forms the isolation structure 120 shown in FIG. 12 .

[0125] It should be noted that the number of the first openings 501 and the second openings 502 in FIG. 12 is only an example, and the present disclosure does not limit the specific number of the first openings 501 and the second openings 502 .

[0126] In some embodiments, referring to FIG. 12 and FIG. 13 , forming a first welding structure 310 and a second welding structure 320 includes:

[0127] After forming the isolation structure 120, a first welding structure 310 is formed at least in the first opening 501 using a deposition process, and a second welding structure 320 is formed at least in the second opening 502 using a deposition process, and the top surfaces of the first welding structure 310 and the second welding structure 320 are both higher than the top surface of the isolation structure 120. The first welding structure 310 and the second welding structure 320 both include a first portion 301 and a second portion 302 located on the first portion 301, the first portion 301 of the first welding structure 310 is located in the first opening 501, and the first portion 301 of the second welding structure 320 is located in the second opening 502.

[0128] In the embodiment of the present disclosure, the first part 301 and the second part 302 may be formed by an integral molding method.

[0129] It can be understood that in the above embodiment, after forming the semiconductor material layer 111 , no planarization process is performed, and the opening 501 is directly formed and the semiconductor layer 110 is formed, which can save process flow and process time.

[0130] 14 to 19 are another schematic diagram of the formation process of the semiconductor layer, the first welding structure and the second welding structure provided by the present disclosure.

[0131] 14 to 16 , step S20 is performed to form a semiconductor layer 110 on the stack structure 100 and the channel structure 210 from one side of the channel structure 210 protruding from the stack structure 100 .

[0132] In some embodiments, referring to FIGS. 14 to 16 , a semiconductor layer 110 is formed on the stacked structure 100 and the channel structure 210 , further comprising:

[0133] Before forming the first opening 501, the semiconductor material layer 111 shown in Figure 14 is planarized. After the planarization, as shown in Figure 15, the top surface of the semiconductor material layer 111 located directly above the channel structure 210 is flush with the top surface of the semiconductor material layer 111 located directly above the stacked structure 100.

[0134] A portion of the semiconductor material layer 111 in FIG. 15 that is located above the contact structure 220 is removed, and finally a first opening 501 is formed to expose the contact structure 220 . The remaining semiconductor material layer 111 forms the semiconductor layer 110 shown in FIG. 16 .

[0135] In the embodiment of the present disclosure, a semiconductor material layer 111 can be formed by a deposition process, and then the semiconductor material layer 111 is etched to form a semiconductor layer 110, and finally the semiconductor layer 110 is laser crystallized to form a laser crystallized semiconductor layer 110, for example, to form laser crystallized polysilicon.

[0136] In some embodiments, the semiconductor material layer 111 may be laser crystallized to form a laser crystallized semiconductor material layer 111 , and then the laser crystallized semiconductor material layer 111 may be etched to form a laser crystallized semiconductor layer 110 .

[0137] 19 , step S30 is performed to form a first welding structure 310 and a second welding structure 320 . The first welding structure 310 penetrates the semiconductor layer 110 and is connected to the contact structure 220 , and the second welding structure 320 is connected to the semiconductor layer 110 .

[0138] The first welding structure 310 is used to lead out the contact structure 220, and the second welding structure 320 is used to lead out the channel structure 210. The conductive material used for the first welding structure 310 and the second welding structure 320 includes but is not limited to aluminum.

[0139] 17 to 19, the method further comprises: forming an isolation layer 121 covering the sidewalls and bottom wall of the first opening 501 and the semiconductor layer 110 by a deposition process as shown in FIG17; the isolation layer 121 completely covers the semiconductor layer 110. The material used for the isolation layer 121 includes but is not limited to silicon oxide.

[0140] An etching process is used to remove at least the isolation layer 121 on the bottom wall of the first opening 501 to expose the contact structure 220; and a portion of the isolation layer 121 on the semiconductor layer 110 is removed to form a second opening 502, and the second opening 502 exposes the semiconductor layer 110; the remaining isolation layer 121 forms the isolation structure 120 shown in Figure 18.

[0141] It should be noted that the number of the first openings 501 and the second openings 502 in FIG. 18 is only an example, and the present disclosure does not limit the specific number of the first openings 501 and the second openings 502 .

[0142] In some embodiments, referring to FIG. 19 , forming a first welding structure 310 and a second welding structure 320 includes:

[0143] After forming the isolation structure 120, a first welding structure 310 is formed at least in the first opening 501 using a deposition process, and a second welding structure 320 is formed at least in the second opening 502 using a deposition process, and the top surfaces of the first welding structure 310 and the second welding structure 320 are both higher than the top surface of the isolation structure 120. The first welding structure 310 and the second welding structure 320 both include a first portion 301 and a second portion 302 located on the first portion 301, the first portion 301 of the first welding structure 310 is located in the first opening 501, and the first portion 301 of the second welding structure 320 is located in the second opening 502.

[0144] The first welding structure 310 and the second welding structure 320 can be used for testing and can also be used to connect with other external components or other semiconductor structures. In some embodiments, the size of the second part 302 along the X direction is larger than the size of the first part 301 along the X direction, which can increase the contact area with other components and reduce the poor contact between other components and the above-mentioned welding structure.

[0145] In the embodiment of the present disclosure, the first part 301 and the second part 302 are integrally formed. A welding layer covering the isolation structure 120 can be formed on the isolation structure 120 by a deposition process, and then the welding layer is grooved to form the first welding structure 310 and the second welding structure 320 .

[0146] In the disclosed embodiment, the conductive material used in the first welding structure 310 and the second welding structure 320 can be aluminum. The first welding structure 310 and the second welding structure 320 can be formed by a single deposition process, saving process costs. The first welding structure 310 and the second welding structure 320 can be used to lead out the contact structure 220 and the channel structure 210, respectively, avoiding the use of a high aspect ratio conductive through-hole structure to lead out the contact structure 220 and the channel structure 210. Etching to form a through-hole with a high aspect ratio is not only difficult, but also further limits the type of conductive material filled in the through-hole.

[0147] In some embodiments, a stack structure 100, a contact structure 220, and a channel structure 210 are provided, including:

[0148] 20 and 21 , a stacked structure 100, a contact structure 220, and a channel structure 210 are formed on a base structure 600; the base structure 600 includes a substrate 610 and a first semiconductor layer 620 between the substrate 610 and the stacked structure 100, and the channel structure 210 extends into the first semiconductor layer 620; or, the base structure 600 includes a substrate 610, and the channel structure 210 extends into the substrate 610;

[0149] The base structure 600 is removed to expose a portion of the channel structure 210 .

[0150] 20 , the base structure 600 may include a substrate 610 and a first semiconductor layer 620 . The channel structure 210 extends into the first semiconductor layer 620 .

[0151] 21 , the base structure 600 may include a substrate 610 . The channel structure 210 extends into the substrate 610 .

[0152] The substrate 610 may be a single semiconductor material substrate (eg, a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (eg, a germanium silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0153] The material used for the first semiconductor layer 620 includes, but is not limited to, polysilicon, polycrystalline germanium, and polycrystalline silicon germanium.

[0154] The embodiment of the present disclosure further provides a method for forming a semiconductor device, which will be further described below in conjunction with FIG. 22 and FIG. 23 .

[0155] In some embodiments, a first semiconductor structure 400 as shown in FIG. 22 may be provided first, the first semiconductor structure 400 including a peripheral circuit (not shown in FIG. 22), and then the first semiconductor structure 400 is bonded to a side of the structure shown in FIG. 20 or FIG. 21 away from the base structure 600 along the Z direction, as shown in FIG. 22, so that the base structure 600 faces upward, and then the substrate 610 in FIG. 20 and the first isolation layer between the substrate 610 and the first semiconductor layer 620 are removed by an etching process, or the substrate 610 in FIG. 21 is removed by an etching process to form the structure shown in FIG. 23, and then the first semiconductor layer 620 in FIG. 23 is removed, and then the semiconductor layer, the first contact structure, and the second contact structure are formed by the above-mentioned method for forming a semiconductor structure, thereby forming a semiconductor device. It should be noted that FIG. 7 to FIG. 21 may also include a first semiconductor structure (not shown).

[0156] In other embodiments, the semiconductor layer, the first welding structure and the second welding structure may be formed by using the above method for forming a semiconductor structure, and then the first semiconductor structure may be bonded to a side of the semiconductor structure away from the semiconductor layer along the Z direction to form a semiconductor device.

[0157] In some embodiments, the channel structure 210 includes a channel layer and a functional layer surrounding the channel layer. After removing the base structure 600, a portion of the functional layer is exposed. The method further includes:

[0158] After removing the substrate structure 600 , the exposed functional layer is removed to expose a portion of the channel layer.

[0159] In some embodiments, the channel structure 210 can be formed by etching the initial channel structure 211 in FIG. 20 or FIG. 21, and the initial channel structure 211 includes an initial functional layer and a channel layer. After removing the substrate structure 600, the initial functional layer is exposed above the top of the stacked structure 100, and the portion of the initial functional layer above the stacked structure 100 can be removed by an etching process to form a functional layer, exposing part of the channel layer.

[0160] Although the present disclosure has been described with reference to the current specific embodiments, a person of ordinary skill in the art should recognize that the above embodiments are only used to illustrate the present disclosure, and various equivalent changes or substitutions may be made without departing from the spirit of the present disclosure. Therefore, any changes or modifications to the above embodiments within the spirit of the present disclosure shall fall within the scope of the claims of this application.

Claims

A semiconductor structure comprising: Stacked structure; A semiconductor layer, located on the stacked structure; A channel structure, penetrating the stacked structure and extending into the semiconductor layer; A contact structure extending along a stacking direction of the stacking structure; A first welding structure and a second welding structure; wherein the first welding structure penetrates the semiconductor layer and is connected to the contact structure, and the second welding structure is connected to the semiconductor layer. The semiconductor structure according to claim 1, wherein The first welding structure and the second welding structure each include a first portion and a second portion located on the first portion; wherein a size of the second portion along a first direction is greater than a size of the first portion along the first direction, and the first direction is perpendicular to the stacking direction. The semiconductor structure according to claim 2, wherein The size of the first part along the first direction is a first size, and the size of the first part along the stacking direction is a second size; the second size: the first size is less than 1:

5. The semiconductor structure according to claim 2, wherein The first part and the second part are integrally formed. The semiconductor structure according to claim 1, wherein A dimension of a portion of the channel structure extending to the semiconductor layer along the stacking direction is less than 200 nm. The semiconductor structure according to claim 1, wherein A top surface of the semiconductor layer located directly above the channel structure is flush with a top surface of the semiconductor layer located directly above the stacked structure. The semiconductor structure according to claim 1, wherein A top surface of the semiconductor layer located directly above the channel structure is higher than a top surface of the semiconductor layer located directly above the stacked structure. The semiconductor structure according to claim 1, wherein The material of the first welding structure and the material of the second welding structure both include aluminum. The semiconductor structure according to claim 1, wherein The semiconductor structure further includes an isolation structure located at least between the first welding structure and the semiconductor layer. The semiconductor structure according to claim 1, wherein The stacking structure includes alternately stacked first material layers and insulating layers, the stacking structure includes a third part and a fourth part arranged in parallel along a direction perpendicular to the stacking direction, the contact structure runs through the third part, the channel structure runs through the fourth part, the first material layer in the third part includes a sacrificial layer, and the first material layer in the fourth part includes a conductive layer. The semiconductor structure according to claim 1, wherein The channel structure comprises a functional layer and a channel layer, wherein the functional layer is located in the stacked structure, the channel layer is located in the stacked structure and extends into the semiconductor layer, and the functional layer covers a side wall of the channel layer located in the stacked structure. A semiconductor device comprises a first semiconductor structure and a semiconductor structure as claimed in any one of claims 1 to 11; the first semiconductor structure is located on one side of the semiconductor structure that is away from the semiconductor layer on two opposite sides along the stacking direction, and the first semiconductor structure is connected to the semiconductor structure by hybrid bonding. The semiconductor device according to claim 12, wherein The first semiconductor structure includes: a peripheral circuit connected to a contact structure in the semiconductor structure. A method for forming a semiconductor structure, comprising: Providing a stacking structure, a contact structure, and a channel structure, wherein the channel structure penetrates the stacking structure and protrudes from the stacking structure, and the contact structure extends along a stacking direction of the stacking structure; A semiconductor layer is formed on the stack structure and the channel structure from a side of the channel structure protruding from the stack structure; a first welding structure and a second welding structure are formed, the first welding structure penetrates the semiconductor layer and is connected to the contact structure, and the second welding structure is connected to the semiconductor layer. The forming method according to claim 14, wherein: The semiconductor layer is formed on the stacked structure and the channel structure, comprising: forming a semiconductor material layer on the stacked structure, the channel structure, and the contact structure; the top surface of the semiconductor material layer located directly above the channel structure and the contact structure is higher than the top surface of the semiconductor material layer located directly above the stacked structure; removing a portion of the semiconductor material layer to form a first opening and expose the contact structure, and the remaining semiconductor material layer forms the semiconductor layer. The forming method according to claim 15, wherein: The forming of the semiconductor layer on the stacked structure and the channel structure also includes: before forming the first opening, planarizing the semiconductor material layer so that the top surface of the semiconductor material layer directly above the channel structure is flush with the top surface of the semiconductor material layer directly above the stacked structure. The forming method according to claim 15, wherein: The method also includes: forming an isolation layer covering the side walls, bottom wall and semiconductor layer of the first opening; removing at least the isolation layer on the bottom wall of the first opening to expose the contact structure; and removing part of the isolation layer on the semiconductor layer to form a second opening, wherein the second opening exposes the semiconductor layer; the remaining isolation layer forms an isolation structure. The forming method according to claim 17, wherein: The forming of the first welding structure and the second welding structure includes: after forming the isolation structure, forming the first welding structure at least in the first opening, and forming the second welding structure at least in the second opening, the first welding structure and the second welding structure each include a first part and a second part located on the first part, the first part of the first welding structure is located in the first opening, and the second part of the second welding structure is located in the second opening. The forming method according to claim 14, wherein: The method of providing a stacking structure, a contact structure, and a channel structure includes: forming a stacking structure, a contact structure, and a channel structure on a base structure; the base structure includes a substrate and a first semiconductor layer between the substrate and the stacking structure, and the channel structure extends into the first semiconductor layer; or, the base structure includes a substrate, and the channel structure extends into the substrate; and removing the base structure to expose a portion of the channel structure. The forming method according to claim 19, wherein: The channel structure includes a channel layer and a functional layer surrounding the channel layer. After removing the base structure, a portion of the functional layer is exposed. The method further includes: after removing the base structure, removing the exposed functional layer to expose a portion of the channel layer.

Images