Stacked FET with contact placeholder structure

Abstract

A semiconductor structure is provided that includes a first FET device region that includes a plurality of first FETs, each of the plurality of first FETs including a first source / drain region (28) on each side of a functional gate structure. A second FET device region is stacked over the first FET device region and includes a plurality of second FETs, each of the plurality of second FETs including a second source / drain region (46) on each side of the functional gate structure. The structure further includes at least one first front side contact placeholder structure (32) positioned adjacent to one of the first source / drain regions of the at least one first FET, and at least one second front side contact placeholder structure (52) positioned adjacent to at least one of the second source / drain regions of the at least one second FET.

Description

Background Art

[0001] The present application relates to semiconductor technology, and more particularly to a semiconductor structure including stacked field effect transistors (FETs) with flexible signal and power routing.

[0002] Integrated circuits are continually scaled down to smaller feature sizes and higher transistor densities. Three-dimensional (3D) integration increases transistor density by exploiting the Z dimension, building up in the X and Y dimensions, and building out laterally. Another development that can be used for increasingly densely packaged semiconductor devices is the use of both front-side and back-side interconnects to establish electrical connections between semiconductor devices. Whether the integrated circuit includes one device layer (or equivalently "device area") or multiple device layers, the use of back-side interconnects can improve various aspects of semiconductor device configuration and performance, particularly with respect to density constraints. Summary of the invention

[0003] The present application provides a semiconductor structure with flexible signal and power routing. The semiconductor structure includes a second FET device stacked on a first FET device, wherein the source / drain region of the second FET device is staggered relative to the source / drain region of the first FET device, and wherein a front side contact placeholder structure is located in a device region including the first FET device and the second FET device. Note that the staggering of the first source / drain region and the second source / drain region is not 100% staggered; some overlap of these stacked source / drain regions (in a vertical plane from the first source / drain region and the second source / drain region) may occur.

[0004] In one aspect of the present application, a semiconductor structure is provided. In one embodiment, the semiconductor structure includes a first FET device region, the first FET device region includes a plurality of first FETs, each of the plurality of first FETs includes a first source / drain region located on each side of a functional gate structure. The second FET device region is stacked above the first FET device region and includes a plurality of second FETs, each of the plurality of second FETs includes a second source / drain region located on each side of the functional gate structure. The structure also includes at least one first front side contact placeholder structure positioned adjacent to one of the first source / drain regions of at least one of the first FETs, and at least one second front side contact placeholder structure positioned adjacent to at least one of the second source / drain regions of at least one of the second FETs. The presence of the first and second front side contact placeholder structures provides design flexibility in the structure.

[0005] In an embodiment of the present application, the middle portion of each first source / drain region is staggered relative to the middle portion of each second source / drain region. In such an embodiment, the end of each first source / drain region can overlap the end of each second source / drain region; this helps to reduce the battery height. In such an embodiment, at least one first front side contact placeholder structure is staggered relative to at least one second front side contact placeholder structure, and at least one first front side contact placeholder structure is located below one of the second source / drain regions in the second FET, and at least one second front side contact placeholder structure is located above one of the first source / drain regions of one of the first FETs. These embodiments enable flexible signal and back side power routing.

[0006] In some embodiments of the present application, the structure further comprises a stacked FET device separation layer separating the first FET device region from the second FET device region. The stacked FET device separation layer provides device isolation between the first FET device region and the second FET device region.

[0007] In some embodiments of the present application, the structure further includes a bottom dielectric isolation layer, the bottom dielectric isolation layer being located below each of the first source / drain regions and present in the first FET device region. The bottom dielectric isolation layer increases electrical isolation of the structure and prevents the formation of unwanted parasitic capacitance.

[0008] In some embodiments of the present application, the at least one first front side contact placeholder structure contacts a VSS power supply, and the VSS power supply is connected to a back side power distribution network. This enables connection to the back side of the structure.

[0009] In some embodiments of the present application, the structure further comprises a signal line located above the second FET device region, wherein the signal line contacts an additional back-end-of-line (BEOL) structure, which enables connection to the front side of the structure.

[0010] In some embodiments of the present application, a carrier wafer is located on additional BEOL structures.

[0011] In some embodiments of the present application, another of the second source / drain regions is wired to a VDD power supply through a backside source / drain contact structure that extends from the second FET device region and completely passes through the first FET device region.

[0012] In some embodiments of the present application, another one of the first source / drain regions is wired to a VSS power supply through a backside source / drain contact structure extending into the first FET device region.

[0013] In some embodiments of the present application, another first source / drain region in the first source / drain region and another second source / drain region in the second source / drain region are electrically connected through a shared source / drain contact structure.

[0014] In some embodiments of the present application, at least one first front side contact placeholder structure and at least one second front side contact placeholder structure both include a placeholder dielectric material. The placeholder dielectric material may be designed to exert stress on nearby structures.

[0015] In some embodiments of the present application, at least one of the source / drain regions is wired to a signal line located above the second FET device region through a first source / drain region front side contact structure and a metal via.

[0016] In some embodiments of the present application, at least one of the second source / drain regions is wired to a signal line located above the second FET device region through a second source / drain region front side contact structure and a metal via.

[0017] In some embodiments of the present application, each of the first source / drain regions is located on the surface of the bottom dielectric isolation layer, and each of the second source / drain regions is located on the surface of the stacked FET device separation layer, which is located between the first FET device region and the second FET device region.

[0018] In some embodiments of the present application, the at least one first contact placeholder structure extends through the shallow trench isolation region and the first interlayer dielectric material layer, the first interlayer dielectric material layer is positioned to be laterally adjacent to and above each first source / drain region, and the at least one second front side contact placeholder structure extends through the second interlayer dielectric material layer, the second interlayer dielectric material layer is positioned to be laterally adjacent to and above each second source / drain region.

[0019] In some embodiments of the present application, the first FET and the second FET are nanosheet-containing FETs, wherein the functional gate structure wraps around a nanosheet of semiconductor channel material present in each of the first FET device region and the second FET device region.

[0020] In some embodiments of the present application, the first FET has a first conductivity type and the second FET has a second conductivity type, and wherein the second conductivity type is different from the first conductivity type.

[0021] In some embodiments of the present application, the first FET has a first conductivity type and the second FET has a second conductivity type, and wherein the second conductivity type has the same conductivity type as the first conductivity type.

[0022] In another aspect of the present application, a method for forming a semiconductor structure is provided. The method of the present application will become more apparent by referring to the following drawings and detailed description of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a top view showing a device layout that can be adopted according to an embodiment of the present application.

[0024] Figure 2A-2B The methods that can be used in this application are Figure 1 A cross-sectional view of an exemplary semiconductor structure taken at XX and YY shown in the figure, the exemplary semiconductor structure includes a semiconductor substrate, a bottom dielectric isolation layer located on the semiconductor substrate, a plurality of stacks containing first nanosheets of alternating first sacrificial semiconductor material nanosheets and first semiconductor channel material nanosheets located on the bottom dielectric isolation layer, a first sacrificial gate structure spanning each stack containing first nanosheets, a first source / drain region extending outward from each first semiconductor channel material nanosheet, and a first front-side interlayer dielectric (ILD) material layer located on top of the first source / drain region.

[0025] Figure 3A-3B After forming a plurality of first front side contact placeholder structures, Figure 2A-2B A cross-sectional view of an exemplary semiconductor structure is shown.

[0026] FIG. 4A to FIG. 4B After forming a stacked FET device separation layer and forming a material stack of alternating second sacrificial semiconductor material layers and second semiconductor channel material layers on the stacked FET device separation layer, respectively, FIG. 3A to FIG. 3B A cross-sectional view of an exemplary semiconductor structure is shown.

[0027] Figure 5A-5B After forming a plurality of second sacrificial gate structures spanning different portions of the material stack, patterning the material stack using at least the second sacrificial gate structure as a pattern mask to provide a plurality of second nanosheet-containing stacks of alternating second sacrificial semiconductor material nanosheets and second semiconductor channel material nanosheets, forming a second source / drain region extending outwardly from each second semiconductor channel material nanosheet, and forming a second front-side ILD material layer, Figure 4A-4B A cross-sectional view of an exemplary semiconductor structure shown in FIG.

[0028] Figure 6A-6Brespectively after removing each second sacrificial gate structure and each first sacrificial gate structure, removing each of the second sacrificial semiconductor material nanosheets and the first sacrificial semiconductor material nanosheets so as to suspend each second semiconductor channel material nanosheet and each first semiconductor channel material nanosheet and form a functional gate structure Figure 5A-5B A cross-sectional view of an exemplary semiconductor structure shown in FIG. 1 , wherein the functional gate structure includes a first functional gate structure portion encapsulating a suspended first semiconductor channel material nanosheet and a second functional gate structure portion encapsulating a suspended second semiconductor channel material nanosheet.

[0029] Figure 7A-7B After forming a plurality of second front side contact placeholder structures Figure 6A-6B A cross-sectional view of an exemplary semiconductor structure is shown, wherein a plurality of second front side contact placeholder structures are staggered relative to a plurality of first front side contact placeholder structures, and each of the first front side contact placeholder structures is located below one of the second source / drain regions, and each of the second front side contact placeholder structures is located above one of the first source / drain regions.

[0030] Figures 8A-8B After forming a middle-of-line (MOL) dielectric material layer having contact openings that physically expose the first set of second front side contact placeholder structures, Figure 7A-7B A cross-sectional view of an exemplary semiconductor structure is shown.

[0031] Figure 9A-9B respectively after removing the physically exposed first set of second front side contact placeholder structures by etching and continuing etching to physically expose the first set of first source / drain regions located under the removed first set of second front side contact placeholder structures Figure 8A-B A cross-sectional view of an exemplary semiconductor structure is shown.

[0032] Figures 10A-10B After forming source / drain contact openings that physically expose the first set of second source / drain regions, respectively, Figures 9A-9B A cross-sectional view of an exemplary semiconductor structure is shown.

[0033] Figures 11A-11B In various contact openings and through Figures 8A-8B After forming the front side source / drain containing structure in the opening provided by etching, Figures 10A-10B A cross-sectional view of an exemplary semiconductor structure shown in

[0034] Figures 12A-12B After forming the back-end-of-line (BEOL) dielectric material layer and the M1 signal line, respectively. Figures 11A-11B A cross-sectional view of an exemplary semiconductor structure shown in FIG.

[0035] Figures 13A-13B After forming additional BEOL structures and carrier wafers, respectively Figures 12A-12B A cross-sectional view of an exemplary semiconductor structure is shown.

[0036] FIG. 14A to FIG. 14B They are FIG. 13A to FIG. 13B A cross-sectional view of the exemplary semiconductor structure shown in FIG. 5 after the wafer has been flipped to allow backside processing of the structure.

[0037] Figures 15A-15B respectively after removing the first semiconductor material layer of the semiconductor substrate to physically expose the etching stop layer of the semiconductor substrate Figures 14A-14B A cross-sectional view of an exemplary semiconductor structure is shown.

[0038] Figures 16A-16B After removing the etching stop layer and the second semiconductor material layer of the semiconductor substrate, Figures 15A-15B A cross-sectional view of an exemplary semiconductor structure shown in FIG.

[0039] Figures 17A-17B After forming the backside ILD material layer Figures 16A-16B A cross-sectional view of an exemplary semiconductor structure shown in FIG.

[0040] Figures 18A-18B After forming a patterned mask on the backside ILD material layer Figures 17A-17B A cross-sectional view of an exemplary semiconductor structure shown in FIG. 1 , wherein a patterned mask has an opening that physically exposes one of the first front side contact placeholder structures,

[0041] Figures 19A-19B respectively after etching through the structure using the pattern mask as an etch mask to physically expose the surface of one of the second source / drain regions Figures 18A-18B A cross-sectional view of an exemplary semiconductor structure shown in FIG.

[0042] Figure 20A-20B respectively after forming a backside first source / drain contact opening to one of the first source / drain regions, Figure 19A-19B A cross-sectional view of an exemplary semiconductor structure is shown.

[0043] Figures 21A-21B In the first source / drain contact opening and Figures 19A-19B After forming the backside source / drain contact structure in the opening provided by the etching performed in Figures 20A-20B A cross-sectional view of an exemplary semiconductor structure shown in FIG.

[0044] Figures 22A-22B After forming the backside power rail and backside power distribution network, respectively Figures 21A-21B A cross-sectional view of an exemplary semiconductor structure shown in FIG. DETAILED DESCRIPTION

[0045] The present application will now be described in more detail by reference to the following discussion and the accompanying drawings of the present application. It should be noted that the drawings of the present application are provided for illustration purposes only and, therefore, are not drawn to scale. It should also be noted that identical and corresponding elements are represented by identical reference numerals.

[0046] In the following description, many specific details, such as specific structures, components, materials, dimensions, processing steps and techniques are set forth to provide an understanding of the various embodiments of the present application. However, it will be appreciated by those of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other cases, well-known structures or processing steps are not described in detail to avoid obscuring the present application.

[0047] It will be understood that when an element as a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or intervening elements may also be present. Conversely, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "under" or "beneath" another element, it can be directly under or beneath the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly under" or "directly beneath" another element, there are no intervening elements.

[0048] First reference Figure 1 , shows a top view of an exemplary semiconductor device layout that can be used according to an embodiment of the present application. The semiconductor device layout shown includes various active device areas AA separated from each other by non-active device areas (not specifically marked in the figure). Within each active device area AA, there are multiple gate structures GS, which are oriented parallel to each other. Figure 1 The semiconductor device layout shown in will be used to describe the stacked nanosheet FET device according to the embodiment of the present application. Although stacked nanosheet devices are described and shown, the present application is applicable to other stacked FET devices, including, for example, stacked planar FET devices, stacked FinFET devices, or stacked nanowire devices. Hybrid stacked devices, such as FinFET devices and nanosheet devices, are also contemplated.

[0049] Figure 1 Including passing through Figure 1 A tangent line XX to the middle active device area AA is depicted in FIG. Figure 1 Also includes a tangent line YY, which is perpendicular to XX and passes through the Figure 1The source / drain region in each active device area AA depicted in FIG. The tangent line YY is between a pair of adjacent gate structures present in each active device area AA. In the present application, Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A and Fig.22A The various processing steps and Figure 1 An exemplary semiconductor structure of the cut line XX is shown, Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.19B , Fig. 20B , Fig. 21B and Fig. 22B The various processing steps and Figure 1 An exemplary semiconductor structure is shown with cut line YY in mind.

[0050] Reference now Figure 2A-2B , respectively through Figure 1XX and YY shown in the figure show an exemplary semiconductor structure that can be used in the present application. The exemplary semiconductor structure includes a semiconductor substrate 10 / 12 / 14, a bottom dielectric isolation layer 16 located on the semiconductor substrate 10 / 12 / 14, and a plurality of first nanosheet stacks (as an example, a first nanosheet stack) of alternating first sacrificial semiconductor material nanosheets 18 and first semiconductor channel material nanosheets 20 located on the bottom dielectric isolation layer 16. Figure 2A 1 , a first semiconductor material layer 10, an etch stop layer 12, and a second semiconductor material layer 14. The semiconductor substrate includes a first semiconductor material layer 10, an etch stop layer 12, and a first sacrificial gate structure 22 spanning each stack 18 / 20 including a first nanosheet, a first source / drain region 28 extending outward from each first semiconductor channel material nanosheet 20, and a first front-side interlayer dielectric (ILD) material layer 30 located on top of the first source / drain region 28.

[0051] The exemplary structure also includes a shallow trench isolation region 15 positioned laterally adjacent to the non-etched portion of the second semiconductor material layer 14 of the semiconductor substrate, a first gate spacer 24 positioned laterally adjacent to each sacrificial gate structure 22, and a first inner spacer 26 positioned laterally adjacent to an end wall of each first sacrificial semiconductor material nanosheet 18. The first inner spacer 26 is located below each of the first semiconductor channel material nanosheets 20.

[0052] The first semiconductor material layer 10 of the semiconductor substrate is composed of a first semiconductor material having semiconductor properties. Examples of the first semiconductor material that can be used to provide the first semiconductor material layer 10 include, but are not limited to, silicon (Si), silicon germanium (SiGe) alloys, silicon germanium carbide (SiGeC) alloys, germanium (Ge), III / V compound semiconductors, or II / VI compound semiconductors. The second semiconductor material layer 14 is composed of a second semiconductor material. The second semiconductor material providing the second semiconductor material layer 14 may be the same in composition or different in composition from the first semiconductor material providing the first semiconductor material layer 10. In some embodiments of the present application, the etch stop layer 12 may be composed of a dielectric material, such as silicon dioxide and / or boron nitride. In other embodiments of the present application, the etch stop layer 12 is composed of a semiconductor material that is different in composition from the semiconductor material providing both the first semiconductor material layer 10 and the second semiconductor material layer 14.

[0053] In one example, the first semiconductor material layer 10 is composed of silicon, the etch stop layer 12 is composed of silicon dioxide, and the second semiconductor material layer 14 is composed of silicon. Such a semiconductor substrate including silicon / silicon dioxide / silicon may be referred to as a silicon-on-insulator (SOI) substrate. In another example, the first semiconductor material layer 10 is composed of silicon, the etch stop layer 12 is composed of silicon germanium, and the second semiconductor material layer 14 is composed of silicon. Such a semiconductor substrate including silicon / silicon germanium / silicon may be referred to as a bulk semiconductor substrate.

[0054] The shallow trench isolation region 15 is composed of any trench dielectric material, such as, for example, silicon oxide. In some embodiments, the trench dielectric material, such as SiN, may exist along the sidewalls and bottom wall of the trench dielectric material. The shallow trench isolation region 15 may have a topmost surface coplanar with the topmost surface of the unetched portion of the second semiconductor material layer 14.

[0055] As described above, each first nanosheet-containing stack (each stack is a vertical stack of nanosheets) includes alternating first sacrificial semiconductor material nanosheets 18 and second semiconductor channel material nanosheets 20 stacked one on top of the other. Within each first nanosheet-containing stack, there may be "n" first semiconductor channel material nanosheets 20 and "n or n+1" first sacrificial semiconductor material nanosheets 18; the "n+1" embodiment is not shown, where n is an integer starting from 1. In the illustrated embodiment, each vertical nanosheet-containing stack includes "n" first sacrificial semiconductor material nanosheets 18 and "n" first semiconductor channel material nanosheets 20. As an example, each first nanosheet-containing stack includes two first semiconductor channel material nanosheets 20 and two first sacrificial semiconductor material nanosheets 18.

[0056] Each first sacrificial semiconductor material nanosheet 18 is composed of a third semiconductor material, and each first semiconductor channel material nanosheet 20 is composed of a fourth semiconductor material different from the third semiconductor material. The third and fourth semiconductor materials include one of the semiconductor materials mentioned above for the first semiconductor material layer 10. In some embodiments, the first semiconductor channel material nanosheet 20 is composed of a fourth semiconductor material capable of providing a high channel mobility for an NFET device. In other embodiments, the first semiconductor channel material nanosheet 20 is composed of a fourth semiconductor material capable of providing a high channel mobility for a PFET device.

[0057] Each first sacrificial semiconductor material nanosheet 18 has a first width, and each first semiconductor channel material nanosheet 20 has a second width greater than the first width. In one example, the first width is 10nm to 100nm, and the second width is 20nm to 130nm. Each first sacrificial semiconductor material nanosheet 18 and each first semiconductor channel material nanosheet 20 have the same length. In one example, the length of each first sacrificial semiconductor material nanosheet 18 and each first semiconductor channel material nanosheet 20 is 10nm to 130nm. The vertical height of each first sacrificial semiconductor material nanosheet 18 and each first semiconductor channel material nanosheet 20 is in the range of 4nm to 20nm. The vertical height of each first sacrificial semiconductor material nanosheet 18 can be equal to, greater than, or less than the vertical height of each first semiconductor channel material nanosheet 20.

[0058] The first sacrificial gate structure 22 includes at least a sacrificial gate material. In some embodiments, the first sacrificial gate structure 22 may include a sacrificial gate dielectric material. The sacrificial gate dielectric material may be composed of a dielectric material such as, for example, silicon dioxide. The sacrificial gate material may include, but is not limited to, polysilicon, amorphous silicon, amorphous silicon germanium, tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, platinum, or alloys of such metals.

[0059] The first gate spacer 24 is composed of a gate spacer dielectric material. Examples of gate spacer dielectric materials that can be used to provide the first gate spacer 24 include, but are not limited to, SiN, SiBCN, SiOCN, or SiOC. The bottom dielectric isolation layer 16 is composed of one of the gate spacer dielectric materials mentioned above for the first gate spacer 24.

[0060] The bottom dielectric spacer 16 and the first gate spacer 24 are formed simultaneously, so they are composed of the same compositional gate spacer dielectric material. The bottom dielectric spacer 16 may have a thickness of 5 nm to 50 nm; however, other thicknesses of the bottom dielectric spacer 16 are expected and may be used as the thickness of the bottom dielectric spacer 16.

[0061] The first inner spacer 26 is composed of one of the gate spacer dielectric materials mentioned above for the first gate spacer 24. The gate spacer dielectric material providing the first inner spacer 26 may be compositionally identical to the gate dielectric spacer material providing the first gate spacer 24 or compositionally different.

[0062] The first source / drain region 28 is composed of a semiconductor material and a first dopant. As used herein, a "source / drain or S / D" region may be a source region or a drain region, depending on the subsequent wiring and application of voltage during the operation of a field effect transistor (FET). As is well known, the source / drain region is located on each side of the gate structure. The semiconductor material providing the first source / drain region 28 may include one of the semiconductor materials of the first semiconductor material layer 10 for the semiconductor substrate described above. The semiconductor material providing the first source / drain region 28 may be the same in composition or different in composition from each first semiconductor channel material nanosheet 20. The first dopant present in the first source / drain region 28 may be a p-type dopant or an n-type dopant. The term "p-type" refers to the addition of impurities to an intrinsic semiconductor that produces a defect in valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants (i.e., impurities) include, but are not limited to, boron, aluminum, gallium, phosphorus, and indium. "N-type" refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants (ie, impurities) include, but are not limited to, antimony, arsenic, and phosphorus. In one example, the first source / drain region 28 may have a thickness ranging from 4×10 20 Atom / cm 3 Up to 3×10 21 Atom / cm 3 As shown, the first source / drain region 28 contacts the bottom dielectric isolation layer 16 (see, for example, Figure 2A-2B ).

[0063] The first front side ILD material layer 30 may be composed of a dielectric material including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. The term "low-k" used throughout this application refers to a dielectric material having a dielectric constant of less than 4.0. Unless otherwise specified, all dielectric constants mentioned herein are measured relative to a vacuum.

[0064] Figure 2A-2B The exemplary structure shown in can be formed using conventional nanosheet stacking processes known to those skilled in the art. In one example, Figure 2A-2BThe exemplary structure shown in can be formed by first forming a sacrificial placeholder material layer (not shown) on the surface of the second semiconductor material layer 14. The sacrificial placeholder material layer can include a semiconductor material that is different in composition from the second semiconductor material providing the second semiconductor material layer 14, the third semiconductor material providing each first sacrificial semiconductor material nanosheet 18, and the fourth semiconductor material providing each first semiconductor channel material nanosheet 20. The formation of the placeholder material layer can include an epitaxial growth process or any other deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or evaporation. After forming the placeholder material layer, a material stack of alternating layers of the third semiconductor material and the fourth semiconductor material is formed by epitaxial growth or by using one of the deposition processes described above for forming the placeholder material layer. The material stack and the placeholder material layer can then be patterned using lithography and etching into a multilayer material structure that includes the remaining portion of the placeholder material layer and the remaining portion of the material stack.

[0065] The term "epitaxial growth" or "epitaxially grown" means the growth of a second semiconductor material on the growth surface of a first semiconductor material, wherein the grown second semiconductor material has the same crystalline characteristics as the first semiconductor material. In an epitaxial deposition process, the chemical reactants provided by the source gas are controlled and the system parameters are set so that the deposited atoms arrive at the growth surface of the first semiconductor material with sufficient energy to move around on the growth surface and orient themselves to the crystal arrangement of the atoms of the growth surface. Examples of various epitaxial growth process equipment that can be used in the present application include, for example, rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE). The temperature of epitaxial deposition is typically in the range of 550°C to 900°C. Although higher temperatures generally result in faster deposition, faster deposition may result in crystal defects and film rupture.

[0066] A first sacrificial gate structure 22 is then formed on the multi-layer material stack by depositing a sacrificial gate dielectric material (if present) and a blanket layer of sacrificial gate material. The deposition of the sacrificial gate material and the blanket layer of sacrificial gate dielectric material (if present) includes, but is not limited to, CVD, PECVD, PVD, ALD, or any combination of such deposition processes. After forming these blanket layers, the blanket layer of sacrificial gate dielectric material (if present) and the sacrificial gate dielectric material are converted into a sacrificial gate structure 22 using a patterning process (including photolithography and etching). Etching may include dry etching and / or wet chemical etching. Dry etching may include reactive ion etching (RIE), plasma etching, or ion beam etching (IBE). During this etching, the second semiconductor material layer 14 may be etched, and shallow trench isolation regions 15 may be formed using techniques known to those skilled in the art. Next, the placeholder material layer present in the multi-layer material stack is removed using an etching process that selectively removes the placeholder material layer. A space (or gap) is formed between the bottommost sacrificial semiconductor material layer and the second semiconductor material layer 14 of the multi-layer material stack. The structure is not free floating, but is held in place by the first sacrificial gate structure 22. Next, the first gate spacer 24 and the bottom dielectric isolation layer 16 are formed simultaneously. Notably, the first gate spacer 24 and the bottom dielectric isolation layer 16 are formed by depositing a gate dielectric spacer material followed by a spacer etch. The deposition fills the gap and forms the bottom dielectric isolation layer 16. In an embodiment, the first gate spacer 24 may be I-shaped and have a topmost surface coplanar with the topmost surface of the first sacrificial gate structure 22.

[0067] After forming the first gate spacer 24 and the bottom dielectric isolation layer 16, a multilayer material stack including alternating layers of a third semiconductor material and a fourth semiconductor material is etched, wherein the first sacrificial gate structure 22 and the first gate spacer 24 are used as an etching mask. The etching stops on the bottom dielectric isolation layer 16. In the present application, the unetched (i.e., remaining) portion of each third semiconductor material layer is referred to as a first sacrificial semiconductor material nanosheet 18, and the unetched (i.e., remaining) portion of each fourth semiconductor material layer is referred to as a first semiconductor channel material nanosheet 20. Next, a first inner spacer 26 is formed. The first inner spacer 26 is formed by first recessing each sacrificial semiconductor material nanosheet to form an inner spacer gap adjacent to the end of each first sacrificial semiconductor material nanosheet 18. After this recessing step, the remaining (i.e., recessed) first sacrificial semiconductor material nanosheet 18 has a reduced lateral width compared to the width of the original sacrificial semiconductor material nanosheet. The recessing includes a lateral etching process that selectively removes the sacrificial semiconductor material nanosheet relative to the first semiconductor channel material nanosheet 20. Next, first inner spacers 26 are formed in the inner spacer gaps by conformal deposition of a spacer dielectric material followed by isotropic etching. Next, first source / drain regions 28 are formed by epitaxial growth as defined above, and thereafter a first front side ILD material layer 30 is formed on top of the source / drain regions by deposition followed by a planarization process.

[0068] Reference now Figure 3A-3B , respectively, show the first front side contact placeholder structure 32 after forming a plurality of Figure 2A-2B . A first front side contact placeholder structure 32 is formed laterally adjacent to each first source / drain region 28, and each of the first front side contact placeholder structures 32 extends through the first ILD material layer 30, the shallow trench isolation region 15, and into a portion of the second semiconductor material layer 14. Therefore, each of the first front side contact placeholder structures 32 contacts a subsurface of the second semiconductor material layer 14. The term "subsurface" is used throughout this application to refer to a surface of a material that is between a topmost surface of a material and a bottommost surface of a material.

[0069] The first front side contact placeholder structure 32 is composed of any suitable placeholder dielectric material, such as, for example, SiC, SiCO, and combinations thereof. The placeholder dielectric material providing the front side contact placeholder structure 32 may be designed to exert stress on nearby structures.

[0070] Each first front side contact placeholder structure 32 can be formed by first forming an opening in the exemplary structure, which passes through the first ILD material layer 30 and the shallow trench isolation region 15 and physically exposes a sub-surface of the second semiconductor material layer 14. The opening can be formed by lithography and etching (such as, for example, RIE). After the opening is formed, the opening is filled with a placeholder dielectric material and / or metal using a deposition process. A planarization process such as chemical mechanical polishing (CMP) can be after the deposition of the placeholder dielectric material and / or metal. Each first front side contact placeholder structure 32 has a topmost surface that is coplanar with the topmost surface of the first ILD material layer 30. The number of first front side contact placeholder structures 32 is not limited to Figure 3A-3B Four shown.

[0071] Reference now FIG. 4A to FIG. 4B , respectively showing the material stack 36L / 38L after forming the stacked FET device separation layer 34 and forming the alternating second sacrificial semiconductor material layer 36L and second semiconductor channel material layer 38L on the stacked FET device separation layer 34. FIG. 3A to FIG. 3B The exemplary semiconductor structure shown in FIG. The stacked FET device separation layer 34 includes a dielectric material layer, such as silicon dioxide, tetraethyl orthosilicate (TEOS), fluorinated tetraethyl orthosilicate (FTEOS), and combinations thereof. The stacked FET device separation layer 34 is typically deposited on Figure 3A-3B On the exemplary structure shown in .

[0072] The material stack 36L / 38L is formed by an epitaxial process as defined above and then photolithographically patterned. Each second sacrificial semiconductor material layer 36L is composed of a fifth semiconductor material, and each second semiconductor channel material layer 38L is composed of a sixth semiconductor material, wherein the sixth semiconductor material is different in composition from the fifth semiconductor material layer. The fifth semiconductor material is typically the same in composition as the third semiconductor material used to provide each first sacrificial semiconductor material nanosheet 18, while the sixth semiconductor material may be the same or different in composition from the fourth semiconductor material providing each first semiconductor channel material nanosheet 20. In one example, each first semiconductor channel material nanosheet 20 is composed of a fourth semiconductor material suitable for use with an NFET, and each second semiconductor channel material layer 38L is composed of a sixth semiconductor material suitable for use with a PFET device. The material stack 36L / 38L may include "m" second semiconductor channel material layers 38L and "m or m+1" second sacrificial semiconductor material layers 36L; the "m+1" embodiment is not shown, where m is an integer starting from 1. In the illustrated embodiment, each material stack 36L / 38L includes "m" second sacrificial semiconductor material layers 36L and "m" second semiconductor channel material layers 38L. As an example, each material stack 36L / 38L includes two second semiconductor channel material layers 38L and two second sacrificial semiconductor material layers 36L.

[0073] Reference now Figure 5A-5B , respectively showing Figure 4A-4B The exemplary semiconductor structure shown in , after forming a plurality of second sacrificial gate structures 40 spanning over different portions of the material stack 36L / 38L, patterning the material stack 36L / 38L using at least the second sacrificial gate structure 40 as a pattern mask to provide a plurality of second nanosheet-containing stacks of alternating second sacrificial semiconductor material nanosheets 36 and second semiconductor channel material nanosheets 38, forming a second source / drain region 46 extending outward from each second semiconductor channel material nanosheet 38, and forming a second front-side ILD material layer 48. In the present application, a second gate spacer 42 is formed after forming the second sacrificial gate structure 40, and the second sacrificial gate structure 40 and the second gate spacer 42 are used as a combined etching mask. In this embodiment, and after forming the stack containing the second nanosheet, a second inner spacer 44 is formed at the end wall of each second sacrificial semiconductor material nanosheet 36L.

[0074] The second sacrificial gate structure 40 includes the materials described above for the first sacrificial gate structure 22. The second gate spacer 42 and the second inner dielectric spacer 44 include the materials described above for the first gate spacer 24 and the first inner spacer 26. The second source / drain region 46 includes a semiconductor material and a second dopant. The semiconductor material providing the second source / drain region 46 may be the same in composition or different in composition from the semiconductor material providing the first source / drain region 28. The second dopant may have the same conductivity type or a different conductivity type as the first dopant mentioned above when providing the first source / drain region 28. The second ILD material layer 40 includes one of the dielectric materials mentioned above for the first ILD material layer 30.

[0075] The above is forming Figure 2A-2B The exemplary structures shown in the nanosheet processing mentioned herein can be adapted and used to provide Figure 5A-5B . In this embodiment, the remaining (unetched) portion of each second sacrificial semiconductor material layer 36L forms a second sacrificial semiconductor material nanosheet 36 of the second nanosheet-containing stack, and the remaining (unetched) portion of each second semiconductor channel material layer 38L forms a second semiconductor channel material nanosheet 38 of the second nanosheet-containing stack. The length, width, and height of the second sacrificial semiconductor material nanosheet 36 and the second semiconductor channel material nanosheet 38 are within the ranges mentioned above for the first sacrificial semiconductor material nanosheet 18 and the first semiconductor channel material nanosheet 20, respectively.

[0076] like Figure 5A As shown, each second nanosheet-containing stack 36 / 38 is located vertically above and aligned with the first nanosheet-containing stack 18 / 20. Figure 5B , the second source / drain region 46 is staggered over the first source / drain region 28. It should be noted that in the present application, there can be some overlap between the first source / drain region 28 and the second source / drain region 46; however, the middle (or center) portion of each of the first source / drain region 28 and the second source / drain region 46 is staggered. This overlap helps reduce the cell height.

[0077] Reference now Figure 6A-6B , respectively, after removing each second sacrificial gate structure 40 and each first sacrificial gate structure 22, removing each of the second sacrificial semiconductor material nanosheets 36 and the first sacrificial semiconductor material nanosheets 18 so as to suspend each second semiconductor channel material nanosheet 38 and each first semiconductor channel material nanosheet 20 and form a functional gate structure Figure 5A-5BThe exemplary semiconductor structure shown in FIG. 1 includes a first functional gate structure portion 50B wrapping around the suspended first semiconductor channel material nanosheet 20 and a second functional gate structure portion 50A wrapping around the suspended second semiconductor channel material nanosheet 36. As shown in the figure, a first FET device region D1 and a second FET device region D2 are now formed, each of which includes a functional gate structure wrapped around the semiconductor channel material nanosheet present in the corresponding FET device region.

[0078] The removal of each second sacrificial gate structure 40 and each first sacrificial gate structure 22 includes an etching process that selectively removes the materials that respectively provide the second sacrificial gate structure 40 and the first sacrificial gate structure 22. Typically, a single etch is used, but if different materials are used when providing the second sacrificial gate structure 40 and the first sacrificial gate structure 22, multiple etches may be used.

[0079] Removing each of the second sacrificial semiconductor material nanosheet 36 and the first sacrificial semiconductor material nanosheet 18 may include an etching process that selectively removes the second sacrificial semiconductor material nanosheet 36 and the first sacrificial semiconductor material nanosheet 18 relative to the second semiconductor channel material nanosheet 38 and the first semiconductor material nanosheet 20. Typically, a single etch is used, but if different materials are used in providing the second sacrificial semiconductor material nanosheet 36 and the first sacrificial semiconductor material nanosheet 18, multiple etches may be used.

[0080] The functional gate structure including the first functional gate structure portion 50B and the second functional gate structure portion 50A includes at least a gate dielectric material layer and a gate electrode; the gate dielectric material layer and the gate electrode are not separately shown in the drawings of the present application. Note that the first functional gate structure portion 50B is generally identical in composition to the second functional gate structure portion 50A of the functional gate structure. As is well known, the gate dielectric material layer of the functional gate structure is in direct contact with each semiconductor channel material nanosheet, and the gate electrode is located on the gate dielectric material layer. In some embodiments, the gate structure includes a work function metal (WFM) layer (not shown) located between the gate dielectric material layer and the gate electrode. In other embodiments, the WFM layer is used only as a gate electrode.

[0081] The gate dielectric material layer of the functional gate structure is composed of a gate dielectric material such as, for example, silicon oxide, or a dielectric material having a dielectric constant greater than 4.0 (such dielectric materials may be referred to as high-k gate dielectric materials). Illustrative examples of high-k gate dielectric materials include metal oxides such as, for example, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), zirconium silicon oxynitride (ZrSiOxNy), tantalum oxide (TaOx), titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3) and / or lead zinc niobate (Pb(Zn,Nb)O). The high-k gate dielectric material may further include dopants such as lanthanum (La), aluminum (Al) and / or magnesium (Mg).

[0082] The gate electrode of the functional gate structure may include a material containing a conductive metal, including but not limited to tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), zirconium (Zr), cobalt (Co), copper (Cu), aluminum (Al), lead (Pb), platinum (Pt), tin (Sn), silver (Ag) or gold (Au), tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC X ), titanium carbide (TiC), titanium aluminum carbide, tungsten silicide (WSi2), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide or nickel silicide.

[0083] In some embodiments, the WFM layer can be used as a conductive metal-containing material to provide a gate electrode, or as a separate layer located between a previous layer of gate dielectric material and the gate electrode. The WFM layer can be used to set the threshold voltage of the FET to a desired value. In some embodiments, the WFM layer can be selected to achieve an n-type threshold voltage shift. As used herein, "n-type threshold voltage shift" means a shift of the effective work function of a material containing a work function metal toward the conduction band of silicon in a silicon-containing material. In one embodiment, the work function of the n-type work function metal is 4.1 eV to 4.3 eV. Examples of such materials that can achieve an n-type threshold voltage shift include (but are not limited to) titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or a combination thereof. In other embodiments, the WFM layer can be selected to achieve a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal is in the range of 4.9 eV to 5.2 eV. As used herein, "threshold voltage" is the lowest achievable gate voltage that will turn on a semiconductor device (e.g., a transistor) by making the channel of the device conductive. As used herein, the term "p-type threshold voltage shift" refers to a shift of the effective work function of a work-function metal material toward the valence band of silicon in a silicon-containing material. Examples of such materials that can achieve a p-type threshold voltage shift include, but are not limited to, titanium nitride and tantalum carbide, hafnium carbide, and combinations thereof.

[0084] The functional gate structure including the first functional gate structure portion 50B and the second functional gate structure portion 50A is formed by depositing a gate dielectric material layer, an optional WFM layer and a gate electrode layer or a gate dielectric material layer and a WFM layer, and then performing a planarization process. The deposition of the gate dielectric material layer may include CVD, PECVD or ALD, and the deposition of the WFM layer and / or the gate electrode layer may include CVD, PECVD, PVD, ALD or sputtering. When the materials of the first functional gate structure portion 50B and the second functional gate structure portion 50A providing the functional gate structure are different, a blocking mask technique may be used. It should be noted that the FET present in the first FET device region may have the same conductivity type or a different conductivity type as the FET present in the second FET device region.

[0085] Reference now Figure 7A-7B , respectively, show the formation of a plurality of second front side contact placeholder structures 52 after Figure 6A-6B, wherein a plurality of second front side contact placeholder structures 52 are staggered relative to a plurality of first front side contact placeholder structures 32, and each of the first front side contact placeholder structures 32 is located below one of the second source / drain regions 46, and each of the second front side contact placeholder structures 52 is located above one of the first source / drain regions 28. Each of the second front side contact placeholder structures 52 includes a placeholder dielectric material as described above (the dielectric material may be designed to introduce stress to adjacent structures). Each of the second front side contact placeholder structures 52 is formed by photolithography and etching to form an opening through the second ILD material layer. The opening is located between the second source / drain regions 46, as shown in FIG. Figure 7B As shown. The etching stops on the topmost surface of the stacked FET device separation layer 34. One of the placeholder dielectric materials mentioned above for the first front side contact placeholder structure 32 is then deposited, and thereafter a planarization process is used to remove any placeholder material formed outside the opening and on top of the second ILD material layer 48. The number of second front side contact placeholder structures 52 formed is not limited to three, as shown in FIG. Figure 7B shown.

[0086] Reference now Figures 8A-8B , respectively, show the middle of the process (MOL) dielectric material layer 54 after forming the contact opening 58 Figure 7A-7B In the exemplary semiconductor structure shown, the contact opening 58 physically exposes the first group of second front side contact placeholder structures 52. The MOL dielectric material layer 54 can be composed of one of the dielectric materials mentioned above for the first ILD material layer 30. The MOL dielectric material layer 54 can be formed by a deposition process (such as, for example, CVD, PECVD or spin coating). The formation of the contact opening 58 includes depositing a mask material layer 56, such as an organic planarization layer (OPL), on the MOL dielectric material layer 54. The deposition of the mask material layer 56 includes, but is not limited to, CVD, PECVD or spin coating. The deposited mask material layer 56 is then patterned and etched by photolithography to include a pre-contact opening. The pre-contact opening is then transferred to the MOL dielectric material layer 54 by using transfer etching. In some embodiments, the pre-contact opening and the contact opening 58 are formed by the same etching.

[0087] Reference now Figure 9A-9B , respectively, after removing the physically exposed first set of second front side contact placeholder structures 52 by etching and continuing etching to physically expose the first set of first source / drain regions 28 located below the removed first set of second front side contact placeholder structures 52. Figure 8A-B This provides an extended contact opening 58E, such as Fig. 9BAs shown. The etch for removing the physically exposed first set of second front side contact placeholder structures 52 is selective in removing the placeholder material providing the second front side contact placeholder structures 52. The continued etch includes another etch that removes the second ILD material layer 48, the stacked FET device separation layer 34, and the first ILD material layer 30 while stopping on the surface of the underlying first source / drain region 28. The continued etch may be different from the etch for removing the physically exposed first set of second front side contact placeholder structures 52. In forming FIG. 9A to FIG. 9B After forming the structure shown in FIG. 5 , the mask material layer 56 may be removed from the top of the MOL dielectric material layer 54 using a material removal process that selectively removes the mask material that provides the mask material layer 56 .

[0088] Reference now Figures 10A-10B , respectively, after forming source / drain contact openings 60 that physically expose the first set of second source / drain regions 46. Figures 9A-9B The exemplary semiconductor structure shown in FIG. Fig. 10B As shown, at least one of the second source / drain contact openings 60 may be merged with one of the extended contact openings 58E. The source / drain contact openings 60 may be formed by photolithography and etching.

[0089] Reference now Figures 11A-11B , respectively, showing various contact openings 60 and through Figures 8A-8B After the front side source / drain containing structures 61, 62, 63 are formed in the extended opening 58E provided by etching Figures 10A-10B In the present application, a front side source / drain contact structure that contacts only one of the first source / drain regions 28 may be referred to as a first source / drain region front side contact structure 61, a front side source / drain contact structure that contacts only one of the second source / drain regions 46 may be referred to as a second source / drain region front side contact structure 62, and a front side source / drain contact structure that contacts both the first source / drain region 28 and the second source / drain region 46 may be referred to as a shared source / drain contact structure 63.

[0090] The front side source / drain inclusion structures 61, 62, 63 may be formed using any known metallization process. The front side source / drain inclusion structures 61, 62, 63 include at least a contact conductor material, such as, for example, W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or an alloy thereof. In an embodiment, each front side source / drain inclusion structure 61, 62, 63 may also include a silicide liner (such as TiSi, NiSi, NiPtSi, etc.) and an adhesive metal liner (such as TiN). The contact conductor material may be formed by any suitable deposition method, such as ALD, CVD, PVD, or electroplating. In some embodiments (not shown), before forming the contact conductor material, a metal semiconductor alloy region may be formed in each of the contact opening 62 and the extension opening 58. The metal semiconductor alloy region may be composed of a silicide or a bactericide. In one or more embodiments of the present application, the metal semiconductor alloy region may be formed by first depositing a metal layer (not shown) in the trench. The metal layer may include a metal such as Ni, Co, Pt, W, Ti, Ta, a rare earth metal (e.g., Er, Yt, La), an alloy thereof, or any combination thereof. The metal layer may be deposited by ALD, CVD, PVD, or ALD. The thickness of the metal layer may be 2 nm to 10 nm, but smaller and larger thicknesses may also be used. A diffusion barrier layer (not shown) such as TiN or TaN may then be formed on the metal layer. An annealing process may then be performed at an elevated temperature to induce a reaction of the semiconductor material of the source / drain region to provide a metal semiconductor alloy region. The unreacted portion of the metal layer and the diffusion barrier layer (if present) are then removed, for example, by an etching process (or multiple etching processes). In one embodiment, the etching process may be a wet etch that selectively removes the metal in the metal layer relative to the metal semiconductor alloy in the metal semiconductor alloy region.

[0091] Each front side source / drain containing structure 61, 62, 63 may include one or more source / drain contact pads (not shown). In one or more embodiments, the contact pads (not shown) may include a diffusion barrier material. Exemplary diffusion barrier layer materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. The contact pads may be formed using a conformal deposition process including CVD or ALD. The formed contact pads may have a thickness in the range of 1 nm to 5 nm, although lesser and greater thicknesses may also be used.

[0092] In any of the above embodiments, block mask technology may be used to change the composition of the front side source / drain inclusion structures 61 , 62 , 63 .

[0093] Reference now Figures 12A-12B, respectively, after forming the back-end-of-line (BEOL) dielectric material layer 64 and the M1 signal line 66L Figures 11A-11B ; some of the signal lines 66L include metal vias that connect the signal line to one of the front-side source / drain containing structures 61, 62, 63. It is noteworthy that metal via 66B is used to connect one of the signal lines 66L to the first source / drain region front-side contact structure 61, metal via 66C is used to connect one of the signal lines 66L to the second source / drain region front-side contact structure 62, and metal via 66D connects one of the signal lines 66L to the shared source / drain contact structure. In addition, metal via 66A is used to connect one of the signal lines 66L to the second portion 50A of the functional gate structure, as shown in FIG. Fig. 12A shown.

[0094] The BEOL dielectric material layer 64 includes any interconnect dielectric material and the dielectric material mentioned above when providing the first ILD material layer 30. The BEOL dielectric material layer 64 can be formed by a deposition process, including, for example, CVD, PECVD, ALD, or spin coating. The signal line 66L including the metal vias 66A, 66B, 66C, and 66D can be formed using any known metallization process. The signal line 66L including the metal vias 66A, 66B, 66C, and 66D is composed of a conductive material such as Cu, Co, W, or Ru, with a thin metal bonding pad.

[0095] Reference now Figures 13A-13B , respectively, after forming additional BEOL structures 68 and a carrier wafer 70 Figures 12A-12B . The additional BEOL structure 68 includes one or more interconnect dielectric material layers including one or more wiring / via regions embedded thereon. The additional BEOL structure 68 may be formed using BEOL processing techniques known to those skilled in the art. The carrier wafer 70 may include one of the semiconductor materials mentioned above for the first semiconductor material layer 10. In the present application, the carrier wafer 70 is bonded to the additional BEOL structure 68. This includes processing of the front side of the wafer; that is, the portion of the structure that is located above the semiconductor substrate.

[0096] Reference now Figures 14A-14B , respectively, after the wafer is flipped (180°) to allow backside processing of the structure. Figures 13A-13B The exemplary semiconductor structure shown in FIG. The flipping of the structure can be performed by hand or by using a mechanical device (eg, a robotic arm). After flipping, the first semiconductor material layer 10 is now physically exposed.

[0097] Reference now Figures 15A-15B, respectively show the etching stop layer 12 after the first semiconductor material layer 10 of the semiconductor substrate is removed to physically expose the semiconductor substrate. Figures 14A-14B The removal of the first semiconductor material layer 10 may be performed using a material removal process that selectively removes the semiconductor material providing the first semiconductor material layer 10 .

[0098] Reference now Figures 16A-16B , respectively showing the etching stop layer 12 and the second semiconductor material layer 14 after removing the semiconductor substrate Figures 15A-15B . After these removal steps, the bottom dielectric isolation layer 16 as well as the shallow trench isolation region 15 and the first front side contact placeholder structure 32 are physically exposed. The removal of the etch stop layer 12 includes a material removal process that selectively removes the etch stop layer 12. The removal of the second semiconductor material layer 14 includes a material removal process that selectively removes the second semiconductor material layer 14. In some embodiments, the first semiconductor material layer 10, the etch stop layer 12, and the second semiconductor layer 14 can be removed using a single material removal process.

[0099] Reference now Figures 17A-17B , respectively show the back side ILD material layer 72 after forming Figures 16A-16B The exemplary semiconductor structure shown in FIG. The backside ILD material layer 72 includes one of the dielectric materials mentioned above for the first ILD material layer 30. The backside ILD material layer 72 may be formed using a deposition process such as, for example, CVD, PECVD, or ALD.

[0100] Reference now Figures 18A-18B , respectively show the back side ILD material layer 72 after forming a patterned mask 74 Figures 17A-17B The exemplary semiconductor structure shown, wherein the patterned mask 74 has an opening 76 that physically exposes one of the first front side contact placeholder structures 32. The patterned mask 74 includes any mask material, such as OPL. The patterned mask 74 can be formed by depositing a mask material and then performing photolithographic patterning.

[0101] Reference now Figures 19A-19B , respectively, after etching through the structure using the pattern mask 74 as an etch mask to physically expose the surface of one of the second source / drain regions 46. Figures 18A-18BThe exemplary semiconductor structure shown in FIG. 4 ; the physically exposed second source / drain region 46 should not include any front side source / drain inclusion structures 61, 62, 63 in contact therewith. The etching includes one or more etching processes capable of removing the physically exposed first front side contact placeholder structure 32 and the stacked FET device separation layer 34 below. The back side contact opening 76E is formed by this step of the present application. After the back side contact opening 76E is formed, the patterned mask 74 can be removed using any material removal process that selectively removes the masking material that provides the patterned mask 74.

[0102] Reference now Figure 20A-20B , Figure 20A-20B After forming the backside first source / drain contact opening 78 to physically expose one of the first source / drain regions 28, Figure 19A-19B A cross-sectional view of an exemplary semiconductor structure shown; a backside first source / drain contact opening 78 is physically exposed on the first source / drain region 28, which does not include any frontside source / drain containing structures 61, 62, 63 in contact therewith. The backside first source / drain contact opening 78 can be formed by photolithography and etching. The etching removes portions of the backside ILD material layer 72 and the bottom dielectric isolation layer 16.

[0103] Reference now Figures 21A-21B , respectively showing the contact opening 78 and the Figures 19A-19B After forming the back side source / drain contact structures 80, 81 in the openings (i.e., 76E) provided by the etching performed in Figures 20A-20B . The backside source / drain contact structure contacting the first source / drain region 28 may be referred to as a first backside source / drain contact structure 80, and the backside source / drain contact structure contacting the second source / drain region 46 may be referred to as a second backside source / drain contact structure 81. The backside source / drain contact structures 80, 81 may include the materials described above for the frontside source / drain containing structures 61, 62, 63. The backside source / drain contact structures 80, 81 may be formed using any known metallization process.

[0104] Reference now Figures 22A-22B , respectively, after forming the backside power rails 82, 83 and the backside power distribution network 84 Figures 21A-21B The exemplary semiconductor structure shown in . Backside power rail 82 is the VDD power source, while backside power rail 83 is the VSS power source.

[0105] This step of the present application begins by first forming additional backside ILD material on top of the previously formed backside ILD material layer 72. Collectively, the backside ILD material layer 72 and the added backside ILD material are labeled as element 73 in the drawings. A metallization process is then used to form backside power rails 82, 83. The backside power rails 82, 83 include conductive power rail materials, including but not limited to tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), copper (Cu), platinum (Pt), rhodium (Rh), or palladium (Pd) with a thin metal adhesion layer (such as TiN, TaN, etc.).

[0106] As shown, two of the backside power rails 83 used as VSS sources are connected to the first frontside contact placeholder structure, while another backside power rail 83 used as VSS power supply is connected to the second backside source / drain contact structure 81. As also shown, two of the backside power rails 82 used as VDD sources are buried in the backside ILD material multilayer structure 73, while another backside power rail 82 used as VDD power supply is connected to the backside source / drain contact structure 80.

[0107] After forming the backside conductive structures 82, 83, a backside power distribution network 84 is formed. The backside power distribution network 84 includes elements / components configured to distribute power to the stacked FETs.

[0108] Fig.22A and Fig. 22B(Flipped 180° from the illustration) shows an exemplary semiconductor structure of the present application, which includes a first FET device region D1, including a plurality of first FETs, each of the plurality of first FETs including a first source / drain region 28 located on each side of a functional gate structure (i.e., the first portion 50B of the functional gate structure defined above). A second FET device region D2 is stacked above the first FET device region D1 and includes a plurality of second FETs, each of the plurality of second FETs including a second source / drain region 46 located on each side of a functional gate structure (i.e., the second portion 50B of the functional gate structure defined above). The structure also includes at least one first front side contact placeholder structure 32 positioned adjacent to one of the first source / drain regions 28 of at least one of the first FETs, and at least one second front side contact placeholder structure 52 positioned adjacent to at least one of the second source / drain regions 46 of at least one of the second FETs. As previously described, the first source / drain regions 28 are staggered relative to the second source / drain regions 46, and the at least one first front side contact placeholder structure 32 is staggered relative to the at least one first front side contact placeholder structure 32. In the present application, the at least one first front side contact placeholder structure 32 is located below one of the second source / drain regions 46, and the at least one second front side contact placeholder structure 52 is located above one of the first source / drain regions 28.

[0109] Although the present application has been specifically shown and described with respect to the preferred embodiments of the present application, it will be understood by those skilled in the art that the foregoing and other changes may be made in form and detail without departing from the spirit and scope of the present application. Therefore, the present application is not intended to be limited to the exact form and details described and shown, but to fall within the scope of the appended claims.

Claims

1. A semiconductor structure comprising: a first field effect transistor (FET) device region including a plurality of first FETs, each first FET of the plurality of first FETs including a first source / drain region on each side of a functional gate structure; a second FET device region stacked above the first FET device region and comprising a plurality of second FETs, each second FET of the plurality of second FETs comprising a second source / drain region on each side of the functional gate structure; at least one first front side contact placeholder structure, the at least one first front side contact placeholder structure being located adjacent to one of the first source / drain regions of at least one of the first FETs; and At least one second front side contact placeholder structure is positioned adjacent to at least one second source / drain region of at least one second FET of the second FETs.

2. The semiconductor structure according to claim 1, wherein: The middle portion of each first source / drain region is staggered relative to the middle portion of each second source / drain region.

3. The semiconductor structure according to claim 2, wherein: An end portion of each first source / drain region overlaps an end portion of each second source / drain region.

4. The semiconductor structure of claim 2 or 3, wherein the at least one first front side contact placeholder structure is staggered relative to the second front side contact placeholder structure, and the at least one first front side contact placeholder structure is located below one of the second source / drain regions of one of the second FETs, and the at least one second front side contact placeholder structure is located above one of the first source / drain regions of one of the first FETs. 5 . The semiconductor structure according to claim 1 , further comprising a stacked FET device separation layer separating the first FET device region from the second FET device region. 6 . The semiconductor structure of claim 1 , further comprising a bottom dielectric isolation layer beneath each first source / drain region and present in the first FET device region. 7 .

7. The semiconductor structure of any one of claims 1 to 6, wherein the at least one first front side contact placeholder structure contacts a VSS power supply, and the VSS power supply is connected to a back side power distribution network. 8 . The semiconductor structure of claim 1 , further comprising a signal line located above the second FET device region, wherein the signal line contacts an additional back-end-of-line (BEOL) structure.

9. The semiconductor structure of claim 8, wherein the carrier wafer is located on an additional BEOL structure.

10. A semiconductor structure according to any one of claims 1 to 9, wherein the other of the second source / drain regions is wired to a VDD power supply through a backside source / drain contact structure, the backside source / drain contact structure extending from the second FET device region and completely passing through the first FET device region.

11. The semiconductor structure of any one of claims 1 to 10, wherein the other of the first source / drain regions is wired to a VSS power supply through a backside source / drain contact structure extending into the first FET device region.

12. The semiconductor structure according to any one of claims 1 to 11, wherein: The other one of the first source / drain regions and the other one of the second source / drain regions are electrically connected via a shared source / drain contact structure. 13 . The semiconductor structure of claim 1 , wherein the at least one first front side contact placeholder structure and the at least one second front side contact placeholder structure both comprise a placeholder dielectric material.

14. The semiconductor structure according to any one of claims 1 to 13, wherein at least one of the first source / drain regions is wired to a signal line located above the second FET device region through a first source / drain region front side contact structure and a metal via.

15. The semiconductor structure according to any one of claims 1 to 14, wherein at least one of the second source / drain regions is wired to a signal line located above the second FET device region through a second source / drain region front side contact structure and a metal via.

16. A semiconductor structure according to any one of claims 1 to 15, wherein each of the first source / drain regions is located on the surface of a bottom dielectric isolation layer, and each of the second source / drain regions is located on the surface of a stacked FET device separation layer, and the stacked FET device separation layer is located between the first FET device region and the second FET device region.

17. The semiconductor structure of any one of claims 1 to 16, wherein the at least one first contact placeholder structure extends through a shallow trench isolation region and a first interlayer dielectric material layer, the first interlayer dielectric material layer being positioned laterally adjacent to and above each first source / drain region, and the at least one second front side contact placeholder structure extends through a second interlayer dielectric material layer, the second interlayer dielectric material layer being positioned laterally adjacent to and above each second source / drain region.

18. A semiconductor structure according to any one of claims 1 to 17, wherein the first FET and the second FET are nanosheet-containing FETs, and wherein the functional gate structure wraps around a nanosheet of semiconductor channel material present in each of the first FET device region and the second FET device region.

19. The semiconductor structure of any one of claims 1 to 18, wherein the first FET has a first conductivity type, and the second FET has a second conductivity type, and wherein the second conductivity type is different from the first conductivity type.

20. The semiconductor structure of any one of claims 1 to 19, wherein the first FET has a first conductivity type, and the second FET has a second conductivity type, and wherein the second conductivity type has the same conductivity as the first conductivity type.

21. A method of forming a semiconductor structure according to any one of claims 1 to 20.

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