Deposition mask and method for manufacturing a deposition mask

Abstract

The invention relates to a deposition mask and a method for manufacturing a deposition mask. The deposition mask includes: a silicon substrate including: a plurality of cell regions; a mask frame region other than the plurality of cell regions, the mask frame region including a mask rib region separating the plurality of cell regions; and an outer frame region disposed at an outermost portion of the silicon substrate; a mask rib disposed in the mask rib region; a mask film disposed in each of the plurality of unit regions; a first metal frame disposed in the outer frame region; and a second metal frame surrounding an exterior of the silicon substrate and connected to the first metal frame.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0151731 filed in the Korean Intellectual Property Office on November 6, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a deposition mask and a method for manufacturing the deposition mask. Background Art

[0004] Wearable devices that are developed in the form of glasses or helmets and focus at a distance close to the user's eyes are being developed. For example, the wearable device may be a head-mounted display (HMD) device or AR glasses. Such a wearable device provides an augmented reality (hereinafter, referred to as "AR") image or a virtual reality (hereinafter, referred to as "VR") image to the user.

[0005] Wearable devices such as HMD devices or AR glasses may require a display specification of at least 2000 pixels per inch (PPI) to allow the user to use the device for a long time without feeling dizzy. For this reason, organic light emitting diodes on silicon (OLEDoS) have emerged, which are small organic light emitting display devices with high resolution. OLEDoS technology is a technology that arranges an organic light emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is arranged.

[0006] It will be understood that this technical background section is intended, in part, to provide a useful background for understanding the technology. However, this technical background section may also include ideas, concepts or realizations that were not known or understood as part of the subject matter disclosed herein by a person skilled in the relevant art before the corresponding effective filing date. Summary of the invention

[0007] Aspects of the present disclosure provide a deposition mask capable of manufacturing a high-resolution display panel by forming a mask film on a silicon substrate and a method for manufacturing the deposition mask.

[0008] Aspects of the present disclosure also provide a deposition mask and a method for manufacturing the deposition mask that enable the deposition mask to be attached to a substrate to be deposited without a separate structure inside a deposition apparatus.

[0009] Aspects of the present disclosure also provide a deposition mask capable of improving alignment accuracy and preventing mura defects due to sagging of the mask and a method for manufacturing the deposition mask.

[0010] According to an embodiment, a deposition mask may include: a silicon substrate including: a plurality of unit regions; a mask frame region other than the plurality of unit regions, the mask frame region including a mask rib region separating the plurality of unit regions; and an outer frame region disposed at the outermost portion of the silicon substrate; mask ribs disposed in the mask rib region; a mask membrane (or mask membrane, maskmembrane) disposed in each of the plurality of unit regions; a first metal frame disposed in the outer frame region; and a second metal frame surrounding the outside of the silicon substrate and connected to the first metal frame.

[0011] The silicon substrate may have a substantially circular shape in a plan view, and the second metal frame may have a substantially ring shape surrounding an outside of the silicon substrate in a plan view.

[0012] The silicon substrate may include a frame opening exposing a lower surface of the first metal frame in the outer frame region, and the second metal frame is connected to the first metal frame through the frame opening.

[0013] The first metal frame and the second metal frame may be connected to each other by welding.

[0014] The welded portion where the welding is performed may be continuously connected along the circumference of the second metal frame.

[0015] The welded portion where the welding is performed may be discontinuously connected along the periphery of the second metal frame.

[0016] The deposition mask may further include: at least one metal sheet spanning across the silicon substrate. Both ends of the metal sheet may be connected to the second metal frame respectively.

[0017] The metal sheet may extend along the mask rib region at a lower portion of the silicon substrate, and the second metal frame may include a lower step portion on which the metal sheet is seated.

[0018] The metal sheet may extend along the mask rib region at a lower portion of the silicon substrate, and a groove is provided on a side surface of the second metal frame, the metal sheet being inserted into the groove.

[0019] The metal sheet may extend along the mask rib region at an upper portion of the silicon substrate, and the second metal frame may include an upper step portion on which the metal sheet is seated.

[0020] The thickness of the first metal frame may be greater than the thickness of the mask film.

[0021] The masking film may include a coating.

[0022] The mask ribs may be formed as part of the silicon substrate.

[0023] The mask ribs may include a plating film formed by the same process as the mask film.

[0024] The mask rib may include a stacked structure of a portion of a silicon substrate and a coating film formed by the same process as the mask film.

[0025] A method for manufacturing a deposition mask may include: preparing a silicon substrate, the silicon substrate including a plurality of unit regions and a mask frame region other than the plurality of unit regions, the mask frame region including a mask rib region separating the plurality of unit regions and an outer frame region disposed at the outermost portion of the silicon substrate; forming a mask membrane and a first metal frame by performing an electroplating process; forming unit openings corresponding to the plurality of unit regions and a frame opening exposing a lower surface of the first metal frame by etching a rear surface of the silicon substrate; aligning a second metal frame surrounding the outside of the silicon substrate with the silicon substrate; and connecting the first metal frame and the second metal frame to each other.

[0026] The silicon substrate has a substantially circular shape in a plan view, and the second metal frame has a substantially ring shape surrounding the outside of the silicon substrate in a plan view.

[0027] Connecting the first metal frame and the second metal frame to each other may include a welding process.

[0028] The welded portion where the welding process is performed may be continuously connected along the circumference of the second metal frame.

[0029] The welded portion where the welding process is performed may be discontinuously connected along the circumference of the second metal frame.

[0030] According to the deposition mask and the method for manufacturing the deposition mask according to the embodiment, a high-resolution display panel may be manufactured by forming a mask film on a silicon substrate.

[0031] The deposition mask may be attached to the substrate to be deposited without a separate structure inside the deposition apparatus.

[0032] Alignment accuracy can be improved, and uneven defects due to sagging of the mask can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0034] Figure 1 is a schematic perspective view showing a head mounted display device according to an embodiment;

[0035] Figure 2 It is shown Figure 1 An exploded perspective view of an example of a head mounted display device;

[0036] Figure 3is a schematic perspective view showing a head mounted display device according to an embodiment;

[0037] Figure 4 is an exploded perspective view showing a display device according to an embodiment;

[0038] Figure 5 is a schematic cross-sectional view showing an example in which a portion of a display panel according to an embodiment is cut;

[0039] Figure 6 is a schematic perspective view of a mask according to an embodiment;

[0040] Figure 7 is a schematic plan view of a mask according to an embodiment;

[0041] Figure 8 is a flow chart illustrating a method for manufacturing a mask according to an embodiment;

[0042] Figures 9 to 13 is a schematic cross-sectional process diagram for describing a method for manufacturing a mask according to an embodiment;

[0043] Fig.14 is a schematic plan view of a mask for describing a position of a welding portion between a silicon substrate and a second metal frame according to an embodiment;

[0044] Fig.15 is a schematic plan view of a mask in which a position of a welding portion between a silicon substrate and a second metal frame is changed according to an embodiment;

[0045] Fig.16 is a flow chart illustrating a method for manufacturing a mask according to an embodiment;

[0046] Figures 17 to 21 is a schematic cross-sectional process diagram for describing a method for manufacturing a mask according to an embodiment;

[0047] Fig. 22 is a flow chart illustrating a method for manufacturing a mask according to an embodiment;

[0048] Figure 23 to Figure 27 is a schematic cross-sectional process diagram for describing a method for manufacturing a mask according to an embodiment;

[0049] Fig.28 is a schematic plan view of a mask including a metal sheet according to an embodiment;

[0050] Fig.29 and Fig.30 is a schematic cross-sectional view of a mask in which a metal sheet is coupled (or connected) to a lower surface of a silicon substrate according to an embodiment;

[0051] Fig.31 is a schematic cross-sectional view of a mask in which a metal sheet is coupled (or connected) to an upper surface of a silicon substrate according to an embodiment;

[0052] Fig.32 is a schematic plan view of a mask including a metal sheet according to an embodiment;

[0053] Fig.33 is a conceptual diagram for describing coupling (or connection) of a first metal frame and a second metal frame using an adhesive;

[0054] Fig.34 is a conceptual diagram for describing coupling (or connection) of a first metal frame and a second metal frame using screws;

[0055] Fig.35 is a schematic cross-sectional view of a mask in which a mask rib region has a stacked structure of silicon and metal on silicon according to an embodiment;

[0056] Fig.36 is a schematic cross-sectional view of a mask for describing a thickness of a first metal frame according to an embodiment; and

[0057] Fig.37 and Fig.38 is a schematic cross-sectional view of a mask illustrating a dummy metal pattern provided in a dummy frame region between a first metal frame and an outermost cell region according to an embodiment. DETAILED DESCRIPTION

[0058] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0059] It will also be understood that when a layer or substrate is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, the same reference numerals refer to the same components.

[0060] In the drawings, for convenience of description and for clarity, the size, thickness, ratio, and scale of elements may be exaggerated. The same reference numerals denote the same elements throughout.

[0061] As used herein, “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0062] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in either a conjunctive sense or a disjunctive sense and may be understood to be equivalent to "and / or".

[0063] In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0064] It will be understood that although the terms "first", "second", etc. may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0065] The term "overlap" or "overlapped" means that a first object may be above or below a second object, or on one side of the second object, or vice versa. In addition, the term "overlap" or "overlapped" may include stacking, stacking, facing or facing, extending over, covering or partially covering, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art.

[0066] The terms "facing" and "facing" mean that the first element may be directly or indirectly opposed to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposed to each other, although still facing each other.

[0067] When an element is described as “not overlapping or to not overlap” another element, this may include the elements being spaced apart, offset or separated from each other or any other suitable terminology as would be appreciated and understood by one of ordinary skill in the art.

[0068] When used in this specification, the terms “comprises, comprising, includes and / or including,” “has, have and / or having” and variations thereof indicate the presence of stated features, integers, steps, operations, elements, components and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0069] As used herein, "about" or "approximately" includes the stated value and means within the range of acceptable deviations for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0070] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formalized sense.

[0071] It will be understood that when an element (or region, layer, part, etc.) is referred to in the specification as being "on", "connected to" or "coupled to" another element, the element may be directly disposed on, directly connected to or directly coupled to the other element, or an intervening element may be disposed between the element and the other element.

[0072] It will be understood that the term "connected to" or "coupled to" may include a physical or electrical connection or either a physical or electrical coupling.

[0073] The features of each of the various embodiments of the present disclosure may be partially or completely combined with each other and may interact with each other differently technically, and the various embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0074] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0075] Figure 1 is a schematic perspective view showing a head mounted display device 1 according to the embodiment. Figure 2 It is shown Figure 1An exploded perspective view of an example of a head-mounted display device 1. The first direction X is a width direction of the head-mounted display device 1, the second direction Y is a height direction of the head-mounted display device 1, and the third direction Z is a thickness direction of the head-mounted display device 1.

[0076] Reference Figure 1 and Figure 2 According to the embodiment, the head-mounted display device 1 may include a first display device 10_1, a second display device 10_2, a display device accommodating portion 110, an accommodating portion cover 120, a first eyepiece 131, a second eyepiece 132, a head-mounted band 140, an intermediate frame 160, a first optical member 151, a second optical member 152, a control circuit board 170, and a connector.

[0077] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is connected to the reference Figure 4 and Figure 5 The display device 10 described is substantially the same. Therefore, reference will be made to Figure 4 and Figure 5 The description of the first display device 10_1 and the second display device 10_2 is replaced by the description of the first display device 10_1 and the second display device 10_2.

[0078] The first optical member 151 may be disposed between the first display device 10_1 and the first eyepiece 131. The second optical member 152 may be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 may include at least one convex lens.

[0079] The middle frame 160 may be disposed between the first display device 10_1 and the control circuit board 170, and may be disposed between the second display device 10_2 and the control circuit board 170. The middle frame 160 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0080] The control circuit board 170 may be disposed between the middle frame 160 and the display device receiving portion 110. The control circuit board 170 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 170 may convert an image source input from the outside into digital video data, and may transmit the digital video data to the first display device 10_1 and the second display device 10_2 through the connector.

[0081] The control circuit board 170 may transmit digital video data corresponding to a left-eye image optimized for the left eye of the user to the first display device 10_1, and may transmit digital video data corresponding to a right-eye image optimized for the right eye of the user to the second display device 10_2. As an example, the control circuit board 170 may transmit the same digital video data to the first display device 10_1 and the second display device 10_2.

[0082] The display device receiving portion 110 is used to receive the first display device 10_1, the second display device 10_2, the middle frame 160, the first optical member 151, the second optical member 152, the control circuit board 170, and the connector. The receiving portion cover 120 is provided to cover an open surface of the display device receiving portion 110. The receiving portion cover 120 may include a first eyepiece 131 and a second eyepiece 132, where the user's left eye is provided, and where the user's right eye is provided. Figure 1 and Figure 2 1 and 132 are shown to be provided separately, but the embodiments of the specification are not limited thereto. The first eyepiece 131 and the second eyepiece 132 may be integrated into one body.

[0083] The first eyepiece 131 may be aligned with the first display device 10_1 and the first optical member 151, and the second eyepiece 132 may be aligned with the second display device 10_2 and the second optical member 152. Therefore, the user may observe the image of the first display device 10_1 magnified as a virtual image by the first optical member 151 through the first eyepiece 131, and may observe the image of the second display device 10_2 magnified as a virtual image by the second optical member 152 through the second eyepiece 132.

[0084] The head-mounted strap 140 is used to fix the display device housing portion 110 to the user's head so that the first eyepiece 131 and the second eyepiece 132 of the housing portion cover 120 are respectively disposed on the user's left eye and the user's right eye. In the case where the display device housing portion 110 is implemented as light weight and small size, the head-mounted display device 1 may include a Figure 3 , rather than the headband 140 .

[0085] The head mounted display device 1 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0086] Figure 3 1 is a schematic perspective view showing a head mounted display device 1_1 according to the embodiment.

[0087] Reference Figure 3 The head mounted display device 1_1 according to the embodiment may be a glasses type display device in which the display device accommodating portion 120_1 is implemented as light weight and small size. The head mounted display device 1_1 according to the embodiment may include a display device 10_3, a left eye lens 311, a right eye lens 312, a support frame 350, glasses frame legs 341 and 342, an optical member 320, an optical path conversion member 330, and a display device accommodating portion 120_1.

[0088] Figure 3 The display device 10_3 shown in FIG. Figure 4 and Figure 5 The display device 10 described is substantially the same. Therefore, reference will be made to Figure 4 and Figure 5 The description of the display device 10_3 is replaced by the description of the display device 10_3.

[0089] The display device accommodating portion 120_1 may include a display device 10_3, an optical member 320, and an optical path conversion member 330. Since an image displayed in the display device 10_3 is enlarged by the optical member 320 and its optical path is converted by the optical path conversion member 330, the image may be provided to the right eye of the user through the right eye lens 312. Therefore, the user may observe an augmented reality image in which a virtual image displayed in the display device 10_3 and a real image observed through the right eye lens 312 are combined through the right eye.

[0090] exist Figure 3 3 shows that the display device accommodating portion 120_1 is disposed at the right distal end of the supporting frame 350, but the specification is not limited thereto. For example, the display device accommodating portion 120_1 may be disposed at the left distal end of the supporting frame 350, and in this case, the image of the display device 10_3 may be provided to the left eye of the user. As an example, the display device accommodating portion 120_1 may be disposed at both the left distal end and the right distal end of the supporting frame 350. In this case, the user may observe the image displayed in the display device 10_3 through both the user's left eye and the user's right eye.

[0091] Figure 4 is an exploded perspective view showing a display device 10 according to an embodiment.

[0092] Reference Figure 4, the display device 10 according to the embodiment is a device for displaying a moving image or a still image. The display device 10 according to the embodiment can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be applied to a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. As an example, the display device 10 can be applied to a smart watch, a watch phone, and a head-mounted display (HMD) for realizing virtual reality and augmented reality.

[0093] The display device 10 according to the embodiment may include a display panel 410 , a heat dissipation layer 420 , a circuit board 430 , a driving circuit 440 , and a power supply circuit 450 .

[0094] The display panel 410 may be formed in a planar shape similar to a quadrilateral. For example, the display panel 410 may have a planar shape similar to a quadrilateral having short sides in the first direction DR1 (or the first direction X) and long sides in the second direction DR2 (or the second direction Y) intersecting the first direction DR1. In the display panel 410, the corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded to have a selectable curvature, or may be formed at right angles. The planar shape of the display panel 410 is not limited to a quadrilateral, and may be formed similarly to other polygons, circles, or ellipses. The planar shape of the display device 10 may follow the planar shape of the display panel 410, but the present specification is not limited thereto.

[0095] The display panel 410 may include a display area where an image is displayed and a non-display area where an image is not displayed.

[0096] The display area may include pixels, and each of the plurality of pixels may include a sub-pixel ( Figure 5 The sub-pixels SP1, SP2 and SP3 in the embodiment of the present invention include pixel transistors. The pixel transistors may be formed by a semiconductor process and may be disposed on a semiconductor substrate ( Figure 5 For example, the pixel transistor may be formed of a complementary metal oxide semiconductor (CMOS).

[0097] The heat dissipation layer 420 may overlap the display panel 410 in the third direction DR3 (or the third direction Z), which is the thickness direction of the display panel 410. The heat dissipation layer 420 may be disposed on one surface or one surface of the display panel 410, for example, on the rear surface of the display panel 410. The heat dissipation layer 420 is used to dissipate heat generated from the display panel 410. The heat dissipation layer 420 may include a metal layer having high thermal conductivity, such as a graphite layer, a silver (Ag) layer, a copper (Cu) layer, or an aluminum (Al) layer.

[0098] The circuit board 430 may be electrically connected to the pads of the pad area of ​​the display panel 410 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 430 may be a flexible printed circuit board or a flexible film made of a flexible material. Figure 4 4 shows that the circuit board 430 is not folded, but the circuit board 430 may be bent. In this case, one end or one end of the circuit board 430 may be disposed on the rear surface of the display panel 410. One end or one end of the circuit board 430 may be the other end or the opposite end of the pad of the circuit board 430 connected to the pad area of ​​the display panel 410 by using a conductive adhesive member.

[0099] The driving circuit 440 may receive digital video data and a timing signal from the outside, and may generate a scanning timing control signal, an emission timing control signal, and a data timing control signal for controlling the display panel 410 according to the timing signal.

[0100] The power circuit 450 may generate a panel driving voltage according to a power voltage from the outside.

[0101] The driving circuit 440 and the power supply circuit 450 may each be formed as an integrated circuit (IC) and attached to one surface or one surface of the circuit board 430 .

[0102] Figure 5 FIG. 4 is a diagram showing a display panel 410 (see FIG. 4 ) according to an embodiment of the present invention Figure 4 ) is a schematic cross-sectional view of an example in which a portion of the sample is cut. For example, Figure 5 A partial cross-sectional structure of a display area including sub-pixels SP1 , SP2 , and SP3 is shown.

[0103] Reference Figure 5 , the display panel 410 may include a semiconductor back panel SBP, a light emitting element back panel EBP, a light emitting element layer EMI, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate (not shown).

[0104] The semiconductor backplane SBP may include a semiconductor substrate SSUB including a pixel transistor PTR, a semiconductor insulating film covering the pixel transistor PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively.

[0105] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. The well area WA may be provided on the upper surface of the semiconductor substrate SSUB. The well area WA may be a region doped with a second type of impurity. The second type of impurity may be different from the first type of impurity described above. For example, in the case where the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. As an example, in the case where the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0106] Each of the plurality of well regions WA may include a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0107] Each of the source region SA and the drain region DA may be a region doped with first type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be disposed on one side or one side of the gate electrode GE, and the drain region DA may be disposed on the other side or the other side of the gate electrode GE.

[0108] Each of the plurality of well regions WA may further include a first low-concentration impurity region disposed between the channel region CH and the source region SA and a second low-concentration impurity region disposed between the channel region CH and the drain region DA. The first low-concentration impurity region may be a region having an impurity concentration lower than that of the source region SA. The second low-concentration impurity region may be a region having an impurity concentration lower than that of the drain region DA. The distance between the source region SA and the drain region DA may be increased by the first low-concentration impurity region and the second low-concentration impurity region. Therefore, since the length of the channel region CH of each of the plurality of pixel transistors PTR may be increased, a breakdown phenomenon and a hot carrier phenomenon caused by a short channel may be prevented.

[0109] The first semiconductor insulating film SINS1 may be disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 may be formed of silicon carbonitride (SiCN) or silicon oxide (SiO x ) type inorganic film, but the embodiments of this specification are not limited to this.

[0110] The second semiconductor insulating film SINS2 may be provided on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may be formed of silicon oxide (SiO x ) type inorganic film, but the embodiments of this specification are not limited to this.

[0111] The contact terminal CTE may be disposed on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, the source region SA, and the drain region DA of each of the plurality of pixel transistors PTR through a hole passing through the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The contact terminal CTE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0112] The third semiconductor insulating film SINS3 may be disposed on a side surface of each of the plurality of contact terminals CTE. The upper surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 may be formed of silicon oxide (SiO x ) type inorganic membrane, but the present disclosure is not limited thereto.

[0113] The semiconductor substrate SSUB may be replaced with a glass substrate or a polymer resin substrate (such as a polyimide resin substrate). In this case, the thin film transistor may be disposed on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that does not bend, and the polymer resin substrate may be a flexible substrate that may be bent or curved.

[0114] The light emitting element back plate EBP may include first to eighth metal layers ML1 to ML8 , reflective electrodes RL1 to RL4 , via holes VA1 to VA10 , and step layers STPL The light emitting element back plate EBP may include interlayer insulating films INS1 to INS10 .

[0115] The first to eighth metal layers ML1 to ML8 are used to implement a circuit of the first sub-pixel SP1 by connecting the contact terminal CTE exposed from the semiconductor backplane SBP.

[0116] The first interlayer insulating film INS1 may be disposed on the semiconductor backplane SBP. Each of the plurality of first vias VA1 may pass through the first interlayer insulating film INS1 and be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the plurality of first metal layers ML1 may be disposed on the first interlayer insulating film INS1 and may be connected to the first vias VA1.

[0117] The second interlayer insulating film INS2 may be disposed on the first interlayer insulating film INS1 and the first metal layer ML1. Each of the plurality of second vias VA2 may be connected to the first metal layer ML1 exposed by passing through the second interlayer insulating film INS2. Each of the plurality of second metal layers ML2 may be disposed on the second interlayer insulating film INS2 and may be connected to the second vias VA2.

[0118] The third interlayer insulating film INS3 may be disposed on the second interlayer insulating film INS2 and the second metal layer ML2. Each of the plurality of third vias VA3 may be connected to the second metal layer ML2 exposed by passing through the third interlayer insulating film INS3. Each of the plurality of third metal layers ML3 may be disposed on the third interlayer insulating film INS3 and may be connected to the third via VA3.

[0119] The fourth interlayer insulating film INS4 may be disposed on the third interlayer insulating film INS3 and the third metal layer ML3. Each of the plurality of fourth vias VA4 may be connected to the third metal layer ML3 exposed by passing through the fourth interlayer insulating film INS4. Each of the plurality of fourth metal layers ML4 may be disposed on the fourth interlayer insulating film INS4 and may be connected to the fourth via VA4.

[0120] The fifth interlayer insulating film INS5 may be disposed on the fourth interlayer insulating film INS4 and the fourth metal layer ML4. Each of the plurality of fifth vias VA5 may be connected to the fourth metal layer ML4 exposed by passing through the fifth interlayer insulating film INS5. Each of the plurality of fifth metal layers ML5 may be disposed on the fifth interlayer insulating film INS5 and may be connected to the fifth via VA5.

[0121] The sixth interlayer insulating film INS6 may be disposed on the fifth interlayer insulating film INS5 and the fifth metal layer ML5. Each of the plurality of sixth vias VA6 may be connected to the fifth metal layer ML5 exposed by passing through the sixth interlayer insulating film INS6. Each of the plurality of sixth metal layers ML6 may be disposed on the sixth interlayer insulating film INS6 and may be connected to the sixth via VA6.

[0122] The seventh interlayer insulating film INS7 may be disposed on the sixth interlayer insulating film INS6 and the sixth metal layer ML6. Each of the plurality of seventh vias VA7 may be connected to the sixth metal layer ML6 exposed by passing through the seventh interlayer insulating film INS7. Each of the plurality of seventh metal layers ML7 may be disposed on the seventh interlayer insulating film INS7 and may be connected to the seventh via VA7.

[0123] The eighth interlayer insulating film INS8 may be disposed on the seventh interlayer insulating film INS7 and the seventh metal layer ML7. Each of the plurality of eighth vias VA8 may be connected to the seventh metal layer ML7 exposed by passing through the eighth interlayer insulating film INS8. Each of the plurality of eighth metal layers ML8 may be disposed on the eighth interlayer insulating film INS8 and may be connected to the eighth via VA8.

[0124] The first metal layer ML1 to the eighth metal layer ML8 and the first through hole VA1 to the eighth through hole VA8 may be formed of substantially the same material. The first metal layer ML1 to the eighth metal layer ML8 and the first through hole VA1 to the eighth through hole VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy including any one of them. The first through hole VA1 to the eighth through hole VA8 may be formed of substantially the same material. The first interlayer insulating film INS1 to the eighth interlayer insulating film INS8 may be formed of silicon oxide (SiO x ) type inorganic membrane, but the description is not limited thereto.

[0125] The thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be respectively greater than the thickness of the first through hole VA1, the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, and the thickness of the sixth through hole VA6. Each of the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially the same.

[0126] Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than each of the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than each of the thickness of the seventh through hole VA7 and the thickness of the eighth through hole VA8. Each of the thickness of the seventh through hole VA7 and the thickness of the eighth through hole VA8 may be greater than each of the thickness of the first through hole VA1, the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, and the thickness of the sixth through hole VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same.

[0127] The ninth interlayer insulating film INS9 may be disposed on the eighth interlayer insulating film INS8 and the eighth metal layer ML8. The ninth interlayer insulating film INS9 may be formed of silicon oxide (SiO x ) type inorganic film, but the present invention is not limited to this.

[0128] Each of the plurality of ninth vias VA9 may be connected to the eighth metal layer ML8 exposed by passing through the ninth interlayer insulating film INS9. The ninth via VA9 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0129] Each of the plurality of first reflective electrodes RL1 may be disposed on the ninth interlayer insulating film INS9 and may be connected to the ninth via VA9. The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0130] Each of the plurality of second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the second reflective electrode RL2 may be formed of titanium nitride (TiN).

[0131] In the first sub-pixel SP1, the step layer STPL may be disposed on the second reflective electrode RL2. The step layer STPL may not be disposed in each of the second sub-pixel SP2 and the third sub-pixel SP3. The thickness of the step layer STPL may be set in consideration of the wavelength of the light of the first color and the distance from the first light emitting layer to the fourth reflective electrode RL4, so as to facilitate reflection of the light of the first color emitted from the first light emitting layer of the first sub-pixel SP1. The step layer STPL may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x ) type inorganic film is formed, but the embodiment is not limited thereto.

[0132] In the first subpixel SP1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2 and the step layer STPL. In the second subpixel SP2 and the third subpixel SP3, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0133] At least one of the first reflective electrode RL1 , the second reflective electrode RL2 , and the third reflective electrode RL3 may be omitted.

[0134] Each of the plurality of fourth reflective electrodes RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be a layer that reflects light from the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3. The fourth reflective electrode RL4 may include a metal having a high reflectivity to facilitate reflecting light. The fourth reflective electrode RL4 may be formed of aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), an APC alloy (which is an alloy of silver (Ag), palladium (Pd), and copper (Cu)), or a stacked structure of an APC alloy and ITO (ITO / APC / ITO), but the present specification is not limited thereto.

[0135] The tenth interlayer insulating film INS10 may be disposed on the ninth interlayer insulating film INS9 and the fourth reflective electrode RL4. The tenth interlayer insulating film INS10 may be formed of silicon oxide (SiO x ) type inorganic film, but the present invention is not limited to this.

[0136] Each of the plurality of tenth through holes VA10 may be connected to the fourth reflective electrode RL4 exposed by passing through the tenth interlayer insulating film INS10. The tenth through hole VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. Due to the step layer STPL, the thickness of the tenth through hole VA10 in the first sub-pixel SP1 may be less than the thickness of the tenth through hole VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3.

[0137] The light emitting element layer EMI may be disposed on the light emitting element back panel EBP. The light emitting element layer EMI may include light emitting elements LE each including a first electrode AND, an intermediate layer IL, and a second electrode CAT, and a pixel defining film PDL.

[0138] The first electrode AND of each of the plurality of light emitting elements LE may be disposed on the tenth interlayer insulating film INS10 and may be connected to the tenth through hole VA10. The first electrode AND of each of the plurality of light emitting elements LE may be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth through hole VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth through holes VA1 to VA9, the first to eighth metal layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the plurality of light emitting elements LE may include any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the first electrode AND of each of the plurality of light emitting elements LE may be formed of titanium nitride (TiN).

[0139] The pixel definition film PDL may be disposed on a partial region of the first electrode AND of each of the plurality of light emitting elements LE. The pixel definition film PDL may cover an edge of the first electrode AND of each of the plurality of light emitting elements LE. The pixel definition film PDL is used to separate the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3.

[0140] The first light emitting area EA1 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second light emitting area EA2 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third light emitting area EA3 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0141] The pixel definition film PDL may include a first pixel definition film PDL1, a second pixel definition film PDL2, and a third pixel definition film PDL3. The first pixel definition film PDL1 may be disposed on the edge of the first electrode AND of each of the plurality of light emitting elements LE, the second pixel definition film PDL2 may be disposed on the first pixel definition film PDL1, and the third pixel definition film PDL3 may be disposed on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may be formed of silicon oxide (SiO x ) type inorganic film, but the present invention is not limited to this.

[0142] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0143] The intermediate layer IL may have a tandem structure including intermediate layers IL1, IL2, and IL3 that emit light of different colors. For example, the intermediate layer IL may include a first intermediate layer IL1 that emits light of a first color, a second intermediate layer IL2 that emits light of a third color, and a third intermediate layer IL3 that emits light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be sequentially stacked on each other.

[0144] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer may be sequentially stacked with each other. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a third color, and a second electron transport layer may be sequentially stacked with each other. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a second color, and a third electron transport layer may be sequentially stacked with each other.

[0145] The intermediate layer IL covers the first electrode AND at the opening of the pixel defining film PDL and covers the pixel defining film PDL between the sub-pixels SP1 , SP2 , and SP3 disposed adjacent to each other, and a portion of the intermediate layer IL may be disconnected.

[0146] According to an embodiment, by disconnecting the intermediate layer IL between the sub-pixels SP1, SP2, and SP3 adjacent to each other, leakage current between the sub-pixels SP1, SP2, and SP3 adjacent to each other and color crosstalk can be prevented. Color crosstalk refers to a phenomenon in which, for example, a red sub-pixel adjacent to a blue sub-pixel is unintentionally activated while the blue sub-pixel emits blue light. Color crosstalk occurs due to leakage current, and color crosstalk may occur in a case where a blue sub-pixel and a red sub-pixel having a large difference in voltage of a driving pixel are adjacent to each other. For example, leakage current is a phenomenon in which, while a driving current is supplied to a light-emitting element LE of a blue sub-pixel to activate the blue sub-pixel, a portion of the driving current is transmitted to a red sub-pixel through at least a portion of a conductive layer of the intermediate layer IL. In the event of leakage current, the red sub-pixel may be unintentionally activated while the blue sub-pixel is activated.

[0147] The number of the intermediate layers IL1, IL2, and IL3 emitting light of different colors is not limited to Figure 5 . For example, the intermediate layer IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other of the two intermediate layers may include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and supplying charges to the other intermediate layer may be provided between the two intermediate layers.

[0148] exist Figure 5 , it is shown that the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 are all arranged in the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3, but the present specification is not limited thereto. For example, the first intermediate layer IL1 may be arranged in the first light-emitting area EA1, and may not be arranged in the second light-emitting area EA2 and the third light-emitting area EA3. The second intermediate layer IL2 may be arranged in the second light-emitting area EA2, and may not be arranged in the first light-emitting area EA1 and the third light-emitting area EA3. The third intermediate layer IL3 may be arranged in the third light-emitting area EA3, and may not be arranged in the first light-emitting area EA1 and the second light-emitting area EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0149] The second electrode CAT may be disposed on the third intermediate layer IL3. The second electrode CAT may be disposed on the third intermediate layer IL3 of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The second electrode CAT may be formed of a transparent conductive material (TCO) capable of transmitting light, such as ITO or indium zinc oxide (IZO), or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). In the case where the second electrode CAT is formed of a semi-transmissive conductive material, light emission efficiency may be improved in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 through a microcavity.

[0150] The encapsulation layer TFE may be disposed on the light emitting element layer EMI. The encapsulation layer TFE may include one or more inorganic films to prevent oxygen or moisture from penetrating into the light emitting element layer EMI. The encapsulation layer TFE may include at least one organic film to protect the light emitting element layer EMI from foreign matter such as dust. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0151] The first encapsulation inorganic film TFE1 may be disposed on the second electrode CAT, the encapsulation organic film TFE2 may be disposed on the first encapsulation inorganic film TFE1, and the second encapsulation inorganic film TFE3 may be disposed on the encapsulation organic film TFE2. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 may be formed as a silicon nitride (SiN x ) film, silicon oxynitride (SiO x N y ) film, silicon oxide (SiO x ) film, titanium oxide (TiO x ) film and aluminum oxide (AlO x ) films are multiple films in which one or more inorganic films are alternately stacked with each other. The encapsulating organic film TFE2 may be a monomer. As an example, the encapsulating organic film TFE2 may be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0152] The adhesive layer ADL may be a layer for adhering the encapsulation layer TFE and the optical layer OPL. The adhesive layer ADL may be a double-sided adhesive member. The adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive resin member.

[0153] The optical layer OPL may include color filters CF1, CF2, and CF3, a lens LNS, and a filling layer FIL. The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the adhesive layer ADL.

[0154] The first color filter CF1 may overlap with the first emission area EA1 of the first subpixel SP1. The first color filter CF1 may transmit light of a first color, for example, light in a blue wavelength band. The blue wavelength band may be in the range of about 370 nm to about 460 nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0155] The second color filter CF2 may overlap with the second light emitting area EA2 of the second sub-pixel SP2. The second color filter CF2 may transmit light of a second color, for example, light in a green wavelength band. The green wavelength band may be in the range of about 480 nm to about 560 nm. Therefore, the second color filter CF2 may transmit light of a second color among the light emitted from the second light emitting area EA2.

[0156] The third color filter CF3 may overlap with the third light emitting area EA3 of the third sub-pixel SP3. The third color filter CF3 may transmit light of a third color, for example, light in a red wavelength band. The red wavelength band may be in the range of about 600 nm to about 750 nm. Therefore, the third color filter CF3 may transmit light of a third color among the light emitted from the third light emitting area EA3.

[0157] Each of the plurality of lenses LNS may be disposed on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be for increasing the light directed to the display device 10 (see Figure 4 Each of the plurality of lenses LNS may have a cross-sectional shape that is convex in an upward direction.

[0158] The filling layer FIL may be disposed on the lens LNS. The filling layer FIL may have a selectable refractive index so that light travels in a third direction DR3 at an interface between the lens LNS and the filling layer FIL. The filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0159] The covering layer CVL may be disposed on the filling layer FIL. The covering layer CVL may be a glass substrate or a polymer resin substrate (such as a polyimide resin substrate). In the case where the covering layer CVL is a glass substrate, the covering layer CVL may be attached to the filling layer FIL. In this case, the filling layer FIL may be used to adhere the covering layer CVL. In the case where the covering layer CVL is a glass substrate, the covering layer CVL may be used as a packaging substrate. In the case where the covering layer CVL is a polymer resin substrate (such as a polyimide resin substrate), the covering layer CVL may be directly coated on the filling layer FIL.

[0160] A polarizing plate (not shown) may be provided on one surface or one surface of the cover layer CVL. The polarizing plate may be a structure for preventing degradation of visibility due to reflection of external light. The polarizing plate may include a linear polarizing plate and a phase delay film. For example, the phase delay film may be a λ / 4 (quarter wavelength) plate, but the present specification is not limited thereto. However, in the case where degradation of visibility due to reflection of external light is sufficiently improved by the first color filter CF1, the second color filter CF2, and the third color filter CF3, the polarizing plate may also be omitted.

[0161] Figure 6 is a schematic perspective view of a mask MK according to the embodiment. Figure 7 is a schematic plan view of a mask MK according to the embodiment. Figure 6 A schematic perspective view showing a state in which one unit mask UM is separated from a plurality of unit masks UM. Figure 6 and Figure 7 The mask MK of the embodiment shown in FIG. 1 can be used to deposit reference Figure 5 The display panel 410 (see Figure 4 ). For example, the intermediate layer IL may emit light of a different color from each of the sub-pixels SP1, SP2, and SP3.

[0162] Reference Figure 6 and Figure 7 , the mask MK according to the embodiment may be a shadow mask in which the mask membrane MM is disposed on the silicon substrate 700. The mask MK according to the embodiment may be named a 'silicon mask'.

[0163] According to an embodiment, the mask MK may include a silicon substrate 700 , and the mask rib region 721 and the mask membrane MM may be disposed on the silicon substrate 700 .

[0164] The silicon substrate 700 may include a cell region 710 corresponding to the cell mask UM and a mask frame region 720. The mask frame region 720 may be a remaining region except the cell region 710. The mask frame region 720 may include a mask rib region 721 separating the cell region 710 and an outer frame region 722 located on the outside of the silicon substrate 700.

[0165] The mask frame MF is disposed in the mask frame region 720. The mask frame MF may be formed of silicon as a part of the silicon substrate 700. The mask frame MF may be formed of metal (e.g., a coating film) formed on the silicon substrate 700. The mask frame MF may include a stacked structure including silicon as a part of the silicon substrate 700 and metal (e.g., a coating film) formed on the silicon.

[0166] The mask rib region 721 of the mask frame region 720 may be a region that separates the unit regions 710. For example, the unit regions 710 may be arranged in a matrix form, and the mask rib region 721 may be arranged to surround each unit region 710. Fig.11 The mask ribs 7211 in the silicon substrate 700 are provided in such a mask rib region 721. According to an embodiment, by forming the mask ribs 7211 from a magnetic metal material, a magnetic member (e.g., a magnetic chuck) inside a deposition device (not shown) can be used to prevent sagging of the mask MK. However, the present disclosure is not limited to forming the mask ribs 7211 from a magnetic metal material, and the mask ribs 7211 can be formed from a silicon substrate 700. The mask ribs 7211 can be formed from a silicon substrate 700 and a metal provided on the silicon substrate 700. The mask ribs 7211 can be formed from a silicon substrate 700 and an inorganic film provided on the silicon substrate 700.

[0167] A cell opening COP and a unit mask UM masking at least a portion of the cell opening COP may be disposed in each of the plurality of cell regions 710 of the silicon substrate 700 .

[0168] The cell opening COP may pass through the mask frame MF along a thickness direction (eg, third direction DR3 ) of the mask MK. The cell opening COP may be generated by etching a portion of the silicon substrate 700 from a rear direction DR4 .

[0169] Each unit mask UM may include a mask film MM, and the mask film MM may include a mask shadow ( Fig.10 ), and a mask opening ( Fig.10 The mask shadows 1011 may be arranged in a matrix form within each unit mask UM, and the mask openings OP may be arranged between the mask shadows 1011.

[0170] In the case where the deposition material evaporates from the deposition source inside the deposition device, the mask shadow 1011 can be used as a blocking portion to mask the substrate to be deposited (e.g., the display panel 410 or the backplane substrate). Therefore, the deposition material generated by the deposition source can be deposited on the surface of the substrate to be deposited (e.g., the display panel 410 or the backplane substrate) through the mask opening OP of the mask membrane MM.

[0171] The mask opening OP of the mask film MM may be named a “hole” or a “mask hole.” The mask opening OP may pass through the unit mask UM along a thickness direction (eg, third direction DR3 ) of the mask MK.

[0172] One unit mask UM may be used for a deposition process of one display panel 410. In the present disclosure, the term "unit mask UM" may be replaced with a term such as a mask unit UM.

[0173] The outer frame region 722 of the mask frame region 720 is a region that supports the entire mask MK and may be disposed to surround the outside of the mask MK. The first metal frame ( Fig.10 The first metal frame 1020) is set in at least a portion of the outer frame area 722.

[0174] The first metal frame 1020 is formed of a metal material and is disposed to surround the outside of the mask MK. For example, the silicon substrate 700 may have a circular shape in a plan view, and the first metal frame 1020 may have a ring shape surrounding the outside of the silicon substrate 700 in a plan view.

[0175] The first metal frame 1020 is coupled to a second metal frame ( Fig.12 700). The second metal frame 1210 may have an annular shape surrounding the outside of the silicon substrate 700 in a plan view. The second metal frame 1210 is coupled to the first metal frame 1020 disposed on the outside of the silicon substrate 700. For example, the first metal frame 1020 may be disposed in an outer frame region 722 which is the outside of the silicon substrate 700, and the lower surface of the first metal frame 1020 may be exposed due to etching the silicon substrate 700. The lower surface of the first metal frame 1020 exposed by etching the silicon substrate 700 may be coupled to the upper surface of the second metal frame 1210. An example of a method of coupling the first metal frame 1020 and the second metal frame 1210 includes welding, but the present disclosure is not limited thereto. For example, in addition to welding, an example of a method of coupling the first metal frame 1020 and the second metal frame 1210 may also include coupling by an adhesive or a screw.

[0176] In the present disclosure, the lower surface or the rear surface refers to a surface facing a rear direction DR4 of the silicon substrate, and the rear direction DR4 refers to a direction from the mask MK toward a deposition source.

[0177] The second metal frame 1210 may have substantially the same size as the silicon substrate 700. For example, the second metal frame 1210 may have a ring shape surrounding the silicon substrate 700, and the diameter of the second metal frame 1210 may be substantially the same as the diameter of the silicon substrate 700. However, the diameter of the second metal frame 1210 may also be designed to be larger than the diameter of the silicon substrate 700.

[0178] According to the embodiment, by forming a shadow mask (e.g., a mask film MM) on the silicon substrate 700, the mask MK for manufacturing a high-resolution display panel 410 can be easily realized. By disposing the first metal frame 1020 on the outside of the silicon substrate 700 and coupling the first metal frame 1020 to the second metal frame 1210 provided separately from the silicon substrate 700, the mask MK can be attached to the substrate to be deposited without a separate structure inside the deposition device. Since the sagging of the mask MK is reduced due to the coupling of the first metal frame 1020 and the second metal frame 1210, the mask MK according to the embodiment can prevent uneven defects.

[0179] Figure 8 is a flowchart illustrating a method for manufacturing a mask according to an embodiment. Figures 9 to 13 is a schematic cross-sectional process diagram for describing a method for manufacturing a mask according to an embodiment.

[0180] In the following, reference will be made to Figures 8 to 13 A method for manufacturing a mask MK (see Figure 6 ) method. The following description is only a part of the process of manufacturing the mask MK, and an additional process for forming a component described with reference to the present disclosure may be performed before or after each step. The process of manufacturing the mask MK may be additionally performed before or after each step described below.

[0181] Reference Figure 8 and Fig. 9 In step 810, a silicon substrate 700 is prepared. The silicon substrate 700 may include a silicon substrate 700 corresponding to a unit mask UM (see Figure 7 ) of the cell region 710 and the mask frame region 720 (see Figure 7 ). The mask frame region 720 may be a remaining region except the cell region 710. The mask frame region 720 may include a mask rib region 721 separating the cell region 710 and an outer frame region 722 located on the outside of the silicon substrate 700.

[0182] Reference Figure 8 and Fig.10 In step 820, a mask film MM and a first metal frame 1020 are formed by performing an electroplating process. The electroplating process may include: forming a photoresist pattern for forming a mask film MM on a silicon substrate 700; growing an electroplated film including the photoresist pattern on the silicon substrate 700; and removing the photoresist pattern.

[0183] The region where the photoresist pattern is removed from each unit region 710 of the silicon substrate 700 becomes a mask opening OP of the mask membrane MM. The plating film may include tungsten (W) or copper (Cu). In each unit region 710 of the silicon substrate 700, a mask shadow 1011 of the mask membrane MM is formed by the plating film.

[0184] The first metal frame 1020 connected to the mask film MM is formed on at least a portion of the outer frame region 722 of the silicon substrate 700 using plating. The mask shadow 1011 of the mask film MM and the first metal frame 1020 may be formed by the same electroplating process.

[0185] The cross section of the mask membrane MM (e.g., the cross section of each mask shadow 1011) may have a reverse tapered shape, the width of which narrows from the front direction (third direction DR3) of the silicon substrate 700 to the rear direction DR4 of the silicon substrate 700. The cross section of the mask opening OP may have a regular tapered shape, the width of which increases from the front direction (third direction DR3) of the silicon substrate 700 to the rear direction DR4 of the silicon substrate 700. According to an embodiment of the present disclosure, by making the cross section of the mask membrane MM have a reverse tapered shape, shadow defects during the deposition process can be reduced.

[0186] The thickness of the mask film MM (for example, the thickness of each mask shadow 1011) may be less than about 2 μm. In the case where the thickness of the mask film MM is less than about 2 μm, there may be a problem that the mask film MM is easily warped, but by using the portion of the silicon substrate 700 located between the cell regions 710 adjacent to each other as the mask rib 7211 (see Fig.11 ), this problem can be prevented. In the mask MK according to the embodiment (see Figure 6 ), the thickness of the mask film MM is less than about 2 μm, thereby reducing shadow defects and preventing the mask MK from sagging.

[0187] Reference Figure 8 and Fig.11, in step 830, the rear surface of the silicon substrate 700 is etched. For example, the process of etching the rear surface of the silicon substrate 700 may include: forming a photoresist pattern on the rear surface of the silicon substrate 700; etching a portion of the silicon substrate 700 from the rear direction DR4 using the photoresist pattern; and removing the photoresist pattern. Therefore, a cell opening COP corresponding to the cell region 710 and a frame opening 1111 exposing the lower surface of the first metal frame 1020 in the outer frame region 722 are formed in the rear surface of the silicon substrate 700. A portion of the first metal frame 1020 may be supported by a portion of the silicon substrate 700 disposed in the outer frame region 722, and the lower surface of the remaining region except for a portion of the first metal frame 1020 may be exposed through the frame opening 1111 during the process.

[0188] According to an embodiment, a portion of the silicon substrate 700 corresponding to the mask rib region 721 is masked in the process of etching the rear surface of the silicon substrate 700. Therefore, the mask rib 7211 located between the cell regions 710 adjacent to each other may be formed by the portion of the silicon substrate 700 masked in the etching process.

[0189] Reference Figure 8 and Fig.12 In step 840, the second metal frame 1210 surrounding the outside of the silicon substrate 700 is aligned with the silicon substrate 700. The second metal frame 1210 may have a ring shape surrounding the outside of the silicon substrate 700 in a plan view. The second metal frame 1210 is aligned with the outer frame region 722 of the silicon substrate 700. For example, the second metal frame 1210 may be aligned to overlap with the frame opening 1111 of the silicon substrate 700 that exposes the lower surface of the first metal frame 1020. The thickness of the second metal frame 1210 may be thicker than the thickness of the silicon substrate 700.

[0190] The second metal frame 1210 may be made of a rigid material, such as stainless steel, Invar, nickel (Ni), cobalt (Co), a nickel alloy, and / or a nickel-cobalt alloy.

[0191] Reference Figure 8 and Fig.13 In step 850, the first metal frame 1020 and the second metal frame 1210 are coupled to each other. Fig.13As shown in the welding 1311 in the figure, the process of coupling the first metal frame 1020 and the second metal frame 1210 to each other may include welding 1311. In the present disclosure, the area where the first metal frame 1020 and the second metal frame 1210 are welded is defined as a "welding portion". According to an embodiment, the welding portion may be provided in the outer frame area 722 of the silicon substrate 700 and may be provided along the periphery of the second metal frame 1210. Fig.14 and Fig.15 Describes the given position of the welded part.

[0192] exist Figures 8 to 13 In the embodiment of the present invention, the process of coupling the first metal frame 1020 and the second metal frame 1210 to each other (step 850) is performed after the process of etching the rear surface of the silicon substrate 700 (step 830), but the present disclosure is not limited thereto. For example, the process of coupling the first metal frame 1020 and the second metal frame 1210 to each other (step 850) may also be performed before the process of etching the rear surface of the silicon substrate 700 (step 830).

[0193] Fig.14 is a schematic plan view of a mask for describing a position of a welding portion 1411 between a silicon substrate 700 and a second metal frame 1210 according to an embodiment.

[0194] Reference Fig.14 , the welding portion 1411 between the silicon substrate 700 and the second metal frame 1210 may be provided to extend continuously along the periphery of the second metal frame 1210. For example, the welding portion 1411 is provided along the overlapping portion of the outer frame region 722 of the silicon substrate 700 and the second metal frame 1210. The welding portion 1411 may be provided to extend continuously in a ring shape when the mask MK is viewed in a plan view.

[0195] Fig.15 is a schematic plan view of a mask in which a position of a welding portion 1511 between a silicon substrate 700 and a second metal frame 1210 is changed according to an embodiment.

[0196] Reference Fig.15 , the welding portion 1511 between the silicon substrate 700 and the second metal frame 1210 may be disposed discontinuously along the periphery of the second metal frame 1210. For example, the welding portion 1511 is disposed along the overlapping portion of the outer frame region 722 of the silicon substrate 700 and the second metal frame 1210, and may be disposed to be spaced apart at a specified interval. In the present specification, the interval between the welding portions 1511 adjacent to each other is not limited.

[0197] exist Fig.15 In the embodiment, Fig.14Different from the embodiment of the present invention, the stress applied to the silicon substrate 700 can be reduced by discontinuously setting the welding portion 1511. For example, when the welding portion 1511 is designed as Fig.15 In the case of the discontinuous point form in the embodiment, sagging or deformation of the silicon substrate due to stress applied to the silicon substrate 700 can be reduced.

[0198] Fig.16 is a flowchart illustrating a method for manufacturing a mask according to an embodiment. Figures 17 to 21 2 is a schematic cross-sectional process diagram for describing a method for manufacturing a mask according to an embodiment.

[0199] Figures 16 to 21 Examples and Figures 8 to 13 The embodiment of the present invention may be different in that the mask rib 7211 located between the unit regions 710 adjacent to each other may be formed by plating.

[0200] In the following, reference will be made to Figures 16 to 21 A method for manufacturing a mask MK (see Figure 6 ) method. The following description is only a part of the process of manufacturing the mask MK, and an additional process for forming a component described with reference to the present disclosure may be performed before or after each step. The process of manufacturing the mask MK may be additionally performed before or after each step described below.

[0201] Reference Fig.16 and Fig.17 In step 1610, a silicon substrate 700 is prepared. The silicon substrate 700 may include a unit mask UM (see Figure 7 ) corresponding to the unit region 710 and the mask frame region 720 (see Figure 7 ). The mask frame region 720 may be a remaining region except the cell region 710. The mask frame region 720 may include a mask rib region 721 separating the cell region 710 and an outer frame region 722 located on the outside of the silicon substrate 700.

[0202] Reference Fig.16 and Fig.18 In step 1620, a mask film MM, a mask rib 7211, and a first metal frame 1020 are formed by performing an electroplating process. The electroplating process may include: forming a photoresist pattern for forming a mask film MM on a silicon substrate 700; growing an electroplated film including the photoresist pattern on the silicon substrate 700; and removing the photoresist pattern.

[0203] The region where the photoresist pattern is removed from each unit region 710 of the silicon substrate 700 becomes a mask opening OP of the mask membrane MM. The plating film may include tungsten (W) or copper (Cu). In each unit region 710 of the silicon substrate 700, a mask shadow 1011 of the mask membrane MM is formed by the plating film.

[0204] The mask ribs 7211 formed by plating are disposed in the mask rib region 721 of the silicon substrate 700. According to an embodiment, by forming the mask ribs 7211 by a magnetic metal material, a magnetic member (eg, a magnetic chuck) inside a deposition device (not shown) may be used to prevent sagging of the mask MK.

[0205] The first metal frame 1020 connected to the mask film MM is formed on at least a portion of the outer frame region 722 of the silicon substrate 700 using plating. The mask shadow 1011 of the mask film MM and the first metal frame 1020 may be formed by the same electroplating process.

[0206] The thickness of the mask film MM (eg, the thickness of each mask shadow 1011) and the thickness of the mask rib 7211 may be about 2 μm or more. Fig.18 In the embodiment of Fig.10 In different embodiments, the thickness of the coating film can be formed to be about 2 μm or more. Fig.18 In the embodiment, by forming the mask film MM and the mask rib 7211 by a plating film having a thickness of about 2 μm or more, the magnetic force can be increased, and thus the effect of preventing the mask MK from sagging can be increased by using a magnetic member (e.g., a magnetic suction cup).

[0207] Reference Fig.16 and Fig.19 , in step 1630, the rear surface of the silicon substrate 700 is etched. For example, the process of etching the rear surface of the silicon substrate 700 may include: forming a photoresist pattern on the rear surface of the silicon substrate 700; etching a portion of the silicon substrate 700 from the rear direction DR4 using the photoresist pattern; and removing the photoresist pattern. Therefore, a cell opening COP corresponding to the cell region 710 and a frame opening 1111 exposing the lower surface of the first metal frame 1020 in the outer frame region 722 are formed in the rear surface of the silicon substrate 700. A portion of the first metal frame 1020 may be supported by a portion of the silicon substrate 700 disposed in the outer frame region 722, and the lower surface of the remaining region except for a portion of the first metal frame 1020 may be exposed through the frame opening 1111 during the process.

[0208] In step 1630, the same as step 830 (see Figure 8), a portion of the silicon substrate 700 corresponding to the mask rib region 721 is also etched. Therefore, only the mask rib 7211 formed by the plating film remains in the mask rib region 721.

[0209] Reference Fig.16 and Fig. 20 In step 1640, the second metal frame 1210 surrounding the outside of the silicon substrate 700 is aligned with the silicon substrate 700. The second metal frame 1210 may have a ring shape surrounding the outside of the silicon substrate 700 in a plan view. The second metal frame 1210 is aligned with the outer frame region 722 of the silicon substrate 700. For example, the second metal frame 1210 may be aligned to overlap with the frame opening 1111 of the silicon substrate 700 that exposes the lower surface of the first metal frame 1020. The thickness of the second metal frame 1210 may be thicker than the thickness of the silicon substrate 700.

[0210] Reference Fig.16 and Fig.21 In step 1650, the first metal frame 1020 and the second metal frame 1210 are coupled to each other. Fig.21 As shown at welding 1311 in FIG. 1 , the process of coupling the first metal frame 1020 and the second metal frame 1210 to each other may include welding 1311 .

[0211] exist Figures 16 to 21 In the embodiment of the present invention, the process of coupling the first metal frame 1020 and the second metal frame 1210 to each other (step 1650) is performed after the process of etching the rear surface of the silicon substrate 700 (step 1630), but the present disclosure is not limited thereto. For example, the process of coupling the first metal frame 1020 and the second metal frame 1210 to each other (step 1650) may also be performed before the process of etching the rear surface of the silicon substrate 700 (step 1630).

[0212] Fig. 22 is a flowchart illustrating a method for manufacturing a mask according to an embodiment. Figure 23 to Figure 27 2 is a schematic cross-sectional process diagram for describing a method for manufacturing a mask according to an embodiment.

[0213] Figure 22 to Figure 27 Examples and Figures 8 to 13 The embodiment of the present invention may be different in that the mask shadow 1011 of the mask film MM may be formed of an inorganic film pattern.

[0214] In the following, reference will be made to Figure 22 to Figure 27 A method for manufacturing a mask MK (see Figure 6) method. The following description is only a part of the process of manufacturing the mask MK, and an additional process for forming a component described with reference to the present disclosure may be performed before or after each step. The process of manufacturing the mask MK may be additionally performed before or after each step described below.

[0215] Reference Fig. 22 and Fig.23 In step 2210, a silicon substrate 700 is prepared. The silicon substrate 700 may include a silicon substrate 700 corresponding to a unit mask UM (see Figure 7 ) of the cell region 710 and the mask frame region 720 (see Figure 7 ). The mask frame region 720 may be a remaining region except the cell region 710. The mask frame region 720 may include a mask rib region 721 separating the cell region 710 and an outer frame region 722 located on the outside of the silicon substrate 700.

[0216] Reference Fig. 22 and Fig.24 In step 2220, a mask film MM is formed by performing an inorganic film deposition and an inorganic film patterning process. The process of forming the mask film MM may include: depositing an inorganic film on the silicon substrate 700; forming a photoresist pattern on the inorganic film; patterning a portion of the inorganic film using the photoresist pattern; and removing the photoresist pattern.

[0217] The inorganic film may include a silicon-based material. For example, the inorganic film pattern may include silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x ) at least one material.

[0218] The mask film MM disposed in each unit region 710 may include a mask shadow 2411 and a mask opening OP formed in an inorganic film pattern.

[0219] Reference Fig. 22 and Fig.24 In step 2230 , a first metal frame 1020 connected to the mask membrane MM is formed in the outer frame region 722 of the silicon substrate 700 .

[0220] The first metal frame 1020 may be formed of a plating film. The plating film may include tungsten (W) or copper (Cu).

[0221] The first metal frame 1020 may be made of a rigid material, such as titanium nitride (TiN), stainless steel, Invar, nickel (Ni), cobalt (Co), nickel alloy, and / or nickel-cobalt alloy.

[0222] The process of forming the first metal frame 1020 may be the same process as the process of forming the alignment key of the mask MK. For example, the alignment key is provided in a portion of the outer frame region 722 of the silicon substrate 700, and the first metal frame 1020 and the alignment key may be formed of the same material in the same process.

[0223] Reference Fig. 22 and Fig.25 , in step 2240, the rear surface of the silicon substrate 700 is etched. For example, the process of etching the rear surface of the silicon substrate 700 may include: forming a photoresist pattern on the rear surface of the silicon substrate 700; etching a portion of the silicon substrate 700 from the rear direction DR4 using the photoresist pattern; and removing the photoresist pattern. Therefore, a cell opening COP corresponding to the cell region 710 and a frame opening 1111 exposing the lower surface of the first metal frame 1020 in the outer frame region 722 are formed in the rear surface of the silicon substrate 700. A portion of the first metal frame 1020 may be supported by a portion of the silicon substrate 700 disposed in the outer frame region 722, and the lower surface of the remaining region except for a portion of the first metal frame 1020 may be exposed through the frame opening 1111 during the process.

[0224] Reference Fig. 22 and Fig.26 In step 2250, the second metal frame 1210 surrounding the outside of the silicon substrate 700 is aligned with the silicon substrate 700. The second metal frame 1210 may have a ring shape surrounding the outside of the silicon substrate 700 in a plan view. The second metal frame 1210 is aligned with the outer frame region 722 of the silicon substrate 700. For example, the second metal frame 1210 may be aligned to overlap with the frame opening 1111 of the silicon substrate 700 that exposes the lower surface of the first metal frame 1020. The thickness of the second metal frame 1210 may be thicker than the thickness of the silicon substrate 700.

[0225] The second metal frame 1210 may be made of a rigid material, such as stainless steel, Invar, nickel (Ni), cobalt (Co), a nickel alloy, and / or a nickel-cobalt alloy.

[0226] Reference Fig. 22 and Fig. 27 In step 2260, the first metal frame 1020 and the second metal frame 1210 are coupled to each other. Fig. 27As shown at welding 1311 in FIG. 1 , the process of coupling the first metal frame 1020 and the second metal frame 1210 to each other may include welding 1311 .

[0227] exist Figure 22 to Figure 27 In the embodiment of the present invention, the process of coupling the first metal frame 1020 and the second metal frame 1210 to each other (step 2260) is performed after the process of etching the rear surface of the silicon substrate 700 (step 2240), but the present disclosure is not limited thereto. For example, the process of coupling the first metal frame 1020 and the second metal frame 1210 to each other (step 2260) may also be performed before the process of etching the rear surface of the silicon substrate 700 (step 2240).

[0228] Fig.28 is a schematic plan view of a mask MK including a metal sheet 2811 according to an embodiment. Fig.29 and Fig.30 is a mask MK (see FIG. 1 ) in which the metal sheet 2811 is coupled (or connected) to the lower surface of the silicon substrate 700 according to an embodiment. Fig.28 ). For example, Figure 29 to Figure 30 is along Fig.28 Schematic cross-sectional view of the mask taken along line AA′ shown in FIG.

[0229] Reference Figures 28 to 30 The mask MK according to the embodiment may further include a metal sheet 2811 that supports the mask MK in the rear direction DR4. The metal sheet 2811 may be disposed to cross the mask MK in the horizontal direction in a plan view, or may be disposed to cross the mask MK in the vertical direction in a plan view. Fig.28 28 shows that the metal sheet 2811 crosses the mask MK in the vertical direction, but the present disclosure is not limited thereto.

[0230] The metal sheet 2811 may be made of a rigid material. For example, the material of the metal sheet 2811 may include Invar, but is not limited thereto. The material of the metal sheet 2811 may include stainless steel, nickel (Ni), cobalt (Co), a nickel alloy, and / or a nickel-cobalt alloy.

[0231] Both ends of the metal sheet 2811 are fixed by being coupled to the second metal frame 1210 in the outer frame region 722 of the silicon substrate 700 .

[0232] According to the embodiment, Fig.29 As shown in FIG. 1 , a lower step portion H1 on which a metal sheet 2811 is disposed may be formed on a rear portion of the second metal frame 1210 corresponding to the outer frame region 722 of the silicon substrate 700. The metal sheet 2811 may be coupled to the lower step portion H1 of the second metal frame 1210 by an adhesive or welding process.

[0233] According to an embodiment, Fig.30 As shown in , the second metal frame 1210 may not have the lower step portion H1, but may instead include a groove 1211 in which the metal sheet 2811 is embedded. The side surface of the second metal frame 1210 may include the groove 1211 in which the metal sheet 2811 is embedded, and the height of the groove 1211 may be designed to be substantially the same as the height of the metal sheet 2811. Both ends of the metal sheet 2811 are embedded in the groove 1211 formed on the side surface of the second metal frame 1210, and the remaining part supports the mask rib 7211. For example, the metal sheet 2811 may include a first portion 2811a supporting the mask rib 7211 in the mask rib region 721 of the silicon substrate 700, and a second portion 2811b located at each end of the first portion 2811a and embedded in the groove 1211 of the second metal frame 1210.

[0234] The metal sheet 2811 is disposed to extend from one side or one side of the silicon substrate 700 along the mask rib region 721 of the silicon substrate 700 to the other side or the other side of the silicon substrate 700 .

[0235] Fig.31 is a mask MK (see FIG. 1 ) in which the metal sheet 2811 is coupled (or connected) to the upper surface of the silicon substrate 700 according to an embodiment. Fig.28 ). For example, Fig.31 is along Fig.28 Schematic cross-sectional view of the mask MK taken along line AA′ shown in FIG.

[0236] Fig.31 Examples and Fig.29 and Fig.30 The embodiment may be different in that the metal sheet 2811 may be coupled to the upper surface of the second metal frame 1210 and the upper surface 7211 a of the mask rib 7211 .

[0237] Reference Fig.31 , the mask MK according to the embodiment may include a metal sheet 2811 coupled to the upper surface of the second metal frame 1210. An upper step portion 1210a on which the metal sheet 2811 is disposed may be formed on an upper surface of the second metal frame 1210 corresponding to the outer frame region 722 of the silicon substrate 700. The metal sheet 2811 may be coupled to the upper step portion 1210a of the second metal frame 1210 by an adhesive or a welding process.

[0238] The metal sheet 2811 may include a first portion 2811a disposed to overlap the mask rib 7211 in the mask rib region 721 of the silicon substrate 700 and a second portion 2811b located at each end of the first portion 2811a and coupled to the upper step portion 1210a of the second metal frame 1210 .

[0239] Fig.32 is a schematic plan view of a mask MK including a metal sheet 2811 according to an embodiment.

[0240] Fig.32 Examples and Figure 28 to Figure 31 The difference of the embodiment may be that the mask MK may be coupled to the metal sheet 2811.

[0241] Reference Fig.32 , the mask MK according to the embodiment is coupled to the metal sheet 2811. The metal sheet 2811 may be disposed to cross the mask MK in a horizontal direction in a plan view, or may be disposed to cross the mask MK in a vertical direction in a plan view.

[0242] exist Fig.32 2 shows that two metal sheets 2811 are disposed across the mask MK in the horizontal direction, and three metal sheets 2811 are disposed across the mask MK in the vertical direction, but the present disclosure is not limited thereto. Fig.32 The metal sheet 2811 shown in FIG. Figure 28 to Figure 31 The metal sheet 2811 is coupled to the second metal frame 1210 in the same or similar manner as described.

[0243] Fig.33 33 is a conceptual diagram for describing coupling (or connection) of the first metal frame 1020 and the second metal frame 1210 using an adhesive 3310 .

[0244] Fig.33 Examples and Fig.13 The embodiment may be different in that the first metal frame 1020 and the second metal frame 1210 may be coupled using an adhesive 3310.

[0245] Reference Fig.33 , in the mask MK according to the embodiment (see Fig.32 ), the first metal frame 1020 may be disposed in the outer frame region 722 of the silicon substrate 700, and the first metal frame 1020 may be coupled to the second metal frame 1210 provided separately from the silicon substrate 700 using an adhesive 3310.

[0246] Fig.34 34 is a conceptual diagram for describing the coupling (or connection) of the first metal frame 1020 and the second metal frame 1210 using the screws 3410 .

[0247] Fig.34 Examples and Fig.13 The embodiment may be different in that the first metal frame 1020 and the second metal frame 1210 may be coupled using screws 3410 .

[0248] Reference Fig.34 , in the mask MK according to the embodiment (see Fig.32 ), the first metal frame 1020 may be disposed in the outer frame region 722 of the silicon substrate 700, and the first metal frame 1020 may be coupled to the second metal frame 1210 provided separately from the silicon substrate 700 using screws 3410.

[0249] Fig.35 is a schematic cross-sectional view of a mask in which a mask rib region 721 has a stack structure of silicon and metal on silicon according to an embodiment.

[0250] Fig.35 Examples and Figures 16 to 21 The embodiment of the present invention may be different in that the mask rib 7211 may include a stacked structure of a silicon substrate 700 and a coating film formed on the silicon substrate 700 .

[0251] Reference Fig.35 , according to the mask MK of the embodiment (see Fig.32 ) may include a mask film MM formed by plating, and a mask rib 7211 made of the same metal as the mask film MM and a silicon substrate 700 supporting the mask rib 7211 at the bottom are arranged in the mask rib region 721. For example, in Fig.16 In step 1630, the rear surface of the silicon substrate 700 corresponding to the mask rib region 721 is etched, but the rear surface of the silicon substrate 700 corresponding to the mask rib region 721 may be left without being etched. Therefore, the mask rib 7211 according to the embodiment may include a stacked structure of the silicon substrate 700 and the plated film on the silicon substrate 700.

[0252] Fig.36 is a mask MK (see Fig.32 ) is a schematic cross-sectional view of the .

[0253] Fig.36 Examples and Figures 8 to 21 The embodiment of the present invention may differ in that the thickness of the first metal frame 1020 may be greater than the thickness of the mask film MM (eg, the thickness of the mask shadow 1011). According to the embodiment, the first metal frame 1020 and the second metal frame 1210 may be welded more easily.

[0254] Reference Fig.36In the mask MK according to the embodiment, the first metal frame 1020 is provided in the outer frame region 722, and the thickness of the first metal frame 1020 is greater than the thickness of the mask membrane MM (e.g., the thickness of the mask shadow 1011). According to the embodiment, by increasing the thickness of the first metal frame 1020, the rigidity of the mask MK can be further increased, and the sagging of the mask can be reduced.

[0255] Fig.37 and Fig.38 is a mask MK (see FIG. 1 ) showing dummy metal patterns 3711 and 3711a provided in the dummy frame region 722b between the first metal frame 1020 and the outermost cell region 710 according to an embodiment. Fig.32 ) is a schematic cross-sectional view of the .

[0256] Reference Fig.37 and Fig.38 , a dummy frame region 722b is defined between the first metal frame 1020 and the outermost unit region 710. For example, the outer frame region 722 may include a dummy frame region 722b adjacent to the outermost unit region 710, and an outermost frame region 722a disposed at the outside of the dummy frame region 722b and in which the first metal frame 1020 is formed. The outermost frame region 722a may be referred to as a first region, and the dummy frame region 722b may be referred to as a second region. For example, the outer frame region 722 may include a first region in which the first metal frame 1020 is formed, and a second region disposed inside the first region and adjacent to the unit opening COP.

[0257] In the present disclosure, the outermost cell region 710 refers to a cell region 710 disposed at the outermost portion among a plurality of cell regions 710 included in the mask MK. For example, the outermost cell region 710 may refer to a cell region 710 adjacent to the outer frame region 722 among the plurality of cell regions 710.

[0258] According to an embodiment, Fig.37 As shown in , dummy metal patterns 3711 and 3711a may be formed in the dummy frame region 722b. The dummy metal patterns 3711 and 3711a may be disposed on the same layer as the mask film MM and the first metal frame 1020. For example, the dummy metal patterns 3711 and 3711a may be formed by the same electroplating process as the mask film MM and the first metal frame 1020. The dummy metal patterns 3711 and 3711a include dummy metals 3711 disposed at intervals in the dummy frame region 722b, and dummy openings 3711a disposed between the dummy metals 3711.

[0259] Fig.38 Examples and Fig.37The difference of the embodiment may be that a metal that is continuously connected without openings may be provided in the dummy frame region 722b. Fig.38 As shown in FIG. 1 , a dummy metal 3711 that is continuously connected without being disconnected may be provided between the first metal frame 1020 and the outermost cell region 710 . The dummy metal 3711 according to an embodiment may be connected to the first metal frame 1020 .

[0260] according to Fig.37 An embodiment of Fig.38 Unlike the embodiment of the present invention, by providing the dummy metal 3711 and the dummy opening 3711a provided between the dummy metal 3711 in the dummy frame region 722b, the stress applied to the silicon substrate 700 can be reduced. Fig.37 In the embodiment, since the dummy opening 3711a is provided, Fig.38 Compared with the embodiment of the present invention, sagging or deformation of the silicon substrate 700 caused by the stress applied to the silicon substrate 700 can be reduced.

[0261] Embodiments have been described above with reference to the accompanying drawings, but it will be understood by those skilled in the art that various modifications and changes may be made without departing from the technical spirit or basic features of the present disclosure. Therefore, it should be understood that the above embodiments are illustrative rather than restrictive in all aspects.

[0262] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the disclosed embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A deposition mask, wherein: The deposition mask comprises: Silicon substrate, including: Multiple unit areas; a mask frame region other than the plurality of unit regions, the mask frame region including a mask rib region separating the plurality of unit regions; and An outer frame region, arranged at the outermost portion of the silicon substrate; a mask rib disposed in the mask rib region; a mask film disposed in each of the plurality of unit regions; a first metal frame disposed in the outer frame region; and A second metal frame surrounds the outside of the silicon substrate and is connected to the first metal frame.

2. The deposition mask according to claim 1, wherein: The silicon substrate has a circular shape in a plan view, and The second metal frame has a ring shape surrounding the outer portion of the silicon substrate in a plan view.

3. The deposition mask according to claim 2, wherein: The silicon substrate includes a frame opening that exposes a lower surface of the first metal frame in the outer frame region, and The second metal frame is connected to the first metal frame through the frame opening.

4. The deposition mask according to claim 3, wherein: The first metal frame and the second metal frame are connected to each other by welding.

5. The deposition mask according to claim 4, wherein: The welded portion where the welding is performed is continuously connected along the periphery of the second metal frame.

6. The deposition mask according to claim 4, wherein: The welded portion where the welding is performed is discontinuously connected along the periphery of the second metal frame.

7. The deposition mask according to claim 1, wherein: The deposition mask further comprises: at least one metal sheet, spanning the silicon substrate, Wherein, two ends of the metal sheet are respectively connected to the second metal frame.

8. The deposition mask according to claim 7, wherein: The metal sheet extends along the mask rib region at a lower portion of the silicon substrate, and The second metal frame includes a lower step portion on which the metal sheet is seated.

9. The deposition mask according to claim 7, wherein: The metal sheet extends along the mask rib region at a lower portion of the silicon substrate, and A groove is provided on a side surface of the second metal frame, and the metal sheet is embedded in the groove.

10. The deposition mask according to claim 7, wherein: The metal sheet extends along the mask rib region at the upper portion of the silicon substrate, and The second metal frame includes an upper step portion, and the metal sheet is seated on the upper step portion.

11. The deposition mask according to claim 1, wherein: The thickness of the first metal frame is greater than the thickness of the mask film.

12. The deposition mask according to claim 1, wherein: The mask film includes a coating film.

13. The deposition mask according to claim 12, wherein: The mask rib is formed as a portion of the silicon substrate.

14. The deposition mask according to claim 12, wherein: The mask rib includes a plating film formed by the same process as that of the mask film.

15. The deposition mask according to claim 12, wherein: The mask rib includes a stacked structure of a portion of the silicon substrate and a coating film formed by the same process as the mask film.

16. A method for manufacturing a deposition mask, wherein: The method comprises: preparing a silicon substrate, the silicon substrate comprising a plurality of unit regions and a mask frame region other than the plurality of unit regions, the mask frame region comprising a mask rib region separating the plurality of unit regions and an outer frame region disposed at the outermost portion of the silicon substrate; forming a mask film and a first metal frame by performing an electroplating process; forming cell openings corresponding to the plurality of cell regions and a frame opening exposing a lower surface of the first metal frame by etching a rear surface of the silicon substrate; aligning a second metal frame surrounding the exterior of the silicon substrate with the silicon substrate; and The first metal frame and the second metal frame are connected to each other.

17. The method according to claim 16, wherein: The silicon substrate has a circular shape in a plan view, and The second metal frame has a ring shape surrounding the outer portion of the silicon substrate in a plan view.

18. The method according to claim 16, wherein: The connecting the first metal frame and the second metal frame to each other includes a welding process.

19. The method according to claim 18, wherein: The welded portion where the welding process is performed is continuously connected along the circumference of the second metal frame.

20. The method according to claim 18, wherein: A welded portion where the welding process is performed is discontinuously connected along a circumference of the second metal frame.

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