Alignment mark and micro light-emitting diode chip wafer with alignment mark

Abstract

The invention provides an alignment mark group which comprises a first alignment mark, the first alignment mark is located on a cutting channel of an exposure unit of a wafer, the first alignment mark comprises a transverse positioning mark and a longitudinal positioning mark, the transverse positioning mark comprises a first searching unit and a first precise alignment unit, and the longitudinal positioning mark comprises a second searching unit and a second precise alignment unit; wherein the longitudinal positioning mark comprises a second searching unit and a second accurate alignment unit.

Description

Background Art

[0002] Micro Light Emitting Diode (MLED) technology is a high-pixel density LED flat display technology that uses micron-sized LEDs as pixel elements and is assembled on a control backplane at a micron-sized period. The core structure of a MLED is a PN junction diode, which is composed of direct bandgap semiconductor materials. When the upper and lower electrodes apply a forward bias to the MLED to allow current to flow, electrons and holes recombine in the active region and emit single-color photons at the same time.

[0003] When manufacturing micro-LEDs, multiple semiconductor processing steps are usually required, and the multiple semiconductor processing steps carried out before and after will involve the alignment process. Alignment, in simple terms, is to ensure that the previous and subsequent process steps overlap in the correct position. This is usually achieved by automatic recognition of special marks on the wafer substrate by semiconductor processing equipment or manual recognition. For the wafer, alignment marks need to be made on the substrate surface during the first photolithography. Subsequently, etching (dry or wet) is performed on the dielectric layer or metal layer on the wafer through photolithography to form alignment marks. These marks provide reference points for subsequent semiconductor processing.

[0004] The alignment process is crucial for semiconductor manufacturing. If misalignment occurs due to inaccurate alignment, the pattern will be distorted or unable to be accurately aligned, which will ultimately affect the luminous efficiency and electrical characteristics of the micro-LED device. As the resolution, light output and other performance of micro-LED chips continue to improve, the structure of micro-LED devices has become more complex, the line width has become smaller, and the position requirements between product layers have become higher and higher, and more and more precise. This has led to higher and higher precision and difficulty in the manufacturing process of micro-LEDs. For some special structures, different types / models of exposure machines need to be used for lithography; and different types / models of exposure machines have their own corresponding set of alignment marks, which cannot be used universally. It is usually necessary to arrange a variety of alignment marks on the substrate of the micro-LED chip for accurate alignment of multiple processes. However, the existing alignment marks are large in size, occupying a large amount of the effective area of ​​the micro-LED chip, and have the disadvantages of long alignment process, low efficiency and high cost.

[0005] In summary, it is necessary to provide an alignment mark for a micro light emitting diode chip that can achieve alignment accuracy and efficiency. Summary of the invention

[0006] Technical field: Starting from the prior art, the task of the present invention is to provide a positioning mark group, including: a first positioning mark, the first positioning mark is located on the cutting path of the exposure unit of the wafer, the first positioning mark includes a lateral positioning mark and a longitudinal positioning mark, wherein the lateral positioning mark includes a first searching unit and a first precise positioning unit, wherein the longitudinal positioning mark includes a second searching unit and a second precise positioning unit.

[0007] In some embodiments of the present invention, the first searching unit includes three rows of first rectangular blocks, each row of first rectangular blocks includes a plurality of first rectangular blocks arranged in a transverse direction;

[0008] The first precise alignment unit includes five columns of second rectangular blocks, and each column of second rectangular blocks includes a plurality of second rectangular blocks arranged in a longitudinal direction.

[0009] In some embodiments of the present invention, the first rectangular block has a lateral length of 4 microns and a longitudinal width of 3 microns, and the second rectangular block is a square with a side length of 4 microns.

[0010] In some embodiments of the present invention, the spacing between adjacent first rectangular blocks in each row of first rectangular blocks is 3 microns, the lateral length of each row of first rectangular blocks is 87 microns, and the longitudinal width is 4 microns, the first rectangular block in the second row is between the first rectangular block in the first row and the first rectangular block in the third row, the spacing between the first rectangular block in the first row and the first rectangular block in the second row is 16 microns, and the spacing between the first rectangular block in the second row and the first rectangular block in the third row is 22 microns, the spacing between adjacent second rectangular blocks in each column of second rectangular blocks is 4 microns, the longitudinal width of each column of second rectangular blocks is 52 microns, the lateral length is 4 microns, and the spacing between two adjacent columns of second rectangular blocks is 16 microns.

[0011] In some embodiments of the present invention, the first searching unit and the first precise alignment unit are arranged side by side in a lateral direction, and a clearance area is formed around the first searching unit and the first precise alignment unit.

[0012] In some embodiments of the present invention, one side of the first search unit is adjacent to one side of the first precise alignment unit along the horizontal direction, the interval between the first search unit and the first precise alignment unit is not less than 60 microns, the other side of the first search unit is not less than 60 microns away from the boundary of the clearance area along the horizontal direction, the other side of the first precise alignment unit is not less than 60 microns away from the boundary of the clearance area along the horizontal direction, the first search unit is not less than 20 microns away from the boundary of the clearance area along the longitudinal direction, and the first precise alignment unit is not less than 19 microns away from the boundary of the clearance area along the longitudinal direction.

[0013] In some embodiments of the present invention, the transverse positioning mark is rotated 90 degrees to become the longitudinal positioning mark.

[0014] In some embodiments of the present invention, the transverse positioning mark is located in the transverse cutting path of the exposure unit, the longitudinal positioning mark is located in the longitudinal cutting path of the exposure unit, and the clearance area of ​​the transverse positioning mark and the clearance area of ​​the longitudinal positioning mark do not overlap with each other.

[0015] In some embodiments of the present invention, the alignment mark group also includes: a second alignment mark, which is located on the cutting path of the exposure unit of the wafer, and the second alignment mark includes a rectangular mark and a cross mark; and / or multiple third alignment marks, which are located on the cutting path or chip area of ​​the exposure unit of the wafer.

[0016] In some embodiments of the present invention, the rectangular mark is a square with a length of 40 microns and a width of 40 microns, and the cross mark includes vertically intersecting horizontal and vertical lines, and the length of the horizontal and vertical lines is 40 microns and the width is 10 microns.

[0017] In some embodiments of the present invention, a clearance area is formed around the second alignment mark, and the clearance area of ​​the second alignment mark does not overlap with the clearance areas of other alignment marks.

[0018] In some embodiments of the present invention, one side of the rectangular mark along the transverse direction is adjacent to one side of the cross mark, the interval between the rectangular mark and the cross mark is not less than 60 microns, the other side of the rectangular mark along the transverse direction is not less than 60 microns from the boundary of the clearance area, the other side of the cross mark along the transverse direction is not less than 60 microns from the boundary of the clearance area, the distance between both sides of the rectangular mark along the longitudinal direction and the boundary of the clearance area is not less than 25 microns, and the distance between both sides of the cross mark along the longitudinal direction and the boundary of the clearance area is not less than 25 microns.

[0019] In some embodiments of the present invention, the third alignment mark is a square mark with a side length of 30 microns.

[0020] In some embodiments of the present invention, the third alignment mark is surrounded by a clearance area, the clearance area of ​​the third alignment mark does not overlap with the clearance areas of other alignment marks, and the distance between the third alignment mark and the clearance area boundary in the horizontal and vertical directions is not less than 30 microns.

[0021] In some embodiments of the present invention, the plurality of third alignment marks are dispersedly disposed at four corners of the exposure unit.

[0022] In some embodiments of the present invention, the alignment mark group further includes: a plurality of fourth alignment marks, wherein the fourth alignment marks are located on a chip region of an exposure unit of the wafer.

[0023] In some embodiments of the present invention, each chip area of ​​the exposure unit has a fourth alignment mark.

[0024] In some embodiments of the present invention, the fourth alignment mark includes a plurality of blocks arranged in an array.

[0025] In some embodiments of the present invention, the fourth alignment mark includes four blocks arranged in a 2*2 matrix, each block is a square with a side length of 45 microns, the interval between two blocks in the first row is 30 microns, the interval between two blocks in the second row is 30 microns, the interval between two blocks in the first column is 30 microns, and the interval between two blocks in the second column is 30 microns.

[0026] In some embodiments of the present invention, no simple pattern can exist within a range of 500 micrometers around the fourth alignment mark.

[0027] In some embodiments of the present invention, the distance between the fourth alignment mark and the edge of the wafer should be greater than 3 mm.

[0028] In some embodiments of the present invention, the alignment mark group is visible on the wafer surface.

[0029] In some embodiments of the present invention, the alignment mark group is located on the second top layer of the wafer and buried under the transparent medium.

[0030] The present invention also provides a wafer, comprising one or more exposure units, wherein the exposure units are provided with an alignment mark group.

[0031] In some embodiments of the present invention, the exposure unit includes a plurality of micro-LED chips, the micro-LED chips are separated by cutting lines, the micro-LED chip includes a plurality of micro-LED pixels arranged in an array, and each micro-LED pixel includes a micro-LED.

[0032] In some embodiments of the present invention, the micro-light emitting diode includes a pixel driving backplane; a lower electrode layer located on the pixel driving backplane and electrically connected to the pixel driving backplane; a semiconductor light emitting table located on the lower electrode layer and emitting light; and an upper electrode layer in contact with the top of the semiconductor light emitting table.

[0033] In some embodiments of the present invention, the semiconductor light-emitting mesa includes a first type epitaxial layer, a light-emitting layer and a second type epitaxial layer, the first type epitaxial layer is a semiconductor material having a first conductivity type and includes multiple semiconductor layers, and the second type epitaxial layer is a semiconductor material having a second conductivity type and includes multiple semiconductor layers.

[0034] In some embodiments of the present invention, the light-emitting layer is a quantum well light-emitting layer.

[0035] In some embodiments of the present invention, the first to fourth alignment marks are located on a substrate of a pixel driving backplane or on a substrate of a semiconductor light emitting mesa.

[0036] In some embodiments of the present invention, the semiconductor light-emitting table is a platform with an inverted trapezoidal cross-section, and the semiconductor light-emitting table is bonded to the pixel driving backplane through a hybrid bonding process. The fourth alignment mark is located on one of the substrates of the pixel driving backplane or the substrates of the semiconductor light-emitting table. The other of the substrates of the pixel driving backplane or the substrates of the semiconductor light-emitting table has a pattern that matches the fourth alignment mark. After the semiconductor light-emitting table and the pixel driving backplane complete the hybrid bonding process, the fourth alignment mark overlaps with the pattern.

[0037] Advantage 1: Reduced size and increased number of chips placed

[0038] The alignment mark provided by the embodiment of the present invention is significantly smaller than the existing alignment mark, which reduces the wafer area occupied by the alignment mark, thereby reducing the cutting path size and increasing the area reserved for the chip area on the wafer. When the wafer size remains unchanged, more chips can be placed on the wafer of the same size, which brings positive effects in terms of space utilization and chip output quantity.

[0039] Advantage 2: Compatibility and improved process efficiency

[0040] In the embodiment of the present invention, one exposure unit can be integrated with alignment marks that meet the requirements of different processes and different machines, forming an alignment mark group that is compatible with alignment of different machines and processes. Its function is to construct alignment marks on the first layer and / or alignment layer, providing a reference for the alignment of subsequent different machines and processes, thereby ensuring subsequent orderly exposure, and ultimately effectively improving the process efficiency of the product.

[0041] In general, the alignment marks in the embodiments of the invention have obvious advantages in saving wafer space and improving process efficiency, and are helpful for semiconductor manufacturing and other related industries to better carry out production activities. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The present invention will be further described below in conjunction with specific embodiments with reference to the accompanying drawings.

[0043] Figure 1 A schematic cross-sectional view of a micro light emitting diode structure according to an embodiment of the present invention is shown.

[0044] Figure 2 A schematic cross-sectional view of a micro light emitting diode structure according to another embodiment of the present invention is shown.

[0045] Figure 3 A top view of a wafer for manufacturing micro light emitting diode chips according to an embodiment of the present invention is shown.

[0046] Figure 4 A schematic diagram showing a process of exposing the entire wafer at one time according to an embodiment of the present invention is shown.

[0047] Figure 5 A top view of an exposure unit according to an embodiment of the present invention is shown.

[0048] Figure 6 FIG. 5 is an enlarged schematic diagram of a first alignment mark 530 according to an embodiment of the present invention.

[0049] Figure 7 An enlarged schematic diagram of a second alignment mark 540 according to an embodiment of the present invention is shown.

[0050] Figure 8 An enlarged schematic diagram of a rectangular mark in the third alignment mark 550 according to an embodiment of the present invention is shown.

[0051] Fig. 9 A schematic diagram showing the overlap of a photolithography pattern and a third alignment mark according to an embodiment of the present invention is shown.

[0052] Fig.10 A top view of an exposure unit according to another embodiment of the present invention is shown.

[0053] Fig.11 An enlarged schematic diagram of a fourth alignment mark 560 according to an embodiment of the present invention is shown.

[0054] Fig.12 A schematic diagram showing a fourth alignment mark after a hybrid bonding process according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0055] It should be noted that the components in the figures may be shown exaggeratedly for the sake of illustration and are not necessarily true to scale. In the figures, identical or functionally identical components are provided with the same reference numerals.

[0056] In the present invention, unless otherwise specified, "arranged on...", "arranged above..." and "arranged above..." do not exclude the existence of an intermediate between the two. In addition, "arranged on or above..." merely indicates the relative positional relationship between two components, and in certain cases, such as after reversing the product direction, it can also be converted into "arranged below or below...", and vice versa.

[0057] In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.

[0058] In the present invention, unless otherwise specified, the quantifiers "a", "an" and "an" do not exclude the presence of a plurality of elements.

[0059] In the present invention, the term “connected” may refer to both being directly connected or being indirectly connected via an intermediate element.

[0060] In the present invention, the term "configuration" refers to the setting of the shape, structure, material and / or function of the target object to achieve the desired technical effect, wherein "configuration" includes a variety of alternative technical means for achieving the technical effect, which become obvious under the teaching of the present invention.

[0061] It should also be noted that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but those of ordinary skill in the art will understand that under the teachings of the present invention, the required parts or components may be added according to the needs of the specific scenario. In addition, unless otherwise specified, the features in different embodiments of the present invention may be combined with each other. For example, a feature in the second embodiment may be used to replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the disclosure scope or recorded scope of the present application.

[0062] It should also be noted that within the scope of the present invention, the terms "same", "equal", "equal to" and the like do not mean that the values ​​of the two are absolutely equal, but allow a certain reasonable error, that is, the terms also cover "substantially the same", "substantially equal", "substantially equal to". By analogy, in the present invention, the terms "perpendicular to", "parallel to" and the like indicating directions also cover the meanings of "substantially perpendicular to" and "substantially parallel to".

[0063] Micro-LED chips of different structural types have different requirements for mark alignment points. Therefore, in the embodiments of the present invention, multiple groups of different types of alignment marks are used, and the size and position of the alignment marks are optimized at the same time, so as to reduce the substrate alignment time and improve the alignment efficiency, thereby achieving efficient alignment of the micro-LED chip.

[0064] By using the combined alignment mark provided by the present invention, the mixed operation of the stepper lithography machine and the contact / proximity lithography machine can be realized during the lithography operation and the alignment accuracy can be improved. Any mixed operation between the stepper lithography machine and the contact / proximity lithography machine can be realized, and after completing the process steps, the position accuracy of the formed structure can be checked by the alignment mark, thereby improving the product tape-out efficiency and the utilization rate of the exposure machine equipment.

[0065] Figure 1 FIG. 4 is a schematic cross-sectional view of a micro-light emitting diode structure according to an embodiment of the present invention. Figure 1 As shown, the micro light emitting diode structure includes a pixel driving backplane 110 , a lower electrode layer 120 , a conductive layer 130 , a light emitting mesa 140 , an upper electrode layer 150 , a passivation layer 160 , and a microlens 170 .

[0066] For convenience, "upper" is used to mean away from the pixel driving backplane 110, "lower" means towards the pixel driving backplane 110, and other directional terms such as top, bottom, above, below, directly below, below, etc. are also interpreted accordingly.

[0067] Micro-LEDs are basic elements that constitute micro-LED pixels. Each micro-LED pixel may include one or more micro-LED structures. Multiple micro-LED pixels are arranged in an array to form a micro-LED display screen or a micro-LED chip. For example, each pixel in a color micro-LED chip may include multiple micro-LED structures of different colors, while each pixel in a monochrome micro-LED chip may include only a micro-LED structure of one color.

[0068] In an embodiment of the present invention, the size of each micro-LED chip does not exceed 1 cm, preferably does not exceed 20 microns. The micro-LED structure is formed in the micro-LED chip in an array form, and the resolution is, for example, 720*480, 640*480, 1920*1080, 1280*720, 2K or 4K. The diameter of the micro-LED structure is in the nanometer range, for example, 20nm to 100nm. In some embodiments, the pitch of the micro-LED array, that is, the minimum center-to-center distance between the micro-LEDs, can be between about 2 microns and about 50 microns. In some embodiments, the number of pixels on the micro-LED chip can be between thousands and millions.

[0069] In some embodiments, the pixel driving backplane 110 can adopt an integrated circuit chip. The pixel driving backplane 110 includes a substrate, a driving circuit and a contact pad 111. Each micro-light emitting diode corresponds to a contact pad 111, and the contact pad 111 is electrically connected to the lower electrode layer 120. Each driving circuit is a pixel driver. In some cases, the driving circuit is a thin film transistor pixel driver or a silicon CMOS pixel driver. In one embodiment, the substrate of the pixel driving backplane 110 is a Si substrate. In another embodiment, the substrate of the pixel driving backplane 110 is a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO and sapphire substrates. The pixel driving backplane 110 is used to control the lighting and extinguishing of the micro-light emitting diodes in each pixel. In one embodiment, the material of the contact pad 111 is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Pt and Au.

[0070] In some embodiments of the present invention, the pixel drive backplane can be electrically connected to each micro-LED in the micro-LED array via a separate metal interconnect. In some embodiments, each micro-LED can be electrically controlled individually by the pixel drive backplane. In some embodiments, the pixel drive backplane can be electrically connected to the electrodes of the micro-LED chip via metal interconnects. In some embodiments, a dielectric layer can be formed in the gaps between the micro-LEDs. In some embodiments, a dielectric layer can also be formed in the gaps between the interconnects.

[0071] In one embodiment, the lower electrode layer 120 may be a metal bonding composite layer. The light-emitting table 140 of the micro-light-emitting diode may be bonded to the surface of the pixel driving backplane 110 through the metal bonding composite layer 120, and the bonding may be completed by eutectic bonding, hot pressing bonding, and transient liquid phase (TLP) bonding. In one embodiment, the metal bonding composite layer 120 may be disposed on the pixel driving backplane 110. In another embodiment, the metal bonding composite layer 120 is grown on the pixel driving backplane 110. In one embodiment, the thickness of the metal bonding composite layer 120 is 0.1 micron to 3 microns. In a preferred embodiment, the thickness of the metal bonding composite layer 120 is 0.3 μm. In some embodiments, the material of the metal bonding composite layer 120 is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, Ag, and Sn. The metal bonding composite layer 120 may include an ohmic contact layer and a metal bonding layer. In some cases, the metal bonding composite layer 120 includes two metal layers. One of the two metal layers is deposited on a layer above the metal bonding layer in the LED. The corresponding bonding metal layer is deposited on the pixel driving backplane 110. For example, the metal bonding composite layer 120 can be Au-Au bonding, Au-Sn bonding, Au-In bonding, Ti-Ti bonding, Cu-Cu bonding, or a combination of the above. For example, if Au-Au bonding is selected, the two layers of Au require a Cr layer as an adhesive layer and a Pt layer as an anti-diffusion layer respectively. The Pt layer is located between the Au layer and the Cr layer. The Cr and Pt layers are located at the top and bottom of the two bonded Au layers. In some embodiments, when the thickness of the two Au layers is approximately the same, under high pressure and high temperature, the Au on the two layers diffuse mutually to bond the two layers together.

[0072] In some embodiments, the metal bonding composite layer 120 may also function as a reflector to reflect light emitted from the light emitting mesa 140 above.

[0073] In some embodiments, the conductive layer 130 is formed on the bottom surface of the light-emitting mesa 140 to form an electrical connection between the light-emitting mesa 140 and the metal bonding composite layer 120. In some embodiments, the conductive layer 130 can be a conductive transparent layer that is transparent to the light emitted by the light-emitting mesa 140 to improve conductivity and transmittance. In some embodiments, the upper electrode layer 150 is formed on the top surface of the light-emitting mesa 140, and the upper electrode layer 150 is electrically connected to the current spreading structure or the top electrode (not shown).

[0074] In one embodiment, the conductive layer 130, the upper electrode layer 150 and their connecting parts can be a combination of one or more materials such as graphene or indium tin oxide (ITO) or aluminum doped zinc oxide (AZO) or fluorine doped tin oxide (FTO) or other transparent conductive oxides (TCO).

[0075] The light-emitting mesa 140 includes a first type epitaxial layer 141, a second type epitaxial layer 143, and a light-emitting layer 142 located therebetween. The first type epitaxial layer 141 is electrically connected to the conductive layer 130. The second type epitaxial layer 143 is electrically connected to the upper electrode layer 150. In some embodiments, the light-emitting mesa of each micro-light-emitting diode in the micro-light-emitting diode array can be a micron-sized light-emitting mesa. In the three-layer structure, the first type epitaxial layer 141 is closest to the driving backplane 110; the light-emitting layer 142 is located above the first type epitaxial layer and further away from the driving backplane 110; the second type epitaxial layer 143 is located above the light-emitting layer 142 and farthest away from the driving backplane 110. In some embodiments, the light-emitting layer 142 is formed by a plurality of stacked quantum well layers, in particular, quantum well layers stacked in a superlattice. Preferably, the quantum well layers stacked in a superlattice include a plurality of pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the first type epitaxial layer 141 is a semiconductor material having a first conductivity type and includes a plurality of semiconductor layers. The main matrix material of the first type epitaxial layer 141 may be, but is not limited to, composed of materials such as Ga, N, As, P, In or Al. In addition, the first type epitaxial layer 141 may include, from top to bottom, but is not limited to, a waveguide layer, a confinement layer, a transition layer and a window layer; in addition, an ohmic contact layer may be formed below the window layer. In some embodiments, the second type epitaxial layer 143 is a semiconductor material having a second conductivity type and includes a plurality of semiconductor layers. The main matrix material of the second type epitaxial layer 143 may be, but is not limited to, composed of materials such as Ga, N, As, P, In or Al. In addition, the second type epitaxial layer 143 may include, from top to bottom, but is not limited to, a confinement layer and a waveguide layer; in addition, in some embodiments, an ohmic contact layer may be formed on the confinement layer. In one embodiment, the first conductivity type is different from the second conductivity type.

[0076] In some embodiments, the first type epitaxial layer 141 is an N-type GaN layer or an N-type AlGaN layer, and the second type epitaxial layer 143 is a P-type GaN layer or a P-type AlGaN layer, that is, the material of the second type epitaxial layer 143 can be a material layer of the second conductivity type including at least two or more elements of Ga, N, As, Al, In, and P, and the first type epitaxial layer 141 can be a material layer of the first conductivity type including at least two or more elements of Ga, N, As, Al, In, and P. In some embodiments, the light-emitting layer 142 includes a multi-quantum well layer and an electron blocking layer, and the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer. In some embodiments, the light-emitting layer 142 also includes an electron blocking layer, and the electron blocking layer is disposed on a first side of the light-emitting layer, and the first side refers to a side along which electrons migrate out of the light-emitting layer. In another embodiment, the first type epitaxial layer 141 may also be a P-type GaN layer or a P-type AlGaN layer, and the second type epitaxial layer 143 may be an N-type GaN layer or an N-type AlGaN layer.

[0077] In some embodiments, the light emitting layer 142 includes at least one quantum well layer. The thickness of the quantum well layer is between 20 nm and 40 nm, for example, 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x ) y In 1-y P, wherein x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times greater than y.

[0078] In some embodiments, one of the first type epitaxial layer 141 and the second type epitaxial layer 143 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer, and the N-type cladding layer is formed on the doped N-type contact layer. The material of the N-type cladding layer is Al x In 1-x P, wherein x ranges from 0.1 to 0.5, for example, x is 0.5. In addition, in these embodiments, the thickness of the N-type cladding layer is not greater than 350 nm, for example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e 17 cm -3 To 1e 18 cm -3The material of the doped N-type contact layer is GaAs. In some embodiments, the thickness of the doped N-type contact layer is 10 nm to 30 nm. In some embodiments, the doping concentration of the doped N-type contact layer is 2e 18 cm -3 To 1e 19 cm -3 In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al x Ga 1-x ) y In 1-y P, wherein x ranges from 0.5 to 0.9, and y ranges from 0.1 to 0.5. For example, x is 0.8, and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times greater than y. The thickness of the N-type spacer layer is 50 nm to 75 nm, for example 65 nm.

[0079] In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light-emitting layer, and the doped P-type contact layer is formed on the P-type cladding layer. In some embodiments, the material of the P-type cladding layer is Al x In 1-x P, wherein x is 0.3 to 0.5, for example, x is 0.5. In such an embodiment, the thickness of the P-type cladding layer is not greater than 380 nm, for example, the thickness of the P-type cladding layer is 360 nm. In some embodiments, the material of the doped P-type contact layer is GaAs. The thickness of the doped P-type contact layer is 10 nm to 30 nm, for example, 20 nm.

[0080] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first doped P-type transition layer formed on the P-type cladding layer, and a second doped P-type transition layer formed on the first doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al x Ga 1-x ) y In 1-y P, wherein x ranges from 0.5 to 0.9 and y ranges from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times greater than y. In some embodiments, the thickness of the P-type spacer layer is 50 nm to 70 nm, for example 65 nm.

[0081] In some embodiments, the material of the first doped P-type transition layer is (Al x Ga 1-x ) y In 1-yP, wherein x ranges from 0.1 to 0.3 and y ranges from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is y is 1 to 5 times x. In some embodiments, the thickness of the first doped P-type transition layer is 20 nm to 40 nm, for example 30 nm.

[0082] In some embodiments, the material of the second doped P-type transition layer is Al x Ga 1-x As, wherein x ranges from 0.5 to 0.9, for example, x is 0.6. In some embodiments, the thickness of the second doped P-type transition layer is from 10 nm to 30 nm, for example, 20 nm.

[0083] In some embodiments, the doping concentration of the second doped P-type transition layer is greater than the doping density of the first doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times the doping concentration of the second doped P-type transition layer.

[0084] In some embodiments, the doping concentration of the doped P-type contact layer is greater than the doping concentration of the second doped P-type transition layer. In addition, in some embodiments, the doping concentration of the second doped P-type transition layer is 2 to 4 times the doping concentration of the first doped P-type transition layer.

[0085] For example, the doping concentration of the first doped P-type transition layer is greater than 1e 18 cm -3 The doping density of the second doped P-type transition layer is 2e 18 cm -3 -4e 18 cm -3 In the range of 5e 18 cm -3 .

[0086] In some embodiments, the electrode polarity of the conductive layer 130 is determined by the first type epitaxial layer 141, and the electrode polarity of the upper electrode layer 150 is determined by the second type epitaxial layer 143. The electrode polarity of the conductive layer 130 is opposite to the electrode polarity of the upper electrode layer 150. The conductive layer 130 can be, for example, a P electrode or an anode electrode, and the upper electrode layer 150 is an electrode with an opposite polarity to that of the conductive layer 130, such as an N electrode or a cathode electrode, and vice versa.

[0087] In one embodiment, the light-emitting mesa 140 may be a platform with a trapezoidal cross-section, and the bottom lateral dimension of the light-emitting mesa is larger than the top lateral dimension. There is an inclination angle between the side wall of the semiconductor light-emitting mesa 140 and the bottom of the semiconductor light-emitting mesa, and the inclination angle is less than or equal to 90°. In one embodiment, the inclination angle range of the side wall of the light-emitting mesa is: 45° to 90°. In one embodiment, the bottom lateral dimension of the light-emitting mesa exceeds 2 microns. In one embodiment, the top lateral dimension of the light-emitting mesa does not exceed 1.5 microns. In one embodiment, the lateral dimension of the metal bonding composite layer is larger than the bottom lateral dimension of the light-emitting mesa.

[0088] In some embodiments, the light emitting mesa 140 can emit red light, blue light, green light, or light of any other color.

[0089] In some embodiments, the passivation layer 160 covers the side surfaces of the metal bonding composite layer 120, the conductive layer 130, and the light emitting mesa 140. In some embodiments of the present invention, the passivation layer 160 may also cover a portion of the side surfaces of the upper electrode layer 150, and a portion of the top surface of the upper electrode layer 150 is exposed so as to form an electrical connection with the top electrode. In other embodiments of the present invention, the passivation layer 160 does not cover the top surface and the side surfaces of the upper electrode layer 150, so that the upper electrode layers 150 of adjacent LED structures can be connected to each other as a whole to form a common cathode or anode. In some embodiments of the present invention, the passivation layer 160 covers the side surfaces of the metal bonding composite layer 120, the conductive layer 130, the first type epitaxial layer 141, the light emitting layer 142, and a portion of the side surfaces of the second type epitaxial layer 143.

[0090] In one embodiment, the material of the passivation layer is a transparent insulating material, for example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0091] In one embodiment, the insulating medium 180 fills the gaps between the light emitting mesas 140. The insulating medium 180 is transparent to the light emitted by the light emitting mesas 140.

[0092] In some embodiments, the insulating medium 180 is made of a dielectric material such as a solid inorganic material or a plastic material. In some embodiments, the solid inorganic material includes SiO2, Al2O3, Si3N4, SiCN, HfO2, Ta2O5, TiO2, ZrO2, La2O3, MgO, phosphosilicate glass (PSG), borophosphosilicate glass, or any combination thereof. In some embodiments, the plastic material includes a polymer such as SU-8, PermiNex, benzocyclobutene (BCB), or a transparent plastic (resin) including spin-on glass (SOG), or an adhesive Micro Resist BCL-1200, or any combination thereof. In some embodiments, the insulating medium 180 can facilitate the passage of light emitted from the LED structure.

[0093] In some embodiments, microlens 170 is formed on top of light emitting mesa 140. The lateral dimension of the bottom of microlens 170 can be greater than the lateral dimension of the micro-LED light emitting area. In some embodiments, the lateral dimension of the bottom of microlens 102 can be equal to the lateral dimension of the micro-LED light emitting area.

[0094] In some embodiments, one microlens 170 can cover multiple lens-free micro-LEDs. Multiple microlenses constitute a microlens array. The microlens array is arranged above the micro-LED array, wherein at least one microlens is arranged on the surface of the top conductive layer of the micro-LED, and the horizontal profile of the microlens is larger than the maximum horizontal profile of the micro-LED. The microlens is mainly used to converge and / or collimate light. For example, the thickness, curvature and other parameters of the microlens can be adjusted so that the focus of the microlens is located in the light-emitting table of the micro-LED. The microlenses in a microlens array are usually the same. Examples of microlenses include spherical microlenses, aspherical microlenses, Fresnal microlenses and cylindrical microlenses. Figure 1 As shown, in one embodiment, typical shapes of the bottom cross-section of each microlens include circle, square, rectangle and hexagon. The microlenses in the microlens array of the display panel can be the same or different in shape, curvature, optical power, size, base, spacing, etc.

[0095] In some embodiments, the shape of the microlens 170 may be a curved hemispherical shape or a regular hemispherical shape. In some embodiments, the height of the microlens 170 is not greater than 2 microns. In some embodiments, the height of the microlens 170 is not greater than 1 micron. In some embodiments, the height of the microlens 170 is not greater than 0.5 microns. In some embodiments, the width of the microlens 170 is not greater than 4 microns. In some embodiments, the width of the microlens 170 is not greater than 3 microns. In some embodiments, the width of the microlens 170 is not greater than 2 microns. In some embodiments, the width of the microlens 170 is not greater than 1 micron. In some embodiments, the width of the microlens 170 is greater than 1.5.

[0096] In some embodiments, the microlens 170 can be made of various materials that are transparent to the wavelengths of light emitted by the micro-LED. Exemplary transparent materials for the microlens 170 include polymers, dielectric materials. In some embodiments, the dielectric material includes one or more materials such as silicon oxide, silicon nitride, silicon carbide, titanium oxide, zirconium oxide, aluminum oxide, etc. In some embodiments, the microlens 170 is made of photoresist. In some embodiments, the microlens is directly deposited on the surface of the micro-LED by chemical vapor deposition (CVD) technology.

[0097] Figure 2 FIG. 4 is a schematic cross-sectional view of a micro-light emitting diode structure according to another embodiment of the present invention. Figure 2 As shown, the micro light emitting diode structure includes a pixel driving backplane 210 , a lower electrode layer 220 , a conductive layer 230 , a light emitting mesa 240 , an upper electrode layer 250 , a passivation layer 260 , a microlens 270 , an insulating medium 280 and a reflective layer 290 .

[0098] The light emitting mesa 240 includes a first type epitaxial layer 241 , a second type epitaxial layer 243 and a light emitting layer 242 therebetween. The first type epitaxial layer 241 is electrically connected to the conductive layer 230 , and the second type epitaxial layer 243 is electrically connected to the upper electrode layer 250 . Figure 2 The light emitting table 240 is shown with Figure 1 The difference between the light-emitting mesa 140 shown is that the cross-sectional shape of the light-emitting mesa 240 is an inverted trapezoid. The lateral dimension of the bottom of the light-emitting mesa is smaller than the lateral dimension of the top. There is an inclination angle between the side wall of the semiconductor light-emitting mesa 140 and the bottom of the semiconductor light-emitting mesa, and the inclination angle is greater than or equal to 90°. In one embodiment, the inclination angle of the side wall of the light-emitting mesa ranges from 90° to 135°.

[0099] In some embodiments, the passivation layer 260 covers the side surfaces of the conductive layer 230 and the light-emitting mesas 240. In some embodiments of the present invention, the tops of the second type epitaxial layers 243 of adjacent light-emitting mesas 240 are connected to each other, and the passivation layer 260 covers the bottom surface of the connected portion of the second type epitaxial layer 243. At least a portion of the bottom surface of the light-emitting mesas 240 is not covered by the passivation layer 260, and the conductive layer 230 is located on the bottom surface of the light-emitting mesas 240 and forms an electrical connection therewith. The material of the passivation layer 260 is a transparent insulating material, for example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0100] In some embodiments, the reflective layer 290 is formed on surfaces of the passivation layer 260 and the conductive layer 230 that are away from the light emitting mesa 240 .

[0101] In some embodiments, the reflective layer 290 can be a metal layer with high reflectivity, which includes one or more metals such as Pt, Rh, Al, Au and Ag, a stacked DBR layer including TiO2 / SiO2 layers, or any other layer with total reflection properties, including a multilayer omnidirectional reflector (ODR), or a combination thereof.

[0102] In some embodiments, the reflective layer 290 may be one or more reflective coatings. The one or more reflective coatings may reflect light emitted from the light emitting area, thereby enhancing the brightness and luminous efficiency of the micro LED panel or display. For example, light emitted from the light emitting area may reach the one or more reflective coatings and may be reflected upward by the one or more reflective coatings.

[0103] Since the reflective layer can be made of a conductive material, there is a gap 291 between the reflective layers of adjacent micro-mesa structures, thereby avoiding a short circuit between adjacent light-emitting mesas.

[0104] In one embodiment, the insulating medium 280 fills the gaps between the light-emitting mesas 240. The insulating medium 280 is transparent to the light emitted by the light-emitting mesas 240. The material of the insulating medium 280 is similar to that of the insulating medium 180, and will not be described again to simplify the present description.

[0105] In some embodiments, the light-emitting mesa 240 of the micro light-emitting diode can be bonded to the surface of the pixel driving backplane 210 by a hybrid bonding process. For example, in the hybrid bonding process, an oxide bonding layer is deposited at the bottom of the light-emitting mesa structure; and a corresponding oxide bonding layer is deposited on the substrate 110. Then, a through hole can be formed in the oxide bonding layer and filled with metal to form the lower electrode layer 220. A CMP process can be performed on the surface of the lower electrode layer 220 so that the surface of the lower electrode layer 220 is flush with the surface of the oxide bonding layer. Then, the light-emitting mesa 240 is bonded to the substrate 210 under high pressure and high temperature. In some embodiments, the lower electrode layer 220 is electrically connected between the contact 211 on the substrate 210 and the light-emitting mesa 240 above the lower electrode layer 220, and acts as a P electrode.

[0106] In one embodiment, the upper electrode layer 250 is formed on the top surface of the light-emitting mesa 240, and the second type epitaxial layer 243 is electrically connected to the upper electrode layer 250. The material of the upper electrode layer 250 is similar to that of the upper electrode layer 150, and will not be repeated for the sake of simplicity of this specification. In some embodiments, the microlens 270 is formed on the top of the light-emitting mesa 240. The material of the microlens 270 is similar to that of the microlens 170, and will not be repeated for the sake of simplicity of this specification.

[0107] In an embodiment of the present invention, the micro LEDs described above or other similar micro LEDs constitute micro LED pixels, and a plurality of micro LED pixels are arranged in an array to constitute a micro LED chip. The manufacturing process of a micro LED chip usually involves multiple photolithography processes performed in sequence.

[0108] Figure 3 FIG. 2 shows a top view of a wafer for manufacturing a micro light emitting diode chip according to an embodiment of the present invention. Figure 3 As shown, the wafer 300 includes a plurality of exposure units 301 arranged in sequence. Each exposure unit 301 includes one or more micro-LED chips 302. In one embodiment, during the manufacturing process of the micro-LED chips, a stepper lithography machine may be used to sequentially expose the plurality of exposure units 301 in a predetermined order. For example, Figure 3 The serpentine sequence indicated by the middle arrow sequentially exposes each exposure unit 301. When all exposure units have completed exposure, subsequent development, etching and other processes are performed on the entire wafer 300.

[0109] In some embodiments of the present invention, during the manufacturing process of the micro-LED chip, the entire wafer may be exposed and subsequently processed at one time. Figure 4 FIG. 2 is a schematic diagram showing a process of exposing the entire wafer at one time according to an embodiment of the present invention. Figure 4As shown, a thin film is first formed on the substrate, and then a photoresist is formed on the thin film. Next, the photolithography machine exposes the entire wafer at one time to transfer the pattern on the mask to the photoresist. After that, development, etching, degumming and other processes are performed to transfer the pattern on the photoresist to the thin film, thereby achieving thin film patterning.

[0110] Figure 3 The stepper lithography process shown in the figure exposes the material in steps, and after each exposure, the wafer is displaced relative to the mask. This method can increase the exposure field, achieve nanometer-level precision, and is suitable for preparing high-resolution ultra-fine patterns. However, the manufacturing and maintenance costs of stepper lithography machines are high. Figure 4 The photolithography process shown in which the entire wafer is exposed at one time is low cost and suitable for low-resolution scenarios.

[0111] In order to be compatible with a variety of photolithography processes during the manufacturing process of micro-light-emitting diode chips, and to check or verify the alignment accuracy during the manufacturing process, the present invention proposes a positioning mark group, including multiple positioning marks for different processes, to provide a reference for the subsequent alignment of different processes. Each alignment mark is independent of each other, and a certain distance is maintained between the alignment marks, thereby avoiding the problem of mutual influence and mutual occlusion between the alignment marks. The alignment mark is formed on each exposure unit of the wafer to be processed. By giving the coordinates of the alignment mark in the exposure process, the lithography machine automatically goes to the position to find the corresponding alignment mark, performs measurement and adjustment, thereby achieving precise alignment, and the subsequent process achieves lithography alignment by analogy.

[0112] Figure 5 FIG. 2 shows a top view of an exposure unit according to an embodiment of the present invention. Figure 5 As shown, the exposure unit 500 includes four micro-LED chips 511-514. The four micro-LED chips 511-514 are separated by a preset cutting road area 520. The exposure unit 500 also includes a first alignment mark 530, a second alignment mark 540 and a third alignment mark 550. Figure 5 In the illustrated embodiment, the alignment mark is disposed in a non-device area of ​​the wafer to avoid affecting the preparation of the device and to avoid the alignment mark occupying the wafer space, thereby ensuring the utilization rate of the wafer and maximizing the utilization of the wafer. Specifically, the alignment mark is located on the cutting path area 520. All alignment marks are visible on the surface of the wafer. For example, the alignment mark can be located on the sub-top layer of the wafer, buried under the transparent medium. The alignment mark area must not be interfered with by any other pattern from top to bottom. In subsequent processes, only a transparent material layer can be formed above the alignment mark area, and it is not allowed to be covered by non-transparent materials.

[0113] In some embodiments of the present invention, the first alignment mark 530 includes a transverse (X direction) positioning mark and a longitudinal (Y direction) positioning mark. Figure 6 FIG. 5 shows an enlarged schematic diagram of a first alignment mark 530 according to an embodiment of the present invention. Figure 6 As shown, the first alignment mark 530 includes a transverse positioning mark 610 and a longitudinal positioning mark 620 .

[0114] In some embodiments of the present invention, the lateral positioning mark 610 is used for the horizontal coordinate positioning of the exposure unit, and includes a search unit 611 and a precise alignment unit 612. The search unit 611 includes a plurality of first rectangular blocks 613 arranged according to a certain rule. The first rectangular block 613 can be a rectangular block with a lateral length of 4 microns and a longitudinal width of 3 microns. The search unit 611 includes three rows of first rectangular blocks, each row of first rectangular blocks includes 15 rectangular blocks arranged in the transverse direction, and the interval S1 between each adjacent first rectangular block is 3 microns, and the lateral length of each row of first rectangular blocks is 87 microns and the longitudinal width is 4 microns. The first rectangular block in the second row is between the first rectangular block in the first row and the first rectangular block in the third row, the interval K1 between the first rectangular block in the first row and the first rectangular block in the second row is 16 microns, and the interval K2 between the first rectangular block in the second row and the first rectangular block in the third row is 22 microns. Those skilled in the art should understand that the number of first rectangular blocks in each row is not limited to Figure 6 15 are shown. In other embodiments of the present invention, the number of first rectangular blocks in each row may be greater than or less than 15. The precise alignment unit 612 includes a plurality of second rectangular blocks 614 arranged according to a certain rule. The second rectangular blocks 614 may be blocks with a horizontal length of 4 microns and a vertical width of 4 microns. The precise alignment unit 612 includes five columns of second rectangular blocks 614. Each column of second rectangular blocks includes 7 second rectangular blocks arranged in the vertical direction, and the interval S2 between each adjacent second rectangular block is 4 microns. The vertical width of each column of second rectangular blocks is 52 microns, and the horizontal length is 4 microns. The interval K2 between two adjacent columns of second rectangular blocks is 16 microns. Those skilled in the art should understand that the number of second rectangular blocks in each column is not limited to Figure 6 The number of second rectangular blocks shown is 7. In other embodiments of the present invention, the number of second rectangular blocks in each column may be greater than or less than 7.

[0115] The search unit 611 and the precise alignment unit 612 are arranged side by side in the horizontal direction. In order to avoid external graphics interfering with the alignment mark and internal graphics of the alignment mark interfering with each other, a clearance area 615 needs to be set around the search unit 611 and the precise alignment unit 612. Figure 6The rectangular frame in the middle indicates that, except for the alignment mark pattern, no other pattern structures can appear from top to bottom in the rectangular frame. In some embodiments of the present invention, one side of the search unit 611 along the horizontal direction is adjacent to one side of the precise alignment unit 612, and the interval l1 therebetween is not less than 60 microns, and the distance l2 between the other side of the search unit 611 along the horizontal direction and the boundary of the clearance area 615 is not less than 60 microns. The distance l3 between the other side of the precise alignment unit 612 along the horizontal direction and the boundary of the clearance area 615 is not less than 60 microns. The distances l4 and l5 between the two sides of the search unit 611 along the longitudinal direction and the boundary of the clearance area 615 are not less than 20 microns. The distance l6 between the two sides of the precise alignment unit 612 along the longitudinal direction and the boundary of the clearance area 615 is not less than 19 microns.

[0116] In some embodiments of the present invention, the clearance area 615 has a lateral length W of 351 microns and a longitudinal width H of 90 microns.

[0117] In some embodiments of the present invention, the longitudinal positioning mark 620 is used for longitudinal coordinate positioning of the exposure unit, and includes a search unit 621 and a precise alignment unit 622. The basic graphics of the longitudinal positioning mark 620 and the lateral positioning mark 610 are similar, except that the longitudinal positioning mark 620 is obtained by rotating the lateral positioning mark 610 by 90 degrees.

[0118] In some embodiments of the present invention, the first alignment mark 530 is generally used for a stepper lithography machine to determine the position of an exposure unit. By giving the coordinates of the alignment mark in the exposure process, the lithography machine automatically searches for the corresponding alignment mark at the position. The lithography machine can first determine the lateral position of the exposure unit through the lateral positioning mark 610. Specifically, the lithography machine first roughly determines the lateral position of the exposure unit through the search unit 611, and then accurately determines the lateral position of the exposure unit through the precise alignment unit 612. The lithography machine then determines the longitudinal position of the exposure unit through the longitudinal positioning mark 620. Specifically, the lithography machine first roughly determines the longitudinal position of the exposure unit through the search unit 621, and then accurately determines the longitudinal position of the exposure unit through the precise alignment unit 622. The lithography machine accurately positions the exposure unit under the mask through the lateral positioning mark 610 and the longitudinal positioning mark 620, thereby achieving precise alignment. Subsequent processes are analogous to achieve lithography alignment.

[0119] In some embodiments of the present invention, the transverse positioning mark 610 and the longitudinal positioning mark 620 can be set at any position on the cutting path in the exposure unit. The clearance area 615 of the transverse positioning mark 610 and the clearance area 625 of the longitudinal positioning mark 620 cannot overlap each other, thereby preventing interference between the alignment marks. For example, the transverse positioning mark 610 can be located in the transverse cutting path of the exposure unit, and the longitudinal positioning mark 620 can be located in the longitudinal cutting path of the exposure unit.

[0120] In some embodiments of the present invention, the second alignment mark 540 includes a rectangular mark and a cross mark. Figure 7 FIG. 5 shows an enlarged schematic diagram of a second alignment mark 540 according to an embodiment of the present invention. Figure 7 As shown, the second alignment mark 540 includes a rectangular mark 710 and a cross mark 720. The rectangular mark 710 may be a square with a length L1 of 40 microns and a width K1 of 40 microns. The cross mark 720 includes a vertical cross-shaped horizontal line and a vertical line, which have the same size, a length L2 of 40 microns, and a width K2 of 10 microns.

[0121] In order to prevent external graphics from interfering with the alignment mark and internal graphics from interfering with each other, a clearance area 730 needs to be set around the rectangular mark 710 and the cross mark 720. Figure 7 The rectangular frame in the middle indicates that no other pattern structures can appear from top to bottom in the rectangular frame except for the alignment mark pattern. In some embodiments of the present invention, one side of the rectangular mark 710 along the horizontal direction is adjacent to one side of the cross mark 720, and the interval l1 between the two is not less than 60 microns, and the distance l2 between the other side of the rectangular mark 710 along the horizontal direction and the boundary of the clearance area 730 is not less than 60 microns. The distance l3 between the other side of the cross mark 720 along the horizontal direction and the boundary of the clearance area 730 is not less than 60 microns. The distances l4 and l5 between the two sides of the rectangular mark 710 along the longitudinal direction and the boundary of the clearance area 730 are not less than 25 microns. The distances l6 and l7 between the two sides of the cross mark 720 along the longitudinal direction and the boundary of the clearance area 730 are not less than 25 microns.

[0122] In some embodiments of the present invention, the second alignment mark 540 is generally used for alignment and positioning of the entire wafer, for example, Figure 4 The photolithography process shown. During the alignment process, the second alignment mark 540 overlaps with the corresponding pattern on the upper mask, thereby achieving alignment. The alignment accuracy of the second alignment mark 540 is lower than that of the first alignment mark 530. Therefore, the second alignment mark 540 is usually used for the alignment of larger patterns and subsequent manufacturing processes.

[0123] In some embodiments of the present invention, the second alignment mark 540 can be set at any position on the cutting path in the exposure unit. The clearance area of ​​the second alignment mark 540 cannot overlap with the clearance areas of other alignment marks, thereby preventing interference between alignment marks.

[0124] In some embodiments of the present invention, the clearance area 730 has a lateral length W of 260 micrometers and a longitudinal width H of 90 micrometers.

[0125] In some embodiments of the present invention, the third alignment mark 550 includes a rectangular mark. Figure 8FIG. 5 is an enlarged schematic diagram showing a rectangular mark in the third alignment mark 550 according to an embodiment of the present invention. Figure 8 As shown, the rectangular mark 810 may be a square having a length W1 of 30 microns and a width H1 of 30 microns.

[0126] In order to prevent external graphics from interfering with the alignment mark, a clearance area 820 needs to be set around the rectangular mark 810. The clearance area 820 is Figure 8 The rectangular frame in the middle indicates that except for the alignment mark pattern, no other pattern structures can appear from top to bottom in the rectangular frame. The distance l between the rectangular mark 810 and the boundary of the clearance area 820 in the horizontal and vertical directions is not less than 30 microns.

[0127] In some embodiments of the present invention, the clearance area 820 has a lateral length W2 of 90 micrometers and a longitudinal width H2 of 90 micrometers.

[0128] exist Figure 5 In the illustrated embodiment, the third alignment mark 550 may include a plurality of rectangular marks, which may be respectively arranged at any position on the cutting path in the exposure unit or may be arranged in the chip area. The clearance area of ​​each rectangular mark and the clearance area of ​​other alignment marks cannot overlap with each other, thereby preventing interference between the alignment marks.

[0129] In some embodiments of the present invention, the third alignment mark 550 is generally used to check the alignment accuracy of the formed pattern after the process is completed. Fig. 9 As shown, the pattern 910 formed by the photolithography process covers the third alignment mark 550. By calculating the deviation between the pattern 910 and the third alignment mark 550, it is determined whether the pattern formed by the photolithography process meets the requirements. Each rectangular mark in the third alignment mark 550 can be used to detect the alignment accuracy of the pattern formed above the rectangular mark after the process is completed. This accuracy data can reflect the alignment accuracy of the pattern near the area. In order to obtain the alignment accuracy of the pattern on the entire exposure area as accurately as possible, multiple rectangular marks of the third alignment mark 550 can be dispersed and set at the four corners of the exposure area, such as Figure 5 However, those skilled in the art should understand that the number of rectangular marks included in the third alignment mark 550 is not limited to four, and the plurality of rectangular marks of the third alignment mark 550 can be dispersedly arranged at different positions of the exposure area in other ways.

[0130] The following Table 1 shows Figure 5 Parameters of the first to third alignment marks shown in .

[0131] Table 1

[0132]

[0133] The second column of Table 1 gives specific examples of the lateral (X) and longitudinal (Y) dimensions of the clearance areas of the first to third alignment marks, the third column gives the minimum spacing between the alignment mark pattern and other patterns, the fourth column gives the minimum number of marks in one exposure unit, and the fifth column gives the position of the alignment mark.

[0134] Compared with the prior art, the alignment marks provided by the present invention have the advantages of being simplified in number, reducing the occupied area, and increasing the number of chips arranged on the wafer. The size of the entire clearance area of ​​the first alignment mark is significantly reduced, and the design arrangement is more flexible. The size of the clearance area of ​​the second alignment mark is further compressed, which increases the number of chips arranged and reduces unnecessary occupied space.

[0135] In the above embodiments, reference Figures 5 to 9 The first to third alignment marks in an exposure unit are described. However, those skilled in the art should understand that the positions, sizes and shapes of the first to third alignment marks of the present invention are not limited to those shown in the above embodiments. For example, an exposure unit may include M*N micro-LED chips, so the cutting lane areas that divide different chips are criss-crossed meshes. The first to third alignment marks are located in the meshed cutting lanes. Those skilled in the art can set the specific positions of the first to third alignment marks according to actual alignment requirements.

[0136] Fig.10 FIG. 5 is a top view of an exposure unit according to another embodiment of the present invention. The exposure unit 500 includes a first alignment mark 530, a second alignment mark 540, a third alignment mark 550, and a fourth alignment mark 560. The first alignment mark 530, the second alignment mark 540, the third alignment mark 550 and the fourth alignment mark 560 are Figure 5 The structures shown are similar and will not be described in detail in order to simplify the description.

[0137] In some embodiments of the present invention, the fourth alignment mark 560 includes a plurality of squares arranged in an array. Fig.11 FIG. 5 shows an enlarged schematic diagram of a fourth alignment mark 560 according to an embodiment of the present invention. Fig.11 As shown, the fourth alignment mark 560 includes four squares 1101-1104 arranged in a 2*2 matrix. Each square 1101-1104 is a square with a side length of 45 microns. The interval l1 between the two squares 1101 and 1102 in the first row is 30 microns. The interval l2 between the two squares 1103 and 1104 in the second row is 30 microns. The interval l3 between the two squares 1101 and 1103 in the first column is 30 microns. The interval l4 between the two squares 1102 and 1104 in the second column is 30 microns.

[0138] In order to prevent external patterns from interfering with the alignment mark, a clearance area 1105 needs to be set around the fourth alignment mark 560. The clearance area 1105 is Fig.11 The rectangular frame in the middle indicates that no other pattern structures can appear from top to bottom in the rectangular frame except the alignment mark pattern. The distance l5 between the outer edge of the matrix formed by the four squares 1101-1104 and the boundary of the clearance area 1105 in the horizontal and vertical directions is not less than 10 microns. In addition, within the range of 500 microns around the matrix formed by the four squares 1101-1104, no simple pattern can exist to avoid interference with the fourth alignment mark 560.

[0139] In the embodiment of the present invention, when the fourth alignment mark 560 is located in the exposure unit at the edge of the wafer, the distance between the fourth alignment mark 560 and the edge of the wafer should be greater than 3 mm.

[0140] In some embodiments of the present invention, the clearance area 820 has a lateral length of 140 microns and a longitudinal width of 140 microns.

[0141] exist Fig.10 In the illustrated embodiment, a plurality of fourth alignment marks 560 are respectively disposed on the chip area inside the exposure unit. The clearance areas of the plurality of fourth alignment marks 560 cannot overlap with the clearance areas of other alignment marks, thereby preventing mutual interference between alignment marks. For example, a fourth alignment mark 560 may be placed at a corner of each chip. In other embodiments of the present invention, a fourth alignment mark 560 may be placed on each of several specific chips in the exposure unit, while no fourth alignment mark 560 may be placed on the remaining chips.

[0142] In some embodiments of the present invention, the fourth alignment mark 560 is generally used to check the alignment accuracy of a specific process after the process is completed. Figure 2 In the process of completing the hybrid bonding process of the light-emitting mesa 240 of the micro-LED and the pixel driving backplane 210, a fourth alignment mark 560 can be formed on the substrate of the light-emitting mesa 240 of the micro-LED, and a pattern 1210 matching the fourth alignment mark 560 can be formed on the pixel driving backplane 210, as shown in FIG. Fig.12 As shown. Alternatively, the fourth alignment mark 560 may be formed on the pixel driving backplane 210 first, and a pattern 1210 matching the fourth alignment mark 560 may be formed on the substrate of the light emitting table 240 of the micro-LED. After the light emitting table 240 of the micro-LED and the pixel driving backplane 210 complete the hybrid bonding process, the fourth alignment mark 560 overlaps with the pattern 1210. By calculating the deviation between the pattern 1210 and the fourth alignment mark 560, it is determined whether the alignment accuracy between the light emitting table 240 of the micro-LED and the pixel driving backplane 210 after hybrid bonding meets the requirements.

[0143] The following Table 2 shows Fig.10 Parameters of the first to fourth alignment marks shown in .

[0144] Table 2

[0145]

[0146] The second column of Table 2 gives specific examples of the lateral (X) and longitudinal (Y) dimensions of the clearance areas of the first to fourth alignment marks, the third column gives the minimum spacing between the alignment mark pattern and other patterns, the fourth column gives the minimum number of marks in one exposure unit, and the fifth column gives the position of the alignment mark.

[0147] Compared with the existing alignment marks, the alignment marks provided by the embodiments of the present invention are significantly smaller in size, so the wafer area occupied is reduced, thereby reducing the size of the cutting path, thereby increasing the area left for the chip area on the wafer. Therefore, more chips can be placed on a wafer of the same size without changing the wafer size.

[0148] In an embodiment of the present invention, alignment marks required for different processes and different machines are integrated and placed on one exposure unit, that is, an alignment mark group compatible with the alignment of different machines and processes is provided, and its function is to form alignment marks on the first layer and / or the alignment layer, thereby providing a reference for the subsequent alignment of different machines and processes, thereby ensuring subsequent orderly exposure and improving product process efficiency.

[0149] Although some embodiments of the present invention have been described in this application document, it will be appreciated by those skilled in the art that these embodiments are merely shown as examples. Those skilled in the art may conceive of numerous variations, alternatives, and improvements under the teachings of the present invention without departing from the scope of the present invention. The appended claims are intended to define the scope of the present invention and thus cover methods and structures within the scope of these claims themselves and their equivalents.

Claims

1. A registration mark set, comprising: A first alignment mark, the first alignment mark is located on a cutting path of an exposure unit of the wafer, the first alignment mark includes a transverse positioning mark and a longitudinal positioning mark, The lateral positioning mark includes a first search unit and a first precise alignment unit. The longitudinal positioning mark includes a second searching unit and a second precise alignment unit.

2. The alignment mark set according to claim 1, characterized in that: The first searching unit includes three rows of first rectangular blocks, each row of first rectangular blocks includes a plurality of first rectangular blocks arranged in a transverse direction; The first precise alignment unit includes five columns of second rectangular blocks, and each column of second rectangular blocks includes a plurality of second rectangular blocks arranged in a longitudinal direction.

3. The alignment mark set according to claim 2, characterized in that: The first rectangular block has a horizontal length of 4 microns and a vertical width of 3 microns. The second rectangular block is a square with a side length of 4 microns.

4. The alignment mark set according to claim 3, characterized in that: The interval between adjacent first rectangular blocks in each row of first rectangular blocks is 3 microns, the horizontal length of each row of first rectangular blocks is 87 microns, and the vertical width is 4 microns. The first rectangular block in the second row is between the first rectangular block in the first row and the first rectangular block in the third row, the interval between the first rectangular block in the first row and the first rectangular block in the second row is 16 microns, and the interval between the first rectangular block in the second row and the first rectangular block in the third row is 22 microns. The interval between adjacent second rectangular blocks in each column of second rectangular blocks is 4 microns, the longitudinal width of each column of second rectangular blocks is 52 microns, the transverse length is 4 microns, and the interval between two adjacent columns of second rectangular blocks is 16 microns.

5. The alignment mark set according to claim 1, characterized in that: The first searching unit and the first precise alignment unit are arranged side by side in a transverse direction, and a clearance area is formed around the first searching unit and the first precise alignment unit.

6. The alignment mark set according to claim 5, characterized in that: The first search unit is adjacent to one side of the first precise alignment unit along one horizontal side, the interval between the first search unit and the first precise alignment unit is not less than 60 microns, the distance between the first search unit and the boundary of the clearance area along the other horizontal side is not less than 60 microns, the distance between the first precise alignment unit and the boundary of the clearance area along the other horizontal side is not less than 60 microns, the distance between the first search unit and the boundary of the clearance area along the two sides of the longitudinal direction is not less than 20 microns, and the distance between the first precise alignment unit and the boundary of the clearance area along the two sides of the longitudinal direction is not less than 19 microns.

7. The alignment mark set according to any one of claims 1 to 6, characterized in that: The transverse positioning mark is rotated 90 degrees to become the longitudinal positioning mark.

8. The alignment mark set according to claim 1, wherein: The transverse positioning mark is located in the transverse cutting path of the exposure unit, and the longitudinal positioning mark is located in the longitudinal cutting path of the exposure unit. The clearance area of ​​the transverse positioning mark and the clearance area of ​​the longitudinal positioning mark do not overlap each other.

9. The alignment mark set according to claim 1, further comprising: A second alignment mark, the second alignment mark is located on a cutting path of an exposure unit of the wafer, and the second alignment mark includes a rectangular mark and a cross mark; and / or A plurality of third alignment marks are provided, wherein the third alignment marks are located on a cutting path or a chip area of ​​an exposure unit of the wafer.

10. The alignment mark set according to claim 9, characterized in that: The rectangular mark is a square with a length of 40 microns and a width of 40 microns. The cross mark includes vertical and horizontal lines that cross each other vertically, and the length of the horizontal and vertical lines is 40 micrometers and the width is 10 micrometers.

11. The alignment mark set according to claim 9, characterized in that: The second alignment mark has a clearance area around it, and the clearance area of ​​the second alignment mark does not overlap with the clearance areas of other alignment marks.

12. The alignment mark set according to claim 11, wherein: One side of the rectangular mark along the horizontal direction is adjacent to one side of the cross mark, the interval between the rectangular mark and the cross mark is not less than 60 microns, the distance between the other side of the rectangular mark and the boundary of the clearance area along the horizontal direction is not less than 60 microns, the distance between the other side of the cross mark and the boundary of the clearance area along the horizontal direction is not less than 60 microns, the distance between the two sides of the rectangular mark and the boundary of the clearance area along the longitudinal direction is not less than 25 microns, and the distance between the two sides of the cross mark and the boundary of the clearance area along the longitudinal direction is not less than 25 microns.

13. The alignment mark set according to claim 9, characterized in that: The third alignment mark is a square mark with a side length of 30 micrometers.

14. The alignment mark set according to claim 13, characterized in that: The third alignment mark is surrounded by a clearance area, the clearance area of ​​the third alignment mark does not overlap with the clearance areas of other alignment marks, and the distance between the third alignment mark and the clearance area boundary in the horizontal and vertical directions is not less than 30 microns.

15. The alignment mark set according to claim 9, characterized in that: The plurality of third alignment marks are dispersedly arranged at four corners of the exposure unit.

16. The alignment mark set according to claim 1, further comprising: A plurality of fourth alignment marks are provided, wherein the fourth alignment marks are located on a chip region of an exposure unit of the wafer.

17. The alignment mark set according to claim 16, wherein: Each chip area of ​​the exposure unit is provided with a fourth alignment mark.

18. The alignment mark set according to claim 16, wherein: The fourth alignment mark includes a plurality of squares arranged in an array.

19. The alignment mark set according to claim 16, wherein: The fourth alignment mark includes four blocks arranged in a 2*2 matrix, each block is a square with a side length of 45 microns, the interval between two blocks in the first row is 30 microns, the interval between two blocks in the second row is 30 microns, the interval between two blocks in the first column is 30 microns, and the interval between two blocks in the second column is 30 microns.

20. The alignment mark set according to claim 16, wherein: No simple graphics can exist within a range of 500 micrometers around the fourth alignment mark.

21. The alignment mark set according to claim 16, wherein: The distance between the fourth alignment mark and the edge of the wafer should be greater than 3 mm.

22. The alignment mark set according to claim 1, characterized in that: The alignment mark group is visible on the wafer surface.

23. The alignment mark set according to claim 1, characterized in that: The alignment mark group is located on the second top layer of the wafer and buried under the transparent medium.

24. A wafer, comprising one or more exposure units, wherein the exposure units have the alignment mark group according to any one of claims 1 to 23.

25. The wafer according to claim 24, wherein: The exposure unit includes a plurality of micro-LED chips, and the micro-LED chips are separated by cutting lines. The micro-LED chip includes a plurality of micro-LED pixels arranged in an array, and each micro-LED pixel includes a micro-LED.

26. The wafer according to claim 25, characterized in that The micro-LED includes a pixel driving backplane; A lower electrode layer located on the pixel driving backplane and electrically connected to the pixel driving backplane; A semiconductor light-emitting table, located on the lower electrode layer, emitting light; The upper electrode layer is in contact with the top of the semiconductor light-emitting mesa.

27. The wafer according to claim 26, wherein: The semiconductor light-emitting mesa includes a first type epitaxial layer, a light-emitting layer, and a second type epitaxial layer. The first type epitaxial layer is a semiconductor material with a first conductivity type and includes multiple semiconductor layers. The second type epitaxial layer is a semiconductor material with a second conductivity type and includes multiple semiconductor layers.

28. The wafer according to claim 27, wherein: The light-emitting layer is a quantum well light-emitting layer.

29. The wafer according to claim 26, wherein: The first to fourth alignment marks are located on the substrate of the pixel driving backplane or on the substrate of the semiconductor light emitting mesa.

30. The wafer according to claim 29, wherein: The semiconductor light-emitting table is a platform with an inverted trapezoidal cross-section. The semiconductor light-emitting table is bonded to the pixel driving backplane through a hybrid bonding process. The fourth alignment mark is located on one of the substrates of the pixel driving backplane or the semiconductor light-emitting table. The other of the substrates of the pixel driving backplane or the semiconductor light-emitting table has a pattern matching the fourth alignment mark. After the semiconductor light-emitting table and the pixel driving backplane complete the hybrid bonding process, the fourth alignment mark overlaps with the pattern.

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