Transient enhanced double-loop LDO (Low Dropout Regulator) based on flip voltage follower

Abstract

The transient enhancement type double-loop LDO linear voltage regulator comprises a reference current source, a bias circuit, an error amplifier, a transient enhancement circuit, a flip voltage follower circuit and a compensation capacitor, the positive input end of the error amplifier is connected with reference voltage # imgabs0 #, the negative input end of the error amplifier is connected with the output end # imgabs1 # of the whole circuit, and the transient enhancement circuit is connected with the flip voltage follower circuit. The output of the error amplifier is connected to the grid electrode of the induction tube PM2. The transient enhancement circuit is composed of an NM2-3 and a PM4, the grid electrode of the NM2-3 is connected to the drain electrode of the induction tube PM2, and the PM4 is in diode connection and provides bias for the PM3. The error amplifier and the PM2 tube form a slow loop of the whole circuit, and the precision of the output voltage # imgabs2 under various PVT conditions is improved. The fast loop is composed of a power tube PM1, induction tubes PM2, NM1 and PM3 and a transient enhancement circuit, and the fast loop is mainly used for improving the current utilization rate of the whole circuit and improving the transient response speed. According to the invention, the transient response speed and the loop gain are improved under the conditions of low voltage and low power consumption, so that the overall output precision is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a transient enhanced dual-loop LDO linear regulator based on a flip voltage follower. Background Art

[0002] Low dropout linear regulator (LDO) is an important component of current power management modules. For portable electronic devices, power efficiency is a key requirement to extend battery life, and the power supply voltage is getting lower and lower. Therefore, low quiescent current and low voltage drop are essential for power management modules.

[0003] Traditional LDO circuits usually have a high-gain error amplifier and a large output capacitor, so that its main stage point is located at the output node to improve the stability of the overall circuit. However, for the requirements of low voltage, low power consumption and portability, low voltage cannot meet high loop gain, low power consumption cannot meet fast response, and large output capacitors consume huge area, which is undoubtedly catastrophic for portable devices. Therefore, in order to comply with the development trend of circuits, low-power LDO with no load capacitor has become a hot research topic in the field of analog integrated circuits.

[0004] Compared with traditional LDO, the LDO based on flip follower has a fast response speed and can have a better response speed while consuming less current. Therefore, this article is based on the basic structure of flip follower LDO to further improve the overall transient response speed, loop gain and stability. Summary of the invention

[0005] In order to address the deficiencies of the prior art, the present invention provides a transient enhanced dual-loop LDO linear regulator based on a flip voltage follower, which can further improve the transient response speed, accuracy and stability.

[0006] The present invention adopts the following technical solution: The present invention provides a transient enhanced dual-loop LDO linear regulator based on a flip voltage follower, comprising a reference current source, a bias circuit, an error amplifier, a transient enhancement circuit, a flip voltage follower circuit and a compensation capacitor, wherein the positive input terminal of the error amplifier is connected to a reference voltage , the negative input is connected to the output terminal of the entire circuit , the error amplifier output is connected to the gate of the sensing tube PM2, the transient enhancement circuit is composed of NM2~3 and PM4, the gate of NM2~3 is connected to the drain of the sensing tube PM2, PM4 is a diode connection, providing bias for PM3, the error amplifier and PM2 tube form a slow loop of the entire circuit, increasing the output voltage To ensure accuracy under various PVT conditions, the fast loop is composed of power tube PM1, induction tubes PM2, NM1, PM3 and transient enhancement circuit, which mainly improves the current utilization of the entire circuit and increases the transient response speed.

[0007] The slow loop stabilizes the output voltage, and under PVT changes, further consolidates the stability of the fast loop under low power current. The proposed transient enhancement circuit effectively distributes the current of the fast loop under low current conditions, thereby improving the slew rate during charging and discharging. Moreover, the proposed transient enhanced dual-loop LDO linear regulator based on a flip voltage follower has a simple structure, does not have a complex detection circuit, and can operate without load capacitance, thereby saving area and facilitating on-chip integration.

[0008] For any details not provided in the present invention, please refer to the prior art.

[0009] The beneficial effects of the present invention are: 1. The present invention can respond more quickly when the output current changes, and optimize the overshoot voltage or undershoot voltage; 2. The present invention can improve the loop gain of the fast loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings in the specification, which constitute a part of the present application, are used to provide further understanding of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0011] Figure 1 This is the basic structure diagram of the simulated LDO of the present invention.

[0012] Figure 2 This is the transient enhancement circuit of the present invention.

[0013] Figure 3 This is a circuit diagram of the error amplifier in the present invention.

[0014] Figure 4 This is a circuit diagram of a reference current source in the present invention.

[0015] Figures 5 and 6 A graph showing the fast-loop phase margin versus load current test results using a transient enhancement circuit.

[0016] Figure 7 Transient response simulation test results with and without transient enhancement circuit. DETAILED DESCRIPTION

[0017] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of the present invention are clearly and completely described below in conjunction with the drawings in the implementation of this specification, but are not limited to this. Anything not fully described in the present invention shall be based on the conventional technology in the art. Example 1

[0018] The present invention proposes a transient enhanced dual-loop LDO linear regulator based on a flip voltage follower, see Figure 1 , Figure 1 The invention provides a basic structural diagram of a transient enhanced dual-loop LDO linear regulator based on a flip voltage follower, including a reference current source, a bias circuit, an error amplifier, a transient enhancement circuit, a flip voltage follower circuit and a compensation capacitor.

[0019] The positive input of the error amplifier is connected to the reference voltage , the negative input is connected to the output terminal of the entire circuit , the error amplifier output is connected to the gate of the sensing tube PM2, and the error amplifier and PM2 tube form a slow loop of the entire circuit, such as Figure 1 As shown in loop2, the fast loop is composed of power tube PM1, induction tube PM2, NM1, PM3 and transient enhancement circuit. Figure 2 As shown in loop1.

[0020] When the load current switches from light load to heavy load in a short period of time, due to the delay in the loop, a large output current cannot be quickly provided to the output, which will cause the output voltage to drop. When the voltage drops, the gate-source voltage of the induction tube PM2 decreases, and the drain voltage of PM2 also decreases, which is equivalent to It is synchronized with the drain voltage generated by the PM2 tube, so that the gate-source voltage of NM1 increases, causing the current of the capacitor of the PM1 source to flow out, so that the gate voltage of PM1 decreases.

[0021] In the working state of the transient enhancement circuit, when the gate-source voltage of NM1 increases, the gate-source voltage of NM2~3 decreases, resulting in a decrease in the current of the branch of PM4 and NM2~3, thereby reducing the current of the PM3 current source, thereby further accelerating the release of the current of the PM1 gate capacitance and improving the transient response.

[0022] When the load current switches from light load to heavy load in a short period of time, the output current cannot be reduced quickly due to the delay in the loop, which causes the output voltage to rise. When the voltage rises, the gate-source voltage of the induction tube PM2 increases, and the drain voltage of PM2 also increases, which is equivalent to It is synchronized with the drain voltage generated by the PM2 tube, so the gate-source voltage of NM1 decreases, so the current passing through NM1 decreases. Assuming that the entire current source current remains unchanged, the current flows into the capacitor of the PM1 gate, causing the gate voltage of PM1 to rise.

[0023] The working state of the transient enhancement circuit, when the gate-source voltage of NM1 decreases, the gate-source voltage of NM2~3 increases, resulting in an increase in the current of the branch of PM4 and NM2~3, thereby increasing the current of the PM3 current source, further accelerating the current flow into the gate capacitance of PM1 and improving the transient response. Figure 7 The transient response diagrams with and without the transient enhancement circuit are shown below. Figure 7 The figure shows the output voltage transient diagram when the output current is converted from 100μA to 50mA within 1μs and from 50mA to 100μA within 1μs. It can be seen that when the output voltage is converted from 50mA to 100μA within 1μs, the overshoot voltage is significantly improved, and when it is converted from 100μA to 50mA within 1μs, the undershoot voltage is slightly improved. Example 2

[0024] The present invention proposes a transient enhanced dual-loop LDO linear regulator based on a flip voltage follower. Based on Example 1, since the output voltage The induction tube will produce a voltage that is different from the output voltage. The induced voltage leads to the circuit, the loop is disconnected from the induced voltage, and the small signal is analyzed.

[0025] From the perspective of the NM1 and PM3 branches, they belong to the common gate amplifier, and the source of NM1 belongs to the input ,PM1 gate belongs to output ,but: However, from the perspective of the transient enhancement circuit, this branch belongs to a common source amplifier, and the gate input of NM2~3 is , the gate of PM1 belongs to the output ,but: So overall, for the fast loop, the loop gain of the overall fast loop is improved, such as Figures 5 and 6 As shown in the figure, the loop gain diagram and phase diagram of the fast loop when the load current is 100μA and 50mA. It can be seen that the low-frequency gain is more than 100dB and the phase margin is greater than 45°. When the power supply voltage is low, the loop gain is significantly improved. Example 3

[0026] The present invention proposes a transient enhanced dual-loop LDO linear regulator based on a flip voltage follower. Under the condition of ground static current, the loop will change the threshold voltage of the MOS tube under different PVT conditions, which will cause the working voltage of the output voltage to fluctuate. Therefore, a slow loop is used to stabilize the output voltage to be equal to the reference voltage. .

[0027] The slow loop has little effect on transient response, so the power consumption is very small, so there is no need to consider the relationship between low power consumption and transient response.

[0028] The above content is a further detailed description of the present invention in combination with specific preferred implementation modes. It cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as belonging to the protection scope of the present invention.

Claims

1. A transient enhanced dual-loop LDO linear regulator based on a flip voltage follower, characterized in that: Reference current source, bias circuit, error amplifier, transient enhancement circuit, flip voltage follower circuit and compensation capacitor. In the absence of output capacitor, the output voltage is stable.

2. The transient enhanced dual-loop LDO linear regulator based on a flip voltage follower according to claim 1, characterized in that: The error amplifier specifically includes a current source Ibias2, an output pair of transistors PM6, PM5, a diode-connected NM5, and a current source-connected NM4.

3. The transient enhanced dual-loop LDO linear regulator based on flip voltage follower according to claim 1, characterized in that: The bias circuit specifically includes PMOS tubes PM7-PM14, NMOS tubes NM6-NM8 and a resistor R2.

4. The transient enhanced dual-loop LDO linear regulator based on a flip voltage follower according to claim 1, characterized in that: The fast loop based on the flip voltage follower specifically includes an output power tube PM1, an induction tube PM2, and common gate input tubes NM1 and PM3.

5. The transient enhanced dual-loop LDO linear regulator based on flip voltage follower according to claim 1, characterized in that: The transient enhancement circuit specifically includes output tubes NM2~3. The output tubes NM2~3 are stacked into a composite tube to improve the gain of the overall loop. In order to improve the transient response speed, the output tubes NM2~3 all use thin gate oxide tubes. The stacked composite tubes can withstand higher voltages, making the entire circuit more reliable.

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