Linear voltage stabilizing circuit for broadband high power supply noise suppression

Abstract

The invention provides a broadband high power supply noise suppression linear voltage stabilizing circuit. The broadband high power supply noise suppression linear voltage stabilizing circuit comprises a band-gap reference voltage source, a charge pump, an error amplifier, a summation module, a sectional FFRC compensation module, a buffer, an N-type power tube MN and a resistance feedback network. The band-gap reference voltage source is used for generating reference voltage; the charge pump is used for carrying out voltage conversion and supplying power to corresponding modules; the error amplifier is used for comparing the reference voltage with the sampling voltage output by the resistance feedback network, amplifying a comparison result and outputting the comparison result to the summation module; the sectional FFRC compensation module is used for generating compensation voltage according to the change condition of the load current and outputting the compensation voltage to the summation module; the summation module is used for combining the compensation voltage and the amplified comparison result; the buffer is used for driving the N-type power tube MN so that the N-type power tube MN can restrain power supply noise transmitted into the linear voltage stabilizing circuit according to the compensation voltage, and therefore the power supply noise can be restrained in a self-adaptive mode according to the change condition of the load current.

Description

Technical Field

[0001] The invention relates to the technical field of electronic circuits, and in particular to a linear voltage stabilizing circuit with wide-band and high power supply noise suppression. Background Art

[0002] With the rapid development of the Internet of Things, smart wearable devices and various sensors, these smart devices have been widely used in people's daily lives. In order to make these devices work normally and stably, the requirements for power management units are becoming increasingly stringent. An important component of the power management chip is the low dropout regulator (LDO) circuit. LDO is usually connected after the DC-DC switching regulator to reduce the power ripple and provide a clean voltage source for noise-sensitive modules. The advantages of LDO are low circuit complexity, low power consumption, small output noise and power ripple, fast transient response, stability, and low cost. In recent years, the demand for integrating the entire power management system into a single system-on-chip (SOC) solution has continued to increase, and the operating frequency of the switching regulator is increasing to allow a higher level of integration. This trend will increase the frequency of the output ripple, and some modules that are sensitive to power ripple, such as high-speed and high-precision digital-to-analog converters, radio frequency circuits, phase-locked loops, etc., require a low-noise and low-ripple power supply voltage. The operating frequency of traditional DC-DC switching regulators is low, and traditional LDOs can handle ripples in a lower frequency range, so that the power supply circuit is not disturbed by the power ripple as much as possible. However, as the operating frequency of DC-DC switching regulators becomes higher and higher, the traditional LDO connected behind it cannot guarantee that noise-sensitive modules will not be affected by the noise of the DC-DC switching regulator. Therefore, it is very meaningful to design a linear regulator with high power supply noise suppression.

[0003] At present, the Feed-Forward Ripple Cancellation (FFRC) technology is commonly used to eliminate power supply noise. FFRC technology is to establish an additional feed-forward path between the power supply and the control end of the power tube in addition to the original feedback path, so that the power supply ripple appears at the control end of the power tube with appropriate gain. The feedback path must first detect the change in output voltage and then feedback and adjust; while the feed-forward path does not need to detect the output, but directly detects the input change. Therefore, compared with the feedback path, the feed-forward path adjusts the power tube faster, thereby improving the power supply noise suppression ability of the LDO.

[0004] However, the effectiveness of FFRC technology depends largely on the gain of the feedforward path. Generally, the feedforward gain of FFRC technology is a fixed value, and the compensation value is not dynamically adjusted according to the working state of the circuit. It can only improve the power supply ripple rejection ratio (PSRR) within a very limited range of variation, such as the limited load current range of 1-25mA. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention adopts an NMOS tube as a power tube and adopts an FFEC compensation structure, and provides a linear voltage stabilization circuit with wide-band and high power supply noise suppression, specifically comprising:

[0006] The present invention provides a linear voltage stabilization circuit with wide-bandwidth and high power supply noise suppression, comprising:

[0007] Bandgap reference voltage source, charge pump, error amplifier, summing module, segmented FFRC compensation module, buffer, N-type power tube MN, resistor feedback network;

[0008] The first terminal of the bandgap reference voltage source is used to receive an external voltage V in , the second end of the bandgap reference voltage source is connected to the non-inverting input end of the error amplifier and the third end of the segmented FFRC compensation module respectively;

[0009] The first terminal of the segmented FFRC compensation module is used to receive an external voltage V in , the second end is used to receive the voltage V cp , the fourth end is connected to the first end of the summing module;

[0010] The second end of the summing module is connected to the output end of the error amplifier, the third end is connected to the second end of the buffer, and the fourth end is used to receive the voltage V cp ;

[0011] The first terminal of the buffer is used to receive an external voltage V through a charge pump. in The third end is connected to the fifth end of the segmented FFRC compensation module and the gate of the N-type power tube MN. The charge pump is used to convert the external voltage V in Converted to voltage V cp ;

[0012] The drain of the N-type power tube MN is used to connect the external voltage V in ;

[0013] The source of the N-type power tube MN is the output end of the linear voltage regulator circuit with wide-band and high power supply noise suppression, and is respectively connected to the first end of the resistor feedback network and the sixth end of the segmented FFRC compensation module;

[0014] The second end of the resistor feedback network is connected to the inverting input terminal of the error amplifier, and the third end is connected to the ground signal;

[0015] The first terminal of the segmented FFRC compensation module is used to receive an external voltage V in , the second end is used to receive the voltage V cp ;

[0016] The power supply terminal of the error amplifier is used to receive the voltage V cp ;

[0017] Bandgap reference voltage source, used to generate reference voltage V REF ;

[0018] The error amplifier is used to compare the reference voltage V REF The sampled voltage output by the resistor feedback network is amplified and output to the summing module;

[0019] A segmented FFRC compensation module is used to generate a compensation voltage according to a change in the load current of a linear voltage regulator circuit with wide-band high power supply noise suppression, and output the compensation voltage to a summing module;

[0020] A summing module, used for combining the compensation voltage and the amplified comparison result, integrating the DC voltage and the AC voltage, and outputting the integrated result to the buffer;

[0021] Buffer, used to drive N-type power tube MN, stabilize the output voltage of high power supply noise suppression linear voltage regulator circuit;

[0022] The N-type power tube MN is used to convert the gate terminal voltage into a large current and output a stable voltage value. According to the compensation voltage, the incoming high power supply noise is suppressed to suppress the power supply noise of the linear voltage regulator circuit.

[0023] Beneficial effects of the present invention:

[0024] The linear voltage stabilizing circuit with wide-band and high power supply noise suppression provided by the present invention comprises: a bandgap reference voltage source, a charge pump, an error amplifier, a summing module, a segmented FFRC compensation module, a buffer, an N-type power tube MN, and a resistor feedback network; the bandgap reference voltage source is used to generate a reference voltage V REF ; Charge pump, used to convert external voltage V in The value is converted to voltage V cp ; Error amplifier, used to compare the reference voltage V REFand the sampling voltage output by the resistor feedback network, and amplifies the comparison result and outputs it to the summing module; a segmented FFRC compensation module is used to generate a compensation voltage according to the change of the load current of the linear voltage regulator circuit with wide-band high power supply noise suppression, and outputs the compensation voltage to the summing module; the summing module is used to combine the compensation voltage and the amplified comparison result, integrate the DC voltage and the AC voltage, and output the integration result to the buffer; the buffer is used to drive the N-type power tube MN to stabilize the output voltage of the high power supply noise suppression linear voltage regulator circuit; the N-type power tube MN is used to convert the gate terminal voltage into a large current and output a stable voltage value, and suppress the power supply noise of the high power supply noise suppression linear voltage regulator circuit according to the compensation voltage, so that the compensation voltage can be generated according to the change of the load current, and the power supply noise can be adaptively suppressed based on the compensation voltage.

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the structure of a linear voltage stabilization circuit with wide-bandwidth and high power supply noise suppression provided by the present invention;

[0027] Figure 2 A schematic diagram of a compensation principle provided by the present invention;

[0028] Figure 3 The present invention provides a method for obtaining a ds / g m Graph of

[0029] Figure 4 The present invention provides a g ds / g m Schematic diagram of quantization values ​​at different load intervals;

[0030] Figure 5 A schematic diagram of the structure of a current comparator provided by the present invention;

[0031] Figure 6 A schematic diagram of an experimental result provided by the present invention;

[0032] Figure 7 Another schematic diagram of experimental results provided by the present invention;

[0033] Figure 8 A schematic diagram of another experimental result provided by the present invention;

[0034] Fig. 9 The present invention provides another schematic diagram of experimental results. DETAILED DESCRIPTION

[0035] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0036] In order to solve the problems existing in the prior art, the present invention provides a linear voltage regulator circuit with wide-band and high power supply noise suppression, which controls the size of the compensated ripple according to the load current, that is, as the load current range changes, the size of the compensation ripple injected into the gate end of the power tube is adaptively changed, so that the compensation current generated by it and the noise current transmitted by the power supply noise to the LDO output end are offset, so that the LDO has a relatively high power supply noise suppression capability within the entire load range.

[0037] Figure 1 A schematic diagram of a linear voltage stabilization circuit with wide-bandwidth and high power supply noise suppression provided by the present invention is shown in FIG. Figure 1 As shown, the linear voltage regulator circuit 100 with wide-bandwidth and high power supply noise suppression includes:

[0038] A bandgap reference voltage source 10 , a charge pump 20 , an error amplifier 30 , a summing module 40 , a segmented FFRC compensation module 50 , a buffer 60 , an N-type power transistor MN and a resistor feedback network 70 .

[0039] The first terminal of the bandgap reference voltage source 10 is used to receive an external voltage V in The second end of the bandgap reference voltage source 10 is connected to the non-inverting input end of the error amplifier 30 and the third end of the segmented FFRC compensation module 50 respectively.

[0040] The first terminal of the segmented FFRC compensation module 50 is used to receive an external voltage V in , the second end is used to receive the voltage V cp , the fourth end is connected to the first end of the summing module.

[0041] The second end of the summing module 40 is connected to the output end of the error amplifier 30, the third end is connected to the second end of the buffer 60, and the fourth end is used to receive the voltage V cp .

[0042] The first terminal of the buffer 60 is used to receive an external voltage V in , and the third end is respectively connected to the fifth end of the segmented FFRC compensation module 50 and the gate of the N-type power tube MN.

[0043] The charge pump 20 is used to convert the external voltage V in Converted to voltage V cp , providing a voltage higher than V for the N-type power tube MN in High gate voltage and power modules such as error amplifier and summing amplifier.

[0044] The drain of the N-type power tube MN is used to connect the external voltage Vin .

[0045] The source of the N-type power transistor MN is the output end of the linear voltage regulator circuit 100 with wide-bandwidth and high power supply noise suppression, and is respectively connected to the first end of the resistor feedback network 70 and the sixth end of the segmented FFRC compensation module 50 .

[0046] A second terminal of the resistor feedback network 70 is connected to the inverting input terminal of the error amplifier 30 , and a third terminal thereof is connected to the ground signal.

[0047] The first terminal of the segmented FFRC compensation module 50 is used to receive an external voltage V in , the second end is used to receive the voltage V cp .

[0048] The power supply terminal of the error amplifier 30 is used to receive the voltage V cp .

[0049] A bandgap reference voltage source 10 is used to generate a reference voltage V REF .

[0050] The error amplifier 30 is used to compare the reference voltage V REF The comparison result is amplified and then output to the summing module 40 .

[0051] The segmented FFRC compensation module 50 is used to generate a compensation voltage according to the change of the load current of the linear voltage regulator circuit 100 with wide-band and high power supply noise suppression, and output the compensation voltage to the summing module 40 .

[0052] The summing module 40 is used to combine the compensation voltage and the amplified comparison result, integrate the DC voltage and the AC voltage, and output the integration result to the buffer 60 .

[0053] The buffer 60 is used to drive the N-type power tube MN to stabilize the output voltage of the high power supply noise suppression linear voltage regulator circuit.

[0054] The N-type power tube MN is used to convert the gate terminal voltage into a large current and output a stable voltage value. According to the compensation voltage, the incoming high power supply noise is suppressed to suppress the power supply noise of the linear voltage regulator circuit.

[0055] In the circuit provided by the present invention, an NMOS tube is used as a power tube and an FFEC compensation structure is used. The segmented FFRC compensation module 50 generates a compensation voltage according to the change of the load current of the linear voltage regulator circuit 100 with wide-band high power supply noise suppression, and outputs the compensation voltage to the summing module 40. The compensation voltage is integrated with the output end of the error amplifier 30 through the summing amplifier SUM, and is injected into the gate end of the N-type power tube MN after passing through the buffer 60. The transconductance g of the power tubem It is converted into a compensation current at the output end of a linear voltage regulator circuit with wide-bandwidth and high power supply noise suppression, and the power supply noise passes through the power tube internal resistance of 1g ds The noise current coupled to the output end of the linear voltage regulator circuit with wide-band high power supply noise suppression is offset, thereby avoiding the interference of power supply noise on the output voltage of the power tube, so that the linear voltage regulator circuit with wide-band high power supply noise suppression has a higher power supply noise suppression capability.

[0056] In one possible implementation, Figure 1 As shown, the segmented FFRC compensation module 50 includes:

[0057] Amplifier FA, PMOS tube P1, PMOS tube P2, PMOS tube P3, NMOS tube N1, NMOS tube N2, resistor R B and a resistance adaptive adjustment unit 501 .

[0058] Resistor R B The first end of the PMOS tube P2 and the source of the PMOS tube P3 are used to receive the external voltage V in .

[0059] The power supply terminal of the amplifier FA is used to receive the voltage V cp , the inverting input terminal and the resistor R B The non-inverting input terminal is used to receive the reference voltage V output by the bandgap reference voltage source 10. REF Specifically, the voltage V cp The voltage provided by the charge pump. Specifically, the clamping effect of the amplifier FA causes the resistor R B The second end of the ground signal, power supply noise v in Through the resistor R B Converted to noise compensation current v in R B , where R B is the resistance R B resistance value.

[0060] The drain of the NMOS tube N1 is connected to the drain of the PMOS tube P1, the gate of the NMOS tube N1 and the gate of the NMOS tube N2 respectively.

[0061] The gate of the PMOS transistor P2 is connected to the drain of the PMOS transistor P2 and the gate of the PMOS transistor P3 respectively.

[0062] The drain of the NMOS tube N2 is connected to the drain of the PMOS tube P2.

[0063] The source of the NMOS transistor N2, the source of the NMOS transistor N1, and the fifth terminal and the sixth terminal of the resistance adaptive adjustment unit 501 are all connected to the ground signal.

[0064] The first end of the resistance adaptive adjustment unit 501 is connected to the drain of the PMOS tube P3, and the second end is used to receive the external voltage V in The third end is connected to the gate of the N-type power tube MN, and the fourth end is connected to the source of the N-type power tube MN.

[0065] The resistance adaptive adjustment unit 501 is used to adjust its own resistance according to the change of the load current of the linear voltage regulator circuit 100 with wide-band and high power supply noise suppression, so that the segmented FFRC compensation module can adaptively adjust the magnitude of the output compensation voltage.

[0066] The principle of FFRC compensation is explained below. The compensation voltage generation model is shown in Figure 2 . Figure 2 Only some modules closely related to the FFRC compensation principle are shown, including the bandgap reference voltage source (BGR), charge pump (Charge Pump), error amplifier (EA), segmented FFRC compensation module and summing module together constitute the auxiliary module (AUX), and N-type power tube MN. The compensation voltage v generated by the auxiliary module AUX Injected into the gate terminal of the N-type power tube MN, the transconductance g m It is converted into a compensation current at the output of a linear voltage regulator circuit with wide-bandwidth and high power supply noise suppression, which is consistent with the power supply noise v in Through N-type power tube MN internal resistance 1g ds The noise current coupled to the output of the linear voltage regulator circuit with wide-bandwidth high power supply noise suppression is offset. It can be expressed as:

[0067] Δi=g m ·v AUX +g ds ·v in ≈0.

[0068] Therefore, the compensation voltage v AUX The value of should be:

[0069]

[0070] Under different processes and loads, The values ​​are different, see Figure 3 The embodiment of the present invention controls v by connecting different resistance values. AUX By distinguishing different load intervals, see Figure 4 , in each interval, The quantized value of can further improve the feasibility of the circuit.

[0071] like Figure 1 As shown in the figure, the power tube uses an N-type power tube MN. The N-type power tube MN adopts a common drain connection method. The impedance seen from the power supply through the drain end of the N tube is very large, so it has better power supply noise suppression capability than the P tube. For ease of understanding, Figure 1 Also shown is the load capacitance C L and load R L .

[0072] Further, optional, such as Figure 1 As shown, the resistance adaptive adjustment unit 501 includes:

[0073] NMOS tube N3, NMOS tube N4, NMOS tube N5, NMOS tube N6, resistor R T1 , resistor R T2 , resistor R T3 and resistor R T4 , and a first current comparator 5011 , a second current comparator 5012 , a third current comparator 5013 and a fourth current comparator 5014 .

[0074] The drain connection resistance R of NMOS tube N3 T1 The gate is connected to the output end of the first current comparator 5011, and the source is connected to the resistor R T1 The second end of the resistor R T2 and the drain of the NMOS tube N4.

[0075] The gate of the NMOS tube N4 is connected to the output end of the second current comparator 5012, and the source is connected to the resistor R T2 The second end of the resistor R T3 and the drain of the NMOS tube N5.

[0076] The gate of the NMOS tube N5 is connected to the output end of the third current comparator 5013, and the source is connected to the resistor R T3 The second end of the resistor R T4 and the drain of the NMOS tube N6.

[0077] The gate of the NMOS tube N6 is connected to the output end of the fourth current comparator 5014, and the source is connected to the resistor R T4 The second end and ground signal.

[0078] The first input terminal of the first current comparator 5011, the first input terminal of the second current comparator 5012, the first input terminal of the third current comparator 5013 and the first input terminal of the fourth current comparator 5014 are all used to receive an external voltage V in .

[0079] The second input terminal of the first current comparator 5011 , the second input terminal of the second current comparator 5012 , the second input terminal of the third current comparator 5013 , and the second input terminal of the fourth current comparator 5014 are all connected to the gate of the N-type power transistor MN.

[0080] The third input terminal of the first current comparator 5011 , the third input terminal of the second current comparator 5012 , the third input terminal of the third current comparator 5013 and the third input terminal of the fourth current comparator 5014 are all connected to the source of the N-type power transistor MN.

[0081] Each current comparator is used to control the switch state of the corresponding NMOS tube according to the load current of the linear voltage regulator circuit 100 with wide-band and high power supply noise suppression, so as to adjust the resistance of the resistance adaptive adjustment unit 501 .

[0082] Furthermore, the circuit structures of the current comparators are the same, but the parameters of the components are different, and it is optional, such as Figure 5 As shown, each current comparator includes:

[0083] NMOS tube N1-1, NMOS tube N2-1, NMOS tube N3-1, NMOS tube N4-1, PMOS tube P1-1, amplifier SA1, Schmitt trigger U1 and inverter U2, wherein the parameters of the PMOS tubes in each current comparator are different.

[0084] The drain of the NMOS tube N1-1 and the source of the PMOS tube P1-1 are both used to receive an external voltage V in , the NMOS tube N1-1 is a replica of the N-type power tube MN. Exemplarily, the replica ratio is 1 / 1000.

[0085] The gate of the NMOS tube N1 - 1 is connected to the gate of the N-type power tube MN, and the source is connected to the in-phase input terminal of the amplifier SA1 and the drain of the NMOS tube N2 - 1 respectively.

[0086] The inverting input terminal of the amplifier SA1 is connected to the source of the N-type power transistor MN, and the output terminal is connected to the gate of the NMOS transistor N2-1.

[0087] The source of the NMOS transistor N2 - 1 is respectively connected to the drain and gate of the NMOS transistor N3 - 1 and the gate of the NMOS transistor N4 - 1 .

[0088] The source of the NMOS transistor N3 - 1 and the source of the NMOS transistor N4 - 1 are both connected to the ground signal.

[0089] The gate of the PMOS transistor P1 - 1 is used to receive the first bias signal, and the drain is respectively connected to the drain of the NMOS transistor N4 - 1 and the input end of the Schmitt trigger U1 .

[0090] The output end of the Schmitt trigger U1 is connected to the input end of the inverter U2, and the output end of the inverter U2 is the output end of the current comparator.

[0091] Optionally, when the load current is less than 45mA, NMOS tube N3, NMOS tube N4, NMOS tube N5 and NMOS tube N6 are all turned on; when the load current is greater than or equal to 45mA and less than 66mA, NMOS tube N3 is turned off, and NMOS tube N4, NMOS tube N5 and NMOS tube N6 are all turned on; when the load current is greater than or equal to 66mA and less than 88mA, NMOS tube N3 and NMOS tube N4 are turned off, and NMOS tube N5 and NMOS tube N6 are turned on; when the load current is greater than or equal to 88mA and less than 100mA, NMOS tube N3, NMOS tube N4 and NMOS tube N5 are turned off, and NMOS tube N6 is turned on; when the load current is greater than or equal to 100mA, NMOS tube N3, NMOS tube N4, NMOS tube N5 and NMOS tube N6 are all turned off.

[0092] Specifically, the compensation voltage at the drain of the PMOS tube P3 (point S) is expressed as:

[0093] v s =ΣR Ti / R B ·v in ,

[0094] To make ΣR Ti / R B equal The quantized value of the current comparator. The size of the PMOS tube in each current comparator is different, and the fixed current generated by the PMOS tube is different. When the load current is greater than the fixed current value, the current comparator outputs a signal T i is low potential, otherwise it is high potential.

[0095] For example, the current generated by the corresponding replica tube is compared with four fixed currents of 45 μA, 66 μA, 88 μA and 100 μA, which is equivalent to comparing the load current with 45 mA, 66 mA, 88 mA and 100 mA. load When <45mA, the signals T1, T2, T3, and T4 output by the four current comparators are all high potential, the current at point S flows through the switch tube, and the four resistors are short-circuited. At this time, there is no compensation voltage. load When <66mA, T1 is at low potential, T2, T3, and T4 are at high potential, and the current flows through the resistor R T1 , compensation voltage v s =R T1 / R B ·v in When 66mA≤I loadWhen <88mA, T1 and T2 are at low potential, T3 and T4 are at high potential, and the current flows through the resistor R T1 , resistor R T2 , compensation voltage v s =(R T1 +R T2 ) / R B ·v in When 88mA≤I load When the current is less than 100mA, T1, T2, and T3 are at low potential, T4 is at high potential, and the current flows through the resistor R T1 , resistor R T2 , resistor R T3 , compensation voltage v s =(R T1 +R T2 +R T3 ) / R B ·v in . When I load When ≥100mA, T1, T2, T3, and T4 are all at low potential, and the current flows through the resistor R T1 , resistor R T2 , resistor R T3 , resistor R T4 , compensation voltage v s =(R T1 +R T2 +R T3 +R T4 ) / R B ·v in . R Ti Indicates the resistance value of resistor RTi (i=1,2,3,4).

[0096] This circuit controls the size of the compensated ripple through four current comparators and switch tubes, and performs compensation in sections according to the change of load current. That is, with the different load current ranges, the size of the compensated ripple injected into the gate end of the power tube changes adaptively, and the compensation current generated by it offsets the noise current transmitted by the power noise to the output end of the linear voltage regulator circuit with wide-band and high power noise suppression, so that the linear voltage regulator circuit with wide-band and high power noise suppression has a relatively high power noise suppression capability in the entire load range of 0-100mA.

[0097] Further, optional, such as Figure 1 As shown, the summing module 40 includes:

[0098] Resistor R BKB , capacitor C S1 , capacitor C S2 , summing amplifier SUM.

[0099] Resistor R BKB and capacitor CS2 After being connected in parallel, they are connected between the inverting input and output of the amplifier SUM.

[0100] The inverting input of the amplifier SUM is also connected through the capacitor C S1 Connect the segmented FFRC compensation module.

[0101] A non-inverting input terminal of the amplifier SUM is connected to the output terminal of the error amplifier.

[0102] Among them, the capacitor C S1 and capacitor C S2 Used to copy the AC signal in equal proportion to the inverting input terminal of the amplifier SUM.

[0103] Further, optional, such as Figure 1 As shown, the buffer 60 comprises:

[0104] NMOS tube N7, NMOS tube N8, PMOS tube P4 and PMOS tube P5.

[0105] The source of the PMOS tube P4 is used to receive the voltage V cp The gate is used to receive the second bias voltage, and the drain is respectively connected to the source of the PMOS tube P5, the drain of the NMOS tube N8, the gate of the N-type power tube MN and the fifth end of the segmented FFRC compensation module 50.

[0106] The gate of the PMOS transistor P5 is connected to the third terminal of the summing module, and the drain is respectively connected to the gate of the NMOS transistor N8 and the drain of the NMOS transistor N7.

[0107] The gate of the NMOS transistor N7 is used to receive the third bias voltage.

[0108] The source of the NMOS tube N7 and the source of the NMOS tube N8 are both connected to the ground signal.

[0109] Further, optional, such as Figure 1 As shown, the resistor feedback network 70 comprises:

[0110] Resistor R1 and resistor R2.

[0111] The first end of the resistor R1 is connected to the source of the N-type power transistor MN, and the second end is connected to the inverting input end of the error amplifier 20 and the first end of the resistor R2 respectively.

[0112] A second terminal of the resistor R2 is connected to the ground signal.

[0113] In order to further prove the beneficial effects of the present invention, the present invention also provides a set of experimental data. Figure 6 : is a PSRR curve diagram before and after the FFRC compensation technology provided by the embodiment of the present invention is adopted when the load current is 45mA; Figure 7 : is a PSRR curve diagram before and after the FFRC compensation technology provided by the embodiment of the present invention is adopted when the load current is 66mA; Figure 8 is a PSRR curve diagram before and after the FFRC compensation technology provided by the embodiment of the present invention is adopted when the load current is 88mA; Fig. 9 When the load current is 100mA, the PSRR curves before and after the FFRC compensation technology provided by the embodiment of the present invention are used. The yellow line in the figure is the PSRR curve without the FFRC compensation technology of the present invention, and the red line is the PSRR curve with the FFRC compensation technology of the present invention. It can be seen that within the frequency range of 0-500kHz, the present invention has an obvious compensation effect.

[0114] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0115] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A linear voltage regulator circuit with wide-bandwidth and high power supply noise suppression, characterized in that: include: Bandgap reference voltage source, charge pump, error amplifier, summing module, segmented FFRC compensation module, buffer, N-type power tube MN, resistor feedback network; The first terminal of the bandgap reference voltage source is used to receive an external voltage V in , the second end of the bandgap reference voltage source is respectively connected to the non-inverting input end of the error amplifier and the third end of the segmented FFRC compensation module; The first terminal of the segmented FFRC compensation module is used to receive the external voltage V in , the second end is used to receive the voltage V cp , the fourth end is connected to the first end of the summing module; The second end of the summing module is connected to the output end of the error amplifier, the third end is connected to the second end of the buffer, and the fourth end is used to receive the voltage V cp ; The first terminal of the buffer is used to receive the external voltage V through the charge pump. in The third end is respectively connected to the fifth end of the segmented FFRC compensation module and the gate of the N-type power tube MN, and the charge pump is used to convert the external voltage V in Converted to the voltage V cp ; The drain of the N-type power tube MN is used to connect the external voltage V in ; The source of the N-type power tube MN is the output end of the linear voltage regulator circuit with wide-bandwidth and high power supply noise suppression, and is respectively connected to the first end of the resistor feedback network and the sixth end of the segmented FFRC compensation module; The second end of the resistor feedback network is connected to the inverting input end of the error amplifier, and the third end is connected to the ground signal; The first terminal of the segmented FFRC compensation module is used to receive the external voltage V in , the second end is used to receive the voltage V cp ; The power supply terminal of the error amplifier is used to receive the voltage V cp ; The bandgap reference voltage source is used to generate a reference voltage V REF ; The error amplifier is used to compare the reference voltage V REF and the sampling voltage output by the resistor feedback network, and amplifying the comparison result and outputting it to the summing module; The segmented FFRC compensation module is used to generate a compensation voltage according to the change of the load current of the linear voltage regulator circuit with wide-band high power supply noise suppression, and output the compensation voltage to the summing module; The summing module is used to combine the compensation voltage and the amplified comparison result, integrate the DC voltage and the AC voltage, and output the integration result to the buffer; The buffer is used to drive the N-type power tube MN to stabilize the output voltage of the high power supply noise suppression linear voltage stabilization circuit; The N-type power tube MN is used to convert the gate terminal voltage into a large current and output a stable voltage value, and suppress the power supply noise transmitted to the high power supply noise suppression linear voltage stabilization circuit according to the compensation voltage.

2. The circuit according to claim 1, characterized in that The segmented FFRC compensation module comprises: Amplifier FA, PMOS tube P1, PMOS tube P2, PMOS tube P3, NMOS tube N1, NMOS tube N2, resistor R B and a resistance adaptive adjustment unit; The resistor R B The first end of the PMOS tube P2, the source of the PMOS tube P3 are all used to receive the external voltage V in ; The power supply terminal of the amplifier FA is used to receive the voltage V cp , the inverting input terminal and the resistor R B The non-inverting input terminal is used to receive the reference voltage V output by the bandgap reference voltage source. REF ; The drain of the NMOS tube N1 is respectively connected to the drain of the PMOS tube P1, the gate of the NMOS tube N1 and the gate of the NMOS tube N2; The gate of the PMOS tube P2 is connected to the drain of the PMOS tube P2 and the gate of the PMOS tube P3 respectively; The drain of the NMOS tube N2 is connected to the drain of the PMOS tube P2; The source of the NMOS tube N2, the source of the NMOS tube N1, and the fifth terminal and the sixth terminal of the resistance adaptive adjustment unit are all connected to the ground signal; The first end of the resistance adaptive adjustment unit is connected to the drain of the PMOS tube P3, and the second end is used to receive the external voltage V in , the third end is connected to the gate of the N-type power tube MN, and the fourth end is connected to the source of the N-type power tube MN; The resistance adaptive adjustment unit is used to adjust its own resistance according to the change of the load current of the wide-band high power supply noise suppression linear voltage regulator circuit, so that the segmented FFRC compensation module can adaptively adjust the magnitude of the output compensation voltage.

3. The circuit according to claim 2, characterized in that The resistance adaptive adjustment unit comprises: NMOS tube N3, NMOS tube N4, NMOS tube N5, NMOS tube N6, resistor R T1 , resistor R T2 , resistor R T3 and resistor R T4 , and a first current comparator, a second current comparator, a third current comparator and a fourth current comparator; The drain of the NMOS tube N3 is connected to the resistor R T1 The gate is connected to the output end of the first current comparator, and the source is connected to the resistor R T1 The second end of the resistor R T2 and the drain of the NMOS tube N4; The gate of the NMOS tube N4 is connected to the output end of the second current comparator, and the source is connected to the resistor R T2 The second end of the resistor R T3 and the drain of the NMOS tube N5; The gate of the NMOS tube N5 is connected to the output end of the third current comparator, and the source is connected to the resistor R T3 The second end of the resistor R T4 and the drain of the NMOS tube N6; The gate of the NMOS tube N6 is connected to the output end of the fourth current comparator, and the source is connected to the resistor R T4 a second end and the ground signal; The first input terminal of the first current comparator, the first input terminal of the second current comparator, the first input terminal of the third current comparator and the first input terminal of the fourth current comparator are all used to receive the external voltage V in ; The second input end of the first current comparator, the second input end of the second current comparator, the second input end of the third current comparator and the second input end of the fourth current comparator are all connected to the gate of the N-type power tube MN; The third input terminal of the first current comparator, the third input terminal of the second current comparator, the third input terminal of the third current comparator and the third input terminal of the fourth current comparator are all connected to the source of the N-type power tube MN; Each of the current comparators is used to control the switch state of the corresponding NMOS tube according to the load current of the linear voltage regulator circuit with wide-band high power supply noise suppression, so as to adjust the resistance of the resistance adaptive adjustment unit.

4. The circuit according to claim 3, characterized in that include: When the load current is less than 45 mA, the NMOS transistor N3, the NMOS transistor N4, the NMOS transistor N5 and the NMOS transistor N6 are all turned on; When the load current is greater than or equal to 45 mA and less than 66 mA, the NMOS tube N3 is turned off, and the NMOS tube N4, the NMOS tube N5 and the NMOS tube N6 are all turned on; When the load current is greater than or equal to 66 mA and less than 88 mA, the NMOS tube N3 and the NMOS tube N4 are turned off, and the NMOS tube N5 and the NMOS tube N6 are turned on; When the load current is greater than or equal to 88 mA and less than 100 mA, the NMOS tube N3, the NMOS tube N4 and the NMOS tube N5 are turned off, and the NMOS tube N6 is turned on; When the load current is greater than or equal to 100 mA, the NMOS transistor N3 , the NMOS transistor N4 , the NMOS transistor N5 , and the NMOS transistor N6 are all turned off.

5. The circuit according to claim 3, characterized in that Each of the current comparators comprises: NMOS tube N1-1, NMOS tube N2-1, NMOS tube N3-1, NMOS tube N4-1, PMOS tube P1-1, amplifier SA1, Schmitt trigger U1 and inverter U2, wherein the parameters of the PMOS tubes in each of the current comparators are different; The drain of the NMOS transistor N1-1 and the source of the PMOS transistor P1-1 are both used to receive the external voltage V in , the NMOS tube N1-1 is a replica tube of the N-type power tube MN; The gate of the NMOS tube N1-1 is connected to the gate of the N-type power tube MN, and the source is respectively connected to the in-phase input terminal of the amplifier SA1 and the drain of the NMOS tube N2-1; The inverting input terminal of the amplifier SA1 is connected to the source of the N-type power transistor MN, and the output terminal is connected to the gate of the NMOS transistor N2-1; The source of the NMOS tube N2-1 is respectively connected to the drain and gate of the NMOS tube N3-1, and the gate of the NMOS tube N4-1; The source of the NMOS tube N3-1 and the source of the NMOS tube N4-1 are both connected to the ground signal; The gate of the PMOS transistor P1-1 is used to receive the first bias signal, and the drain is respectively connected to the drain of the NMOS transistor N4-1 and the input end of the Schmitt trigger U1; The output end of the Schmitt trigger U1 is connected to the input end of the inverter U2, and the output end of the inverter U2 is the output end of the current comparator.

6. The circuit according to any one of claims 1 to 5, characterized in that: The summing module comprises: Resistor R BKB , capacitor C S1 , capacitor C S2 , summing amplifier SUM; The resistor R BKB and the capacitor C S2 After being connected in parallel, it is connected between the inverting input terminal and the output terminal of the amplifier SUM; The inverting input terminal of the amplifier SUM is also connected to the capacitor C S1 Connecting the segmented FFRC compensation module; A non-inverting input terminal of the amplifier SUM is connected to an output terminal of the error amplifier.

7. The circuit according to claim 6, characterized in that The buffer comprises: NMOS tube N7, NMOS tube N8, PMOS tube P4 and PMOS tube P5; The source of the PMOS tube P4 is used to receive the voltage V cp , the gate is used to receive the second bias voltage, and the drain is respectively connected to the source of the PMOS tube P5, the drain of the NMOS tube N8, the gate of the N-type power tube MN and the fifth end of the segmented FFRC compensation module; The gate of the PMOS tube P5 is connected to the third terminal of the summing module, and the drain is respectively connected to the gate of the NMOS tube N8 and the drain of the NMOS tube N7; The gate of the NMOS tube N7 is used to receive a third bias voltage; The source of the NMOS transistor N7 and the source of the NMOS transistor N8 are both connected to the ground signal.

8. The circuit according to claim 7, characterized in that The resistor feedback network comprises: Resistor R1 and resistor R2; The first end of the resistor R1 is connected to the source of the N-type power tube MN, and the second end is respectively connected to the inverting input end of the error amplifier and the first end of the resistor R2; The second end of the resistor R2 is connected to the ground signal.

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