Wide input range low power consumption fast response pre-stabilization circuit and analog chip

Abstract

The application discloses a wide input range low-power fast response pre-stabilization circuit and analog chip, which comprises a reference current source for generating first and second reference voltages; a current comparator for comparing the driving current capacity of two transistors connected with the first pre-stabilization output circuit in the current comparator, and generating a first control voltage according to the comparison result under the first reference voltage; a control circuit for generating a second control voltage by using a mirror transistor under the second reference voltage; a first pre-stabilization output circuit for generating an output voltage varying with the input power supply voltage under the first control voltage; a second pre-stabilization output circuit for generating an output voltage varying with the input power supply voltage under the second control voltage; and the high-voltage PMOS tube in the first pre-stabilization output circuit and the high-voltage NMOS tube in the second pre-stabilization output circuit are in an off-on state during the variation of the input power supply voltage. The circuit has the characteristics of wide input range and low power consumption.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design technology, specifically relating to a low-power fast-response pre-regulator circuit with a wide input range and an analog chip. Background Technology

[0002] The pre-regulator circuit is a fundamental module of analog chips, used to provide a stable power supply voltage to the relevant startup modules before the chip starts up. As the application scenarios for analog chips' power supply voltages become increasingly widespread, the pre-regulator circuit needs to meet the application requirements of a wide voltage input range.

[0003] Traditional pre-regulated circuits, such as Figure 1 As shown, a high-voltage PMOS transistor is typically linearly controlled by charging a resistor R with a current I. Figure 1 The diagram in the image shows MP, which causes the high-voltage NMOS transistor (MP) to... Figure 1 The diagram illustrates the alternating conduction of the high-voltage NMOS and PMOS transistors under different input power supply voltages. The linear control method employed in this structure cannot guarantee a rapid transition between the high-voltage NMOS and PMOS transistors when the input power supply voltage exceeds the Zener diode breakdown voltage, resulting in slow output voltage changes. Traditional pre-regulator circuits control the conduction and turn-off of the high-voltage PMOS transistors due to the influence of the MOS transistor's threshold voltage and resistance, failing to precisely control their on / off states. Furthermore, the current I cannot be ignored, which worsens the power consumption performance of the pre-regulator circuit. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a low-power, fast-response pre-regulator circuit and analog chip with a wide input range. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] In a first aspect, embodiments of the present invention provide a low-power, fast-response pre-regulator circuit with a wide input range. The pre-regulator circuit includes a reference current source, a current comparator, a control circuit, a first pre-regulator output circuit, and a second pre-regulator output circuit.

[0006] The reference current source is used to generate a first reference voltage and a second reference voltage; the current comparator is connected to the reference current source, and is used to compare the driving current capacity of a low threshold PMOS tube and a high voltage NMOS tube connected to the first pre-regulation output circuit in the current comparator under the action of the first reference voltage when the input power supply voltage is less than or equal to the breakdown voltage of a Zener diode, and generate a first control voltage according to the comparison result; the control circuit is connected to the reference current source, and is used to generate a second control voltage by using a mirror transistor pair under the action of the second reference voltage when the input power supply voltage is greater than the breakdown voltage of the Zener diode; the first pre-regulation output circuit is used to generate an output voltage varying with the input power supply voltage under the control of the first control voltage; wherein the first pre-regulation output circuit comprises a high voltage PMOS tube MP1 and a first load capacitor, the gate of the high voltage PMOS tube MP1 is connected to the current comparator, the source of the high voltage PMOS tube MP1 is connected to the input end of the input power supply voltage, and the drain of the high voltage PMOS tube MP1 is connected to the ground through the first load capacitor and serves as the output end of the output voltage; the second pre-regulation output circuit is used to generate an output voltage varying with the input power supply voltage under the control of the second control voltage; wherein the second pre-regulation output circuit comprises a high voltage NMOS tube MN1 and a first load capacitor, the gate of the high voltage NMOS tube MN1 is connected to the control circuit, the drain of the high voltage NMOS tube MN1 is connected to the input end of the input power supply voltage, and the source of the high voltage NMOS tube MN1 is connected to the ground through the second load capacitor and serves as the output end of the output voltage.

[0007] Wherein the high voltage NMOS tube MN1 and the high voltage PMOS tube MP1 are in an off-on state during the variation of the input power supply voltage.

[0008] In an embodiment of the present application, the pre-regulation circuit further comprises a clamping protection circuit.

[0009] The clamping protection circuit is connected to the current comparator and the gate of the high voltage PMOS tube MP1, and is used to limit the gate-source voltage difference of the high voltage PMOS tube MP1.

[0010] In an embodiment of the present application, the reference current source comprises transistors N1-N5, transistors P1-P4 and a resistor R1; wherein,

[0011] The source of the transistor P1, the source of the transistor P2, and the source of the transistor P3 are connected to an input terminal of an input power voltage, the gate of the transistor P1 is connected to the drain of the transistor P1, the gate of the transistor P2, and the drain of the transistor N1, the drain of the transistor P2 is connected to the gate of the transistor N1, the gate of the transistor N3, and the drain of the transistor N3, the source of the transistor N1 is connected to the drain of the transistor N2, the gate of the transistor N2 is connected to the source of the transistor N3, the drain of the transistor N4, the gate of the transistor N4, the gate of the transistor N5, and the current comparator, the source of the transistor N2 is connected to one end of the resistor R1, the source of the transistor N4, the other end of the resistor R1, and the source of the transistor N5 are all connected to ground, the drain of the transistor N5 is connected to the drain of the transistor P4, the gate of the transistor P4, and the current comparator, and the source of the transistor P4 is connected to the drain of the transistor P3, the gate of the transistor P3, and the control circuit.

[0012] In an embodiment of the present application, the transistors N1 to N5 are all high-voltage NMOS transistors, and the transistors P1 to P4 are all high-voltage PMOS transistors.

[0013] In an embodiment of the present application, the current comparator comprises the transistors P6 to P8, the transistor N6, and the Zener diode D1.

[0014] The source of the transistor P7 and the source of the transistor P8 are connected to an input terminal of an input power voltage, the source of the transistor P6 is connected to the drain of the transistor P7, the gate of the transistor P7, and the gate of the transistor P8, the gate of the transistor P6 is connected to the gate of the transistor P4, the drain of the transistor P6 is connected to the negative electrode of the Zener diode D1, the drain of the transistor P8 is connected to the drain of the transistor N6 and the gate of the high-voltage PMOS transistor MP1, the gate of the transistor N6 is connected to the gate of the transistor N2, and the positive electrode of the Zener diode D1 and the source of the transistor N6 are both connected to ground.

[0015] In an embodiment of the present application, the transistors P6 and P7 are both high-voltage PMOS transistors, the transistor N6 is a high-voltage NMOS transistor, and the transistor P8 is a low-threshold PMOS transistor.

[0016] In an embodiment of the present application, the clamping protection circuit comprises the Zener diode D2, the negative electrode of the Zener diode D2 is connected to an input terminal of an input power voltage, and the positive electrode of the Zener diode D2 is connected to the gate of the high-voltage PMOS transistor MP1.

[0017] In an embodiment of the present application, the control circuit comprises the transistors P9, P10, N7, and N8, the resistors R2 and R3, the Zener diodes D3 and D4. 10 ​

[0018] The source of the transistor P9, the source of the transistor P 10 The one end of the resistance R2, the one end of the resistance R3, and the input end of the input power voltage are connected to the input end, the gate of the transistor P 10 The gate of the transistor P9 is connected with the gate of the transistor P3, the drain of the transistor P9 is connected with the source of the transistor N7, the gate of the transistor N8, and the negative electrode of the Zener diode D3, the drain of the transistor P 10 The drain of the transistor P9 is connected with the source of the transistor N8, the gate of the transistor N7, the negative electrode of the Zener diode D4, and the gate of the high-voltage NMOS transistor MN1, the drain of the transistor N7 is connected with the other end of the resistance R2, the drain of the transistor N8 is connected with the other end of the resistance R3, the positive electrode of the Zener diode D3 and the positive electrode of the Zener diode D4 are grounded; wherein, the transistor P9, the transistor P 10 The mirror transistor pair is composed of the transistor P9 and the transistor P

[0019] In an embodiment of the present application, the transistor P9, the transistor P 10 The transistor N7 and the transistor N8 are all high-voltage NMOS transistors.

[0020] The second aspect, an analog chip, the analog chip comprises the low-power fast-response pre-stabilizing circuit with wide input range of any one of the first aspect.

[0021] The present application has the following beneficial effects:

[0022] The wide input range low-power fast response pre-stabilization circuit provided by the application solves the problems of low input power supply voltage range and large output voltage variation with input power supply voltage fluctuation of the traditional pre-stabilization circuit from the circuit design level, specifically: during the input power supply voltage variation process, the application controls the high-voltage NMOS tube MN1 to work in the scene where the input power supply voltage is greater than the breakdown voltage of the Zener diode and the high-voltage PMOS tube MP1 to work in the scene where the input power supply voltage is less than or equal to the breakdown voltage of the Zener diode by detecting the input power supply voltage and the size of the Zener diode in real time, so that the pre-stabilization circuit can work in the two scenes of low and high input power supply voltage, and a pre-stabilization circuit with a wide input range is realized; the application accurately controls the on and off time of the high-voltage PMOS tube MP1 by means of current comparison, has the characteristics of high flip point precision and high consistency, and uses the high gain characteristic of the current comparator to realize the fast switching of the high-voltage PMOS tube MP1 to respond to the change of the input power supply voltage, which can effectively avoid the problem of large output voltage fluctuation caused by slow switching of the high-voltage PMOS tube MP1; in addition, the current comparator is more power-saving than the traditional scheme, reduces the power consumption, and effectively avoids the problem of deterioration of standby power consumption index caused by synchronous increase of the breakdown voltage of the Zener diode with the input power supply voltage; at the same time, when the high-voltage PMOS tube MP1 is turned off, it is automatically switched to respond to the change of the input power supply voltage by the high-voltage NMOS tube MN1, and the control circuit is used to realize the rapid rise of the gate voltage of the high-voltage NMOS tube MN1, which improves the switching speed of the high-voltage NMOS tube MN1 and accurately controls the on and off of the high-voltage NMOS tube MN1. It can be seen that the high-voltage NMOS tube MN1 and the high-voltage PMOS tube MP1 are alternately turned on by the current comparator and the control circuit, which realizes the high-precision fast transition of the power tube working mode, facilitates the design of each module inside the chip, and provides a new circuit structure and design idea for the design of the wide input voltage pre-stabilization circuit.

[0023] The application will be further described in detail below with reference to the drawings and examples. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a specific circuit schematic diagram of the traditional pre-stabilization circuit;

[0025] Figure 2 is a structure schematic diagram of a wide input range low-power fast response pre-stabilization circuit provided by an embodiment of the application;

[0026] Figure 3 is a specific circuit schematic diagram of the pre-stabilization circuit shown in the figure. Figure 2 DETAILED DESCRIPTION

[0027] ​The application will be described in further detail below with reference to specific embodiments, but the embodiments of the application are not limited thereto.

[0028] Please refer to Figure 2 The embodiment of the application provides a wide input range low-power fast response pre-stabilization circuit. In a first aspect, the embodiment of the application provides a wide input range low-power fast response pre-stabilization circuit. The pre-stabilization circuit comprises a reference current source, a current comparator, a control circuit, a first pre-stabilization output circuit and a second pre-stabilization output circuit, wherein

[0029] The reference current source is used to generate a first reference voltage and a second reference voltage. The current comparator is connected to the reference current source and is used to compare the driving current capacity of a low-threshold PMOS tube and a high-voltage NMOS tube connected to the first pre-stabilization output circuit in the current comparator under the action of the first reference voltage when the input power supply voltage is less than or equal to the breakdown voltage of a Zener diode, and generate a first control voltage according to the comparison result. The control circuit is connected to the reference current source and is used to generate a second control voltage by using a mirror transistor pair under the action of the second reference voltage when the input power supply voltage is greater than the breakdown voltage of the Zener diode. The first pre-stabilization output circuit is used to generate an output voltage varying with the input power supply voltage under the control of the first control voltage. The first pre-stabilization output circuit comprises a high-voltage PMOS tube MP1 and a first load capacitor. The gate of the high-voltage PMOS tube MP1 is connected to the current comparator. The source of the high-voltage PMOS tube MP1 is connected to the input end of the input power supply voltage. The drain of the high-voltage PMOS tube MP1 is connected to the ground through the first load capacitor (C1) and serves as the output end of the output voltage. The second pre-stabilization output circuit is used to generate an output voltage varying with the input power supply voltage under the control of the second control voltage. The second pre-stabilization output circuit comprises a high-voltage NMOS tube MN1 and a second load capacitor. The gate of the high-voltage NMOS tube MN1 is connected to the control circuit. The drain of the high-voltage NMOS tube MN1 is connected to the input end of the input power supply voltage. The source of the high-voltage NMOS tube MN1 is connected to the ground through the second load capacitor (C2) and serves as the output end of the output voltage. Figure 3 Figure 3

[0030] The high-voltage NMOS tube MN1 and the high-voltage PMOS tube MP1 are in an off-on state in the process of varying with the input power supply voltage.

[0031] Here, the high-voltage NMOS tube, the high-voltage PMOS tube and the low-threshold PMOS tube are all conventional definitions in MOS tube devices, and the specific selection of the high-voltage NMOS tube, the high-voltage PMOS tube and the low-threshold PMOS tube is determined by the application scenario.

[0032] Please refer to Figure 2 ​​The pre-stabilization circuit in the embodiment of the application further comprises: a clamping protection circuit connected to the current comparator and the gate of the high-voltage PMOS tube MP1, for limiting the gate-source voltage difference of the high-voltage PMOS tube MP1.

[0033] When the input power supply voltage AVIN is less than or equal to the breakdown voltage of the Zener diode, the high-voltage PMOS tube MP1 works in the linear region, and at this time, the output voltage VOUT of the first pre-stabilization output circuit is equal to the input power supply voltage AVIN, so that the output voltage VOUT still has sufficient power supply capability under the condition that the input power supply voltage is low. When the input power supply voltage AVIN gradually increases and is greater than the breakdown voltage of the Zener diode, the Zener diode breaks down, the driving current generated by the low-threshold PMOS tube is compared with the driving current generated by the high-voltage NMOS tube, and the conduction state of the high-voltage PMOS tube MP1 is synchronously controlled, and when the driving current generated by the low-threshold PMOS tube is greater than the driving current generated by the high-voltage NMOS tube, the high-voltage PMOS tube MP1 will be immediately turned off, wherein the driving current generated by the high-voltage NMOS tube is provided by the reference current source. Before the Zener diode breaks down, the gate voltage of the high-voltage NMOS tube MN1 automatically follows the input power supply voltage AVIN, and after the Zener diode breaks down, the high-voltage NMOS tube MN1 enters the saturation region, and the output voltage VOUT of the second pre-stabilization output circuit is equal to the breakdown voltage of the Zener diode minus Vthn (Vthn is the threshold voltage of the high-voltage NMOS tube MN1), so that when the high-voltage PMOS tube MP1 is turned off, the output voltage VOUT will be automatically supplied by the high-voltage NMOS tube MN1. It can be seen that through the input power supply voltage, the high-voltage NMOS tube MN1 can be controlled to work in the scenario that the input power supply voltage is greater than the breakdown voltage of the Zener diode, and the high-voltage PMOS tube MP1 can be controlled to work in the scenario that the input power supply voltage is less than or equal to the breakdown voltage of the Zener diode, so that the pre-stabilization circuit can work in the two scenarios of low and high input power supply voltages, and a pre-stabilization circuit with a wide input range is realized.

[0034] Next, each part of the pre-stabilization circuit structure shown in Figure 2 will be described in detail.

[0035] In the embodiment of the application, the reference current source is, for example, Figure 3As shown, the circuit comprises transistors N1-N5, transistors P1-P4, and resistor R1; wherein the source of transistor P1, the source of transistor P2, and the source of transistor P3 are connected to an input terminal of an input power supply voltage, the gate of transistor P1 is connected to the drain of transistor P1, the gate of transistor P2, and the drain of transistor N1, the drain of transistor P2 is connected to the gate of transistor N1, the gate of transistor N3, and the drain of transistor N3, the source of transistor N1 is connected to the drain of transistor N2, the gate of transistor N2 is connected to the source of transistor N3, the drain of transistor N4, the gate of transistor N4, the gate of transistor N5, and a current comparator, the source of transistor N2 is connected to one end of resistor R1, the source of transistor N4, the other end of resistor R1, and the source of transistor N5 are all connected to ground, the drain of transistor N5 is connected to the drain of transistor P4, the gate of transistor P4, and the current comparator, and the source of transistor P4 is connected to the drain of transistor P3, the gate of transistor P3, and a control circuit. In the embodiment of the present application, the reference current source composed of transistors N1-N5, transistors P1-P4, and resistor R1 generates a first reference voltage and a second reference voltage for the subsequent current comparator and control circuit: the output node of the first reference voltage is at the gate of transistor N2, Figure 3 V b1 , and the output node of the second reference voltage is at the gate of transistor P3, Figure 3 V b2 .

[0036] In the embodiment of the present application, transistors N1-N5 are all high-voltage NMOS transistors, and transistors P1-P4 are all high-voltage PMOS transistors.

[0037] Further, in the embodiment of the present application, the current comparator is, for example, Figure 3As shown, the transistors include transistors P6 to P8, transistor N6, and Zener diode D1. The sources of transistors P7 and P8 are connected to the input terminal of the power supply voltage. The source of transistor P6 is connected to the drain, gate, and gate of transistor P7 and P8. The gate of transistor P6 is connected to the gate of transistor P4. The drain of transistor P6 is connected to the negative terminal of Zener diode D1. The drain of transistor P8 is connected to the drain of transistor N6 and the gate of high-voltage PMOS transistor MP1. The gate of transistor N6 is connected to the gate of transistor N2. The positive terminal of Zener diode D1 and the source of transistor N6 are both grounded. This invention, through a reasonable setting of the width-to-length ratio of transistors P3, P4, and P6, ensures that when Zener diode D1 fails to break down, the gate voltage V3 of transistor P7 does not change with the increase of the input power supply voltage AVIN. This continues until Zener diode D1 breaks down, at which point the voltage difference between the input power supply voltage AVIN and voltage V3 exceeds the threshold voltage of transistor P8. At this point, transistor P8 conducts, and the drive current of transistor P8 is much greater than the current of transistor N6 replicating the reference current source. Transistor P8 then enters the linear region and outputs the first control voltage, causing the high-voltage PMOS transistor MP1 to quickly enter the cutoff region, thus improving the transient response speed of the system during the transition from a low input power supply voltage to a high input power supply voltage. The first control voltage output by the current comparator... Figure 3 The first control voltage V1 is denoted as V1. When the input power supply voltage is less than or equal to the breakdown voltage of the Zener diode, the first control voltage V1 is the input power supply voltage AVIN. When the input power supply voltage AVIN is greater than the breakdown voltage of the Zener diode, the first control voltage V1 is 0, i.e., AGND.

[0038] In this embodiment of the invention, transistors P6 to P7 are all high-voltage PMOS transistors; transistor N6 is a high-voltage NMOS transistor; and transistor P8 is a low-threshold PMOS transistor.

[0039] Furthermore, in this embodiment of the invention, the clamping protection circuit is as follows: Figure 3 As shown, it includes a Zener diode D2, the negative terminal of which is connected to the input terminal of the input power supply voltage, and the positive terminal of which is connected to the gate of the high-voltage PMOS transistor MP1.

[0040] Furthermore, in embodiments of the present invention, the control circuit is as follows: Figure 3 As shown, it includes transistor P9 and transistor P. 10 Transistor N7, transistor N8, resistor R2, resistor R3, Zener diode D3, Zener diode D4; wherein, the source of transistor P9, transistor P 10 The source of transistor P9, one end of resistor R2, and one end of resistor R3 are all connected to the input terminal of the input power supply voltage. The gate of transistor P9 is connected to the gate of transistor P... 10gate of the transistor P9 is connected with the source of the transistor N7, the gate of the transistor N8, the negative electrode of the Zener diode D3, and the gate of the high-voltage NMOS transistor MN1, the drain of the transistor N7 is connected with the other end of the resistor R2, the drain of the transistor N8 is connected with the other end of the resistor R3, the positive electrode of the Zener diode D3 and the positive electrode of the Zener diode D4 are grounded; wherein the transistor P9, the transistor P 10 gate of the transistor P9 is connected with the source of the transistor N7, the gate of the transistor N8, the negative electrode of the Zener diode D3, and the gate of the high-voltage NMOS transistor MN1, the drain of the transistor N7 is connected with the other end of the resistor R2, the drain of the transistor N8 is connected with the other end of the resistor R3, the positive electrode of the Zener diode D3 and the positive electrode of the Zener diode D4 are grounded; wherein the transistor P9, the transistor P 10 mirror transistor pair. When the high-voltage PMOS transistor MP1 enters the cut-off region under the action of the first control voltage V1, the current of the reference current source is copied through the mirror transistor pair composed of the transistor P9 and the transistor P 10 gate of the transistor P9 is connected with the source of the transistor N7, the gate of the transistor N8, the negative electrode of the Zener diode D3, and the gate of the high-voltage NMOS transistor MN1, the drain of the transistor N7 is connected with the other end of the resistor R2, the drain of the transistor N8 is connected with the other end of the resistor R3, the positive electrode of the Zener diode D3 and the positive electrode of the Zener diode D4 are grounded; wherein the transistor P9, the transistor P ​ , and the second control voltage reaches the breakdown voltage of the Zener diode, the Zener diode D3 and the Zener diode D4 are broken down, and the high-voltage NMOS transistor MN1 enters the saturation region. The second control voltage output by the control circuit is denoted as V2 in the following.

[0041] gate of the transistor P9 is connected with the source of the transistor N7, the gate of the transistor N8, the negative electrode of the Zener diode D3, and the gate of the high-voltage NMOS transistor MN1, the drain of the transistor N7 is connected with the other end of the resistor R2, the drain of the transistor N8 is connected with the other end of the resistor R3, the positive electrode of the Zener diode D3 and the positive electrode of the Zener diode D4 are grounded; wherein the transistor P9, the transistor P 10 mirror transistor pair composed of the transistor P9 and the transistor P 10 , and the second control voltage reaches the breakdown voltage of the Zener diode, the Zener diode D3 and the Zener diode D4 are broken down, and the high-voltage NMOS transistor MN1 enters the saturation region. The second control voltage output by the control circuit is denoted as V2 in the following.

[0042] gate of the transistor P9 is connected with the source of the transistor N7, the gate of the transistor N8, the negative electrode of the Zener diode D3, and the gate of the high-voltage NMOS transistor MN1, the drain of the transistor N7 is connected with the other end of the resistor R2, the drain of the transistor N8 is connected with the other end of the resistor R3, the positive electrode of the Zener diode D3 and the positive electrode of the Zener diode D4 are grounded; wherein the transistor P9, the transistor P 10 are high-voltage PMOS transistors, and the transistor N7 and the transistor N8 are high-voltage NMOS transistors.

[0043] The Zener diode breakdown voltages of the Zener diode D1, the Zener diode D2, the Zener diode D3 and the Zener diode D4 in the embodiment of the application are equal.

[0044] The working process of the pre-stabilization circuit includes:

[0045] When the input supply voltage AVIN is less than the breakdown voltage of the Zener diode, the Zener diode D1 fails to break down, the transistor P6 works in the linear region, the voltage V3 follows the input supply voltage AVIN, the transistor P8 works in the cut-off region, and the driving current of the transistor P8 is far less than the current of the reference current source copied by the transistor N6. The first control voltage V1 is pulled down to AGND, the high-voltage PMOS transistor MP1 enters the linear region, the Zener diode D2 is used to limit the gate-source voltage difference of the high-voltage PMOS transistor MP1 to prevent the high-voltage PMOS transistor MP1 from breaking down, and the output voltage VOUT of the first pre-regulator output circuit is equal to the input supply voltage AVIN. Since the Zener diode D4 fails to break down, the second control voltage V2 is equal to the input supply voltage AVIN, and the gate-source voltage difference of the high-voltage NMOS transistor MN1 is zero, so the high-voltage NMOS transistor MN1 enters the cut-off region.

[0046] When the input supply voltage AVIN gradually increases to be higher than the breakdown voltage of the Zener diode, the Zener diode D1 breaks down. The width-length ratios of the transistors P3, P4, and P6 are set to make the voltage V3 constant until the input supply voltage AVIN and the voltage V3 have a voltage difference greater than the threshold voltage of the transistor P8. At this time, the transistor P8 is turned on, and the width-length ratio of the transistor P8 is set to ensure that the driving current of the transistor P8 is far greater than the current of the reference current source copied by the transistor N6 when the transistor P8 is turned on. The first control voltage V1 is quickly pulled up to the input supply voltage AVIN, and the high-voltage PMOS transistor MP1 enters the cut-off region. At the same time, the second control voltage V2 is raised to the breakdown voltage of the Zener diode by the control circuit, the Zener diodes D3 and D4 break down, the second control voltage V2 is constant, the high-voltage NMOS transistor MN1 enters the saturation region, and the output voltage VOUT of the second pre-regulator output circuit is equal to the second control voltage V2 minus the threshold voltage of the high-voltage NMOS transistor MN1.

[0047] Here, the width-length ratios of the transistors P3, P4, and P6, and the width-length ratio of the transistor P8 are not limited, as long as they meet the requirements. For example, the width-length ratios of the transistors P3, P4, and P6 are designed to make the voltage V3 constant when the input voltage is less than the breakdown voltage of the Zener diode, and the width-length ratio of the transistor P8 is designed to ensure that the driving current of the transistor P8 is far greater than the current of the reference current source copied by the transistor N6.

[0048] Compared to traditional pre-regulator circuits, this invention uses a current comparator to control the on and off of the high-voltage PMOS transistor MP1, precisely controlling the on and off times of both MP1 and MN1. Furthermore, utilizing the high-gain characteristic of the current comparator, the first control voltage V1 at the node can change rapidly, enabling quick transitions in the operating state of MP1. In terms of power consumption, after the output state stabilizes, the power consumption of the current comparator is determined only by the transistor with the lower current flow between N6 and P8, thus offering the advantage of lower power consumption compared to traditional pre-regulator circuits. In addition, the pre-regulator circuit proposed in this invention also employs transistors P9 and P... 10 The method of replicating the reference current source current replaces the traditional approach of charging Zener diodes D3 and D4 with resistors, further reducing power consumption and improving the consistency of the overall control scheme.

[0049] The pre-regulator circuit proposed in this invention can quickly respond and output a stable VOUT when the input power supply voltage AVIN is rapidly powered on. When the input power supply voltage AVIN is rapidly powered on, due to the influence of the gate-terminal parasitic capacitance of the high-voltage NMOS transistor MN1, transistor P... 10 The current generated at the drain of transistor P9 charges the node second control voltage V2 much faster than the current generated at the drain of transistor P9 charges the node voltage V4. At this time, the transient voltage difference between the second control voltage V2 and voltage V4 is greater than the threshold voltage of transistor N8. Transistor N8 turns on and sends current to Zener diode D4 to accelerate charging until transistor N8 enters the cutoff region and the accelerated charging ends. Resistors R2 and R3 are used to reduce the transient overshoot current of transistors N7 and N8.

[0050] In summary, the low-power fast response pre-stabilization circuit with wide input range provided by the embodiment of the present application solves the problems of low input power supply voltage range and large output voltage variation with input power supply voltage fluctuation of the traditional pre-stabilization circuit from the circuit design level. Specifically, during the input power supply voltage variation process, the embodiment of the present application controls the high-voltage NMOS tube MN1 to work in the scenario that the input power supply voltage is greater than the breakdown voltage of the Zener diode and the high-voltage PMOS tube MP1 to work in the scenario that the input power supply voltage is less than or equal to the breakdown voltage of the Zener diode by detecting the input power supply voltage and the size of the Zener diode in real time, so that the pre-stabilization circuit can work in the two scenarios of low and high input power supply voltage, and a pre-stabilization circuit with wide input range is realized. The embodiment of the present application accurately controls the on and off time of the high-voltage PMOS tube MP1 by the current comparison method, has the characteristics of high precision and high consistency of the flip point, and uses the high gain characteristic of the current comparator to realize the fast switching of the high-voltage PMOS tube MP1 to respond to the change of the input power supply voltage, which can effectively avoid the problem of large output voltage fluctuation caused by slow switching of the high-voltage PMOS tube MP1. In addition, the current comparator is more power-saving than the traditional scheme, reduces the power consumption, and effectively avoids the problem that the standby power consumption index deteriorates due to the synchronous increase of the breakdown voltage of the Zener diode with the input power supply voltage. At the same time, when the high-voltage PMOS tube MP1 is turned off, it is automatically switched to respond to the change of the input power supply voltage by the high-voltage NMOS tube MN1, and the control circuit is used to realize the rapid lifting of the gate voltage of the high-voltage NMOS tube MN1, which improves the switching speed of the high-voltage NMOS tube MN1 and accurately controls the on and off of the high-voltage NMOS tube MN1. It can be seen that the high-voltage NMOS tube MN1 and the high-voltage PMOS tube MP1 are alternately turned on by the current comparator and the control circuit, which realizes the high-precision fast transition of the power tube working mode, facilitates the design of each module in the chip, and provides a new circuit structure and design idea for the design of the wide input voltage pre-stabilization circuit.

[0051] In a second aspect, an analog chip includes the low-power fast response pre-stabilization circuit of any of the first aspect.

[0052] For the embodiment of the analog chip of the second aspect, the description is relatively simple because it is basically similar to the circuit embodiment of the first aspect. Please refer to the part of the description of the circuit embodiment of the first aspect.

[0053] In the description of the application, it should be understood that the terms "first", "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0054] Although the application is described herein in conjunction with various embodiments, those skilled in the art, by referring to the description and drawings, can understand and implement other changes of the disclosed embodiments in the implementation of the claimed application. In the description, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude a plurality. Some measures are described in mutually different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0055] The above is a further detailed description of the application in conjunction with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the application to these descriptions. For those skilled in the art, without departing from the concept of the application, a number of simple deductions or substitutions can be made, which should be considered as falling within the protection scope of the application.

Claims

1. A low power fast response pre-regulator circuit with wide input range, characterized in that, The pre-stabilization circuit comprises a reference current source, a current comparator, a control circuit, a first pre-stabilization output circuit and a second pre-stabilization output circuit, wherein The reference current source is configured to generate a first reference voltage and a second reference voltage; the current comparator is connected to the reference current source and is configured to compare the driving current capability of a low-threshold PMOS tube and a high-voltage NMOS tube connected to the first pre-stabilization output circuit in the current comparator under the action of the first reference voltage when the input power supply voltage is less than or equal to the breakdown voltage of a Zener diode, and generate a first control voltage according to the comparison result; the control circuit is connected to the reference current source and is configured to generate a second control voltage by using a mirror transistor pair under the action of the second reference voltage when the input power supply voltage is greater than the breakdown voltage of the Zener diode; the first pre-stabilization output circuit is configured to generate an output voltage varying with the input power supply voltage under the control of the first control voltage; wherein the first pre-stabilization output circuit comprises a high-voltage PMOS tube MP1 and a first load capacitor, the gate of the high-voltage PMOS tube MP1 is connected to the current comparator, the source of the high-voltage PMOS tube MP1 is connected to the input end of the input power supply voltage, and the drain of the high-voltage PMOS tube MP1 is connected to the ground through the first load capacitor and serves as the output end of the output voltage; the second pre-stabilization output circuit is configured to generate an output voltage varying with the input power supply voltage under the control of the second control voltage; wherein the second pre-stabilization output circuit comprises a high-voltage NMOS tube MN1 and a first load capacitor, the gate of the high-voltage NMOS tube MN1 is connected to the control circuit, the drain of the high-voltage NMOS tube MN1 is connected to the input end of the input power supply voltage, and the source of the high-voltage NMOS tube MN1 is connected to the ground through the second load capacitor and serves as the output end of the output voltage; Wherein, the high-voltage NMOS tube MN1 and the high-voltage PMOS tube MP1 are in an off-on state during the variation of the input power supply voltage.

2. The low power consumption fast response pre-regulator circuit with wide input range according to claim 1, characterized in that, The pre-stabilization circuit further comprises a clamping protection circuit; The clamping protection circuit is connected to the current comparator and the gate of the high-voltage PMOS tube MP1 and is configured to limit the gate-source voltage difference of the high-voltage PMOS tube MP1.

3. The low power consumption fast response pre-regulator circuit with wide input range according to claim 1, characterized in that, The reference current source comprises transistors N1 to N5, transistors P1 to P4 and a resistor R1; wherein The source of the transistor P1, the source of the transistor P2 and the source of the transistor P3 are connected to an input terminal of an input power voltage, the gate of the transistor P1 is connected to the drain of the transistor P1, the gate of the transistor P2 and the drain of the transistor N1, the drain of the transistor P2 is connected to the gate of the transistor N1, the gate of the transistor N3 and the drain of the transistor N3, the source of the transistor N1 is connected to the drain of the transistor N2, the gate of the transistor N2 is connected to the source of the transistor N3, the drain of the transistor N4, the gate of the transistor N4, the gate of the transistor N5 and the current comparator, the source of the transistor N2 is connected to one end of the resistor R1, the source of the transistor N4, the other end of the resistor R1 and the source of the transistor N5 are all connected to ground, the drain of the transistor N5 is connected to the drain of the transistor P4, the gate of the transistor P4 and the current comparator, and the source of the transistor P4 is connected to the drain of the transistor P3, the gate of the transistor P3 and the control circuit.

4. The low power consumption fast response pre-regulator circuit with wide input range according to claim 3, characterized in that, The transistors N1 to N5 are all high-voltage NMOS transistors, and the transistors P1 to P4 are all high-voltage PMOS transistors.

5. The low power consumption fast response pre-regulator circuit with wide input range according to claim 3, characterized in that, The current comparator comprises the transistors P6 to P8, the transistor N6 and the Zener diode D1, wherein, the source of the transistor P7 and the source of the transistor P8 are connected to an input terminal of an input power voltage, the source of the transistor P6 is connected to the drain of the transistor P7, the gate of the transistor P7 and the gate of the transistor P8, the gate of the transistor P6 is connected to the gate of the transistor P4, the drain of the transistor P6 is connected to the negative electrode of the Zener diode D1, the drain of the transistor P8 is connected to the drain of the transistor N6 and the gate of the high-voltage PMOS transistor MP1, the gate of the transistor N6 is connected to the gate of the transistor N2, and the positive electrode of the Zener diode D1 and the source of the transistor N6 are both connected to ground.

6. The low power consumption fast response pre-regulator circuit with wide input range according to claim 5, characterized in that, The transistors P6 to P7 are all high-voltage PMOS transistors, the transistor N6 is a high-voltage NMOS transistor, and the transistor P8 is a low-threshold PMOS transistor.

7. The low power consumption fast response pre-regulator circuit with wide input range according to claim 2, characterized in that, The clamping protection circuit comprises the Zener diode D2, the negative electrode of the Zener diode D2 is connected to an input terminal of an input power voltage, and the positive electrode of the Zener diode D2 is connected to the gate of the high-voltage PMOS transistor MP1.

8. The low power consumption fast response pre-regulator circuit with wide input range according to claim 3, characterized in that, The control circuit comprises transistor P9, transistor P 10 , transistor N7, transistor N8, resistor R2, resistor R3, Zener diode D3, Zener diode D4; wherein, The source of the transistor P9, the source of the transistor P 10 The one end of the resistance R2, the one end of the resistance R3, and the input end of the input power voltage are connected, the gate of the transistor P9 is connected with the gate of the transistor P 10 The drain of the transistor P9 is connected with the source of the transistor N7, the gate of the transistor N8, and the negative electrode of the Zener diode D3, the drain of the transistor P 10 The drain of the transistor P9 is connected with the source of the transistor N8, the gate of the transistor N7, the negative electrode of the Zener diode D4, and the gate of the high-voltage NMOS transistor MN1, the drain of the transistor N7 is connected with the other end of the resistance R2, the drain of the transistor N8 is connected with the other end of the resistance R3, the positive electrode of the Zener diode D3 and the positive electrode of the Zener diode D4 are grounded; wherein the transistor P9 and the transistor P 10 constitute the mirror transistor pair.

9. The low power consumption fast response pre-regulator circuit with wide input range according to claim 8, characterized in that, Transistor P9, transistor P 10 Transistor N7, transistor N8 are both high-voltage NMOS tubes.

10. An analog chip, characterized by The analog chip comprises the wide-input-range low-power-consumption fast-response pre-stabilization circuit according to any one of claims 1 to 9.

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