Power supply system of low quiescent current sensor chip, working method and sensor chip

Abstract

The invention provides a power supply system of a low quiescent current sensor chip, a working method and a sensor chip, a high-voltage domain interface control module, a related matching circuit STBYPOR and a power supply switch are added, when the chip is in a standby state, internal BG, LDO, POR, digital controller and Sensor Core can be wholly powered off, and only the STBYPOR works in real time, so that the purpose of low standby power consumption is achieved, and the cost is reduced. And meanwhile, the wakeup time of the chip is not influenced.

Description

Technical Field

[0001] The present invention relates to the technical field of standby and wake-up of sensor chips, and in particular to a power supply system and a working method of a low quiescent current sensor chip and a sensor chip. Background Art

[0002] In order to achieve low standby power consumption and fast wake-up in many sensor chips, the chip power scenarios are defined to meet the compromise between low standby power consumption and fast wake-up; for example, normal working mode (Normal Mode), standby mode (Standby Mode), and sleep mode (Sleep Mode) are defined.

[0003] Figure 1 It is a common power supply and power-on reset solution. VDD is the external power supply of the chip (usually the high voltage part, such as: 3.3V, 1.8V). VDD_INT is the power generated by the internal LDO for the modules inside the chip, which belongs to the low voltage part (usually 1.8V, 1.2V). The internal digital controller works in the internal low voltage power domain. The I2C interface converts the power domain into high voltage through "lev" (Level Shift) and connects to the Pin.

[0004] Figure 2 yes Figure 1 Working timing diagram under the scheme, VDD is powered on, VDD_INT is generated by the internal bandgap reference and LDO. At the same time, the POR module generates the power-on reset signal "POR_RSTB" required by the digital. Under this scheme, the standby has the following limitations:

[0005] a) From sleep to wake-up, the I2C interface needs to be completed, which requires VDD_INT to be constant so that the digital module can process the command sent by the software to complete the wake-up operation.

[0006] The existence of VDD_INT requires both the bandgap reference and the internal LDO to be powered on during sleep mode, which results in additional standby power consumption; usually the bandgap reference plus the LDO consumes several uA of current.

[0007] b) As mentioned in a), the digital module does not need to work at this time, but VDD_INT needs to be charged to operate the wake-up command at any time. This causes leakage of the digital module when the chip is in standby mode. Especially at high temperatures, the leakage of digital circuits is often relatively large. (Generally, the leakage of digital circuits with tens of thousands of gates is also several uA).

[0008] c) Combining a) and b), in order to wake up the chip, its standby power consumption will cause additional standby power consumption because VDD_INT is always on.

[0009] Figure 3 Describes the status of each module in the chip during sleep. The main sources of standby power consumption are: working BG (bandgap reference), LDO, POR, and leakage of Digital Controller.

[0010] In order to solve the problem of extra standby power consumption in sleep mode, a "RESETN" pin can be introduced. The whole chip can be "reset" through the GPIO (General Purperse IO) of the main control chip. At this time, VDD_INT can be pulled to zero by PowerSwitch. LDO and BG can not work, and the digital part is not powered. Figure 4 However, this requires additional GPIO resources of the master controller, especially when the master controller has limited GPIO resources or in a system that requires multiple sensor ICs.

[0011] In standby mode, because it needs to be awakened at any time, there is a problem that the low-voltage power supply cannot be powered off. In this way, BG, LDO and POR need to work in real time, which increases the standby power consumption. The introduction of RESETB IO Pin can solve the problem of standby power consumption, but it requires additional IO resources, which is not accepted in some systems with tight IO resources. Summary of the invention

[0012] In view of the defects in the prior art, an object of the present invention is to provide a power supply system and a working method of a low quiescent current sensor chip and a sensor chip.

[0013] The power supply system of the low static current sensor chip provided by the present invention comprises: a bandgap reference, a low voltage dropout regulator, a power supply voltage, a power-on reset, a fuse, an oscillator, a digital controller, a sensor core, a level conversion, a standby power-on reset and a digital interface;

[0014] A power switch is connected between the bandgap reference, the low-voltage dropout regulator and the power supply voltage, and the bandgap reference, the low-voltage dropout regulator transmits the internal power supply voltage to the digital controller;

[0015] A power switch is connected between the power-on reset and the power supply voltage, and the power-on reset connection level conversion is carried out and the power-on reset signal is transmitted to the digital controller;

[0016] The fuse is directly connected to the supply voltage;

[0017] The oscillator transmits the clock signal to the digital controller. The oscillator uses a bandgap reference and an internal supply voltage generated by a low-dropout regulator.

[0018] The sensor core transmits data signals to the digital controller, and the digital controller transmits control signals to the sensor core. The sensor core uses an internal power supply voltage generated by a bandgap reference and a low-dropout regulator;

[0019] The digital controller is connected to the level converter, then to the digital interface, and then to the serial data line and serial clock line;

[0020] One end of the standby power-on reset is connected to the power supply voltage, and the other end is connected to the digital interface, and the standby power-on reset signal is transmitted to the digital interface;

[0021] The digital interface transmits the power switch control signal to the power switch. The digital interface is directly controlled by the external communication by connecting with the serial data line and the serial clock line.

[0022] Preferably, in the power-on reset stage: when the power supply is fully powered on, the standby power-on reset signal generated by the standby power-on reset becomes high, and the digital interface completes the reset release; the bandgap reference, low voltage dropout regulator, and power-on reset are all in the power grounding state and do not work; the oscillator, sensor core, and digital controller power supplies are in the grounding state; the fuse power supply is in the connected state, but does not work; in the power-on reset stage, the digital interface is reset by the standby power-on reset, and both the serial data line and the serial clock line IO are in the default state, and communication is impossible.

[0023] Preferably, after the power-on reset phase is over, the serial data line, serial clock line and digital interface default states have been released, the chip is in a sleep state, and the wake-up operation can be completed at any time through the serial data line and serial clock line.

[0024] Preferably, in the sleep stage: after completing the power-on reset and before the chip wakes up, the bandgap reference, low-dropout regulator, power-on reset, oscillator, sensor core and digital controller are all in a power grounding state; the fuse power supply is in an on state, but not working; the digital interface completes the reset and does not work; in the sleep stage, only the standby power-on reset is in a real-time low-power working state.

[0025] Preferably, in the wake-up stage: a wake-up instruction is sent through the serial data line and the serial clock line, the power switch is closed, the bandgap reference and the low-voltage dropout regulator start to start, the internal power supply voltage rises, the power-on reset signal sent by the power-on reset becomes high, and the digital controller is reset and released; the bandgap reference, the low-voltage dropout regulator, and the power-on reset start working, and the zero-power static mode is maintained after the fuse is read, the oscillator, the sensor core, and the digital controller are in a non-working state, and the standby power-on reset maintains a low-power working state.

[0026] Preferably, in the normal working stage: working instructions are written through the serial data line and the serial clock line, the bandgap reference, low dropout regulator, power-on reset, and standby power-on reset remain in working state, and the oscillator, sensor core and digital controller are awakened to work normally to collect and quantify relevant data.

[0027] The working method of the power supply system provided by the present invention comprises:

[0028] Power-on reset stage: When the power supply is fully powered on, the standby power-on reset signal generated by the standby power-on reset becomes high, and the digital interface completes the reset release; the bandgap reference, low-dropout regulator, and power-on reset are all in the power ground state and do not work; the oscillator, sensor core, and digital controller power are in the ground state; the fuse power supply is in the connected state, but does not work; the digital interface is reset by the standby power-on reset in the power-on reset stage, and both the serial data line and the serial clock line are in the default state, and communication is impossible; after the power-on reset stage, the serial data line, serial clock line, and digital interface default state have been released, the chip is in sleep state, and the wake-up operation can be completed at any time through the serial data line and serial clock line;

[0029] Sleep stage: After the power-on reset is completed, the chip is in the state before waking up. The bandgap reference, low-dropout regulator, power-on reset, oscillator, sensor core and digital controller are all in the power grounding state; the fuse power supply is connected but not working; the digital interface completes the reset but does not work; in the sleep stage, only the standby power-on reset is in a real-time low-power working state;

[0030] Wake-up phase: a wake-up command is sent through the serial data line and the serial clock line, the power switch is closed, the bandgap reference and the low-dropout regulator start to start, the internal power supply voltage rises, the power-on reset signal sent by the power-on reset becomes high, and the digital controller reset is released; the bandgap reference, the low-dropout regulator, and the power-on reset start to work, and the zero-power static mode is maintained after the fuse is read. The oscillator, the sensor core, and the digital controller are in a non-working state, and the standby power-on reset maintains a low-power working state;

[0031] Normal working phase: writing working instructions through the serial data line and serial clock line, the bandgap reference, low dropout regulator, power-on reset, and standby power-on reset remain in working state, and the oscillator, sensor core, and digital controller are awakened to work normally to collect and quantify relevant data.

[0032] The sensor chip provided according to the present invention comprises the power supply system of the low static current sensor chip.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] The present invention adds a high-voltage domain interface control module and related supporting circuits STBY_POR and a power switch. When the chip is in standby mode, the internal BG, LDO, POR, digital controller, and sensor core can be completely powered off, and only STBY_POR works in real time, so as to achieve the purpose of low standby power consumption without affecting the wake-up time of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0036] Figure 1 Provide power supply and PowerScenario solutions for existing Sensor chips;

[0037] Figure 2 It is the timing diagram of Power Sequence and Scenario under the existing scheme;

[0038] Figure 3 This is a working status diagram of the internal modules under the existing solution in standby mode;

[0039] Figure 4 To add "RESETB" IO Pin to reduce standby power consumption;

[0040] Figure 5 The power supply and PowerScenario solution proposed by the present invention;

[0041] Figure 6 It is the PowerSequence and Scenario timing diagram of the present invention;

[0042] Figure 7 This is a working state diagram of the internal modules of the present invention in standby mode. DETAILED DESCRIPTION

[0043] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0044] Example

[0045] The present invention proposes a power supply system for a low quiescent current sensor chip, specifically:

[0046] Add a high-voltage domain I2C DIG part to handle the wake-up of the I2C interface, so that all the internal low-voltage domain parts can be powered off, and the bandgap reference BG and LDO parts can also be turned off directly. Further reduce the standby power consumption. Of course, the I2C DIG part also needs a STBY POR circuit as its reset signal generation circuit. When the entire chip is in standby (sleep), only this "STBY POR" works, and its current consumption can be as small as <100nA~200nA.

[0047] The purpose of the present invention is to further reduce the standby power consumption of the Sensor chip without consuming IO resources.

[0048] In view of the limitation that the internal power supply of the existing sensor chip power supply solution needs to be always on in standby mode, this case adds I2C Dig digital control of the high-voltage power domain, STBY POR and related Power Switch to achieve the purpose of turning off the internal power supply in standby mode, thereby reducing standby power consumption. The specific block diagram is as follows Figures 5 to 7 shown.

[0049] Figure 5 is based on Figure 1 and Figure 4 Block diagram of the proposed solution to reduce standby power consumption. Figure 6 It is a diagram of the power-on sequence and power supply scenario of this solution. Figure 7 It is the working status of the internal module when the solution is in standby mode.

[0050] According to the following Figure 5 to Figure 7 , to describe the working status of each mode below.

[0051] like Figure 5 The power supply system of the low static current sensor chip includes: bandgap reference BG, low voltage dropout regulator LDO, power-on reset POR, fuse FUSE, oscillator OSC, digital controller Digital Controller, sensor core SensorCore, level conversion lev, standby power-on reset STBY POR and digital interface IIC DIG;

[0052] A power switch is connected between the bandgap reference BG, the low-dropout voltage regulator LDO and the power supply voltage VDD, and the bandgap reference BG and the low-dropout voltage regulator LDO transmit the internal power supply voltage VDD_INT to the digital controller Digital Controller;

[0053] A power switch is connected between the power-on reset POR and the power supply voltage VDD, the power-on reset POR connects the level conversion lev and transmits the power-on reset signal POR_RSTB to the digital controller Digital Controller;

[0054] The fuse FUSE is directly connected to the power supply voltage VDD;

[0055] The oscillator OSC transmits the clock signal Clock to the digital controller Digital Controller. The oscillator uses the internal power supply voltage VDD_INT generated by the bandgap reference BG and the low dropout regulator LDO.

[0056] The sensor core Sensor Core transmits a data signal Date to the digital controller Digital Controller, and the digital controller Digital Controller transmits a control signal Control Signal to the sensor core SensorCore. The sensor core uses the bandgap reference BG and the internal power supply voltage VDD_INT generated by the low-dropout regulator LDO;

[0057] The digital controller is connected to the level converter lev, then to the digital interface IIC DIG, and then to the serial data line SDA and the serial clock line SCL;

[0058] One end of the standby power-on reset STBY POR is connected to the power supply voltage VDD, and the other end is connected to the digital interface IIC DIG, and the standby power-on reset signal POR_RSTB_STBY is transmitted to the digital interface IIC DIG;

[0059] The digital interface IIC DIG transmits the power switch control signal POWER_EN to the power switch, and the connection between the digital interface IICDIG and the serial data line SDA and the serial clock line SCL is directly controlled by the external communication.

[0060] Power-on reset stage: When the power supply is fully powered on, the standby power-on reset signal POR_RSTB_STBY generated by the standby power-on reset STBY POR becomes high, and the digital interface IIC DIG completes the reset release; at this stage, the bandgap reference BG, the low-dropout regulator LDO, and the power-on reset POR are all in the power grounding state and do not work; the oscillator OSC, the sensor core Sensor Core, and the digital controller Digital Controller power are in the grounding state; the fuse FUSE power supply is in the connected state, but does not work; at this stage, the digital interface IIC DIG is reset by the standby power-on reset STBY POR, and the serial data line SDA and the serial clock line SCL are both in the default state, and communication is impossible; after this stage, the default state of the serial data line SDA, the serial clock line SCL, and the digital interface IIC DIG has been released, and the chip is in a sleep state, and the wake-up operation can be completed at any time through the serial data line SDA and the serial clock line SCL.

[0061] Sleep stage: After the power-on reset is completed, the chip is in the state before waking up. The bandgap reference BG, low-dropout regulator LDO, power-on reset POR, oscillator OSC, sensor core Sensor Core and digital controller Digital Controller are all in the power grounding state; the fuse FUSE power supply is connected but not working; the digital interface IIC DIG completes the reset and does not work; in this stage, only the standby power-on reset STBY POR is in the real-time low-power working state. The power consumption current is only 100~200nA.

[0062] Wake-up phase: The wake-up command is sent through the serial data line SDA and the serial clock line SCL, the power switch is closed, the bandgap reference BG and the low-dropout regulator LDO start to start, the internal power supply voltage VDD_INT rises, the power-on reset signal POR_RSTB sent by the power-on reset POR becomes high, and the digital controller Digital Controller is reset and released; in this state, the bandgap reference BG, the low-dropout regulator LDO, and the power-on reset POR start to work, the fuse FUSE is read and maintained in zero-power static mode, the oscillator OSC, the sensor core Sensor Core and the digital controller Digital Controller are in a non-working state, and the standby power-on reset STBY POR maintains a low-power working state. At this time, the current power consumption of the entire chip will be maintained at the order of several uA.

[0063] Normal working stage: the working instructions are written through the serial data line SDA and the serial clock line SCL, the whole chip is in normal working state, the bandgap reference BG, the low voltage dropout regulator LDO, the power-on reset POR, the standby power-on reset STBY POR remain in working state, the oscillator OSC, the sensor core Sensor Core and the digital controller Digital Controller are awakened to work normally to collect and quantify relevant data. The awakening to normal state can be completed by hardware, so that the awakening time can be controlled at the level of dozens of us.

[0064] The present invention also provides a working method of a power supply system, comprising:

[0065] Power-on reset stage: When the power supply is fully powered on, the standby power-on reset signal generated by the standby power-on reset becomes high, and the digital interface completes the reset release; the bandgap reference, low-dropout regulator, and power-on reset are all in the power ground state and do not work; the oscillator, sensor core, and digital controller power are in the ground state; the fuse power supply is in the connected state, but does not work; the digital interface is reset by the standby power-on reset in the power-on reset stage, and both the serial data line and the serial clock line are in the default state, and communication is impossible; after the power-on reset stage, the serial data line, serial clock line, and digital interface default state have been released, the chip is in sleep state, and the wake-up operation can be completed at any time through the serial data line and serial clock line;

[0066] Sleep stage: After the power-on reset is completed, the chip is in the state before waking up. The bandgap reference, low-dropout regulator, power-on reset, oscillator, sensor core and digital controller are all in the power grounding state; the fuse power supply is connected but not working; the digital interface completes the reset but does not work; in the sleep stage, only the standby power-on reset is in a real-time low-power working state;

[0067] Wake-up phase: a wake-up command is sent through the serial data line and the serial clock line, the power switch is closed, the bandgap reference and the low-dropout regulator start to start, the internal power supply voltage rises, the power-on reset signal sent by the power-on reset becomes high, and the digital controller reset is released; the bandgap reference, the low-dropout regulator, and the power-on reset start to work, and the zero-power static mode is maintained after the fuse is read. The oscillator, the sensor core, and the digital controller are in a non-working state, and the standby power-on reset maintains a low-power working state;

[0068] Normal working phase: writing working instructions through the serial data line and serial clock line, the bandgap reference, low dropout regulator, power-on reset, and standby power-on reset remain in working state, and the oscillator, sensor core, and digital controller are awakened to work normally to collect and quantify relevant data.

[0069] The present invention also provides a sensor chip, including a power supply system of the low static current sensor chip.

[0070] Those skilled in the art know that, in addition to implementing the system, device and its various modules provided by the present invention in a purely computer-readable program code, it is entirely possible to implement the same program in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers and embedded microcontrollers by logically programming the method steps. Therefore, the system, device and its various modules provided by the present invention can be considered as a hardware component, and the modules included therein for implementing various programs can also be considered as structures within the hardware component; the modules for implementing various functions can also be considered as both software programs for implementing the method and structures within the hardware component.

[0071] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A power supply system for a low quiescent current sensor chip, characterized in that: include: Bandgap references, low dropout regulators, power-on resets, fuses, oscillators, digital controllers, sensor cores, level shifting, standby power-on resets, and digital interfaces; A power switch is connected between the bandgap reference, the low-voltage dropout regulator and the power supply voltage, and the bandgap reference, the low-voltage dropout regulator transmits the internal power supply voltage to the digital controller; A power switch is connected between the power-on reset and the power supply voltage, and the power-on reset connection level conversion is carried out and the power-on reset signal is transmitted to the digital controller; The fuse is directly connected to the supply voltage; The oscillator transmits the clock signal to the digital controller. The oscillator uses a bandgap reference and an internal supply voltage generated by a low-dropout regulator. The sensor core transmits data signals to the digital controller, and the digital controller transmits control signals to the sensor core. The sensor core uses an internal power supply voltage generated by a bandgap reference and a low-dropout regulator; The digital controller is connected to the level converter, then to the digital interface, and then to the serial data line and serial clock line; One end of the standby power-on reset is connected to the power supply voltage, and the other end is connected to the digital interface, and the standby power-on reset signal is transmitted to the digital interface; The digital interface transmits the power switch control signal to the power switch. The digital interface is directly controlled by the external communication by connecting with the serial data line and the serial clock line.

2. The power supply system of the low quiescent current sensor chip according to claim 1, characterized in that: Power-on reset stage: When the power supply is fully powered on, the standby power-on reset signal generated by the standby power-on reset becomes high, and the digital interface completes the reset release; the bandgap reference, low-dropout regulator, and power-on reset are all in the power ground state and do not work; the oscillator, sensor core, and digital controller power supplies are in the ground state; the fuse power supply is in the connected state, but does not work; in the power-on reset stage, the digital interface is reset by the standby power-on reset, and both the serial data line and the serial clock line IO are in the default state, and communication is impossible.

3. The power supply system of the low quiescent current sensor chip according to claim 2, characterized in that: After the power-on reset phase, the serial data line, serial clock line and digital interface default state have been released, the chip is in sleep state, and the wake-up operation can be completed at any time through the serial data line and serial clock line.

4. The power supply system of the low quiescent current sensor chip according to claim 1, characterized in that: Sleep stage: After the power-on reset is completed, the chip is in the state before waking up. The bandgap reference, low-dropout regulator, power-on reset, oscillator, sensor core and digital controller are all in the power grounding state; the fuse power supply is connected but not working; the digital interface is reset but not working; During the sleep phase, only the standby power-on reset is in real-time low-power working state.

5. The power supply system of the low quiescent current sensor chip according to claim 1, characterized in that: Wake-up phase: a wake-up command is sent through the serial data line and the serial clock line, the power switch is closed, the bandgap reference and the low-dropout regulator start to start, the internal power supply voltage rises, the power-on reset signal sent by the power-on reset becomes high, and the digital controller reset is released; the bandgap reference, the low-dropout regulator, and the power-on reset start working, and the zero-power static mode is maintained after the fuse is read. The oscillator, the sensor core, and the digital controller are in a non-working state, and the standby power-on reset maintains a low-power working state.

6. The power supply system of the low quiescent current sensor chip according to claim 1, characterized in that: Normal working phase: writing working instructions through the serial data line and serial clock line, the bandgap reference, low dropout regulator, power-on reset, and standby power-on reset remain in working state, and the oscillator, sensor core, and digital controller are awakened to work normally to collect and quantify relevant data.

7. A method for operating a power supply system, characterized in that: A power supply system using the low quiescent current sensor chip according to any one of claims 1 to 6, comprising: Power-on reset stage: When the power supply is fully powered on, the standby power-on reset signal generated by the standby power-on reset becomes high, and the digital interface completes the reset release; the bandgap reference, low-dropout regulator, and power-on reset are all in the power ground state and do not work; the oscillator, sensor core, and digital controller power are in the ground state; the fuse power supply is in the connected state, but does not work; the digital interface is reset by the standby power-on reset in the power-on reset stage, and both the serial data line and the serial clock line are in the default state, and communication is impossible; after the power-on reset stage, the serial data line, serial clock line, and digital interface default state have been released, the chip is in sleep state, and the wake-up operation can be completed at any time through the serial data line and serial clock line; Sleep stage: After the power-on reset is completed, the chip is in the state before waking up. The bandgap reference, low-dropout regulator, power-on reset, oscillator, sensor core and digital controller are all in the power grounding state; the fuse power supply is connected but not working; the digital interface completes the reset but does not work; in the sleep stage, only the standby power-on reset is in a real-time low-power working state; Wake-up phase: a wake-up command is sent through the serial data line and the serial clock line, the power switch is closed, the bandgap reference and the low-dropout regulator start to start, the internal power supply voltage rises, the power-on reset signal sent by the power-on reset becomes high, and the digital controller reset is released; the bandgap reference, the low-dropout regulator, and the power-on reset start to work, and the zero-power static mode is maintained after the fuse is read. The oscillator, the sensor core, and the digital controller are in a non-working state, and the standby power-on reset maintains a low-power working state; Normal working phase: writing working instructions through the serial data line and serial clock line, the bandgap reference, low dropout regulator, power-on reset, and standby power-on reset remain in working state, and the oscillator, sensor core, and digital controller are awakened to work normally to collect and quantify relevant data.

8. A sensor chip, characterized in that: A power supply system comprising the low quiescent current sensor chip according to any one of claims 1 to 6.

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