Band-gap reference circuit resistant to single-particle transient effect and chip of band-gap reference circuit

Abstract

The invention belongs to the field of analog circuits, and particularly relates to a band-gap reference circuit capable of resisting a single-particle transient effect and a chip of the band-gap reference circuit. The scheme comprises a reference voltage generating circuit, a pulse width reinforcing circuit and an output circuit. Wherein the pulse width reinforcing circuit comprises a two-stage inverter and a transmission tube which are connected to a key node in the reference voltage generating circuit; the circuit can accelerate recovery of an abnormal state of the reference voltage generation circuit caused by a single-particle transient effect through a charge dissipation principle, and is used as a starting circuit of the reference voltage generation circuit. The output circuit is connected to an output node of the reference voltage generating circuit, detects the pulse amplitude of an output signal generated by the reference voltage generating circuit through a Schmitt trigger or a comparator and other devices, and then cuts off the part, exceeding a safety threshold value, in the output band-gap reference voltage signal. The problems that the output stability of an existing band-gap reference circuit is greatly influenced by the single-particle transient effect, and normal work in the radiation environment is difficult are solved.

Description

Technical Field

[0001] The invention belongs to the field of analog circuits, and in particular relates to a bandgap reference circuit and a chip thereof capable of resisting single particle transient effects. Background Art

[0002] With the advancement of world science and technology and the vigorous development of the aerospace industry, more and more electronic equipment is entering space with spacecraft. In the outer space environment, spacecraft are exposed to various cosmic ray radiation for a long time. Particles in the space radiation environment will penetrate the shielding layer of the spacecraft and interact with the integrated circuit to produce radiation effects, causing performance degradation or malfunction of electronic devices, and even causing system damage, affecting the safety of the spacecraft on orbit.

[0003] As a circuit that can provide a stable and independent voltage reference, the bandgap reference circuit is widely used in multiple circuit modules, such as DC / DC converters, low dropout linear regulators (LDO), analog-to-digital converters (ADC), digital-to-analog converters (DAC), and comparators. Existing bandgap references are sensitive to single-particle transient effects. In the space radiation environment, when heavy ions bombard the sensitive nodes of the bandgap reference circuit, SET disturbances will be generated along its propagation path, and eventually transient pulses will be generated on the output DC level. Therefore, all sub-circuit systems that rely on this reference voltage will be affected, resulting in errors and even global functional interruptions. Therefore, it is of great significance and necessity to design a bandgap reference circuit that can tolerate single-particle transient effects. Summary of the invention

[0004] In order to solve the problem that the output stability of the existing bandgap reference circuit is greatly affected by the single particle transient effect and is difficult to work normally in a radiation environment, the present invention provides a bandgap reference circuit and a chip thereof that are resistant to the single particle transient effect.

[0005] The technical solution provided by the present invention is:

[0006] A bandgap reference circuit resistant to single-particle transient effects, comprising: a reference voltage generating circuit, a pulse width reinforcement circuit and an output circuit. The reference voltage generating circuit is composed of PMOS tubes P1-P6, NMOS tubes N1-N4, resistors R1-R6, and PNP transistors Q1 and Q2. N1-N4, P1-P4, R4, and R5 form a Cascode current mirror structure. On the ground paths on both sides of the Cascode current mirror structure, the nodes connected to the drains of P3, P1, N3, and N1 are denoted as A, C, E, and G; the nodes connected to the drains of P4, P2, N4, and N2 are denoted as B, D, F, and H.

[0007] The pulse width reinforcement circuit is used to accelerate the recovery of the abnormal state of the reference voltage generation circuit caused by the single particle transient effect through the charge dissipation principle, and serves as the startup circuit of the reference voltage generation circuit. The pulse width reinforcement circuit is composed of PMOS tubes P7~P10, P12~P15, NMOS tubes N5, N7~N10, and transistor Q3. Among them, the gate of P8 is connected to node D, the drain of P8 is connected to the source of P7; the gate of P7 is connected to node F, and the drain of P7 is connected to the drain of N5. The gate of N5 is connected to node E; the source of N5 is connected to the emitter of Q3, and the connection point is recorded as node K. The base and collector of Q3 are grounded; the sources of P8~P10, P12~P15 are connected to VDD; the drains of P12 and N7 are connected to the gates of P13 and N8; the drains of P13 and N8 are connected to the gate of P9; the gates of P12 and N7 and the drain of P9 are connected to node C. The drains of P14 and N9 are connected to the gates of P15 and N10; the drains of P15 and N10 are connected to the gate of P10; the gates of P14 and N9 and the drain of P10 are connected to the node E; the sources of N7 to N10 are connected to the node K.

[0008] The output circuit is connected to the output node J of the reference voltage generating circuit and is used to output the required bandgap reference voltage through the output port Vout.

[0009] In the single-particle transient-resistant bandgap reference circuit provided by the present invention, the number ratio of Q3 in the pulse width reinforcement circuit to Q1 in the reference voltage generation circuit is 1:1; and the emitter voltages of Q1 and Q3 are made the same through N5, P7, and P8.

[0010] In the bandgap reference circuit for resisting single-particle transient effects provided by the present invention, the gate-source voltage of N7 in the pulse width reinforcement circuit is equal to the voltage difference from the gate of N3 to the emitter of Q1, and the gate-source voltage of N9 is equal to the voltage difference from the gate of N1 to the emitter of Q1. By adjusting the component parameters of N7, N8, P12, and P13, as well as the component parameters of N9, N10, P14, and P15, the tolerance of the pulse width reinforcement circuit to single-particle transient effects can be adjusted.

[0011] As a further improvement of the present invention, the logic of the pulse width reinforcement circuit starting the reference voltage generation circuit is: when VDD is powered on, the gate voltage of P9 and P10 is low, and P9 and P10 are turned on; thereby charging the gate terminals of N1 to N4 in the Cascode current mirror structure. After charging is completed, the outputs of nodes C and E are flipped by the two-stage inverter in the pulse width reinforcement circuit, so that the gates of P9 and P10 are high; at this time, P9 and P10 are turned off, isolating the pulse width reinforcement circuit from the reference voltage generation circuit.

[0012] As a further improvement of the present invention, the output circuit includes an output unit, a positive pulse detection unit and a negative pulse detection unit. The output unit includes a PMOS tube N6 and an NMOS tube N11; the drain of N6 is connected to the node J, the source of N6 and P11 are connected, and the drain of P11 is connected to the output port Vout.

[0013] The positive pulse detection unit is connected between the gate of N6 and the node J, and is used to turn off N6 when the output signal of the J node in the reference voltage generation circuit exceeds the preset safety threshold. The negative pulse detection unit is connected between the gate of P11 and the node J, and is used to turn off P11 when the output signal of the J node in the reference voltage generation circuit exceeds the preset safety threshold.

[0014] As a further improvement of the present invention, the positive pulse detection unit and the negative pulse detection unit are implemented using Schmitt triggers or comparator circuits; and the safety threshold of the pulse amplitude of the output bandgap reference voltage is adjusted by adjusting the component parameters in the positive pulse detection unit and the negative pulse detection unit.

[0015] As a further improvement of the present invention, the Schmitt trigger is composed of three PMOS tubes P16~P18 and three NMOS tubes N11~N13, and the circuit connection relationship is: the gates of P16, P17, N11, and N12 are connected to the output node of the reference voltage generating circuit; the source of P16 and the drain of N13 are connected to VDD; the drain of P16 is connected to the source of P17 and P18; the source of N11 and N13 is connected to the drain of N12; the source of N12 and the drain of P18 are grounded; the drains of P17 and N11 are connected to the gates of N13 and P18, and are used to connect the gates of the PMOS tube or NMOS tube to be controlled.

[0016] As a further improvement of the present invention, the circuit connection relationship of the cascode current mirror in the reference voltage generating circuit is:

[0017] The sources of P3 and P4 are connected to VDD; the drain of P3 is connected to the source of P1, and the connection point is recorded as node A; the drain of P4 is connected to the source of P2, and the connection point is recorded as node B; the drain of P1 is connected to the gates of N3 and N4 and one end of R4, and the connection point is recorded as C; the other end of R4 is connected to the drain of N3 and the gates of N1 and N2, and the connection point is recorded as E; the gates of P3 and P4 are connected to the drain of P2 and one end of R5, and the connection point is recorded as node D; the other end of R5 is connected to the gates of P1 and P2 and the drain of N4, and the connection point is recorded as node F; the source of N3 is connected to the drain of N1, and the connection point is recorded as G; the source of N4 is connected to the drain of N2, and the connection point is recorded as H.

[0018] As a further improvement of the present invention, the circuit connection relationship of the reference voltage generating circuit is as follows: the source of N1 is connected to the emitter of Q1 and grounded through R1; the source of N2 is connected to the emitter of Q1 through R3 and grounded through R2; the collectors and bases of Q1 and Q2 are grounded. The source of P6 is connected to VDD; the gate of P6 is connected to node D; the drain of P6 is connected to the source of P5, and the connection point is marked as I; the gate of P5 is connected to node F; the drain of P5 is grounded through R6, and the connection point between the two is marked as node J.

[0019] The present invention also includes a chip, which adopts the aforementioned bandgap reference circuit resistant to single-particle transient effects.

[0020] The technical solution provided by the present invention has the following beneficial effects:

[0021] The bandgap reference circuit for resisting single-particle transient effects provided by the present invention adopts a newly designed pulse width reinforcement circuit, which can, on the one hand, utilize the principle of charge dissipation to accelerate the recovery process of the circuit from an abnormal state under radiation bombardment, and shorten the pulse width of the circuit output when it is affected by radiation. On the other hand, it can also be used as a startup circuit for a reference voltage generating circuit in the circuit, and realize automatic isolation of the two after the latter is started, thereby minimizing the impact on the stability of the output signal.

[0022] The improved bandgap reference circuit provided by the present invention also introduces a special pulse amplitude reinforcement mechanism in the output module. The circuit can detect the pulse amplitude of the output of the reference voltage generating circuit through devices such as a Schmitt trigger or a comparator, and then automatically cut off the output of the circuit when the amplitude of the output signal exceeds a preset safety threshold, thereby alleviating the impact of radiation bombardment on the amplitude of the circuit output.

[0023] In addition, the circuit designed by the present invention not only has excellent performance compared with the traditional circuit, but also maintains a small area overhead. The circuit can achieve good suppression of single-particle transient impact while avoiding the increase of circuit power consumption, so it has outstanding practical value and is suitable for large-scale promotion and application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a circuit diagram of the traditional bandgap reference circuit introduced in Embodiment 1 of the present invention.

[0025] Figure 2 A circuit diagram of a bandgap reference circuit resistant to single event transient effects using a pulse width reinforcement circuit is provided in Embodiment 1 of the present invention.

[0026] Figure 3 This is a circuit diagram of a bandgap reference circuit for resisting single event transient effects and having both pulse width reinforcement and pulse amplitude reinforcement functions provided in Example 1 of the present invention.

[0027] Figure 4 It is the signal flow diagram of the circuit of the present invention at the startup stage in the test experiment.

[0028] Figure 5-Figure 7 The figure is a comparison diagram of the output waveforms of three typical nodes in the circuit of the present invention and the traditional circuit after being bombarded by a single particle transient pulse in the test experiment.

[0029] Figure 8 The Monte Carlo curve of the output voltage of the circuit of the present invention changing with temperature under the condition of -40°C to 150°C in the test experiment.

[0030] Fig. 9 It is a histogram of the temperature drift coefficient of the output voltage of the circuit of the present invention in the test experiment.

[0031] Fig.10 The output voltage histogram is used to characterize the output stability of the circuit of the present invention under different process angles in the test experiment.

[0032] Fig.11 This is the layout design of the circuit of the present invention in the test experiment. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0034] Example 1

[0035] This embodiment provides a bandgap reference circuit that is resistant to single-event transient effects. Figure 1 The technical solution provided in this embodiment is improved on the basis of the traditional bandgap reference circuit using the cascode current mirror structure. Figure 1 The startup part used in the traditional bandgap reference circuit is upgraded to a more excellent pulse width reinforcement circuit, so that the large amount of excess charge generated by the circuit when bombarded by radiation is dissipated faster, shortening the pulse width generated at the output end. On the other hand, this embodiment also Figure 1 The output end of the traditional bandgap reference circuit is improved, and the actual output of the bandgap reference circuit is detected in real time through the improved circuit, and the pulse output with excessive amplitude is isolated at the output end until the bandgap reference voltage generating circuit resumes normal operation.

[0036] Specifically, Figure 1The conventional bandgap reference circuit shown in the figure consists of two parts: a reference voltage generating circuit and a startup circuit. The reference voltage generating circuit consists of 6 PMOS transistors P1 to P6, 4 NMOS transistors N1 to N4, 6 resistors R1 to R6, and 2 PNP transistors Q1 and Q2. In the reference voltage generating circuit, N1 to N4, P1 to P4, R4, and R5 form a cascode current mirror structure. The circuit connection relationship of the cascode current mirror is as follows: the sources of P3 and P4 are connected to VDD; the drain of P3 is connected to the source of P1, and the connection point is recorded as node A; the drain of P4 is connected to the source of P2, and the connection point is recorded as node B; the drain of P1 is connected to the gates of N3 and N4 and one end of R4, and the connection point is recorded as C; the other end of R4 is connected to the drain of N3 and the gates of N1 and N2, and the connection point is recorded as E; the gates of P3 and P4 are connected to the drain of P2 and one end of R5, and the connection point is recorded as node D; the other end of R5 is connected to the gates of P1 and P2 and the drain of N4, and the connection point is recorded as node F; the source of N3 is connected to the drain of N1, and the connection point is recorded as G; the source of N4 is connected to the drain of N2, and the connection point is recorded as H.

[0037] Except for the cascode current mirror, the circuit connection relationship of the rest of the reference voltage generation circuit is as follows: the source of P6 is connected to VDD; the gate of P6 is connected to node D; the drain of P6 is connected to the source of P5, and the connection point is marked as I; the gate of P5 is connected to node F; the drain of P5 is grounded through R6, and the connection point between the two is marked as node J. The source of N1 is connected to the emitter of Q1 and grounded through R1; the source of N2 is connected to the emitter of Q1 through R3 and grounded through R2; the collectors and bases of Q1 and Q2 are grounded.

[0038] In the reference voltage generating circuit provided in this embodiment, P5 and P6 provide bias for the reference voltage generating part through current mirror image; the current mirror composed of P1 to P4 makes the current flowing through N1 and N2 the same, so that the source terminal voltage of N1 and N2 is the same. Figure 1 In the reference voltage generating circuit part, the resistance values ​​of R1 and R2 are equal, and the currents on R1 and R2 are the same, ensuring that the currents flowing through Q1 and Q2 are the same.

[0039] Figure 1 The startup circuit in the traditional bandgap reference circuit shown in the figure is composed of two PMOS tubes and a capacitor C1; the source of P7 and P8 is connected to VDD; the drain of P7 and the gate of P8 are connected to the upper plate of C1; the gate of P7 and the lower plate of C1 are grounded; the drain of P8 is connected to the node C in the cascode current mirror. The working principle of the startup circuit is:

[0040] Since the gate of P7 is grounded, the gate voltage of P7 is always 0 potential; the gate of P8 is connected to capacitor C1, and the gate of P8 is also 0 potential when it is not powered on. When VDD is powered on, the source voltage V GS When the threshold voltage Vth is exceeded, P7 and P8 are turned on. P8 charges the gates of N1 to N4 of the core circuit to complete the normal power-on process of the circuit; P7 charges the capacitor C1 to ensure that the circuit is powered on, and after the circuit is powered on, the voltage of C1 (i.e., the gate voltage of P8) is raised to a high level, so that P8 is turned off after the circuit is powered on and starts to work normally, and the startup circuit will not affect the operation of the core circuit.

[0041] exist Figure 1 Based on the circuit shown in FIG. 1 , the circuit structure of the bandgap reference circuit for resisting single-particle transient effect provided in this embodiment is as follows: Figure 2 As shown, it includes three parts: reference voltage generating circuit, pulse width reinforcement circuit and output circuit.

[0042] Among them, the reference voltage generation circuit still uses Figure 1 The circuit design shown is composed of PMOS tubes P1-P6, NMOS tubes N1-N4, resistors R1-R6, and PNP transistors Q1 and Q2.

[0043] The pulse width reinforcement circuit is used to accelerate the recovery of the abnormal state of the reference voltage generation circuit caused by the single particle transient effect through the charge dissipation principle, and serves as a startup circuit of the reference voltage generation circuit. Figure 2 It can be seen that the pulse width reinforcement circuit in this embodiment is composed of PMOS tubes P7~P10, P12~P15, NMOS tubes N5, N7~N10, and triode Q3. Among them, the gate of P8 is connected to node D, the drain of P8 is connected to the source of P7; the gate of P7 is connected to node F, and the drain of P7 is connected to the drain of N5. The gate of N5 is connected to node E; the source of N5 is connected to the emitter of Q3, and the connection point is recorded as node K. The base and collector of Q3 are grounded; the sources of P8~P10, P12~P15 are connected to VDD; the drains of P12 and N7 are connected to the gates of P13 and N8; the drains of P13 and N8 are connected to the gate of P9; the gates of P12 and N7 and the drain of P9 are connected to node C. The drains of P14 and N9 are connected to the gates of P15 and N10; the drains of P15 and N10 are connected to the gate of P10; the gates of P14 and N9 and the drain of P10 are connected to the node E; the sources of N7 to N10 are connected to the node K.

[0044] The output circuit is connected to the output node J of the reference voltage generating circuit and is used to output the required bandgap reference voltage through the output port Vout. In practical applications, in this embodiment, the output node J of the reference voltage generating circuit can be directly connected to the output port Vout to achieve direct output of the bandgap reference voltage signal generated by the reference voltage generating circuit. Of course, in other more optimized solutions, isolation or filtering devices can also be used to select and output the generated bandgap reference voltage signal.

[0045] Specifically, the pulse width reinforcement circuit in this embodiment can be further divided into a first part consisting of P7, P8, N5 and Q3. And two identical second parts consisting of P9, P12, P13, N7, N8, and P10, P14, P15, N9, N10. The number ratio of Q3 in the pulse width reinforcement circuit of this embodiment to Q1 in the reference voltage generating circuit is 1:1; N5, P7, P8 in the first part can make the emitter voltages of Q1 and Q3 the same, so as to ensure that the gate-source voltage of N7 is equal to the voltage difference from the gate of N3 to the emitter of Q1, and the gate-source voltage of N9 is equal to the voltage difference from the gate of N1 to the emitter of Q1.

[0046] It is well known that when a circuit is bombarded with radiation, the voltage of the corresponding node in it will change. Figure 1 In the conventional circuit shown, taking node B as an example, radiation bombardment will cause the gate voltage of P1~P4 of the circuit to rise and the gate voltage of N1~N4 to drop. At this time, the current of the branch where P3 and P4 are located decreases, the dissipation speed of the large amount of excess charge generated by the circuit due to radiation decreases, the dissipation time increases, and ultimately the pulse width of the bandgap reference voltage signal output by the circuit increases.

[0047] In the embodiment provided Figure 2 In the bandgap reference circuit with the pulse width reinforcement circuit shown, the gate-source voltage of N7 in the second part of the pulse width reinforcement circuit is equal to the voltage difference from the gate of N3 to the emitter of Q1, and the gate-source voltage of N9 is equal to the voltage difference from the gate of N1 to the emitter of Q1. Taking node B as an example, once the node is bombarded by radiation, a large number of holes will be generated at node B due to radiation, and the gate voltages of N1 to N4 will drop, that is, the gate-source voltages of N7 and N9 will drop, and the two-stage inverter will output a low level, and P9 and P10 will be turned on to charge the gates of N1 to N4. Ensure that the drain current on N2 and N4 is large, accelerate the dissipation speed of the excess holes at node B through nodes N2 and N4, and thus shorten the pulse width generated at the output end of the circuit due to radiation.

[0048] In combination with the functional principle of the pulse width reinforcement circuit in the bandgap reference circuit for single-particle transient effect resistance provided in this embodiment, it can also be found that the component parameters of N7, N8, P12, P13, and N9, N10, P14, and P15, such as the width-to-length ratio, will affect the circuit's tolerance to single-particle transient effects. By matching the parameters of the above-mentioned MOS tubes, the tolerance of the bandgap reference circuit for single-particle transient effect resistance to radiation can meet the requirements.

[0049] In addition to suppressing the influence of radiation on the pulse width of the circuit output, the pulse width reinforcement circuit in the circuit provided in this embodiment can also be used as a startup circuit to start the reference voltage generation circuit when VDD is powered on. Specifically, the logic of the pulse width reinforcement circuit starting the reference voltage generation circuit is:

[0050] When VDD is powered on, the gate voltage of P9 and P10 is low, and P9 and P10 are turned on, thereby charging the gate terminals of N1 to N4 in the Cascode current mirror structure. During the charging process, the voltage of nodes C and E continues to increase; when charging is completed, the output of nodes C and E is flipped by the two-stage inverter in the pulse width reinforcement circuit, making the gates of P9 and P10 high; at this time, P9 and P10 are turned off, isolating the pulse width reinforcement circuit from the reference voltage generation circuit.

[0051] It can be seen that under normal working mode, the pulse width reinforcement circuit in the bandgap reference circuit resistant to single-particle transient effects provided in this embodiment will automatically be isolated from the reference voltage generating circuit after completing the circuit startup task, thereby avoiding affecting the normal function of the reference voltage generating circuit.

[0052] The influence of radiation bombardment on the reference voltage generating circuit not only increases the pulse width of the bandgap reference voltage signal outputted by the circuit, but also may cause the amplitude of the bandgap reference voltage signal outputted by the circuit to increase. In view of this problem, in the more optimized solution provided in this embodiment, the output circuit part of the bandgap reference circuit resistant to single-particle transient effects can be further improved as follows: Figure 3 The circuit shown includes an output unit, a positive pulse detection unit and a negative pulse detection unit. The output unit includes a PMOS tube N6 and an NMOS tube N11; the drain of N6 is connected to the node J, the source of N6 and P11 are connected, and the drain of P11 is connected to the output port Vout.

[0053] Among them, the positive pulse detection unit is connected between the gate of N6 and node J, and is used to turn off N6 when the output signal of node J in the reference voltage generation circuit exceeds the preset safety threshold. The negative pulse detection unit is connected between the gate of P11 and node J, and is used to turn off P11 when the output signal of node J in the reference voltage generation circuit exceeds the preset safety threshold. That is, the output circuit will only output the bandgap reference voltage signal whose voltage amplitude is within the safety threshold range generated by the reference voltage generation circuit, and the signal components that are higher than the safety threshold will be shielded to achieve signal gating.

[0054] It can be seen from this that: Figure 3 The output module shown is essentially a pulse amplitude reinforcement circuit for reinforcing the pulse amplitude of the output signal of the reference voltage generating circuit, thereby alleviating the problem of excessive output pulse amplitude caused by the circuit being affected by radiation bombardment. In actual application, the positive pulse detection unit and the negative pulse detection unit in the pulse amplitude reinforcement circuit can be implemented using a Schmitt trigger or a comparator circuit. And by adjusting the component parameters (such as size, etc.) in the positive pulse detection unit and the negative pulse detection unit, the circuit's high sensitivity to the output amplitude is adjusted, so that the safety threshold of the pulse amplitude of the output bandgap reference voltage can be controlled. Specifically, as Figure 4 As shown, the Schmitt trigger used in the solution provided in this embodiment is composed of three PMOS tubes P16~P18 and three NMOS tubes N11~N13, and the circuit connection relationship is: the gates of P16, P17, N11, and N12 are connected to the output node of the reference voltage generating circuit; the source of P16 and the drain of N13 are connected to VDD; the drain of P16 is connected to the source of P17 and P18; the source of N11 and N13 is connected to the drain of N12; the source of N12 and the drain of P18 are grounded; the drains of P17 and N11 are connected to the gates of N13 and P18, and are used to connect the gates of the PMOS tube or NMOS tube to be controlled.

[0055] In summary, the bandgap reference circuit resistant to single-particle transient effects provided by this embodiment includes a reference voltage generating circuit, a pulse width reinforcement circuit, and an output circuit with a pulse amplitude reinforcement function. During operation, the pulse width reinforcement circuit is first used to start the reference voltage generating circuit. When the reference voltage generating circuit is working normally, the P9 and P10 tubes in the pulse width reinforcement circuit are turned off, and then partially isolated from the reference voltage generating circuit to avoid affecting the normal operation of the reference voltage generating circuit. When the reference voltage generating circuit is working normally, N6 and P11 in the pulse amplitude reinforcement circuit are turned on, and the bandgap reference voltage signal output by the reference voltage generating circuit is transmitted normally to the output terminal Vout. Once the circuit is affected by radiation, so that the bandgap reference voltage signal output by the reference voltage generating circuit deviates from the ideal value, the Schmitt trigger in the output circuit with a pulse amplitude reinforcement function will detect the corresponding situation and turn off N6 or P11 to prevent the output terminal from generating a pulse with an excessive amplitude until the bandgap reference voltage generating circuit resumes normal operation.

[0056] Performance Testing

[0057] In order to verify the performance of the bandgap reference circuit for resisting single-particle transient effects provided by the present invention, the technicians Figure 3 The bandgap reference circuit scheme of the present invention is simulated and compared with the existing Figure 1 The unhardened bandgap reference circuit shown in Figure 1 is compared to test the circuit performance when bombarded by radiation pulses. Specifically, a double exponential current source is used to simulate the scenario where the circuit is affected by a single-particle transient.

[0058] 1. Circuit startup

[0059] This experiment first tests the normal function of the circuit provided by the present invention, and visualizes the signals of the power supply voltage VDD and the output bandgap reference voltage during the power-on process of the circuit. The obtained signal flow diagram is as follows: Figure 4 shown.

[0060] analyze Figure 4 It can be found that the VDD signal starts to power on at 1μs and completes power on at 2μs. The bandgap reference voltage output by the circuit starts to rise at 2.2μs and starts to stabilize at 2.78μs. The output bandgap reference voltage remains stable in the subsequent process.

[0061] It can be seen that the pulse width reinforcement circuit in the single-particle transient-resistant bandgap reference circuit designed by the present invention can be used as a startup circuit, and then the reference voltage generating circuit is started after the system is powered on so that the latter starts working, and the startup speed of the circuit of the present invention is relatively fast.

[0062] 2. Radiation pulse bombardment

[0063] This experiment further compared Figure 1 and Figure 3 The output performance of the unreinforced and reinforced bandgap reference circuits in the single-particle transient pulse bombardment. In order to cover various typical radiation bombardment scenarios, this experiment selected the A node whose pulse width and assignment of the output signal changed little under the bombardment, the B node whose pulse width of the output signal increased significantly under the bombardment, and the J node whose amplitude of the output signal increased significantly under the bombardment for comparative testing.

[0064] During the test, when the existing unreinforced circuit and the reinforced circuit of the present invention work normally, the A, B, and J nodes of the two circuits are subjected to radiation bombardment tests at 1 μs. The waveforms of the bandgap reference voltage signals output by the two circuits are compared. Figure 5-Figure 7 Analysis Figure 5-Figure 7 It can be found that the amplitude and width of the SET transient pulse generated by the existing circuit after being bombarded by radiation will be significantly increased, while the amplitude and width of the SET transient pulse generated by the circuit of the present invention after being bombarded by radiation will be significantly reduced, and when the circuit of the present invention is induced by the single particle transient effect to cause signal fluctuations, the transient peak value of the bandgap reference voltage signal finally output is no higher than 1.3V, so the back-end devices using the circuit can be protected.

[0065] 3. Temperature adaptability

[0066] In order to test the applicable working environment temperature of the bandgap reference circuit for single-particle transient effect provided by the present invention, the technicians tested the change of the signal output generated by the circuit under the extreme environment temperature conditions of -40℃ to 150℃ with temperature. Then, the experimental data were plotted as follows: Figure 8 The Monte Carlo curve of the output voltage versus temperature shown in Fig. 9 A histogram of the temperature drift coefficient of the circuit shown.

[0067] Combination Figure 8 and Fig. 9 From the data, it can be found that the average temperature drift coefficient of the circuit in 2000 Monte Carlo tests is only 10.9; the output stability under different temperature conditions is high; and under the huge temperature difference of 190℃, the fluctuation range of the signal output does not exceed 2.5%, showing outstanding temperature adaptability. Therefore, the circuit provided in this embodiment can work normally under harsh temperature environment conditions of -40℃ to 150℃.

[0068] 4. Output stability

[0069] In this experiment, the circuit was tested 2000 times under different process angles and adaptation conditions under the same power supply voltage and room temperature. Then the circuit output under different conditions was counted and plotted. Fig.10 The circuit shown is a histogram of the output voltage at room temperature.

[0070] By analyzing the data in the figure, it can be found that the average output voltage of the circuit of the present invention during the test is 1.215V, the variance is 0.004533V, and the 3σ accuracy of the output voltage is 1.12%, which shows that the stability of the output voltage of the circuit of the present invention at room temperature is very outstanding.

[0071] 4. Layout and power consumption

[0072] This experiment also aims at Figure 3 The circuit scheme shown in the figure is designed for layout design, and the circuit layout obtained is as follows Fig.11 As shown, analysis Fig.11 In the layout, you can find:

[0073] The final layout area of ​​the present invention is 0.0079mm 2 , after reinforcement, it only increases by 392.3um compared with before reinforcement 2 This shows that although the solution of the present invention adds a new circuit module, it does not require excessive area loss. The power consumption after reinforcement is still within an acceptable range, and the reinforced bandgap reference circuit has basically no impact on other performances compared to the unreinforced circuit, so it can be widely used and promoted.

[0074] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A bandgap reference circuit resistant to single event transient effects, characterized in that: It includes: The reference voltage generating circuit is composed of PMOS tubes P1-P6, NMOS tubes N1-N4, resistors R1-R6, and PNP transistors Q1 and Q2; wherein N1-N4, P1-P4, R4, and R5 form a cascode current mirror structure; on the ground paths on both sides of the cascode current mirror structure, the nodes connected to the drains of P3, P1, N3, and N1 are denoted as A, C, E, and G; the nodes connected to the drains of P4, P2, N4, and N2 are denoted as B, D, F, and H; A pulse width reinforcement circuit is used for accelerating the recovery of an abnormal state of a reference voltage generating circuit caused by a single particle transient effect through the charge dissipation principle, and serving as a startup circuit of the reference voltage generating circuit; the pulse width reinforcement circuit is composed of PMOS tubes P7-P10, P12-P15, NMOS tubes N5, N7-N10, and a triode Q3; wherein the gate of P8 is connected to a node D, the drain of P8 is connected to the source of P7; the gate of P7 is connected to a node F, the drain of P7 is connected to the drain of N5; the gate of N5 is connected to a node E; the source of N5 is connected to the The emitters are connected, and the connection point is marked as node K; the base and collector of Q3 are grounded; the sources of P8~P10, P12~P15 are connected to VDD; the drains of P12 and N7 are connected to the gates of P13 and N8; the drains of P13 and N8 are connected to the gate of P9; the gates of P12 and N7 and the drain of P9 are connected to node C; the drains of P14 and N9 are connected to the gates of P15 and N10; the drains of P15 and N10 are connected to the gate of P10; the gates of P14 and N9 and the drain of P10 are connected to node E; the sources of N7~N10 are connected to node K; The output circuit is connected to the output node J of the reference voltage generating circuit and is used to output the required bandgap reference voltage through the output port Vout.

2. The single event transient (SEET) resistant bandgap reference circuit according to claim 1, wherein: The number ratio of Q3 in the pulse width reinforcement circuit to Q1 in the reference voltage generation circuit is 1:1; and the emitter voltages of Q1 and Q3 are made the same through N5, P7, and P8.

3. The single event transient resistant bandgap reference circuit according to claim 2, characterized in that: In the pulse width reinforcement circuit, the gate-source voltage of N7 is equal to the voltage difference from the gate of N3 to the emitter of Q1, and the gate-source voltage of N9 is equal to the voltage difference from the gate of N1 to the emitter of Q1; by adjusting the component parameters of N7, N8, P12, P13, and the component parameters of N9, N10, P14, and P15, the tolerance of the pulse width reinforcement circuit to single-particle transient effects can be adjusted.

4. The single event transient resistant bandgap reference circuit according to claim 2, characterized in that: The logic of the pulse width reinforcement circuit starting the reference voltage generation circuit is: When VDD is powered on, the gate voltage of P9 and P10 is at a low level, and P9 and P10 are turned on; thereby charging the gate terminals of N1 to N4 in the Cascode current mirror structure; after charging is completed, the outputs of nodes C and E are flipped by the two-stage inverter in the pulse width reinforcement circuit, so that the gates of P9 and P10 are at a high level; at this time, P9 and P10 are turned off, and the pulse width reinforcement circuit is isolated from the reference voltage generation circuit.

5. The single event transient resistant bandgap reference circuit according to claim 1, wherein: The output circuit includes an output unit, a positive pulse detection unit and a negative pulse detection unit; the output unit includes a PMOS tube N6 and an NMOS tube N11, the drain of N6 is connected to the node J, the source of N6 and P11 are connected, and the drain of P11 is connected to the output port Vout; the positive pulse detection unit is connected between the gate of N6 and the node J, and is used to turn off N6 when the output signal of the J node in the reference voltage generation circuit exceeds a preset safety threshold; The negative pulse detection unit is connected between the gate of P11 and the node J, and is used to turn off P11 when the output signal of the node J in the reference voltage generation circuit exceeds a preset safety threshold.

6. The single event transient resistant bandgap reference circuit according to claim 5, characterized in that: The positive pulse detection unit and the negative pulse detection unit are implemented by using a Schmitt trigger or a comparator circuit; The safety threshold of the pulse amplitude of the output bandgap reference voltage is adjusted by adjusting the component parameters in the positive pulse detection unit and the negative pulse detection unit.

7. The single event transient resistant bandgap reference circuit according to claim 6, characterized in that: The Schmitt trigger is composed of three PMOS tubes P16 to P18 and three NMOS tubes N11 to N13, and the circuit connection relationship is: The gates of P16, P17, N11, and N12 are connected to the output node of the reference voltage generating circuit; the source of P16 and the drain of N13 are connected to VDD; the drain of P16 is connected to the source of P17 and P18; the source of N11 and N13 is connected to the drain of N12; the source of N12 and the drain of P18 are grounded; the drains of P17 and N11 are connected to the gates of N13 and P18, and are used to connect the gates of the PMOS tube or NMOS tube to be controlled.

8. The single event transient resistant bandgap reference circuit according to claim 1, characterized in that: The circuit connection relationship of the cascode current mirror in the reference voltage generating circuit is: The sources of P3 and P4 are connected to VDD; the drain of P3 is connected to the source of P1, and the connection point is recorded as node A; the drain of P4 is connected to the source of P2, and the connection point is recorded as node B; the drain of P1 is connected to the gates of N3 and N4 and one end of R4, and the connection point is recorded as C; the other end of R4 is connected to the drain of N3 and the gates of N1 and N2, and the connection point is recorded as E; the gates of P3 and P4 are connected to the drain of P2 and one end of R5, and the connection point is recorded as node D; the other end of R5 is connected to the gates of P1 and P2 and the drain of N4, and the connection point is recorded as node F; the source of N3 is connected to the drain of N1, and the connection point is recorded as G; the source of N4 is connected to the drain of N2, and the connection point is recorded as H.

9. The single event transient (SEET) resistant bandgap reference circuit according to claim 1, wherein: The circuit connection relationship of the reference voltage generating circuit is: The source of N1 is connected to the emitter of Q1 and grounded through R1; the source of N2 is connected to the emitter of Q1 through R3 and grounded through R2; the collectors and bases of Q1 and Q2 are grounded; the source of P6 is connected to VDD; the gate of P6 is connected to node D; the drain of P6 is connected to the source of P5, and the connection point is marked as I; the gate of P5 is connected to node F; the drain of P5 is grounded through R6, and the connection point between the two is marked as node J.

10. A chip, characterized in that: It adopts the bandgap reference circuit resistant to single-particle transient effects as described in any one of claims 1-9.

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