Band-gap reference circuit based on high-order temperature compensation

Abstract

The invention belongs to the field of analog integrated circuit design, and particularly relates to a band-gap reference circuit based on high-order temperature compensation. Only two operational amplifiers are used, by means of the clamping function of the operational amplifiers twice, PTAT current with a monomial coefficient is generated through the voltage difference of emitter-base voltages of two bipolar transistors firstly, then CTAT current with a logarithmic coefficient is generated, and then PTAT current with the logarithmic coefficient is obtained; respectively converting the two PTAT currents into a voltage with a primary term positive temperature coefficient and a voltage with a logarithmic term positive temperature coefficient by using a resistor, and compensating a primary term negative temperature coefficient and a logarithmic term negative temperature coefficient of the emitter-base voltage of the bipolar transistor by using the two different types of positive temperature coefficient voltages; and finally, the reference output voltage with the zero temperature coefficient is obtained. The method is realized by adopting a 0.18 mu m process, can be industrialized, and is wider in application range; and the method is not influenced by temperature, power supply voltage and process fluctuation.

Description

Technical Field

[0001] The invention belongs to the field of analog integrated circuit design, and in particular relates to a bandgap reference circuit based on high-order temperature compensation. Background Art

[0002] The bandgap reference circuit is a circuit that can provide a stable reference voltage. Its output voltage is usually independent of the supply voltage and temperature changes. Therefore, it is widely used in analog circuits, mixed analog and digital circuits, and high-precision electronic devices. The traditional bandgap reference circuit achieves temperature compensation by combining a voltage with a positive temperature coefficient (usually generated by the thermoelectric potential difference of a diode) and a voltage with a negative temperature coefficient (generated by the PN junction voltage of a diode), thereby achieving an output with a zero temperature coefficient within a certain temperature range.

[0003] However, traditional bandgap reference circuits usually only provide first-order temperature compensation, which means that their temperature coefficients will still show nonlinear changes over a large range, resulting in limited accuracy of the output voltage, especially in wide temperature range applications. How to further improve the temperature stability of the reference circuit has become a problem to be solved. Summary of the invention

[0004] In view of the above problems or deficiencies, the purpose of the present invention is to provide a bandgap reference voltage source with a low temperature drift coefficient and high precision at -40 to 125°C. The circuit is not affected by temperature, power supply voltage, and process fluctuations, and stably outputs the set bandgap reference voltage. The bandgap circuit is different from the previous first-order temperature compensation. It adopts a high-order temperature compensation method to compensate the high-order terms of the emitter-base voltage of the bipolar transistor with respect to temperature, thereby obtaining a reference voltage VREF with a low temperature drift coefficient and high precision. The present invention is implemented using a 0.18μm process, can be industrialized, and has a wider range of applications.

[0005] To achieve the above objectives, the present invention adopts the following technical solutions:

[0006] A bandgap reference circuit based on high-order temperature compensation comprises a bandgap reference core circuit, a temperature compensation circuit and a start-up circuit.

[0007] The bandgap reference core circuit includes a first transistor Q1, a second transistor Q2, a first resistor R1, a third PMOS transistor MP3, a fourth PMOS transistor MP4 and a first operational amplifier OP1.

[0008] The base and collector of the first triode Q1 are short-circuited and grounded, and the emitter is connected to the drain of the third PMOS tube MP3 and the non-inverting input terminal of the first operational amplifier OP1 through the first resistor R1; the base and collector of the second triode Q2 are short-circuited and grounded, and the emitter is connected to the drain of the fourth PMOS tube MP4 and the inverting input terminal of the first operational amplifier OP1; the gate of the third PMOS tube MP3 is connected to the gate of the fourth PMOS tube MP4, and is connected to the output terminal of the first operational amplifier OP1, and the source of the third PMOS tube MP3 and the source of the fourth PMOS tube MP4 are both connected to the power supply voltage.

[0009] The temperature compensation circuit includes a third transistor Q3, a third NMOS transistor MN3, a fifth PMOS transistor MP5, a second resistor R2, a third resistor R3, a fourth resistor R4 and a second operational amplifier OP2.

[0010] The base and collector of the third triode Q3 are short-circuited and grounded, and the emitter is connected to the drain of the third NMOS tube MN3 through the fourth resistor R4; the gate of the fifth PMOS tube MP5 is connected to the gate of the fourth PMOS tube MP4, the source thereof is connected to the power supply voltage, and the drain is also connected to the drain of the third NMOS tube MN3 through the second resistor R2; one end of the third resistor R3 is grounded, and the other end is connected to the source of the third NMOS tube MN3 and the inverting input end of the second operational amplifier OP2; the non-inverting input end of the second operational amplifier OP2 is connected to the inverting input end of the first operational amplifier OP1, and the output end of the second operational amplifier OP2 is connected to the gate of the third NMOS tube MN3; the drain of the fifth PMOS tube MP5 serves as the output voltage end VREF of the entire bandgap reference circuit based on high-order temperature compensation.

[0011] The startup circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2.

[0012] The source of the first NMOS tube MN1 is grounded, and the gate is connected to the gate of the second PMOS tube MP2 and connected together to the VREF output terminal; the drain of the first NMOS tube MN1 is connected to the drain of the second PMOS tube MP2 and connected to the gate of the second NMOS tube MN2; the source of the first PMOS tube MP1 is connected to the power supply voltage, and the gate and the drain are short-circuited and connected to the source of the second PMOS tube MP2; the source of the second NMOS tube MN2 is grounded, and the drain is connected to the gate of the third PMOS tube MP3.

[0013] The present invention uses the clamping function of an operational amplifier twice, firstly generates a current with a linear coefficient and proportional to the absolute temperature PTAT through the voltage difference of the emitter-base voltage of two bipolar transistors (Q1, Q2) with different numbers of parallel connections, and then generates a current with a logarithmic coefficient and inversely proportional to the absolute temperature CTAT. According to Kirchhoff's current law, the two currents are subtracted to obtain the PTAT current with the logarithmic coefficient. Then, the two PTAT currents are respectively converted into a voltage with a linear positive temperature coefficient and a voltage with a logarithmic positive temperature coefficient by using a resistor, and the linear negative temperature coefficient and the logarithmic negative temperature coefficient of the emitter-base voltage of the bipolar transistor are compensated by using the two different types of positive temperature coefficient voltages. Finally, a reference output voltage with a zero temperature coefficient is obtained.

[0014] In summary, the present invention adopts a high-order temperature compensation method, uses only two operational amplifiers, has a simple structure, not only compensates for the first-order term of the emitter-base voltage of the bipolar transistor with respect to temperature, but also better compensates for the higher-order terms of temperature, so as to realize a low-temperature drift and high-precision bandgap reference circuit. The present invention realizes a low-temperature drift coefficient and high-precision bandgap reference voltage source in the temperature range of -40 to 125°C. The circuit is not affected by temperature, power supply voltage, and process fluctuations, and stably outputs the set bandgap reference voltage. The bandgap circuit is different from the previous first-order temperature compensation. It adopts a high-order temperature compensation method to compensate for the higher-order terms of the emitter-base voltage of the bipolar transistor with respect to temperature, thereby obtaining a low-temperature drift coefficient and high-precision reference voltage VREF. The present invention is implemented using a 0.18μm process, can be industrialized, and has a wider range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural block diagram of the present invention based on a high-order temperature compensation bandgap circuit;

[0016] Figure 2 It is a circuit structure diagram of the present invention based on a high-order temperature compensation bandgap circuit;

[0017] Figure 3 is a temperature characteristic diagram of an output reference voltage based on a high-order temperature compensation bandgap circuit in an embodiment;

[0018] Figure 4 It is a structural diagram of a comparative first-order temperature compensation bandgap circuit;

[0019] Figure 5 It is a temperature characteristic diagram of the output reference voltage of a comparative first-order temperature compensation bandgap circuit. DETAILED DESCRIPTION

[0020] In order to better describe the content of the present invention, further description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0021] A bandgap reference circuit based on high-order temperature compensation, the structural block diagram of which is shown in FIG. Figure 1 As shown, it includes a bandgap reference core circuit, a temperature compensation circuit and a startup circuit, and finally outputs a bandgap reference voltage VREF. The startup circuit is connected to the bandgap reference core circuit and the temperature compensation circuit. The bandgap reference core circuit provides a positive temperature coefficient current. The temperature compensation circuit adds and subtracts positive and negative temperature coefficients to compensate for the high-order temperature-related components of the negative temperature coefficient voltage of the transistor emitter-base.

[0022] The specific circuit structure of the present invention is as follows Figure 2 As shown:

[0023] The bandgap reference core circuit includes a first transistor Q1, a second transistor Q2, a first resistor R1, a third PMOS transistor MP3, a fourth PMOS transistor MP4 and a first operational amplifier OP1.

[0024] The base and collector of the first triode Q1 are short-circuited and grounded, and the emitter is connected to the drain of the third PMOS tube MP3 and the non-inverting input terminal of the first operational amplifier OP1 through the first resistor R1; the base and collector of the second triode Q2 are short-circuited and grounded, and the emitter is connected to the drain of the fourth PMOS tube MP4 and the inverting input terminal of the first operational amplifier OP1; the gate of the third PMOS tube MP3 is connected to the gate of the fourth PMOS tube MP4, and is connected to the output terminal of the first operational amplifier OP1, and the source of the third PMOS tube MP3 and the source of the fourth PMOS tube MP4 are both connected to the power supply voltage.

[0025] The positive temperature coefficient current PTAT generated by the bandgap reference core circuit passes through the third PMOS tube MP3, the fourth PMOS tube MP4, and is mirrored to the drain I of the fifth PMOS tube MP5. PTAT1 According to the temperature property of transistor emitter-base voltage, we can get the expression of transistor emitter-base voltage with respect to temperature:

[0026]

[0027] Where V g0 is the bandgap voltage of silicon extrapolated to 0K, T r is the reference temperature, V EB (T r ) is the emitter-base voltage at Tr temperature, k is the Boltzmann constant, q is the unit electron charge, η is a temperature constant that depends on the process, x is the temperature dependence order of the collector current, and is a variable that depends on the temperature characteristics of the collector current. The stronger the PTAT characteristics of the current flowing through the transistor, the larger the x, and vice versa, the smaller the x, the closer it is to 0.

[0028] According to the clamping characteristics of the first operational amplifier OP1 and the voltage properties of the transistor, the positive temperature coefficient current I copied to the drain of the fifth PMOS tube MP5 can be obtained. pTAT1 :

[0029]

[0030] Wherein N is the number of unit transistors connected in parallel to the first triode Q1 . The second triode Q2 usually includes only one unit transistor, so N is also the ratio of the number of unit transistors connected in parallel to the first triode Q1 and the second triode Q2 .

[0031] The temperature compensation circuit includes a third transistor Q3, a third NMOS transistor MN3, a fifth PMOS transistor MP5, a second resistor R2, a third resistor R3, a fourth resistor R4 and a second operational amplifier OP2.

[0032] The base and collector of the third triode Q3 are short-circuited and grounded, and the emitter is connected to the drain of the third NMOS tube MN3 through the fourth resistor R4; the gate of the fifth PMOS tube MP5 is connected to the gate of the fourth PMOS tube MP4, the source thereof is connected to the power supply voltage, and the drain is also connected to the drain of the third NMOS tube MN3 through the second resistor R2; one end of the third resistor R3 is grounded, and the other end is connected to the source of the third NMOS tube MN3 and the inverting input end of the second operational amplifier OP2; the non-inverting input end of the second operational amplifier OP2 is connected to the inverting input end of the first operational amplifier OP1, and the output end of the second operational amplifier OP2 is connected to the gate of the third NMOS tube MN3; the drain of the fifth PMOS tube MP5 serves as the output voltage end VREF of the entire bandgap reference circuit based on high-order temperature compensation.

[0033] The clamping of the second operational amplifier OP2 generates a negative temperature coefficient current CTAT flowing through the third resistor R3, which is expressed as:

[0034]

[0035] Where V EB2 is the emitter-base voltage of the second transistor Q2, and x1 is the order of the temperature dependence of the collector current of the second transistor Q2.

[0036] According to KCL, the expression of the positive temperature coefficient current PTAT flowing through the fourth resistor R4 is:

[0037]

[0038] The emitter-base voltage V of the third transistor Q3 EB3 have:

[0039]

[0040] Where x2 is the order of the temperature dependence of the collector current of the third transistor Q3.

[0041] Because I PTAT2 Than I PTAT1 The positive temperature coefficient is larger and more positively correlated with temperature, so x1<x2.

[0042] Therefore V REF It can be expressed as:

[0043]

[0044] By adjusting the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4, V REF The non-constant coefficient of the temperature in the expression is adjusted to 0, and the reference voltage output V that is independent of temperature can be obtained. REF .

[0045] The startup circuit includes a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1, and a second NMOS tube MN2. The source of the first NMOS tube MN1 is grounded, and the gate is connected to the gate of the second PMOS tube MP2 and connected to the VREF output terminal; the drain of the first NMOS tube MN1 is connected to the drain of the second PMOS tube MP2 and connected to the gate of the second NMOS tube MN2; the source of the first PMOS tube MP1 is connected to the power supply voltage, and the gate and the drain are short-circuited and connected to the source of the second PMOS tube MP2; the source of the second NMOS tube MN2 is grounded, and the drain is connected to the gate of the third PMOS tube MP3.

[0046] The first NMOS tube MN1 and the second PMOS tube MP2 form a group of inverters. When the circuit is not started, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are in the off state, VREF=0, and the inverter output formed by the MN1 and MP2 is high level, so that the second NMOS tube MN2 is turned on, and the gate voltages of the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are pulled down to a low level, thereby turning on the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5, so that the subsequent circuit can be started normally.

[0047] Wait until the circuit starts normally, V REF The gate voltages of the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are no longer affected by the startup circuit, so as to ensure the normal operation of the subsequent circuits.

[0048] Figure 3 is a temperature characteristic diagram of the output reference voltage of the high-order temperature compensation bandgap circuit according to the embodiment; Figure 3 As shown, based on the 180nm BCD process, the reference voltage output in the range of -40-125°C is 1V, and the temperature drift coefficient is 1.75ppm / °C. It can be seen from the figure that within the temperature range, the difference between the highest voltage and the lowest voltage is 287.6μV.

[0049] Compared with the high-order temperature compensation method adopted in the present invention, Figure 4 The traditional first-order temperature compensation circuit shown in the figure is used as a comparative example. The curve of its output reference voltage changing with temperature is shown in Figure 5 As shown. Based on the 180nm BCD process, the temperature drift coefficient of this solution in the range of -40-125℃ is 5.94ppm / ℃. It can be seen from the figure that within the temperature range, the difference between the highest voltage and the lowest voltage is 1.16mV.

[0050] It can be seen from the above embodiments that the present invention adopts a high-order temperature compensation method to compensate for the higher-order terms of the emitter-base voltage of the bipolar transistor with respect to temperature, thereby obtaining a reference voltage VREF with a low temperature drift coefficient and high precision; it is a bandgap reference voltage source with a low temperature drift coefficient and high precision at -40 to 125°C, and is not affected by temperature, power supply voltage, and process fluctuations, and stably outputs the set bandgap reference voltage; it is implemented using a 0.18μm process, can be industrialized, and has a wider range of applications.

Claims

1. A bandgap reference circuit based on high-order temperature compensation, characterized in that: Including bandgap reference core circuit, temperature compensation circuit and startup circuit; The bandgap reference core circuit includes a first transistor Q1, a second transistor Q2, a first resistor R1, a third PMOS transistor MP3, a fourth PMOS transistor MP4 and a first operational amplifier OP1; The base and collector of the first triode Q1 are short-circuited and grounded, and the emitter is connected to the drain of the third PMOS tube MP3 and the non-inverting input terminal of the first operational amplifier OP1 through the first resistor R1; the base and collector of the second triode Q2 are short-circuited and grounded, and the emitter is connected to the drain of the fourth PMOS tube MP4 and the inverting input terminal of the first operational amplifier OP1; the gate of the third PMOS tube MP3 is connected to the gate of the fourth PMOS tube MP4, and is connected to the output terminal of the first operational amplifier OP1, and the source of the third PMOS tube MP3 and the source of the fourth PMOS tube MP4 are both connected to the power supply voltage; The temperature compensation circuit includes a third transistor Q3, a third NMOS transistor MN3, a fifth PMOS transistor MP5, a second resistor R2, a third resistor R3, a fourth resistor R4 and a second operational amplifier OP2; The base and collector of the third triode Q3 are short-circuited and grounded, and the emitter is connected to the drain of the third NMOS tube MN3 through the fourth resistor R4; the gate of the fifth PMOS tube MP5 is connected to the gate of the fourth PMOS tube MP4, the source thereof is connected to the power supply voltage, and the drain is also connected to the drain of the third NMOS tube MN3 through the second resistor R2; one end of the third resistor R3 is grounded, and the other end is connected to the source of the third NMOS tube MN3 and the inverting input end of the second operational amplifier OP2; the non-inverting input end of the second operational amplifier OP2 is connected to the inverting input end of the first operational amplifier OP1, and the output end of the second operational amplifier OP2 is connected to the gate of the third NMOS tube MN3; the drain of the fifth PMOS tube MP5 serves as the output voltage end VREF of the entire bandgap reference circuit based on high-order temperature compensation; The startup circuit includes a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1 and a second NMOS tube MN2; the source of the first NMOS tube MN1 is grounded, and the gate is connected to the gate of the second PMOS tube MP2 and connected together to the VREF output terminal; the drain of the first NMOS tube MN1 is connected to the drain of the second PMOS tube MP2, and connected to the gate of the second NMOS tube MN2; the source of the first PMOS tube MP1 is connected to the power supply voltage, and the gate and the drain are short-circuited and connected to the source of the second PMOS tube MP2; the source of the second NMOS tube MN2 is grounded, and the drain is connected to the gate of the third PMOS tube MP3.

2. The bandgap reference circuit based on high-order temperature compensation as claimed in claim 1, characterized in that: The positive temperature coefficient current PTAT generated by the bandgap reference core circuit is mirrored to the drain electrode I of the fifth PMOS tube MP5 through the third PMOS tube MP3, the fourth PMOS tube MP4, and the pTAT1 , Wherein N is the number of unit transistors connected in parallel to the first triode Q1, and the second triode Q2 is only one unit transistor, so N is also the ratio of the number of unit transistors connected in parallel to the first triode Q1 and the second triode Q2.

3. The bandgap reference circuit based on high-order temperature compensation as claimed in claim 1, characterized in that: The clamping of the second operational amplifier OP2 generates a negative temperature coefficient current CTAT flowing through the third resistor R3: Where V EB2 is the emitter-base voltage of the second transistor Q2, V g0 is the bandgap voltage of silicon extrapolated to 0K, T r is the reference temperature, V EB (T r ) is the emitter-base voltage at Tr temperature, k is the Boltzmann constant, q is the unit electron charge, and η is a temperature constant that depends on the process; x1 is the order of the temperature dependence of the collector current of the second transistor Q2; According to KCL, the expression of the positive temperature coefficient current PTAT flowing through the fourth resistor R4 is: The emitter-base voltage V of the third transistor Q3 EB3 have: Where x2 is the order of the temperature dependence of the collector current of the third transistor Q3; Because I PTAT2 Than I PTAT1 The positive temperature coefficient is larger and more positively correlated with temperature, so x1<x2; V REF Expressed as:

4. The bandgap reference circuit based on high-order temperature compensation as claimed in claim 3, characterized in that: By adjusting the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4, V REF The coefficient of the non-constant term related to temperature in the expression is adjusted to 0, and the reference voltage output V is obtained which is independent of temperature. REF .

5. The bandgap reference circuit based on high-order temperature compensation as claimed in claim 1, characterized in that: The first NMOS tube MN1 and the second PMOS tube MP2 form a group of inverters. When the circuit is not started, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are in the off state, VREF=0, and the inverter output formed by MN1 and MP2 is high level, so that the second NMOS tube MN2 is turned on, and the gate voltages of the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are pulled down to a low level, thereby turning on the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5, so that the subsequent circuit can be started normally; Wait until the circuit starts normally, V REF The gate voltages of the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are no longer affected by the startup circuit, so as to ensure the normal operation of the subsequent circuits.

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