A bandgap reference circuit based on high order temperature compensation

Abstract

The application belongs to the field of analog integrated circuit design, and particularly relates to a band gap reference circuit based on high-order temperature compensation. The application only uses two operational amplifiers, and twice uses the clamping function of the operational amplifier. Firstly, a PTAT current with a first-order coefficient is generated through the voltage difference of the emitter-base voltages of two bipolar transistors, and then a CTAT current with a logarithmic coefficient is generated, and a PTAT current with a logarithmic coefficient is further obtained. Then, the two kinds of PTAT currents are respectively converted into a voltage with a first-order positive temperature coefficient and a voltage with a logarithmic positive temperature coefficient by using resistors, and the first-order negative temperature coefficient and the logarithmic negative temperature coefficient of the emitter-base voltage of the bipolar transistor are compensated by using the two kinds of positive temperature coefficient voltages. Finally, a reference output voltage with zero temperature coefficient is obtained. The application is realized by using a 0.18 mu m process, can be industrialized, and is more universal in application range, and is not affected by temperature, power voltage and process fluctuation.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design, and specifically relates to a bandgap reference circuit based on high-order temperature compensation. Background Technology

[0002] A bandgap reference circuit is a circuit that provides a stable reference voltage. Its output voltage is typically independent of supply voltage and temperature variations, making it widely used in analog circuits, mixed-signal circuits, and high-precision electronic equipment. Traditional bandgap reference circuits achieve temperature compensation by combining a voltage with a positive temperature coefficient (usually generated by the thermoelectric potential difference of a diode) and a voltage with a negative temperature coefficient (generated by the PN junction voltage of a diode), thereby achieving a zero-temperature coefficient output within a certain temperature range.

[0003] However, traditional bandgap reference circuits typically only provide first-order temperature compensation, meaning their temperature coefficient still exhibits nonlinear variations over a wide range, limiting the accuracy of the output voltage, especially in applications requiring high precision over a wide temperature range. Therefore, improving the temperature stability of reference circuits has become a pressing issue. Summary of the Invention

[0004] To address the aforementioned problems and shortcomings, the present invention aims to provide a high-precision bandgap reference voltage source with a low temperature drift coefficient in the range of -40 to 125°C. This circuit is unaffected by temperature, power supply voltage, and process fluctuations, and stably outputs the set bandgap reference voltage. Unlike previous first-order temperature compensation methods, this bandgap circuit employs a higher-order temperature compensation method to compensate for the higher-order terms of the emitter-base voltage of the bipolar transistor with respect to temperature, thereby obtaining a high-precision reference voltage VREF with a low temperature drift coefficient. This invention is implemented using a 0.18μm process, making it industrially feasible and applicable to a wider range of applications.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A bandgap reference circuit based on high-order temperature compensation includes a bandgap reference core circuit, a temperature compensation circuit, and a startup circuit.

[0007] The bandgap reference core circuit includes a first transistor Q1, a second transistor Q2, a first resistor R1, a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a first operational amplifier OP1.

[0008] The base and collector of the first transistor Q1 are shorted and grounded, and the emitter is connected to the drain of the third PMOS transistor MP3 and the non-inverting input of the first operational amplifier OP1 through the first resistor R1; the base and collector of the second transistor Q2 are shorted and grounded, and the emitter is connected to the drain of the fourth PMOS transistor MP4 and the inverting input of the first operational amplifier OP1; the gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected and connected to the output of the first operational amplifier OP1, and the sources of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both connected to the power supply voltage.

[0009] The temperature compensation circuit includes a third transistor Q3, a third NMOS transistor MN3, a fifth PMOS transistor MP5, a second resistor R2, a third resistor R3, a fourth resistor R4, and a second operational amplifier OP2.

[0010] The base and collector of the third transistor Q3 are shorted and grounded, and the emitter is connected to the drain of the third NMOS transistor MN3 through the fourth resistor R4. The gate of the fifth PMOS transistor MP5 is connected to the gate of the fourth PMOS transistor MP4, its source is connected to the power supply voltage, and its drain is also connected to the drain of the third NMOS transistor MN3 through the second resistor R2. One end of the third resistor R3 is grounded, and the other end is connected to the source of the third NMOS transistor MN3 and the inverting input of the second operational amplifier OP2. The non-inverting input of the second operational amplifier OP2 is connected to the inverting input of the first operational amplifier OP1, and the output of the second operational amplifier OP2 is connected to the gate of the third NMOS transistor MN3. The drain of the fifth PMOS transistor MP5 serves as the output voltage terminal VREF of the entire bandgap reference circuit based on high-order temperature compensation.

[0011] The startup circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2.

[0012] The source of the first NMOS transistor MN1 is grounded, and its gate is connected to the gate of the second PMOS transistor MP2 and together connected to the VREF output terminal. The drain of the first NMOS transistor MN1 is connected to the drain of the second PMOS transistor MP2 and connected to the gate of the second NMOS transistor MN2. The source of the first PMOS transistor MP1 is connected to the power supply voltage, and its gate and drain are shorted and connected to the source of the second PMOS transistor MP2. The source of the second NMOS transistor MN2 is grounded, and its drain is connected to the gate of the third PMOS transistor MP3.

[0013] This invention utilizes the clamping function of an operational amplifier twice. First, it generates a PTAT current with a first-order coefficient proportional to the absolute temperature by using the voltage difference between the emitter-base voltages of two bipolar transistors (Q1, Q2) connected in parallel with different numbers of transistors. Then, it generates a CTAT current with a logarithmic coefficient proportional to the absolute temperature. According to Kirchhoff's current law, these two currents are subtracted to obtain a PTAT current with a logarithmic coefficient. Next, resistors are used to convert these two PTAT currents into voltages with a positive first-order temperature coefficient and voltages with a positive logarithmic temperature coefficient, respectively. These two different types of positive temperature coefficient voltages are used to compensate for the negative first-order and negative logarithmic temperature coefficients of the emitter-base voltage of the bipolar transistors. Finally, a reference output voltage with zero temperature coefficient is obtained.

[0014] In summary, this invention employs a high-order temperature compensation method, using only two operational amplifiers, resulting in a simple structure. It not only compensates for the first-order temperature-related term of the emitter-base voltage of the bipolar transistor but also better compensates for the higher-order temperature-related terms, achieving a low-drift, high-precision bandgap reference circuit. This invention realizes a low-drift, high-precision bandgap reference voltage source within a temperature range of -40 to 125°C. This circuit is unaffected by temperature, power supply voltage, or process fluctuations, stably outputting the set bandgap reference voltage. Unlike previous first-order temperature compensation methods, this bandgap circuit uses a high-order temperature compensation method to compensate for the higher-order temperature-related term of the emitter-base voltage of the bipolar transistor, thereby obtaining a low-drift, high-precision reference voltage VREF. This invention is implemented using a 0.18μm process, making it industrially feasible and applicable to a wider range of applications. Attached Figure Description

[0015] Figure 1 This is a block diagram of the structure of the present invention based on a high-order temperature-compensated bandgap circuit;

[0016] Figure 2 This is a circuit structure diagram of the present invention based on a high-order temperature-compensated bandgap circuit;

[0017] Figure 3 This is a temperature characteristic diagram of the output reference voltage based on a high-order temperature-compensated bandgap circuit in an embodiment.

[0018] Figure 4 This is a structural diagram of a comparative first-order temperature-compensated bandgap circuit.

[0019] Figure 5 This is a temperature characteristic diagram of the output reference voltage of a comparative first-order temperature-compensated bandgap circuit. Detailed Implementation

[0020] To better describe the content of this invention, the following will provide further explanation in conjunction with the accompanying drawings and specific embodiments.

[0021] A bandgap reference circuit based on high-order temperature compensation, the block diagram of which is shown below. Figure 1 As shown, it includes a bandgap reference core circuit, a temperature compensation circuit, and a startup circuit, ultimately outputting a bandgap reference voltage VREF. The startup circuit is connected to both the bandgap reference core circuit and the temperature compensation circuit. The bandgap reference core circuit provides a positive temperature coefficient current, while the temperature compensation circuit compensates for the higher-order temperature-dependent components of the transistor's emitter-base negative temperature coefficient voltage by adding and subtracting positive and negative temperature coefficients.

[0022] The specific circuit structure of this invention is as follows: Figure 2 As shown:

[0023] The bandgap reference core circuit includes a first transistor Q1, a second transistor Q2, a first resistor R1, a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a first operational amplifier OP1.

[0024] The base and collector of the first transistor Q1 are shorted and grounded, and the emitter is connected to the drain of the third PMOS transistor MP3 and the non-inverting input of the first operational amplifier OP1 through the first resistor R1; the base and collector of the second transistor Q2 are shorted and grounded, and the emitter is connected to the drain of the fourth PMOS transistor MP4 and the inverting input of the first operational amplifier OP1; the gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected and connected to the output of the first operational amplifier OP1, and the sources of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both connected to the power supply voltage.

[0025] The positive temperature coefficient current PTAT generated by the bandgap reference core circuit flows through the third PMOS transistor MP3, the fourth PMOS transistor MP4, and is mirrored to the drain I of the fifth PMOS transistor MP5. PTAT1 Based on the temperature-dependent properties of the emitter-base voltage of a transistor, the expression for the emitter-base voltage with respect to temperature can be obtained:

[0026]

[0027] Where V g0 T is the bandgap voltage of silicon extrapolated to 0K. r For reference temperature, V EB (T r ) is the emitter-base voltage at temperature Tr, k is the Boltzmann constant, q is the unit electron charge, η is a temperature constant that depends on the process, and x is the temperature dependence order of the collector current, which is a variable that depends on the temperature characteristics of the collector current. The stronger the PTAT characteristic of the current flowing through the transistor, the larger x is, and vice versa, the smaller x is, and the closer it is to 0.

[0028] Based on the clamping characteristics of the first operational amplifier OP1 and the voltage characteristics of the transistor, the positive temperature coefficient current I that is replicated to the drain of the fifth PMOS transistor MP5 can be obtained. pTAT1 :

[0029]

[0030] Where N is the number of unit transistors connected in parallel with the first transistor Q1. The second transistor Q2 usually contains only one unit transistor, so N is also the ratio of the number of unit transistors connected in parallel with the first transistor Q1 and the second transistor Q2.

[0031] The temperature compensation circuit includes a third transistor Q3, a third NMOS transistor MN3, a fifth PMOS transistor MP5, a second resistor R2, a third resistor R3, a fourth resistor R4, and a second operational amplifier OP2.

[0032] The base and collector of the third transistor Q3 are shorted and grounded, and the emitter is connected to the drain of the third NMOS transistor MN3 through the fourth resistor R4. The gate of the fifth PMOS transistor MP5 is connected to the gate of the fourth PMOS transistor MP4, its source is connected to the power supply voltage, and its drain is also connected to the drain of the third NMOS transistor MN3 through the second resistor R2. One end of the third resistor R3 is grounded, and the other end is connected to the source of the third NMOS transistor MN3 and the inverting input of the second operational amplifier OP2. The non-inverting input of the second operational amplifier OP2 is connected to the inverting input of the first operational amplifier OP1, and the output of the second operational amplifier OP2 is connected to the gate of the third NMOS transistor MN3. The drain of the fifth PMOS transistor MP5 serves as the output voltage terminal VREF of the entire bandgap reference circuit based on high-order temperature compensation.

[0033] The clamping action of the second operational amplifier OP2 generates a negative temperature coefficient current CTAT flowing through the third resistor R3, the expression of which is:

[0034]

[0035] Where V EB2 x is the emitter-base voltage of the second transistor Q2, and x1 is the temperature dependence order of the collector current of the second transistor Q2.

[0036] According to KCL, the expression for the positive temperature coefficient current PTAT flowing through the fourth resistor R4 is:

[0037]

[0038] The emitter-base voltage V of the third transistor Q3 EB3 have:

[0039]

[0040] Where x2 is the temperature dependence order of the collector current of the third transistor Q3.

[0041] Because of I PTAT2 Than I PTAT1 The positive temperature coefficient is larger, and it is more positively correlated with temperature, so x1 < x2.

[0042] Therefore V REF This can be expressed as:

[0043]

[0044] By adjusting the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4, V REF By adjusting the coefficient of the non-constant term related to temperature in the expression to 0, a temperature-independent reference voltage output V can be obtained. REF .

[0045] The startup circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2. The source of the first NMOS transistor MN1 is grounded, and its gate is connected to the gate of the second PMOS transistor MP2 and together connected to the VREF output terminal. The drain of the first NMOS transistor MN1 is connected to the drain of the second PMOS transistor MP2 and connected to the gate of the second NMOS transistor MN2. The source of the first PMOS transistor MP1 is connected to the power supply voltage, and its gate and drain are shorted and connected to the source of the second PMOS transistor MP2. The source of the second NMOS transistor MN2 is grounded, and its drain is connected to the gate of the third PMOS transistor MP3.

[0046] The first NMOS transistor MN1 and the second PMOS transistor MP2 form an inverter. When the circuit is not started, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are in the off state, VREF=0. The inverter formed by MN1 and MP2 outputs a high level, which turns on the second NMOS transistor MN2, pulling the gate voltage of the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 down to a low level, thereby turning on the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5, so that the subsequent circuit can start normally.

[0047] Once the circuit starts up normally, V REF When the voltage drops to a high level, the inverter outputs a low level, turning off the second NMOS transistor MN2. This shuts down the startup circuit, and the gate voltages of the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are no longer affected by the startup circuit, ensuring the normal operation of subsequent circuits.

[0048] Figure 3 This is a temperature characteristic diagram of the output reference voltage based on a high-order temperature-compensated bandgap circuit in an embodiment; for example... Figure 3 As shown, based on the 180nm BCD process, the output reference voltage is 1V within the range of -40-125℃, and the temperature drift coefficient is 1.75ppm / ℃. The figure shows that within this temperature range, the difference between the highest and lowest voltages is 287.6μV.

[0049] In contrast to the high-order temperature compensation method used in this invention, Figure 4 The circuit shown is a traditional first-order temperature compensation circuit, used as a comparative example. Its output reference voltage varies with temperature as shown in the figure. Figure 5 As shown in the figure, based on the 180nm BCD process, the temperature drift coefficient of this scheme is 5.94ppm / ℃ in the range of -40-125℃. It can be seen from the figure that within this temperature range, the difference between the highest and lowest voltages is 1.16mV.

[0050] As can be seen from the above embodiments, the present invention employs a high-order temperature compensation method to compensate for the higher-order terms of the emitter-base voltage of a bipolar transistor with respect to temperature, thereby obtaining a high-precision reference voltage VREF with a low temperature drift coefficient. It is a high-precision bandgap reference voltage source with a low temperature drift coefficient in the range of -40 to 125°C, and is unaffected by temperature, power supply voltage, and process fluctuations, stably outputting the set bandgap reference voltage. It is implemented using a 0.18μm process, making it industrially feasible and applicable to a wider range of applications.

Claims

1. A bandgap reference circuit based on high order temperature compensation, characterized by: The bandgap reference core circuit comprises a first transistor Q1, a second transistor Q2, a first resistor R1, a third PMOS transistor MP3, a fourth PMOS transistor MP4 and a first operational amplifier OP1. The base and the collector of the first transistor Q1 are short-circuited and grounded, the emitter is connected to the drain of the third PMOS transistor MP3 and the non-inverting input terminal of the first operational amplifier OP1 through the first resistor R1; the base and the collector of the second transistor Q2 are short-circuited and grounded, the emitter is connected to the drain of the fourth PMOS transistor MP4 and the inverting input terminal of the first operational amplifier OP1; the gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4, and the output terminal of the first operational amplifier OP1; the source of the third PMOS transistor MP3 and the source of the fourth PMOS transistor MP4 are connected to a power supply voltage. The temperature compensation circuit comprises a third transistor Q3, a third NMOS transistor MN3, a fifth PMOS transistor MP5, a second resistor R2, a third resistor R3, a fourth resistor R4 and a second operational amplifier OP2. The base and the collector of the third transistor Q3 are short-circuited and grounded, the emitter is connected to the drain of the third NMOS transistor MN3 through the fourth resistor R4; the gate of the fifth PMOS transistor MP5 is connected to the gate of the fourth PMOS transistor MP4, the source is connected to a power supply voltage, and the drain is also connected to the drain of the third NMOS transistor MN3 through the second resistor R2; one end of the third resistor R3 is grounded, and the other end is connected to the source of the third NMOS transistor MN3 and the inverting input terminal of the second operational amplifier OP2; the non-inverting input terminal of the second operational amplifier OP2 is connected to the inverting input terminal of the first operational amplifier OP1, and the output terminal of the second operational amplifier OP2 is connected to the gate of the third NMOS transistor MN3; the drain of the fifth PMOS transistor MP5 serves as an output voltage terminal VREF of the entire high-order temperature compensation based bandgap reference circuit. The start-up circuit comprises a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1 and a second NMOS transistor MN2; the source of the first NMOS transistor MN1 is grounded, the gate is connected to the gate of the second PMOS transistor MP2 and is connected to the VREF output terminal; the drain of the first NMOS transistor MN1 and the drain of the second PMOS transistor MP2 are connected to the gate of the second NMOS transistor MN2; the source of the first PMOS transistor MP1 is connected to a power supply voltage, the gate and the drain are short-circuited and connected to the source of the second PMOS transistor MP2; the source of the second NMOS transistor MN2 is grounded, and the drain is connected to the gate of the third PMOS transistor MP3.

3. The high-order temperature compensation based bandgap reference circuit according to claim 1, wherein the clamping of the second operational amplifier OP2 generates a negative temperature coefficient current CTAT flowing through the third resistor R3:

2. The bandgap reference circuit based on high order temperature compensation as claimed in claim 1, wherein: The positive temperature coefficient current PTAT generated by the bandgap reference core circuit passes through the third PMOS tube MP3, the fourth PMOS tube MP4, and the drain I of the fifth PMOS tube MP5 mirrored to the fourth PMOS tube MP4 pTAT1 , Wherein N is the number of unit transistors in parallel with the first triode Q1, and the second triode Q2 is only one unit transistor, so N is also the ratio of the number of unit transistors in parallel with the first triode Q1 and the second triode Q2. According to KCL, the expression of a positive temperature coefficient current PTAT flowing through the fourth resistor R4 is: wherein x2 is the collector current temperature-dependent order of the third transistor Q3. where V EB2 is the emitter-base voltage of the second transistor Q2, V g0 is the bandgap voltage of silicon extrapolated to 0 K, T r is the reference temperature, V EB (T r ) is the emitter-base voltage at the temperature of Tr, k is the Boltzmann constant, q is the elementary electronic charge, η is a process-dependent temperature constant; xi is the collector current temperature dependence order of the second transistor Q2; ​ The emitter-base voltage V of the third transistor Q3 EB3 There are: ​ Because I PTAT2 The positive temperature coefficient of I PTAT1 Is greater, more temperature positive correlation, so x1 < x2; V REF Expressed as:

4. The bandgap reference circuit based on high order temperature compensation as claimed in claim 3, wherein: By adjusting the resistance values of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4, V REF The coefficient of the non-constant term with respect to temperature in the expression is adjusted to 0, obtaining a reference voltage output V REF that is independent of temperature.

5. The bandgap reference circuit based on high-order temperature compensation of claim 1, wherein: The first NMOS tube MN1 and the second PMOS tube MP2 constitute a set of inverters, when the circuit is not started, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are in the off state, VREF=0, the inverter output by the MN1 and MP2 is high, so that the second NMOS tube MN2 is turned on, the gate voltage of the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 is pulled low to low, thereby turning on the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5, so that the subsequent circuit can be normally started. When the circuit is normally started, V REF becomes high level, the output of the inverter is low level, the second NMOS MN2 is turned off, the starting circuit is closed, and the gate voltage of the third PMOS MP3, the fourth PMOS MP4 and the fifth PMOS MP5 is no longer affected by the starting circuit, so as to ensure the normal work of the subsequent circuit.

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