Micro-power-consumption linear power supply turn-back type current-limiting protection circuit and method

Abstract

The invention relates to the technical field of power management integrated circuits, and discloses a micro-power-consumption linear power supply turn-back type current-limiting protection circuit and a micro-power-consumption linear power supply turn-back type current-limiting protection method. An error amplifier of a circuit structure can accurately control the conduction degree of an eighteenth P-type transistor MP18 by comparing a reference voltage VREF with a feedback voltage, so that an output voltage VOUT is adjusted to a set value. The closed-loop feedback mechanism greatly improves the stability of the power supply, and ensures that the output voltage can be kept constant under various load conditions. According to the turn-back type current-limiting protection circuit, by monitoring output current, when the output current exceeds a set threshold value, the turn-back type current-limiting protection circuit can quickly respond and act on the input end of the error amplifier and adjust an output signal of the error amplifier, so that the conduction degree of an eighteenth P-type transistor MP18 is reduced, and current-limiting protection is achieved. The turn-back type current limiting mechanism can effectively prevent power supply damage or short circuit fault caused by overcurrent.

Description

Technical Field

[0001] The present invention relates to the technical field of power management integrated circuits, and in particular to a micro-power linear power supply foldback current limiting protection circuit and method. Background Art

[0002] With the rapid development of semiconductor process technology, the integration of linear regulators is increasing, and the power density is rapidly improving. In practical applications, if the load current of the regulator is too large or in a short-circuit state, and the current of the power transistor is large, it will cause local hot spots and electromigration of the interconnection metal inside the chip, causing the power transistor of the regulator to be damaged or burned and fail to function, seriously threatening the normal operation of the power supply system.

[0003] The current limiting circuit of the linear regulator ensures that the voltage regulating device is in a safe working area. Conventional current limiting circuits are divided into two categories: foldback current limiting voltage and constant current limiting circuit. The static current of each analog branch is in the microampere level. The principle of the foldback current limiting circuit: the current limiting current is controlled by a certain voltage signal of the circuit. When the load of the regulator is too heavy, the output current is greater than the threshold current I MAX The current limiting circuit quickly adjusts the output current of the voltage regulator to the short-circuit current, reducing the power consumption of the voltage regulator itself. If the application transient demand is greater than the current limiting protection threshold current, the output voltage of the voltage regulator will function abnormally. Principle of constant current limiting circuit: The maximum output current of the voltage regulator is always the current limiting threshold current I MAX In the overcurrent or short circuit application state, the voltage regulator itself has a large power and there is a potential risk of damage or failure. If the two existing current limiting protection circuit technology solutions are used, the application scope of the linear voltage regulator is subject to certain restrictions. In the low voltage difference application process of the voltage regulator, the transient current output of the voltage regulator is too large and the output function of the voltage regulator is abnormal. Summary of the invention

[0004] In order to overcome the defects of the above-mentioned prior art, the purpose of the present invention is to provide a micro-power linear power supply foldback current limiting protection circuit and method to solve the technical problem of abnormal output function of the voltage regulator in the prior art when the voltage regulator has a low voltage difference and a large output current application state.

[0005] The present invention is achieved through the following technical solutions: In a first aspect, the present invention provides a micro-power linear power supply foldback current limiting protection circuit, including an error amplifier, a foldback current limiting protection circuit, a buffer, an eighteenth P-type transistor M P18 , a first resistor R1 and a second resistor R2; The positive input of the error amplifier is connected to the reference voltage V REF , the power supply terminal of the error amplifier is connected to the input voltage V INThe output of the error amplifier is connected to the eighteenth P-type transistor M through a buffer P18 The gate of the eighteenth P-type transistor M P18 The source and substrate are connected to the input voltage V IN The eighteenth P-type transistor M P18 The drain of the error amplifier is connected to the ground after passing through the first resistor R1 and the second resistor R2 in sequence; the negative input terminal of the error amplifier is connected in parallel between the first resistor R1 and the second resistor R2; The eighteenth P-type transistor M P18 The output voltage V is set between the drain and the first resistor R1 OUT ; A first test node a1 is provided at the output end of the buffer; a second test node a2 is provided at the input end of the buffer; The foldback current limiting protection circuit has three branches, one of which is connected to the input voltage V IN , one branch connects to the second test node a2; one branch connects to V OUT .

[0006] Preferably, the foldback current limiting protection circuit includes a current limiting mode control circuit and a power transistor gate-source voltage limiting circuit; One end of the current limiting mode control circuit and the power transistor gate-source voltage limiting circuit is connected to the input voltage V IN ; The other ends of the current limiting mode control circuit and the power transistor gate-source voltage limiting circuit are grounded; The output end of the current limiting mode control circuit is connected to the input end of the power transistor gate-source voltage limiting circuit, and the output end of the power transistor gate-source voltage limiting circuit is connected to the second test node a2.

[0007] Further, the current limiting mode control circuit includes a first limiting circuit, a second limiting circuit, a third limiting circuit, a fourth limiting circuit, a fifth limiting circuit, a sixth limiting circuit, a seventh limiting circuit and an eighth limiting circuit; The first limiting circuit, the second limiting circuit, the third limiting circuit, the fourth limiting circuit, the fifth limiting circuit, the sixth limiting circuit, the seventh limiting circuit and the eighth limiting circuit are all arranged in parallel, and each limiting circuit is provided with a plurality of voltage measuring points, and is connected and arranged through the plurality of voltage measuring points; One end of the first limiting circuit, the second limiting circuit, the fourth limiting circuit, and the sixth limiting circuit is connected to the input voltage V IN The other ends of the first limiting circuit, the second limiting circuit, the fourth limiting circuit, the fifth limiting circuit, and the sixth limiting circuit are grounded; wherein the first limiting circuit is connected to the first bias voltage V B1A second bias voltage V is provided between the second limiting circuit and the fourth limiting circuit B2 ; One end of the third limiting circuit is connected to the output voltage V OUT , the other end is grounded; One end of the seventh limiting circuit is connected to the input voltage V IN ; The other end is connected to the measuring point circuit; one end of the measuring point circuit is connected to the output voltage V through the sixth limiting circuit, the fifth limiting circuit, and the fourth limiting circuit in sequence OUT ; The other end is connected to the eighth limiting circuit; One end of the eighth limiting circuit is connected to the input voltage V IN ; The other end is connected to the input of the power transistor gate-source voltage limiting circuit.

[0008] Furthermore, the first limiting circuit is provided with a first P-type transistor M P1 , the second P-type transistor M P2 , the third P-type transistor M P3 , the first N-type transistor M N1 , a first voltage measuring point b1, a second voltage measuring point b2 and a third voltage measuring point b3; The first P-type transistor M P1 The source and substrate are connected to the input voltage V IN , the gate and drain are connected to the first voltage measuring point b1; the second P-type transistor M P2 The source is connected to the first voltage measuring point b1, and the substrate is connected to the input voltage V IN , the gate and drain are connected to the second voltage measuring point b2; the third P-type transistor M P3 The source is connected to the second voltage measuring point b2, and the substrate is connected to the input voltage V IN ,, the gate and drain are connected to the third voltage measuring point b3; the first N-type transistor M N1 The source and substrate are grounded, and the gate is connected to a first bias voltage V B1 , the drain is connected to the third voltage measuring point b3; The second amplitude limiting circuit is provided with a fourth P-type transistor M P4 , the second N-type transistor M N2 , the third N-type transistor M N3 , the fourth N-type transistor M N4 , the fifth N-type transistor M N5 , a fourth voltage measuring point b4, a fifth voltage measuring point b5, a sixth voltage measuring point b6 and a seventh voltage measuring point b7; The fourth P-type transistor M P4 The source and substrate are connected to the input voltage V IN , the gate is connected to the second bias voltage V B2, the drain is connected to the fourth voltage measuring point b4; the second N-type transistor M N2 The source of the third N-type transistor M is connected to the fifth voltage measuring point b5, the substrate is grounded, and the gate and drain are connected to the fourth voltage measuring point b4; N3 The source of the fourth N-type transistor M is connected to the sixth voltage measuring point b6, the substrate is grounded, and the gate and drain are connected to the fifth voltage measuring point b5; N4 The source of the fifth N-type transistor M is connected to the seventh voltage measuring point b7, the substrate is grounded, and the gate and drain are connected to the sixth voltage measuring point b6; N5 The source and substrate are grounded, and the gate and drain are connected to the seventh voltage measuring point b7; The third amplitude limiting circuit is provided with a sixth N-type transistor M N6 , the seventh N-type transistor M N7 , the eighth N-type transistor M N8 , the ninth N-type transistor M N9 , the tenth N-type transistor M N10 , the ninth voltage measuring point b9, the tenth voltage measuring point b 10 , Eleventh voltage measuring point b 11 And the twelfth voltage measurement point b 12 ; The sixth N-type transistor M N6 The source and substrate of the device are connected to the ninth voltage measuring point b9, the gate is connected to the fourth voltage measuring point b4, and the drain is connected to the output voltage V OUT ; The seventh N-type transistor M N7 The source is connected to the tenth voltage measuring point b 10 , the substrate is grounded, the gate and the drain are connected to the ninth voltage measuring point b9; the eighth N-type transistor M N8 The source is connected to the eleventh voltage measuring point b 11 , the substrate is grounded, the gate and drain are connected to the tenth voltage measurement point b 10 ; Ninth N-type transistor M N9 The source is connected to the twelfth voltage measuring point b 12 , the substrate is grounded, the gate and drain are connected to the eleventh voltage measurement point b 11 The tenth N-type transistor M N10 The source and substrate are grounded, and the gate and drain are connected to the twelfth voltage measurement point b. 12 ; The fourth amplitude limiting circuit is provided with a fifth P-type transistor M P5 , the eleventh N-type transistor M N11 , the twelfth N-type transistor M N12 、Thirteenth voltage measurement point b 13 And the fourteenth voltage measurement point b 14 ; The fifth P-type transistor M P5 The source and substrate are connected to the input voltage V IN, the gate is connected to the second bias voltage V B2 , the drain is connected to the thirteenth voltage measuring point b 13 ; Eleventh N-type transistor M N11 The source and substrate of 14 , the gate is connected to the third voltage measuring point b3, and the drain is connected to the thirteenth voltage measuring point b 13 ; Twelfth N-type transistor M N12 The source and substrate of the device are grounded, the gate is connected to the ninth voltage measuring point b9, and the drain is connected to the fourteenth voltage measuring point b 14 ; The fifth amplitude limiting circuit is provided with a sixth P-type transistor M P6 and Zener diode D z1 The sixth P-type transistor M P6 The source is connected to the output voltage V OUT , the drain is connected to the eighteenth voltage measuring point b 18 , the substrate is connected to the input voltage V IN ; The gate is connected to the third voltage measuring point b3; Zener diode D z1 The cathode is connected to the fourteenth voltage measuring point b 14 , anode grounding setting; The sixth amplitude limiting circuit is provided with a seventh P-type transistor M P7 , the thirteenth N-type transistor M N13 And the fifteenth voltage measurement point b 15 ; The seventh P-type transistor M P7 The source and substrate are connected to the input voltage V IN , the gate is connected to the thirteenth voltage measurement point b 13 , the drain is connected to the fifteenth voltage measuring point b 15 ; Thirteenth N-type transistor M N13 The source and substrate are grounded, and the gate is connected to the fourteenth voltage measurement point b 14 , the drain is connected to the fifteenth voltage measuring point b 15 ; The seventh amplitude limiting circuit is provided with an eighth P-type transistor M P8 , the ninth P-type transistor M P9 , the tenth P-type transistor M P10 , 16th voltage measuring point b 16 , Seventeenth voltage measuring point b 17 And the eighteenth voltage measurement point b 18 ; The eighth P-type transistor M P8 The source and substrate are connected to the input voltage V IN , the gate and drain are connected to the sixteenth voltage measuring point b 16 ; Ninth P-type transistor M P9 The source is connected to the sixteenth voltage measuring point b 16, the substrate is connected to the input voltage V IN , the gate and drain are connected to the seventeenth voltage measuring point b 17 ; The tenth P-type transistor M P10 The source is connected to the seventeenth voltage measuring point b 17 , the substrate is connected to the input voltage V IN , the gate and drain are connected to the eighteenth voltage measuring point b 18 ; The eighteenth voltage measurement point b 18 Set on the measuring point circuit; The eighth amplitude limiting circuit is provided with an eleventh P-type transistor M P11 ; Eleventh P-type transistor M P11 The source and substrate are connected to the input voltage V IN , the gate is connected to the eighteenth voltage measuring point b 18 , the drain is connected to the input end of the power transistor gate-source voltage limiting circuit 200 .

[0009] Furthermore, the power transistor gate-source voltage limiting circuit includes a ninth limiting circuit, a tenth limiting circuit and an eleventh limiting circuit; The ninth limiting circuit, the tenth limiting circuit and the eleventh limiting circuit are all arranged in parallel; each limiting circuit is provided with a plurality of voltage measuring points, and is connected and arranged through the plurality of voltage measuring points; One end of the ninth amplitude limiting circuit is connected to the eleventh P-type transistor M P11 The drain of the device and the other end of the device are grounded; One end of the tenth amplitude limiting circuit is connected to the input voltage V IN , the other end is grounded; One end of the eleventh limiting circuit is connected to the input voltage V IN , and the other end is connected to the second test node a2.

[0010] Furthermore, the ninth limiting circuit is provided with a twelfth P-type transistor M P12 , the thirteenth P-type transistor M P13 , the fourteenth P-type transistor M P14 , the fifteenth P-type transistor M P15 , the sixteenth P-type transistor M P16 , the fourteenth N-type transistor M N14 、Nineteenth voltage measurement point b 19 、20th voltage measurement point b 20 、21st voltage measurement point b 21 、22nd voltage measurement point b 22 And the twenty-third voltage measurement point b 23 ; Twelfth P-type transistor M P12 The source and substrate are connected to the nineteenth voltage measuring point b 19 , the gate is connected to the fifteenth voltage measurement point b15 , the drain is connected to the 20th voltage measurement point b 20 ; Thirteenth P-type transistor M P13 The source and substrate are connected to the 20th voltage measurement point b 20 ; The gate and drain are connected to the 21st voltage measurement point b 21 ; Fourteenth P-type transistor M P14 The source and substrate are connected to the 21st voltage measurement point b 21 , the gate and drain are connected to the 22nd voltage measurement point b 22 ; Fifteenth P-type transistor M P15 The source and substrate are connected to the nineteenth voltage measuring point b 19 , the gate and drain are connected to the 22nd voltage measurement point b 22 ; Sixteenth P-type transistor M P16 The source and substrate of 22 , the gate and drain are connected to the 23rd voltage measuring point b 23 ; Fourteenth N-type transistor M N14 The source and substrate are grounded, and the gate is connected to a first bias voltage V B1 , the drain is connected to the 23rd voltage measuring point b 23 ; The tenth amplitude limiting circuit is provided with a seventeenth P-type transistor M P17 、24th voltage measurement point b 24 And LP transistor Q LP1 ; The seventeenth P-type transistor M P17 The source and substrate are connected to the input voltage V IN , the gate is connected to the second bias voltage V B2 , the drain is connected to the 24th voltage measuring point b 24 ; LP type transistor Q LP1 The collector is grounded, and the base is connected to the 23rd voltage measuring point b 23 , the emitter is connected to the 24th voltage measuring point b 24 ; The eleventh limiter circuit is provided with an N-type transistor Q n1 ; The N-type transistor Q n1 The collector of the input voltage V IN , the base is connected to the 24th voltage measuring point b 24 , the emitter is connected to the second test node a2.

[0011] In a second aspect, the present invention further provides a micro-power linear power supply foldback current limiting protection method, based on the above-mentioned micro-power linear power supply foldback current limiting protection circuit, comprising the following process: The input and output voltages of the buffer are set to be equal, that is, the voltages of the first test node a1 and the second test node a2 are equal. In the foldback current limiting protection circuit, the power transistor gate-source voltage limiting circuit is used to perform maximum current limiting according to the state of the regulator in the working mode adopted by the current limiting mode control circuit, which is used to perform foldback current limiting protection for the micro-power linear power supply.

[0012] Preferably, the working modes adopted by the current limiting mode control circuit include a low voltage difference working state non-current limiting working mode, a normal working voltage difference constant current limiting working mode and an output short circuit protection working mode.

[0013] Preferably, when the voltage regulator is in a low voltage difference application state, the current limiting protection is turned off, and the maximum output current of the voltage regulator is determined by the W / L of the power transistor; when the output of the voltage regulator is short-circuited to ground, the current limiting protection circuit is turned on, and the maximum output current of the voltage regulator is determined by the fourteenth P-type transistor M P14 , the fifteenth P-type transistor M P15 and the sixteenth P-type transistor M P16 The width-to-length ratio and threshold voltage determine the maximum output current I OMAX =170mA; when the voltage regulator is in normal working mode, the current limiting protection circuit is turned on, and the maximum current output by the voltage regulator is provided by the fifteenth P-type transistor M P15 and the sixteenth P-type transistor M P16 The width-to-length ratio and threshold voltage determine the maximum output current I OMAX =510mA. Preferably, when the voltage regulator is in a low voltage difference application state, the input-output voltage difference is less than 0.8V; when the voltage regulator is in a normal working mode, the input-output voltage difference is greater than 1V.

[0014] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention provides a micro-power linear power supply foldback current limiting protection circuit, the error amplifier can accurately control the eighteenth P-type transistor M by comparing the reference voltage VREF with the feedback voltage P18 The conduction degree of the output voltage VOUT is adjusted to the set value. This closed-loop feedback mechanism greatly improves the stability of the power supply and ensures that the output voltage remains constant under various load conditions. The foldback current limiting protection circuit monitors the output current. When the output current exceeds the set threshold, it can respond quickly and act on the input of the error amplifier to adjust its output signal, thereby reducing the eighteenth P-type transistor M P18 This foldback current limiting mechanism can effectively prevent power supply damage or short circuit failure caused by overcurrent.

[0015] Furthermore, the current limiting mode control circuit can monitor the magnitude of the output current in real time and trigger the current limiting mode when the current exceeds a preset threshold. By accurately controlling the input signal of the power transistor gate-source voltage limiting circuit, the output current can be accurately limited to prevent circuit damage or failure caused by overcurrent. The main function of the power transistor gate-source voltage limiting circuit is to limit the gate-source voltage of the power transistor, thereby protecting it from damage caused by excessive voltage. When the output current is too large, the circuit can respond quickly and reduce the gate-source voltage, thereby reducing the power consumption and heat generation of the power transistor and extending its service life. The foldback current limiting protection circuit can maintain the stability of the power supply system by accurately controlling the output current and gate-source voltage. In the case of sudden load changes or input voltage fluctuations, the circuit can quickly adjust the output current and voltage to ensure that the system can operate stably under various conditions.

[0016] The present invention also provides a foldback current limiting protection method for a micro-power linear power supply, which uses a current limiting mode control circuit to realize three current limiting protection working modes, including a non-current limiting working mode in a low voltage difference working state, a normal working voltage difference constant current limiting working mode, and an output short circuit protection working mode; the power transistor gate-source voltage limiting circuit design is used to realize the maximum limiting current of the regulator in the normal working voltage difference constant current limiting working mode and the output short circuit protection working mode; the circuit design is simple and can be widely used in linear regulators designed based on BiCMOS and BCD processes. Users can use the configuration reasonably according to the actual application scenarios to meet the high reliability of the regulator in different application scenarios, while effectively protecting the regulator from damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the structure of a micro-power linear power supply foldback current limiting protection circuit in an embodiment of the present invention; Figure 2 It is a schematic diagram of the structure of a micro-power foldback current limiting protection circuit in an embodiment of the present invention; Figure: 1. Error amplifier; 2. Foldback current limiting protection circuit; 3. Buffer; V IN , input voltage; V REF , reference voltage; V OUT , output voltage; R1, first resistor; R2, second resistor; 100, current limiting mode control circuit; 200, power transistor gate-source voltage limiting circuit; a1, first test node; a2, second test node; M P1 , a first P-type transistor; M P2 , a second P-type transistor; M P3 , a third P-type transistor; M P4 , a fourth P-type transistor; M P5 , fifth P-type transistor; M P6 , a sixth P-type transistor; MP7 , seventh P-type transistor; M P8 , the eighth P-type transistor; M P9 , the ninth P-type transistor; M P10 , the tenth P-type transistor; M P11 , eleventh P-type transistor; M P12 , the twelfth P-type transistor; M P13 , thirteenth P-type transistor; M P14 , fourteenth P-type transistor; M P15 , fifteenth P-type transistor; M P16 , sixteenth P-type transistor; M P17 , seventeenth P-type transistor; M P18 , eighteenth P-type transistor; M N1 , a first N-type transistor; M N2 , a second N-type transistor; M N3 , a third N-type transistor; M N4 , a fourth N-type transistor; M N5 , a fifth N-type transistor; M N6 , a sixth N-type transistor; M N7 , a seventh N-type transistor; M N8 , an eighth N-type transistor; M N9 , the ninth N-type transistor; M N10 , the tenth N-type transistor; M N11 , eleventh N-type transistor; M N12 , the twelfth N-type transistor; M N13 , thirteenth N-type transistor; M N14 , a fourteenth N-type transistor; b1, a first voltage measuring point; b2, a second voltage measuring point; b3, a third voltage measuring point; b4, a fourth voltage measuring point; b5, a fifth voltage measuring point; b6, a sixth voltage measuring point; b7, a seventh voltage measuring point; b9, a ninth voltage measuring point; b 10 , the tenth voltage measuring point; b 11 , the eleventh voltage measuring point; b 12 , the twelfth voltage measuring point; b 13 , the thirteenth voltage measuring point; b. 14 , the fourteenth voltage measuring point; b 15 , the fifteenth voltage measuring point; b. 16 , the sixteenth voltage measuring point; b 17 , the seventeenth voltage measuring point; b 18 , the eighteenth voltage measuring point; b 19 , the nineteenth voltage measuring point; b 20 , the twentieth voltage measuring point; b 21 , the 21st voltage measuring point; b 22 , the 22nd voltage measuring point; b 23, the twenty-third voltage measuring point; b 24 , the 24th voltage measuring point; D z1 , Zener diode; V B1 , first bias voltage; V B2 , the second bias voltage; Q n1 , N-type transistor; Q LP1 , LP type transistor. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0019] The purpose of the present invention is to provide a micro-power linear power supply foldback current limiting protection circuit and method to solve the technical problem in the prior art that the output function of the voltage regulator is abnormal in the low voltage difference and large output current application state of the voltage regulator.

[0020] The present invention is further described in detail below in conjunction with the accompanying drawings: Example 1 See also Figure 1 In one embodiment of the present invention, a micro-power linear power supply foldback current limiting protection circuit is provided, comprising an error amplifier 1, a foldback current limiting protection circuit 2, a buffer 3, an eighteenth P-type transistor M P18 , a first resistor R1 and a second resistor R2; the positive input terminal of the error amplifier 1 is connected to a reference voltage V REF , the power supply terminal of the error amplifier 1 is connected to the input voltage V IN The output of the error amplifier 1 is connected to the eighteenth P-type transistor M through the buffer 3. P18 The gate of the eighteenth P-type transistor M P18 The source and substrate are connected to the input voltage V IN The eighteenth P-type transistor M P18 The drain of the error amplifier 1 is connected in parallel between the first resistor R1 and the second resistor R2 and then connected to the ground; the negative input terminal of the error amplifier 1 is connected in parallel between the first resistor R1 and the second resistor R2; the eighteenth P-type transistor M P18 The output voltage V is set between the drain and the first resistor R1 OUTThe output end of the buffer 3 is provided with a first test node a1; the input end of the buffer 3 is provided with a second test node a2; the return current limiting protection circuit 2 is provided with three branches, one branch is connected to the input voltage V IN , one branch is connected to the second test node a2; and one branch is grounded after passing through the first resistor R1 and the second resistor R2.

[0021] Specifically, according to Figure 2 As shown, the foldback current limiting protection circuit 2 includes a current limiting mode control circuit 100 and a power transistor gate-source voltage limiting circuit 200; one end of the current limiting mode control circuit 100 and the power transistor gate-source voltage limiting circuit 200 are connected to the input voltage V IN ; The other ends of the current limiting mode control circuit 100 and the power transistor gate-source voltage limiting circuit 200 are grounded; the output end of the current limiting mode control circuit 100 is connected to the input end of the power transistor gate-source voltage limiting circuit 200, and the output end of the power transistor gate-source voltage limiting circuit 200 is connected to the second test node a2.

[0022] Among them, according to Figure 2 As shown, the current limiting mode control circuit 100 includes a first limiting circuit, a second limiting circuit, a third limiting circuit, a fourth limiting circuit, a fifth limiting circuit, a sixth limiting circuit, a seventh limiting circuit and an eighth limiting circuit; the first limiting circuit, the second limiting circuit, the third limiting circuit, the fourth limiting circuit, the fifth limiting circuit, the sixth limiting circuit, the seventh limiting circuit and the eighth limiting circuit are all arranged in parallel, and each limiting circuit is provided with a plurality of voltage measuring points, and is connected and arranged through the plurality of voltage measuring points; one end of the first limiting circuit, the second limiting circuit, the fourth limiting circuit and the sixth limiting circuit is connected to the input voltage V IN The other ends of the first limiting circuit, the second limiting circuit, the fourth limiting circuit, the fifth limiting circuit, and the sixth limiting circuit are grounded; wherein the first limiting circuit is connected to the first bias voltage V B1 A second bias voltage V is provided between the second limiting circuit and the fourth limiting circuit B2 One end of the third limiting circuit is connected to the output voltage V OUT , and the other end is grounded; one end of the seventh limiting circuit is connected to the input voltage V IN ; The other end is connected to the measuring point circuit; one end of the measuring point circuit is connected to the output voltage V through the sixth limiting circuit, the fifth limiting circuit, and the fourth limiting circuit in sequence OUT ; The other end is connected to the eighth limiting circuit; One end of the eighth limiting circuit is connected to the input voltage V IN ; The other end is connected to the input end of the power transistor gate-source voltage limiting circuit 200.

[0023] Among them, according to Figure 2 As shown, the first limiting circuit is provided with a first P-type transistor M P1 , the second P-type transistor M P2 , the third P-type transistor M P3 , the first N-type transistor M N1 , a first voltage measuring point b1, a second voltage measuring point b2 and a third voltage measuring point b3; the first P-type transistor M P1 The source and substrate are connected to the input voltage V IN , the gate and drain are connected to the first voltage measuring point b1; the second P-type transistor M P2 The source is connected to the first voltage measuring point b1, and the substrate is connected to the input voltage V IN , the gate and drain are connected to the second voltage measuring point b2; the third P-type transistor M P3 The source is connected to the second voltage measuring point b2, and the substrate is connected to the input voltage V IN ,, the gate and drain are connected to the third voltage measuring point b3; the first N-type transistor M N1 The source and substrate are grounded, and the gate is connected to a first bias voltage V B1 , the drain is connected to the third voltage measuring point b3; the second limiting circuit is provided with a fourth P-type transistor M P4 , the second N-type transistor M N2 , the third N-type transistor M N3 , the fourth N-type transistor M N4 , the fifth N-type transistor M N5 , a fourth voltage measuring point b4, a fifth voltage measuring point b5, a sixth voltage measuring point b6 and a seventh voltage measuring point b7; the fourth P-type transistor M P4 The source and substrate are connected to the input voltage V IN , the gate is connected to the second bias voltage V B2 , the drain is connected to the fourth voltage measuring point b4; the second N-type transistor M N2 The source of the third N-type transistor M is connected to the fifth voltage measuring point b5, the substrate is grounded, and the gate and drain are connected to the fourth voltage measuring point b4; N3 The source of the fourth N-type transistor M is connected to the sixth voltage measuring point b6, the substrate is grounded, and the gate and drain are connected to the fifth voltage measuring point b5; N4 The source of the fifth N-type transistor M is connected to the seventh voltage measuring point b7, the substrate is grounded, and the gate and drain are connected to the sixth voltage measuring point b6; N5 The source and substrate of the device are grounded, and the gate and drain are connected to the seventh voltage measuring point b7; the third amplitude limiting circuit is provided with a sixth N-type transistor M N6 , the seventh N-type transistor M N7 , the eighth N-type transistor M N8 , the ninth N-type transistor M N9 , the tenth N-type transistor MN10 , the ninth voltage measuring point b9, the tenth voltage measuring point b 10 , Eleventh voltage measuring point b 11 And the twelfth voltage measurement point b 12 The sixth N-type transistor M N6 The source and substrate of the device are connected to the ninth voltage measuring point b9, the gate is connected to the fourth voltage measuring point b4, and the drain is connected to the output voltage V OUT ; The seventh N-type transistor M N7 The source is connected to the tenth voltage measuring point b 10 , the substrate is grounded, the gate and the drain are connected to the ninth voltage measuring point b9; the eighth N-type transistor M N8 The source is connected to the eleventh voltage measuring point b 11 , the substrate is grounded, the gate and drain are connected to the tenth voltage measurement point b 10 ; Ninth N-type transistor M N9 The source is connected to the twelfth voltage measuring point b 12 , the substrate is grounded, the gate and drain are connected to the eleventh voltage measurement point b 11 ; The tenth N-type transistor M N10 The source and substrate are grounded, and the gate and drain are connected to the twelfth voltage measurement point b. 12 The fourth limiting circuit is provided with a fifth P-type transistor M P5 , the eleventh N-type transistor M N11 , the twelfth N-type transistor M N12 、Thirteenth voltage measurement point b 13 And the fourteenth voltage measurement point b 14 ; The fifth P-type transistor M P5 The source and substrate are connected to the input voltage V IN , the gate is connected to the second bias voltage V B2 , the drain is connected to the thirteenth voltage measuring point b 13 ; Eleventh N-type transistor M N11 The source and substrate of 14 , the gate is connected to the third voltage measuring point b3, and the drain is connected to the thirteenth voltage measuring point b 13 ; Twelfth N-type transistor M N12 The source and substrate of the device are grounded, the gate is connected to the ninth voltage measuring point b9, and the drain is connected to the fourteenth voltage measuring point b 14 The fifth limiting circuit is provided with a sixth P-type transistor M P6 and Zener diode D z1 The sixth P-type transistor M P6 The source is connected to the output voltage V OUT , the drain is connected to the thirteenth voltage measuring point b 13 , the substrate is connected to the input voltage V IN ; The source is connected to the third voltage measuring point b3; Zener diode Dz1 The cathode is connected to the fourteenth voltage measuring point b 14 , the anode is grounded; the sixth limiting circuit is provided with a seventh P-type transistor M P7 , the thirteenth N-type transistor M N13 And the fifteenth voltage measurement point b 15 ; The seventh P-type transistor M P7 The source and substrate are connected to the input voltage V IN , the gate is connected to the thirteenth voltage measurement point b 13 , the drain is connected to the fifteenth voltage measuring point b 15 ; Thirteenth N-type transistor M N13 The source and substrate are grounded, and the gate is connected to the fourteenth voltage measurement point b 14 , the drain is connected to the fifteenth voltage measuring point b 15 The seventh limiting circuit is provided with an eighth P-type transistor M P8 , the ninth P-type transistor M P9 , the tenth P-type transistor M P10 , 16th voltage measuring point b 16 , Seventeenth voltage measuring point b 17 And the eighteenth voltage measurement point b 18 ; The eighth P-type transistor M P8 The source and substrate are connected to the input voltage V IN , the gate and drain are connected to the sixteenth voltage measuring point b 16 ; Ninth P-type transistor M P9 The source is connected to the sixteenth voltage measuring point b 16 , the substrate is connected to the input voltage V IN , the gate and drain are connected to the seventeenth voltage measuring point b 17 ; The tenth P-type transistor M P10 The source is connected to the seventeenth voltage measuring point b 17 , the substrate is connected to the input voltage V IN , the gate and drain are connected to the eighteenth voltage measuring point b 18 ; The eighteenth voltage measurement point b 18 The eighth amplitude limiting circuit is provided with an eleventh P-type transistor M P11 ; Eleventh P-type transistor M P11 The source and substrate are connected to the input voltage V IN , the gate is connected to the eighteenth voltage measuring point b 18 , the drain is connected to the input end of the power transistor gate-source voltage limiting circuit 200 .

[0024] Among them, according to Figure 2As shown, the power transistor gate-source voltage limiting circuit 200 includes a ninth limiting circuit, a tenth limiting circuit and an eleventh limiting circuit; the ninth limiting circuit, the tenth limiting circuit and the eleventh limiting circuit are all arranged in parallel; each limiting circuit is provided with a plurality of voltage measuring points, and is connected and arranged through the plurality of voltage measuring points; one end of the ninth limiting circuit is connected to the eleventh P-type transistor M P11 The drain of the tenth limiter circuit is connected to the input voltage V IN , and the other end is grounded; one end of the eleventh limiting circuit is connected to the input voltage V IN , and the other end is connected to the second test node a2.

[0025] Among them, according to Figure 2 As shown, the ninth limiting circuit is provided with a twelfth P-type transistor M P12 , the thirteenth P-type transistor M P13 , the fourteenth P-type transistor M P14 , the fifteenth P-type transistor M P15 , the sixteenth P-type transistor M P16 , the fourteenth N-type transistor M N14 、Nineteenth voltage measurement point b 19 、20th voltage measurement point b 20 、21st voltage measurement point b 21 、22nd voltage measurement point b 22 And the twenty-third voltage measurement point b 23 ; Twelfth P-type transistor M P12 The source and substrate are connected to the nineteenth voltage measuring point b 19 , the gate is connected to the fifteenth voltage measurement point b 15 , the drain is connected to the 20th voltage measurement point b 20 ; Thirteenth P-type transistor M P13 The source and substrate are connected to the 20th voltage measurement point b 20 ; The gate and drain are connected to the 21st voltage measurement point b 21 ; Fourteenth P-type transistor M P14 The source and substrate are connected to the 21st voltage measurement point b 21 , the gate and drain are connected to the 22nd voltage measurement point b 22 ; Fifteenth P-type transistor M P15 The source and substrate are connected to the nineteenth voltage measuring point b 19 , the gate and drain are connected to the 22nd voltage measurement point b 22 ; Sixteenth P-type transistor M P16 The source and substrate of 22 , the gate and drain are connected to the 23rd voltage measuring point b 23 ; Fourteenth N-type transistor M N14The source and substrate are grounded, and the gate is connected to a first bias voltage V B1 , the drain is connected to the 23rd voltage measuring point b 23 The tenth limiting circuit is provided with a seventeenth P-type transistor M P17 、24th voltage measurement point b 24 And LP transistor Q LP1 ; Seventeenth P-type transistor M P17 The source and substrate are connected to the input voltage V IN , the gate is connected to the second bias voltage V B2 , the drain is connected to the 24th voltage measuring point b 24 ; LP type transistor Q LP1 The collector is grounded, and the base is connected to the 23rd voltage measuring point b 23 , the emitter is connected to the 24th voltage measuring point b 24 The eleventh limiting circuit is provided with an N-type transistor Q n1 ; The N-type transistor Q n1 The collector of the input voltage V IN , the base is connected to the 24th voltage measuring point b 24 , the emitter is connected to the second test node a2.

[0026] Example 2 This embodiment 2 provides a micro-power linear power supply foldback current limiting protection method, based on the micro-power linear power supply foldback current limiting protection circuit described above, including the following process: The input and output voltages of the buffer are equal, that is, the voltages of the first test node a1 and the second test node a2 are equal. The current limiting circuit compares the input voltage and the output voltage. When the regulator is under heavy load, it limits the output voltage of the error amplifier in the regulator loop, thereby controlling the adjustment device 18th P-type transistor M P18 The gate-source voltage V GS , reaches the limit power of the eighteenth P-type transistor M P18 The working current. When V OUT =0V, 3V≤V IN ≤11.5V (input voltage is normal working voltage), V IN -V a1 =V X , V GSMP1 = V X , the operating current of the power transistor is 170mA; when 1.25V≤V OUT ≤11.0V, 3V≤V IN ≤11.5V (input voltage is normal working voltage), V IN -V OUT ≥1V, V IN -V a1= V Y , V GSMP1 = V Y , the operating current of the power transistor is 510mA; when 1.25V≤V OUT ≤11.0V, 3V≤V IN ≤11.5V (input voltage is normal working voltage), V IN -V OUT ≤0.8V, V GSMP1 = V Z , the foldback current limiting protection circuit is in an open circuit state, the output node voltage of the error amplifier in the voltage regulation loop is not controlled by the foldback current limiting protection circuit, and the output current capability of the power transistor is determined by its own width-to-length ratio. Generally, the design I OUT About 1A; when the regulator is in three different working modes, V X ≤V Y ≤V Z .

[0027] In this embodiment, the static current of each analog branch is at the nanoampere level. Without affecting the normal operation of the voltage regulator, three working states are adopted: the first is a low voltage difference working state, in which the current limiting protection circuit does not limit the output current; the second is a voltage regulator output short-circuit state to ground, in which the output circuit is limited to 170mA; the third is a normal working state, in which the output current is limited to 510mA.

[0028] In this embodiment, a micro-power foldback current limiting protection circuit is composed of a current limiting mode control circuit 100 and a power transistor gate-source voltage limiting circuit 200. By comparing the input voltage and the output voltage, the output voltage of the error amplifier in the regulator loop is limited, thereby controlling the adjustment device such as Figure 1 The eighteenth P-type transistor M shown P18 The gate-source voltage V GS , reaches the limit power of the eighteenth P-type transistor M P18 The working current.

[0029] Specifically, the principle of the current limiting mode control circuit 100 is as follows: the first P-type transistor M P1 , the second P-type transistor M P2 , the third P-type transistor M P3 , the first N-type transistor M N1 The first limiting circuit is formed, and the voltage at the third voltage measuring point b3 is equal to the input voltage V IN The difference is V GSMP1 + V GSMP2 + V GSMP3 , the first N-type transistor M N1 is the current mirror transistor, V B1is the first bias voltage. When 7V≤VIN≤11.5, the first N-type transistor M N1 The transistor source and drain are subjected to a higher voltage, and the first P-type transistor M P1 , the second P-type transistor M P2 , the third P-type transistor M P3 , the first N-type transistor M N1 It is a thin gate oxide source-drain high voltage device; the second N-type transistor M N2 , the third N-type transistor M N3 , the fourth N-type transistor M N4 , the fifth N-type transistor M N5 , the fourth P-type transistor M P4 The second limiting circuit is formed, and the difference between the voltage at the fourth voltage measuring point b4 and GND is V GSMN2 + V GS MN3 + V GS GS MN4 +V GS GS MN5 , the fourth P-type transistor M P4 is the current mirror transistor, V B2 is the second bias voltage, when 7V≤VIN≤11.5, the fourth P-type transistor M P4 The transistor source and drain are subjected to a higher voltage, and the second N-type transistor M N2 , the third N-type transistor M N3 , the fourth N-type transistor M N4 , the fifth N-type transistor M N5 , the fourth P-type transistor M P4 A thin gate oxide source-drain high voltage device; a sixth N-type transistor M N6 , the seventh N-type transistor M N7 , the eighth N-type transistor M N8 , the ninth N-type transistor M N9 , the tenth N-type transistor M N10 The signal transmission circuit is composed. When it works normally, the voltage of the ninth voltage measuring point b9 is equal to the output voltage V OUT , the seventh N-type transistor M N7 , the eighth N-type transistor M N8 , the ninth N-type transistor M N9 , the tenth N-type transistor M N10 The transistors form the third limiting circuit. The difference between the voltage at the ninth voltage measuring point b9 and GND is V GSMN7 + V GS MN8 + V GS GS MN9 + V GS GS MN10 , when 7V≤VIN≤11.5V, the sixth N-type transistor M N6 The sixth N-type transistor M is subjected to a higher voltage between the source and the drain. N6 , the seventh N-type transistor M N7, the eighth N-type transistor M N8 , the ninth N-type transistor M N9 , the tenth N-type transistor M N10 The transistor is a thin gate oxide source-drain high voltage device; the fifth P-type transistor M P5 , the eleventh N-type transistor M N11 , the eleventh N-type transistor M N12 The transistors form a common source amplifier circuit, the fifth P-type transistor M P5 is the current mirror transistor, V B2 is the second bias voltage, isolated common-gate device, the thirteenth voltage measurement point b 13 and the fourteenth voltage measuring point b 14 Separate, when 7V≤V IN ≤11.5V, the eleventh N-type transistor M N11 The source and drain bear a larger voltage, and the twelfth N-type transistor M N12 The fifth P-type transistor M is the input transistor of the common source amplifier. P5 , the eleventh N-type transistor M N11 , the twelfth N-type transistor M N12 is a thin gate oxide source-drain high voltage transistor; the seventh P-type transistor M P7 and the thirteenth N-type transistor M N13 The seventh P-type transistor M forms a common source amplifier. P7 is a bias current source, the thirteenth N-type transistor M N13 is an input transistor, the seventh P-type transistor M P7 and the thirteenth N-type transistor M N13 It is a thin gate oxide source-drain high voltage transistor.

[0030] Specifically, the principle of the power transistor gate-source voltage limiting circuit 200 is as follows: when the eleventh P-type transistor M P11 The transistor is turned on, the twelfth P-type transistor M P12 When the transistor is turned off, the 23rd voltage measurement point b 23 The voltage at point V IN -V GSMP15 -V GSMP16 , the fourteenth N-type transistor M N14 For current mirror transistor, when 7V≤V IN ≤11.5V, the fourteenth N-type transistor M N14 The transistor source and drain are subject to a higher voltage, and the LP transistor Q LP1 , N-type transistor Q n1 The voltage of the second test node a2 is equal to the voltage of the twenty-third voltage measurement point b. 23 The voltage is V IN -V GSMP15 -VGSMP16 ; When the eleventh P-type transistor M P11 The transistor is turned on, the twelfth P-type transistor M P12 When the transistor is turned on, the 23rd voltage measurement point b 23 The voltage is V IN -V GSMP14∥GSMP15 -V GSMP16 , the fourteenth N-type transistor M N14 For current mirror transistor, when 7V≤V IN ≤11.5V, the fourteenth N-type transistor M N14 The transistor source and drain are subject to a higher voltage, and the LP transistor Q LP1 , N-type transistor Q n1 The voltage of the second test node a2 is equal to the voltage of the twenty-third voltage measurement point b. 23 The voltage is V IN -V GSMP14∥GSMP15 -V GSMP16 Under this condition, the fourteenth P-type transistor M P14 and the fifteenth P-type transistor M P15 At the same time in the on state.

[0031] When V OUT =0V, 3V≤V IN ≤11.5V (input voltage is normal working voltage), V IN -V OUT ≥V SGMP11 , the sixth P-type transistor M P6 The transistor is turned on, the eighteenth voltage measurement point b 18 The voltage is equal to the output voltage V OUT , the eleventh P-type transistor M P11 Transistor is turned on, the nineteenth voltage measurement point b 19 The voltage is equal to the input voltage V IN , the voltage of the ninth voltage measuring point b9 is equal to V OUT =0V, the twelfth N-type transistor M N12 Transistor is turned off, the fourteenth voltage measurement point b 14 Voltage equal to V IN -V GSMP1 -V GSMP2 -V GSMP3 -V GSMN11 , Zener diode D Z1 Limit the fourteenth voltage measurement point b 14 The voltage is not greater than V DZ (Reverse breakdown voltage of Zener diode), the thirteenth N-type transistor is turned on, the fifteenth voltage measurement point b 15 The voltage of the twelfth P-type transistor M is close to 0V. P12The fourteenth P-type transistor M is turned on. P14 , the fifteenth P-type transistor M P15 , the sixteenth P-type transistor M P16 In saturated working state, the 23rd voltage measurement point b 23 The voltage is shown in formula (1).

[0032] (1) K P is the current transfer factor of the PMOS transistor.

[0033] LP type transistor Q LP1 And N-type transistor Q n1 The voltage of the first test node a2 is equal to the voltage of the twenty-third voltage measuring point b. 23 The maximum driving voltage of the regulator is as shown in formula (2).

[0034] (2) Under this output short-circuit current limiting mode condition, the maximum output current of the regulator is provided by the fourteenth P-type transistor M P14 , the fifteenth P-type transistor M P15 transistor and the sixteenth P-type transistor M P16 The width-to-length ratio and threshold voltage are determined by the design to adjust the maximum output current I OMAX =170mA.

[0035] When 1.25V≤V OUT ≤11.0V, V IN -V OUT ≥V SGMP11 , 3V≤V IN ≤11.5V (input voltage is normal working voltage), the sixth P-type transistor M P6 Conductivity, 18th voltage measurement point b 18 The voltage is equal to the output voltage V OUT , the eleventh P-type transistor M P11 Conductivity, 19th voltage measurement point b 19 The voltage is equal to the input voltage V IN , the voltage at the ninth voltage measuring point b9 is equal to the output voltage V OUT , the twelfth N-type transistor M N12 Conductivity, fourteenth voltage measurement point b 14 The voltage is equal to 0, the Zener diode D Z1 Limit the fourteenth voltage measurement point b 14 The voltage is not greater than V DZ (Reverse breakdown voltage of Zener diode), thirteenth N-type transistor M N13 End, the fifteenth voltage measurement point b15 The voltage is close to the input voltage V IN , the twelfth P-type transistor M P12 The fourteenth P-type transistor M is turned off. P14 The fifteenth P-type transistor M is turned off. P15 , the sixteenth P-type transistor M P16 In saturated working state, the 23rd voltage measurement point b 23 The voltage is shown in formula (3).

[0036] (3) K P is the current transfer factor of the PMOS transistor.

[0037] LP type transistor Q LP1 And N-type transistor Q n1 For an emitter-follower structure, the voltage of the second test node a2 is equal to the voltage of the twenty-third voltage measurement point b 23 The voltage of the second test node a2 is expressed as follows:

[0038] (4) Under this normal application working current limiting mode condition, the maximum output current of the regulator is provided by the fifteenth P-type transistor M P15 and the sixteenth P-type transistor M P16 The width-to-length ratio and threshold voltage are determined by the design to adjust the maximum output current I OMAX =510mA.

[0039] When 1.25V≤V OUT ≤11.0V, V IN -V OUT ≤V SGMP11 , 3V≤V IN ≤11.5V (input voltage is the normal working voltage), the eleventh P-type transistor M P11 The fourteenth N-type transistor M is turned off. N14 For a normal working current mirror, the nineteenth voltage measurement point b 19 The voltage of the twenty-third voltage measuring point b is equal to 0. 23 The voltage of the 24th voltage measuring point b24 is V BE , in normal application mode, the N-type transistor Q n1 Cut off, the current limiting protection circuit output is in high impedance state and does not play the role of current limiting protection.

[0040] In this type of low voltage dropout application, the current limiting protection does not work, and the maximum output current of the regulator is determined by the W / L of the power transistor.

[0041] In summary, the present invention provides a micro-power linear power supply foldback current limiting protection circuit and method, in which the error amplifier can accurately control the conduction degree of the eighteenth P-type transistor MP18 by comparing the reference voltage VREF with the feedback voltage, thereby adjusting the output voltage VOUT to a set value. This closed-loop feedback mechanism greatly improves the stability of the power supply and ensures that the output voltage can remain constant under various load conditions. The foldback current limiting protection circuit monitors the output current. When the output current exceeds the set threshold, it can quickly respond and act on the input end of the error amplifier, adjust its output signal, and then reduce the conduction degree of the eighteenth P-type transistor MP18 to achieve current limiting protection. This foldback current limiting mechanism can effectively prevent power supply damage or short circuit failure caused by overcurrent.

[0042] The present invention adopts a current limiting mode control circuit to realize three current limiting protection working modes, namely, a non-current limiting working mode in a low voltage difference working state, a constant current limiting working mode in a normal working voltage difference, and an output short circuit protection working mode; the gate-source voltage limiting circuit design of a power transistor is used to realize the maximum limiting current of the voltage regulator in the normal working voltage difference constant current limiting working mode and the output short circuit protection working mode; the circuit design is simple and can be widely used in linear voltage regulators designed based on BiCMOS and BCD processes. Users can use the configuration reasonably according to the actual application scenarios to meet the high reliability of the voltage regulator in different application scenarios, and effectively protect the voltage regulator from damage.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A micro-power linear power supply foldback current limiting protection circuit, characterized in that: It includes an error amplifier (1), a foldback current limiting protection circuit (2), a buffer (3), an eighteenth P-type transistor M P18 , a first resistor R1 and a second resistor R2; The positive input terminal of the error amplifier (1) is connected to the reference voltage V REF , the power supply terminal of the error amplifier (1) is connected to the input voltage V IN The output of the error amplifier (1) is connected to the eighteenth P-type transistor M through the buffer (3). P18 The gate of the eighteenth P-type transistor M P18 The source and substrate are connected to the input voltage V IN The eighteenth P-type transistor M P18 The drain of the error amplifier (1) is connected in parallel between the first resistor R1 and the second resistor R2 and then connected to the ground. The eighteenth P-type transistor M P18 The output voltage V is set between the drain and the first resistor R1 OUT ; A first test node a1 is provided at the output end of the buffer (3); a second test node a2 is provided at the input end of the buffer (3); The foldback current limiting protection circuit (2) is provided with three branches, one of which is connected to the input voltage V IN , one branch connects to the second test node a2; one branch connects to V OUT .

2. A micro-power linear power supply foldback current limiting protection circuit according to claim 1, characterized in that: The foldback current limiting protection circuit (2) comprises a current limiting mode control circuit (100) and a power transistor gate-source voltage limiting circuit (200); One end of the current limiting mode control circuit (100) and the power transistor gate-source voltage limiting circuit (200) is connected to an input voltage V IN ; The other ends of the current limiting mode control circuit (100) and the power transistor gate-source voltage limiting circuit (200) are grounded; The output end of the current limiting mode control circuit (100) is connected to the input end of the power transistor gate-source voltage limiting circuit (200), and the output end of the power transistor gate-source voltage limiting circuit (200) is connected to the second test node a2.

3. A micro-power linear power supply foldback current limiting protection circuit according to claim 2, characterized in that: The current limiting mode control circuit (100) comprises a first amplitude limiting circuit, a second amplitude limiting circuit, a third amplitude limiting circuit, a fourth amplitude limiting circuit, a fifth amplitude limiting circuit, a sixth amplitude limiting circuit, a seventh amplitude limiting circuit and an eighth amplitude limiting circuit; The first limiting circuit, the second limiting circuit, the third limiting circuit, the fourth limiting circuit, the fifth limiting circuit, the sixth limiting circuit, the seventh limiting circuit and the eighth limiting circuit are all arranged in parallel, and each limiting circuit is provided with a plurality of voltage measuring points, and is connected and arranged through the plurality of voltage measuring points; One end of the first limiting circuit, the second limiting circuit, the fourth limiting circuit, and the sixth limiting circuit is connected to the input voltage V IN The other ends of the first limiting circuit, the second limiting circuit, the fourth limiting circuit, the fifth limiting circuit, and the sixth limiting circuit are grounded; wherein the first limiting circuit is connected to the first bias voltage V B1 A second bias voltage V is provided between the second limiting circuit and the fourth limiting circuit B2 ; One end of the third limiting circuit is connected to the output voltage V OUT , the other end is grounded; One end of the seventh limiting circuit is connected to the input voltage V IN ; The other end is connected to the measuring point circuit; one end of the measuring point circuit is connected to the output voltage V through the sixth limiting circuit, the fifth limiting circuit, and the fourth limiting circuit in sequence OUT ; The other end is connected to the eighth limiting circuit; One end of the eighth limiting circuit is connected to the input voltage V IN ; The other end is connected to the input end of the power transistor gate-source voltage limiting circuit (200).

4. A micro-power linear power supply foldback current limiting protection circuit according to claim 3, characterized in that: The first limiting circuit is provided with a first P-type transistor M P1 , the second P-type transistor M P2 , the third P-type transistor M P3 , the first N-type transistor M N1 , a first voltage measuring point b1, a second voltage measuring point b2 and a third voltage measuring point b3; The first P-type transistor M P1 The source and substrate are connected to the input voltage V IN , the gate and drain are connected to the first voltage measuring point b1; the second P-type transistor M P2 The source is connected to the first voltage measuring point b1, and the substrate is connected to the input voltage V IN , the gate and drain are connected to the second voltage measuring point b2; the third P-type transistor M P3 The source is connected to the second voltage measuring point b2, and the substrate is connected to the input voltage V IN ,, the gate and drain are connected to the third voltage measuring point b3; the first N-type transistor M N1 The source and substrate are grounded, and the gate is connected to a first bias voltage V B1 , the drain is connected to the third voltage measuring point b3; The second amplitude limiting circuit is provided with a fourth P-type transistor M P4 , the second N-type transistor M N2 , the third N-type transistor M N3 , the fourth N-type transistor M N4 , the fifth N-type transistor M N5 , a fourth voltage measuring point b4, a fifth voltage measuring point b5, a sixth voltage measuring point b6 and a seventh voltage measuring point b7; The fourth P-type transistor M P4 The source and substrate are connected to the input voltage V IN , the gate is connected to the second bias voltage V B2 , the drain is connected to the fourth voltage measuring point b4; the second N-type transistor M N2 The source of the third N-type transistor M is connected to the fifth voltage measuring point b5, the substrate is grounded, and the gate and drain are connected to the fourth voltage measuring point b4; N3 The source of the fourth N-type transistor M is connected to the sixth voltage measuring point b6, the substrate is grounded, and the gate and drain are connected to the fifth voltage measuring point b5; N4 The source electrode is connected to the seventh voltage measuring point b7, the substrate is grounded, and the gate and the drain electrode are connected to the sixth voltage measuring point b6; The fifth N-type transistor M N5 The source and substrate are grounded, and the gate and drain are connected to the seventh voltage measuring point b7; The third amplitude limiting circuit is provided with a sixth N-type transistor M N6 , the seventh N-type transistor M N7 , the eighth N-type transistor M N8 , the ninth N-type transistor M N9 , the tenth N-type transistor M N10 , the ninth voltage measuring point b9, the tenth voltage measuring point b 10 , Eleventh voltage measuring point b 11 And the twelfth voltage measurement point b 12 ; The sixth N-type transistor M N6 The source and substrate of the device are connected to the ninth voltage measuring point b9, the gate is connected to the fourth voltage measuring point b4, and the drain is connected to the output voltage V OUT ; The seventh N-type transistor M N7 The source is connected to the tenth voltage measuring point b 10 , the substrate is grounded, the gate and the drain are connected to the ninth voltage measuring point b9; the eighth N-type transistor M N8 The source is connected to the eleventh voltage measuring point b 11 , the substrate is grounded, the gate and drain are connected to the tenth voltage measurement point b 10 ; The ninth N-type transistor M N9 The source is connected to the twelfth voltage measuring point b 12 , the substrate is grounded, the gate and drain are connected to the eleventh voltage measurement point b 11 The tenth N-type transistor M N10 The source and substrate are grounded, and the gate and drain are connected to the twelfth voltage measurement point b. 12 ; The fourth amplitude limiting circuit is provided with a fifth P-type transistor M P5 , the eleventh N-type transistor M N11 , the twelfth N-type transistor M N12 、Thirteenth voltage measurement point b 13 And the fourteenth voltage measuring point b 14 ; The fifth P-type transistor M P5 The source and substrate are connected to the input voltage V IN , the gate is connected to the second bias voltage V B2 , the drain is connected to the thirteenth voltage measuring point b 13 ; Eleventh N-type transistor M N11 The source and substrate of 14 , the gate is connected to the third voltage measuring point b3, and the drain is connected to the thirteenth voltage measuring point b 13 ; Twelfth N-type transistor M N12 The source and substrate of the device are grounded, the gate is connected to the ninth voltage measuring point b9, and the drain is connected to the fourteenth voltage measuring point b 14 ; The fifth amplitude limiting circuit is provided with a sixth P-type transistor M P6 and Zener diode D z1 The sixth P-type transistor M P6 The source is connected to the output voltage V OUT , the drain is connected to the eighteenth voltage measuring point b 18 , the substrate is connected to the input voltage V IN ; The gate is connected to the third voltage measuring point b3; Zener diode D z1 The cathode is connected to the fourteenth voltage measuring point b 14 , anode grounding setting; The sixth amplitude limiting circuit is provided with a seventh P-type transistor M P7 , the thirteenth N-type transistor M N13 And the fifteenth voltage measurement point b 15 ; The seventh P-type transistor M P7 The source and substrate are connected to the input voltage V IN , the gate is connected to the thirteenth voltage measurement point b 13 , the drain is connected to the fifteenth voltage measuring point b 15 ; Thirteenth N-type transistor M N13 The source and substrate are grounded, and the gate is connected to the fourteenth voltage measurement point b 14 , the drain is connected to the fifteenth voltage measuring point b 15 ; The seventh amplitude limiting circuit is provided with an eighth P-type transistor M P8 , the ninth P-type transistor M P9 , the tenth P-type transistor M P10 , 16th voltage measuring point b 16 , Seventeenth voltage measuring point b 17 And the eighteenth voltage measurement point b 18 ; The eighth P-type transistor M P8 The source and substrate are connected to the input voltage V IN , the gate and drain are connected to the sixteenth voltage measuring point b 16 ; Ninth P-type transistor M P9 The source is connected to the sixteenth voltage measuring point b 16 , the substrate is connected to the input voltage V IN , the gate and drain are connected to the seventeenth voltage measuring point b 17 ; The tenth P-type transistor M P10 The source is connected to the seventeenth voltage measuring point b 17 , the substrate is connected to the input voltage V IN , the gate and drain are connected to the eighteenth voltage measuring point b 18 ; The eighteenth voltage measurement point b 18 Set on the measuring point circuit; The eighth amplitude limiting circuit is provided with an eleventh P-type transistor M P11 ; Eleventh P-type transistor M P11 The source and substrate are connected to the input voltage V IN , the gate is connected to the eighteenth voltage measuring point b 18 , the drain is connected to the input end of the power transistor gate-source voltage limiting circuit 200 .

5. A micro-power linear power supply foldback current limiting protection circuit according to claim 4, characterized in that: The power transistor gate-source voltage limiting circuit (200) comprises a ninth limiting circuit, a tenth limiting circuit and an eleventh limiting circuit; The ninth limiting circuit, the tenth limiting circuit and the eleventh limiting circuit are all arranged in parallel; each limiting circuit is provided with a plurality of voltage measuring points, and is connected and arranged through the plurality of voltage measuring points; One end of the ninth amplitude limiting circuit is connected to the eleventh P-type transistor M P11 The drain of the device and the other end of the device are grounded; One end of the tenth amplitude limiting circuit is connected to the input voltage V IN , the other end is grounded; One end of the eleventh amplitude limiting circuit is connected to the input voltage V IN , and the other end is connected to the second test node a2.

6. A micro-power linear power supply foldback current limiting protection circuit according to claim 5, characterized in that: The ninth amplitude limiting circuit is provided with a twelfth P-type transistor M P12 , the thirteenth P-type transistor M P13 , the fourteenth P-type transistor M P14 , the fifteenth P-type transistor M P15 , the sixteenth P-type transistor M P16 , the fourteenth N-type transistor M N14 、Nineteenth voltage measurement point b 19 、20th voltage measurement point b 20 、21st voltage measurement point b 21 、22nd voltage measurement point b 22 And the twenty-third voltage measurement point b 23 ; Twelfth P-type transistor M P12 The source and substrate are connected to the nineteenth voltage measuring point b 19 , the gate is connected to the fifteenth voltage measurement point b 15 , the drain is connected to the 20th voltage measurement point b 20 ; Thirteenth P-type transistor M P13 The source and substrate are connected to the 20th voltage measurement point b 20 ; The gate and drain are connected to the 21st voltage measurement point b 21 ; Fourteenth P-type transistor M P14 The source and substrate are connected to the 21st voltage measurement point b 21 , the gate and drain are connected to the 22nd voltage measurement point b 22 ; Fifteenth P-type transistor M P15 The source and substrate are connected to the nineteenth voltage measuring point b 19 , the gate and drain are connected to the 22nd voltage measurement point b 22 ; Sixteenth P-type transistor M P16 The source and substrate of 22 , the gate and drain are connected to the 23rd voltage measuring point b 23 ; Fourteenth N-type transistor M N14 The source and substrate are grounded, and the gate is connected to a first bias voltage V B1 , the drain is connected to the 23rd voltage measuring point b 23 ; The tenth amplitude limiting circuit is provided with a seventeenth P-type transistor M P17 、24th voltage measurement point b 24 And LP transistor Q LP1 ; The seventeenth P-type transistor M P17 The source and substrate are connected to the input voltage V IN , the gate is connected to the second bias voltage V B2 , the drain is connected to the 24th voltage measuring point b 24 ; LP type transistor Q LP1 The collector is grounded, and the base is connected to the 23rd voltage measurement point b 23 , the emitter is connected to the 24th voltage measuring point b 24 ; The eleventh amplitude limiting circuit is provided with an N-type transistor Q n1 ; The N-type transistor Q n1 The collector of the input voltage V IN , the base is connected to the 24th voltage measuring point b 24 , the emitter is connected to the second test node a2.

7. A micro-power linear power supply foldback current limiting protection method, based on a micro-power linear power supply foldback current limiting protection circuit according to any one of claims 1 to 6, characterized in that: The process includes the following: The input and output voltages of the buffer (3) are set to be equal, that is, the voltages of the first test node a1 and the second test node a2 are equal, and the power transistor gate-source voltage limiting circuit (200) is used in the foldback current limiting protection circuit (2) to perform maximum current limiting according to the state of the voltage regulator in the working mode adopted by the current limiting mode control circuit (100), so as to perform foldback current limiting protection for the micro-power linear power supply.

8. A micro-power linear power supply foldback current limiting protection method according to claim 7, characterized in that: The working modes adopted by the current limiting mode control circuit (100) include a low voltage difference working state non-current limiting working mode, a normal working voltage difference constant current limiting working mode and an output short circuit protection working mode.

9. A foldback current limiting protection method for a micro-power linear power supply according to claim 7, characterized in that: When the voltage regulator is in a low voltage drop application state, the current limiting protection is turned off, and the maximum output current of the voltage regulator is determined by the W / L of the power transistor; when the output of the voltage regulator is short-circuited to ground, the current limiting protection circuit is turned on, and the maximum output current of the voltage regulator is determined by the fourteenth P-type transistor M P14 , the fifteenth P-type transistor M P15 and the sixteenth P-type transistor M P16 The width-to-length ratio and threshold voltage determine the maximum output current I OMAX =170mA; when the voltage regulator is in normal working mode, the current limiting protection circuit is turned on, and the maximum current output by the voltage regulator is provided by the fifteenth P-type transistor M P15 and the sixteenth P-type transistor M P16 The width-to-length ratio and threshold voltage determine the maximum output current I OMAX =510mA.

10. A micro-power linear power supply foldback current limiting protection method according to claim 9, characterized in that: When the voltage regulator is in a low voltage difference application state, the input-output voltage difference is less than 0.8V; when the voltage regulator is in a normal working mode, the input-output voltage difference is greater than 1V.

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