Single-precision floating-point number extraction operation device and operation method

Abstract

The invention relates to the field of floating-point number operation processing, and discloses a single-precision floating-point number extraction operation device and method. The operation device comprises a floating-point number preprocessing unit, a symbol index processing unit, an initial valuation unit, an initial iteration module, an initial iteration correction module, a multiplexer, an operation iteration unit I, an operation iteration unit II, an operation iteration unit III, a leading zero detection module I, a mantissa rounding compensation unit, a rounding processing module and an operation combination module. According to the device and the method disclosed by the invention, by adding and controlling an additional iteration path, the precision of an initial iteration value is improved, the number of iterations required for calculating to the same precision is reduced, the error between a final iteration result and an actual value is reduced, and the calculation efficiency is improved. The method is suitable for being applied to application scenes such as a microcontroller, a digital signal processor and a CPU (Central Processing Unit) which need to realize hardware extraction operation.

Description

Technical Field

[0001] The present invention relates to the field of floating point number operation processing, and in particular to a single-precision floating point number square root operation device and operation method. Background Art

[0002] Square root operation is a common instruction in the current processor instruction set. Its hardware implementation is generally divided into two categories: digital recursion (based on subtraction operation) and function iteration (based on multiplication operation). Among them, the digital recursion method commonly uses the SRT algorithm, and the two commonly used function iterations are the Newton-Raphson algorithm and the Goldschmidt algorithm. In addition, when the calculation accuracy is not required to be high, the table lookup method can be used to directly obtain a corresponding estimated value based on the mantissa of the input floating point number.

[0003] The above methods have their own advantages and disadvantages:

[0004] The digital recursive method is suitable for hardware circuit implementation and occupies little resources; however, it is slow and difficult to control the precision of floating-point operations. The function iteration method can dynamically adjust the number of iterations to meet the precision requirements, and can obtain high-precision results with fewer iterations under appropriate initial values; however, its hardware implementation complexity is high and the convergence speed is more dependent on the initial value. The table lookup method has fast calculation speed and simple implementation; however, it requires a large storage space for high-precision and large-range values, and the accuracy is also related to the resolution of the lookup table. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a single-precision floating-point square root operation device and operation method, so as to improve the accuracy of the initial iterative value, reduce the number of iterations required for calculation to the same accuracy, and reduce the error.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] A single-precision floating-point square root operation device comprises a floating-point preprocessing unit, a sign exponent processing unit, an initial estimation unit, an initial iteration module, an initial iteration correction module, a multiplexer, an operation iteration unit, a leading zero detection module 1, a mantissa rounding compensation unit, a rounding processing module and an operation combination module;

[0008] The floating point number preprocessing unit is used to split the floating point number into three parts, namely, a sign, an exponent and a mantissa;

[0009] The sign-exponent processing unit is used to receive the sign and exponent sent by the floating-point number preprocessing unit, and judge whether it is a non-negative single-precision floating-point number and a non-standard number according to the sign. If it is non-negative and a non-standard number at the same time, the exponent is shifted and added to obtain the exponential result after the corresponding square root, and the sign bit is retained and sent to the operation combination module; if it is not non-negative or not a non-standard number, a data exception signal is sent to the operation combination module, so that the operation combination module selects the source of the final output result;

[0010] The initial valuation unit comprises two valuation tables, which are used to receive the exponent and mantissa sent by the floating-point number preprocessing unit, and select one of the valuation tables to perform initial valuation on the mantissa according to the parity of the exponent to obtain valuation one, valuation two, valuation three and valuation four. Valuation one and valuation two are sent to the initial iteration module as initial iteration values, and valuation three and valuation four are sent to the initial iteration correction module as initial iteration values;

[0011] The initial iteration module is used to receive the mantissa sent by the floating point number preprocessing unit and the estimation 1 and the estimation 2 sent by the initial estimation unit, perform an iterative operation, and output iterative values ​​x0_1, b0_1 and y0_1, as well as a correction parameter σ;

[0012] The initial iterative correction module is used to receive the mantissa sent by the floating point preprocessing unit and the third and fourth estimates sent by the initial estimation unit, perform iterative correction operations, and output iterative correction values ​​x0_2, b0_2 and y0_2;

[0013] The multiplexer is used to receive the iteration values ​​x0_1, b0_1 and y0_1 sent by the initial iteration module, as well as the correction parameter σ, and the iteration correction values ​​x0_2, b0_2 and y0_2 sent by the initial iteration correction module, and select and output one group thereof according to the correction parameter σ as the iteration values ​​x0, b0, y0;

[0014] The operation iteration unit is used to receive the iteration values ​​x0, b0, y0 sent by the multiplexer, and perform multiplication operation to obtain a 64-bit operation result x3 and an intermediate operation result y2;

[0015] The leading zero detection module 1 is used to receive the operation result x3 sent by the operation iteration unit, and perform leading zero detection on the result to ensure that the first digit of the data format output subsequently is 1;

[0016] The mantissa rounding compensation unit is used to determine whether the mantissa needs to be compensated according to the intermediate operation result y2 of the operation iteration unit, and send a compensation signal to the rounding processing module;

[0017] The rounding processing module: according to the compensation signal sent by the mantissa rounding compensation unit, a shift operation needs to be performed according to the output result of the leading zero detection module 1 to ensure that the first bit of the subsequent output data format is 1, and the shifted data is rounded to obtain a carry parameter;

[0018] The operation combination module is used to receive the high 23 bits and carry parameter of the 64-bit mantissa result sent by the rounding processing module, the data exception signal or the sign and the exponent after square root sent by the sign exponent processing unit, and if the data exception signal is received, the result of the rounding processing module is selected for addition and data splicing processing; if the sign and the exponent after square root are received, the addition and data splicing processing are directly performed to obtain the single-precision floating-point square root operation result that finally complies with the IEEE754 format.

[0019] In the above scheme, the valuation one and the valuation three are the valuations of the reciprocal square root of the mantissa; the valuation two and the valuation four are the valuations of the reciprocal value of the mantissa; and the valuation three is greater than the valuation one, and the valuation four is greater than the valuation two.

[0020] In the above scheme, the initial iteration module includes a multiplier 1, a multiplier 2, a leading zero detection module 2, and a shift addition module 1;

[0021] The multiplier 1 is a 24*8 multiplier, and the multiplier 1 uses Booth coding and Wallace tree to process the estimated value 2 and the mantissa to obtain an output result x0_1 and send it to the multiplexer;

[0022] The second multiplier is a 24*16 multiplier, and the second multiplier uses Booth coding and Wallace tree to process the first estimate and the mantissa, and sends the processing result to the second leading zero detection module;

[0023] The leading zero detection module 2 is used to perform leading zero detection processing on the result output by the multiplier 2;

[0024] The shift addition module 1 is used to receive the operation result of the leading zero detection module 2, perform a shift operation to obtain the shifted result b0_1, and perform an addition truncation operation on b0_1 to obtain the result y0_1, send it to the multiplexer, and output the intermediate value of the shifted result as the correction parameter σ.

[0025] In the above scheme, the initial iterative correction module includes a multiplier three, a multiplier four, a leading zero detection module three, and a shift addition module two;

[0026] The multiplier three is a 24*8 multiplier, and the multiplier three uses Booth coding and Wallace tree to process the valuation four and the mantissa to obtain the output result x0_2 and send it to the multiplexer;

[0027] The multiplier 4 is a 24*16 multiplier, and the multiplier 4 uses Booth coding and Wallace tree to process the estimate 3 and the mantissa, and sends the processing result to the leading zero detection module 3;

[0028] The leading zero detection module three is used to perform leading zero detection processing on the result output by the multiplier four;

[0029] The shift addition module 2 is used to receive the operation result of the leading zero detection module 3, perform a shift operation to obtain the shifted result b0_2, and perform an addition and truncation operation on b0_2 to obtain the result y0_2, and send it to the multiplexer.

[0030] In the above solution, the operation iteration unit includes operation iteration unit 1, operation iteration unit 2 and operation iteration unit 3;

[0031] The operation iteration unit 1 is used to receive the iteration values ​​x0, b0, y0 sent by the multiplexer, perform two serial multiplication operations, and output the operation results x1, b1, y1;

[0032] The operation iteration unit 2 is used to receive the operation results x1, b1, y1 sent by the operation iteration unit 1, perform two serial multiplication operations, and output the operation results x2, b2, y2;

[0033] The operation iteration unit three is used to receive the operation results x2 and y2 of the operation iteration unit two, and perform a 32-bit multiplication operation to obtain a 64-bit operation result x3.

[0034] In a further technical solution, the operation iteration unit 1 includes a multiplier 5, a multiplier 6, a multiplier 7, a leading zero detection module 4, a shift addition module 3 and a truncation module 1;

[0035] The multiplier 5 is used to receive x0 and y0 sent by the multiplexer, perform 32-bit multiplication processing, obtain x1_r and send it to the truncation module 1;

[0036] The multiplier six is ​​used to receive y0 sent by the multiplexer, perform multiplication processing of 32-bit y0 and y0, and take the high 32-bit z0 of the result and send it to the multiplier seven;

[0037] The multiplier seven is used to receive b0 sent by the multiplexer and z0 sent by the multiplier six, perform 32-bit b0 and z0 multiplication processing, and send the obtained result to the leading zero detection module four;

[0038] The leading zero detection module 4 is used to receive the result sent by the multiplier 7, perform 64-bit leading zero detection processing, and send the high 32 bits of the result to the shift addition module 3;

[0039] The shift addition module 3 is used to receive the 32-bit width result sent by the leading zero detection module 4, perform shift and addition processing, obtain the shift result b1 and the addition result y1 respectively, and send them to the truncation module 1;

[0040] The truncation module 1 is used to receive the result x1_r sent by the multiplier 5, and the results b1 and y1 sent by the shift addition module 3, intercept the high 32 bits of x1_r for processing to obtain x1, and send it together with b1 and y1 to the operation iteration unit 2.

[0041] In a further technical solution, the operation iteration unit 2 includes a multiplier 8, a multiplier 9, a multiplier 10, a leading zero detection module 5, a shift addition module 4 and a truncation module 2;

[0042] The multiplier eight is used to receive x1 and y1 sent by the truncation module one, perform 32-bit multiplication processing, obtain x2_r and send it to the truncation module two;

[0043] The multiplier nine is used to receive y1 sent by the truncation module one, perform multiplication processing of 32-bit y1 and y1, and take the high 32 bits z1 of the result and send it to the multiplier ten;

[0044] The multiplier 10 is used to receive b1 sent by the truncation module 1 and z1 sent by the multiplier 6, perform 32-bit b1 and z1 multiplication processing, and send the obtained result to the leading zero detection module 5;

[0045] The leading zero detection module five is used to receive the result sent by the multiplier ten, perform 64-bit leading zero detection processing, and send the high 32 bits of the result to the shift addition module four;

[0046] The shift addition module 4 is used to receive the 32-bit width result sent by the leading zero detection module 5, perform shift and addition processing, obtain the shift result b2 and the addition result y2 respectively, and send them to the truncation module 2;

[0047] The truncation module 2 is used to receive the result x2_r sent by the multiplier 5, and the results b2 and y2 sent by the shift addition module 3, intercept the high 32 bits of x2_r for processing to obtain x2, and send it together with b2 and y2 to the operation iteration unit 3.

[0048] In a further technical solution, the operation iteration unit three includes a multiplier eleven, which is used to perform a 32-bit multiplication operation on the operation results x2 and y2 of the operation iteration unit two to obtain a 64-bit operation result x3.

[0049] A single-precision floating-point number square root calculation method, using the single-precision floating-point number square root calculation device as described above, comprises the following steps:

[0050] (1) The single-precision floating-point number is input into the floating-point preprocessing unit and is split into three parts: sign, exponent, and mantissa;

[0051] (2) The sign and exponent are input into the sign exponent processing unit, which determines whether it is a non-negative single-precision floating-point number and a non-standard number according to the sign. If it is non-negative and a non-standard number at the same time, the exponent is shifted and added to obtain the corresponding exponent result after square root, and the sign bit is retained and sent to the operation combination module; if it is not non-negative or not a non-standard number, a data abnormality signal is sent to the operation combination module for the operation combination module to select the source of the final output result;

[0052] (3) The exponent and mantissa are input into the initial valuation unit. One of the valuation tables is selected according to the parity of the exponent to perform initial valuation on the mantissa, and valuation one, valuation two, valuation three and valuation four are obtained. Valuation one and valuation two are sent to the initial iteration module as initial iteration values, and valuation three and valuation four are sent to the initial iteration correction module as initial iteration values.

[0053] (4) The initial iteration module receives the mantissa sent by the floating point preprocessing unit and the estimation 1 and estimation 2 sent by the initial estimation unit, performs an iterative operation, and outputs the iterative values ​​x0_1, b0_1 and y0_1, as well as the correction parameter σ;

[0054] The initial iterative correction module receives the mantissa sent by the floating point preprocessing unit and the third and fourth estimates sent by the initial estimation unit, performs an iterative correction operation, and outputs iterative correction values ​​x0_2, b0_2 and y0_2;

[0055] (5) The multiplexer receives the iteration values ​​x0_1, b0_1 and y0_1 and the correction parameter σ sent by the initial iteration module, and the iteration correction values ​​x0_2, b0_2 and y0_2 sent by the initial iteration correction module, and selects and outputs one of the sets according to the correction parameter σ, and sends it to the operation iteration unit 1 as the iteration values ​​x0, b0, y0;

[0056] (6) The operation iteration unit performs a multiplication operation on the iteration values ​​x0, b0, y0 sent by the multiplexer to obtain a 64-bit operation result x3 and an intermediate operation result y2;

[0057] (7) The leading zero detection module 1 receives the operation result x3 sent by the operation iteration unit, and performs a leading zero detection on the result to ensure that the first digit of the data format output subsequently is 1;

[0058] (8) The mantissa rounding compensation unit determines whether the mantissa needs to be compensated according to the intermediate operation result y2 of the operation iteration unit, and sends a compensation signal to the rounding processing module;

[0059] (9) The rounding processing module shifts the number of bits from the first bit to the first occurrence of 0 output by the leading zero detection module 1 according to the compensation signal sent by the mantissa rounding compensation unit to ensure that the first bit of the data format output subsequently is 1, and rounds the shifted data to obtain a carry parameter;

[0060] (10) The operation combination module receives the high 23 bits of the 64-bit mantissa result and the carry parameter sent by the rounding processing module, and the data exception signal or the sign and the exponent after the square root sent by the sign-exponent processing unit. If a data exception signal is received, the result of the rounding processing module is selected for addition and data splicing processing. If a sign and the exponent after the square root are received, addition and data splicing processing are directly performed to obtain the final single-precision floating-point square root operation result that conforms to the IEEE754 format.

[0061] In the above scheme, the operations performed in the operation iteration unit include:

[0062] Operation iteration unit one performs two serial multiplication operations on the iteration values ​​x0, b0, y0 sent from the multiplexer, and outputs operation results x1, b1, y1; operation iteration unit two performs two serial multiplication operations on the operation results x1, b1, y1 sent from operation iteration unit one, and outputs operation results x2, b2, y2; operation iteration unit three performs 32-bit multiplication operation on the operation results x2 and y2 of operation iteration unit two to obtain a 64-bit operation result x3.

[0063] Through the above technical solution, the present invention provides a single-precision floating-point square root operation device and operation method having the following characteristics:

[0064] Beneficial effects:

[0065] 1. The present invention improves the accuracy of the initial iteration value and reduces the number of iterations required to calculate to the same accuracy by adding and controlling additional iteration paths (initial iteration correction module). At the same time, during the iteration process, the error between the final iteration result and the actual value is reduced by judging and selecting the intermediate values ​​of the iteration (multiplexer).

[0066] 2. The present invention combines the advantages of the common table lookup method and the conventional iterative method to realize the square root operation of single-precision floating-point numbers. Compared with the traditional table lookup method, the accuracy is higher, and compared with the common iterative method, the speed is faster, that is, the number of initial iterations is reduced. At the same time, during the iteration process, the final result can be compensated by analyzing the iteration results to improve the accuracy. It is suitable for application scenarios such as microcontrollers, digital signal processors, CPUs, etc. that require hardware square root operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0068] Figure 1 The present invention is a schematic diagram of a single-precision floating-point number square root calculation device disclosed in an embodiment of the present invention.

[0069] Figure 2 It is a schematic diagram of a calculation iteration unit;

[0070] Figure 3 It is a schematic diagram of the operation iteration unit 2;

[0071] Figure 4 Schematic diagram of operation iteration unit three. DETAILED DESCRIPTION

[0072] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0073] The present invention provides a single-precision floating-point number square root operation device, such as Figure 1 As shown, it includes a floating point preprocessing unit, a sign exponent processing unit, an initial estimation unit, an initial iteration module, an initial iteration correction module, a multiplexer, an operation iteration unit 1, an operation iteration unit 2, an operation iteration unit 3, a leading zero detection module 1, a mantissa rounding compensation unit, a rounding processing module and an operation combination module. The functions of each module are as follows:

[0074] 1. Floating point preprocessing unit

[0075] The floating point number preprocessing unit is used to split the floating point number into three parts, namely the sign, the exponent and the mantissa.

[0076] 2. Symbolic exponential processing unit

[0077] The sign-exponent processing unit is used to receive the sign and exponent sent by the floating-point preprocessing unit, and judge whether it is a non-negative single-precision floating-point number and a non-standard number according to the sign. If it is non-negative and a non-standard number at the same time, the exponent is shifted and added to obtain the corresponding exponent result after square root, the sign bit is retained, and sent to the operation combination module; if it is not non-negative or not a non-standard number, a data exception signal is sent to the operation combination module, which is used for the operation combination module to select the source of the final output result.

[0078] 3. Initial Valuation Unit

[0079] The initial valuation unit includes two valuation tables, which are used to receive the exponent and mantissa sent by the floating-point number preprocessing unit. According to the parity of the exponent, one of the valuation tables is selected to perform initial valuation on the mantissa, and valuation one, valuation two, valuation three and valuation four are obtained. Valuation one and valuation two are sent to the initial iteration module as initial iteration values, and valuation three and valuation four are sent to the initial iteration correction module as initial iteration values. Among them, valuation one and valuation three are the reciprocal square root value valuations of the mantissa; valuation two and valuation four are the reciprocal value valuations of the mantissa; and valuation three is greater than valuation one, and valuation four is greater than valuation two.

[0080] The two valuation tables are of the same size, both 128 × 40. The valuation table consists of the following: an initial eight-bit valuation table, based on the original eight-bit reciprocal square root valuation, and the corresponding sixteen-bit reciprocal estimate based on the reciprocal square root value (which can reduce the multiplication operation of the first iteration), and the last 16 bits are the correction table of the valuation (that is, some valuations do not meet the accuracy of the final calculation after iteration, because the initial iteration value is too small).

[0081] 4. Initial Iteration Module

[0082] The initial iteration module is used to receive the mantissa sent by the floating point preprocessing unit and the estimation one and estimation two sent by the initial estimation unit, perform iterative operations, and output iterative values ​​x0_1, b0_1 and y0_1, as well as the correction parameter σ.

[0083] The initial iteration module includes multiplier 1, multiplier 2, leading zero detection module 2, and shift addition module 1. Specifically, the functions of each module are as follows:

[0084] Multiplier 1 is a 24*8 multiplier. Multiplier 1 uses Booth coding and Wallace tree to process the value 2 and the mantissa to obtain the output result x0_1 and send it to the multiplexer.

[0085] Multiplier 2 is a 24*16 multiplier. Multiplier 2 uses Booth coding and Wallace tree to process the estimate 1 and the mantissa, and sends the processing result to the leading zero detection module 2;

[0086] The leading zero detection module 2 is used for performing leading zero detection processing on the result output by the multiplier 2;

[0087] The shift addition module 1 is used to receive the operation result of the leading zero detection module 2, perform a shift operation to obtain the shifted result b0_1, and perform an addition truncation operation on b0_1 to obtain the result y0_1, send it to the multiplexer, and output the intermediate value of the shifted result as the correction parameter σ.

[0088] 5. Initial Iteration Correction Module

[0089] The initial iterative correction module is used to receive the mantissa sent by the floating point preprocessing unit and the third and fourth estimates sent by the initial estimation unit, perform iterative correction operations, and output iterative correction values ​​x0_2, b0_2 and y0_2.

[0090] The initial iterative correction module includes multiplier 3, multiplier 4, leading zero detection module 3, and shift addition module 2. Specifically, the functions of each module are as follows:

[0091] Multiplier 3 is a 24*8 multiplier. Multiplier 3 uses Booth coding and Wallace tree to process the evaluation number 4 and the mantissa to obtain the output result x0_2 and send it to the multiplexer.

[0092] The multiplier 4 is a 24*16 multiplier, and the multiplier 4 processes the estimate 3 and the mantissa using Booth coding and Wallace tree, and sends the processing result to the leading zero detection module 3;

[0093] The leading zero detection module 3 is used to perform leading zero detection processing on the result output by the multiplier 4;

[0094] The shift addition module 2 is used to receive the operation result of the leading zero detection module 3, perform a shift operation to obtain the shifted result b0_2, and perform an addition and truncation operation on b0_2 to obtain the result y0_2, which is sent to the multiplexer.

[0095] 6. Multiplexer

[0096] The multiplexer is used to receive the iteration values ​​x0_1, b0_1 and y0_1 sent by the initial iteration module, as well as the correction parameter σ, and the iteration correction values ​​x0_2, b0_2 and y0_2 sent by the initial iteration correction module, and select one group of them according to the correction parameter σ as the iteration value x0, b0, y0. If the correction parameter σ approaches 1, the output result of the initial iteration module is selected, and if it does not approach 1, the output result of the initial iteration correction module is selected.

[0097] 7. Operation iteration unit 1

[0098] The operation iteration unit 1 is used to receive the iteration values ​​x0, b0, y0 sent by the multiplexer, perform two serial multiplication operations, and output the operation results x1, b1, y1.

[0099] like Figure 2 As shown, the operation iteration unit 1 includes a multiplier 5, a multiplier 6, a multiplier 7, a leading zero detection module 4, a shift addition module 3 and a truncation module 1;

[0100] Multiplier 5 is used to receive x0 and y0 sent by the multiplexer, perform 32-bit multiplication, obtain x1_r and send it to truncation module 1;

[0101] Multiplier six is ​​used to receive y0 sent by the multiplexer, perform multiplication of 32-bit y0 and y0, and take the high 32-bit z0 of the result and send it to multiplier seven;

[0102] The multiplier seven is used to receive b0 sent by the multiplexer and z0 sent by the multiplier six, perform 32-bit b0 and z0 multiplication processing, and send the result to the leading zero detection module four;

[0103] The leading zero detection module 4 is used to receive the result sent by the multiplier 7, perform 64-bit leading zero detection processing, and send the high 32 bits of the result to the shift addition module 3;

[0104] The shift addition module 3 is used to receive the 32-bit wide result sent by the leading zero detection module 4, perform shift and addition processing, obtain the shift result b1 and the addition result y1 respectively, and send them to the truncation module 1;

[0105] The truncation module 1 is used to receive the result x1_r sent by the multiplier 5, and the results b1 and y1 sent by the shift addition module 3, intercept the high 32 bits of x1_r for processing to obtain x1, and send it together with b1 and y1 to the operation iteration unit 2.

[0106] 8. Operation Iteration Unit 2

[0107] The operation iteration unit 2 is used to receive the operation results x1, b1, y1 sent by the operation iteration unit 1, perform two serial multiplication operations, and output the operation results x2, b2, y2.

[0108] like Figure 3 As shown, the operation iteration unit 2 includes a multiplier 8, a multiplier 9, a multiplier 10, a leading zero detection module 5, a shift addition module 4 and a truncation module 2;

[0109] Multiplier 8 is used to receive x1 and y1 sent by truncation module 1, perform 32-bit multiplication, obtain x2_r and send it to truncation module 2;

[0110] Multiplier nine is used to receive y1 sent by truncation module one, perform multiplication of 32-bit y1 and y1, and take the high 32-bit z1 of the result and send it to multiplier ten;

[0111] The multiplier ten is used for receiving b1 sent by the truncation module one and z1 sent by the multiplier six, performing 32-bit b1 and z1 multiplication processing, and sending the obtained result to the leading zero detection module five;

[0112] The leading zero detection module five is used to receive the result sent by the multiplier ten, perform 64-bit leading zero detection processing, and send the high 32 bits of the result to the shift addition module four;

[0113] The shift addition module 4 is used to receive the 32-bit wide result sent by the leading zero detection module 5, perform shift and addition processing, obtain the shift result b2 and the addition result y2 respectively, and send them to the truncation module 2;

[0114] The truncation module 2 is used to receive the result x2_r sent by the multiplier 5, and the results b2 and y2 sent by the shift addition module 3, intercept the high 32 bits of x2_r for processing to obtain x2, and send it together with b2 and y2 to the operation iteration unit 3.

[0115] 9. Operation iteration unit 3

[0116] The operation iteration unit three is used to receive the operation results x2 and y2 of the operation iteration unit two, and perform a 32-bit multiplication operation to obtain a 64-bit operation result x3.

[0117] like Figure 4 As shown, the operation iteration unit three includes a multiplier eleven, which is used to perform a 32-bit multiplication operation on the operation results x2 and y2 of the operation iteration unit two to obtain a 64-bit operation result x3.

[0118] 10. Leading zero detection module 1

[0119] The leading zero detection module 1 is used to receive the operation result x3 sent by the operation iteration unit 3, and perform leading zero detection on the result to ensure that the first digit of the subsequent output data format is 1.

[0120] 11. Rounding compensation unit

[0121] The mantissa rounding compensation unit is used to determine whether the mantissa needs to be compensated according to the intermediate operation result y2 of the operation iteration unit 2, and send a compensation signal to the rounding processing module. The closer the operation result y2 is to 1, the more accurate the result value after the final iteration. Since the previous iteration operations will be truncated, it is necessary to determine whether the final mantissa needs to be compensated by the intermediate value of the last iteration parameter. If the deviation between y2 and 1 is greater than the threshold, it will be sent to the rounding processing module to add 1 to achieve compensation of the final result.

[0122] 12. Rounding processing module

[0123] The rounding processing module determines whether compensation is needed based on the signal sent by the mantissa rounding compensation unit, and at the same time needs to perform a shift operation based on the output result of the leading zero detection module 1 to ensure that the first bit of the subsequent output data format is 1, and rounds the shifted data to obtain the carry parameter.

[0124] The 40th bit of the shifted data is set to L, the 39th bit is set to G, and the 38th bit is set to R. The subsequent 37 bits to the 0th bit are self-ORed, and the result is set to S. The method adopted is the nearest value rounding principle. If G=1 and (R=1 or S=1), the mantissa is increased by 1; if G=1 and (R=0 and S=0), it is necessary to judge whether the L bit is 0 or 1. If it is 1, the carry is increased by 1, otherwise it is not increased.

[0125] 13. Operation combination module

[0126] The operation combination module is used to receive the high 23 bits and carry parameters of the 64-bit mantissa result sent by the rounding processing module, the data exception signal or the sign and the exponent after square root sent by the sign exponent processing unit. If the data exception signal is received, the result of the rounding processing module is selected for addition and data splicing processing. If the sign and the exponent after square root are received, addition and data splicing processing are directly performed to obtain the final single-precision floating-point square root operation result that conforms to the IEEE754 format.

[0127] A single-precision floating-point number square root calculation method, using the single-precision floating-point number square root calculation device as above, comprises the following steps:

[0128] (1) The single-precision floating-point number is input into the floating-point preprocessing unit and is split into three parts: sign, exponent, and mantissa;

[0129] (2) The sign and exponent are input into the sign exponent processing unit, which determines whether it is a non-negative single-precision floating-point number and a non-standard number according to the sign. If it is non-negative and a non-standard number at the same time, the exponent is shifted and added to obtain the corresponding exponent result after square root, and the sign bit is retained and sent to the operation combination module; if it is not non-negative or not a non-standard number, a data abnormality signal is sent to the operation combination module for the operation combination module to select the source of the final output result;

[0130] (3) The exponent and mantissa are input into the initial valuation unit. One of the valuation tables is selected according to the parity of the exponent to perform initial valuation on the mantissa, and valuation one, valuation two, valuation three and valuation four are obtained. Valuation one and valuation two are sent to the initial iteration module as initial iteration values, and valuation three and valuation four are sent to the initial iteration correction module as initial iteration values.

[0131] (4) The initial iteration module receives the mantissa sent by the floating point preprocessing unit and the estimation 1 and estimation 2 sent by the initial estimation unit, performs an iterative operation, and outputs the iterative values ​​x0_1, b0_1 and y0_1, as well as the correction parameter σ;

[0132] The initial iterative correction module receives the mantissa sent by the floating point preprocessing unit and the third and fourth estimates sent by the initial estimation unit, performs an iterative correction operation, and outputs iterative correction values ​​x0_2, b0_2 and y0_2;

[0133] (5) The multiplexer receives the iteration values ​​x0_1, b0_1 and y0_1 and the correction parameter σ sent by the initial iteration module, and the iteration correction values ​​x0_2, b0_2 and y0_2 sent by the initial iteration correction module, and selects and outputs one of the sets according to the correction parameter σ, and sends it to the operation iteration unit 1 as the iteration values ​​x0, b0, y0;

[0134] (6) The operation iteration unit performs two serial multiplication operations on the iteration values ​​x0, b0, y0 sent by the multiplexer, and outputs the operation results x1, b1, y1;

[0135] (7) The operation iteration unit 2 performs two serial multiplication operations on the operation results x1, b1, y1 sent by the operation iteration unit 1, and outputs the operation results x2, b2, y2;

[0136] (8) The operation iteration unit 3 performs a 32-bit multiplication operation on the operation results x2 and y2 of the operation iteration unit 2 to obtain a 64-bit operation result x3;

[0137] (9) The leading zero detection module 1 receives the operation result x3 sent by the operation iteration unit 3, and performs a leading zero detection on the result to ensure that the first digit of the data format to be subsequently outputted is 1;

[0138] (10) The mantissa rounding compensation unit determines whether the mantissa needs to be compensated according to the operation result y2 of the operation iteration unit 2, and sends a compensation signal to the rounding processing module;

[0139] (11) The rounding processing module needs to perform a shift operation based on the compensation signal sent by the mantissa rounding compensation unit and the output result of the leading zero detection module 1 to ensure that the first bit of the subsequent output data format is 1, and round the shifted data to obtain a carry parameter;

[0140] (12) The operation combination module receives the high 23 bits and carry parameter of the 64-bit mantissa result sent by the rounding processing module, and the data exception signal or the sign and the exponent after square root sent by the sign-exponent processing unit. If a data exception signal is received, the result of the rounding processing module is selected for addition and data splicing processing. If a sign and the exponent after square root are received, addition and data splicing processing are directly performed to obtain the final single-precision floating-point square root operation result that conforms to the IEEE754 format.

[0141] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A single-precision floating-point number square root calculation device, characterized in that: It includes a floating point number preprocessing unit, a sign exponent processing unit, an initial estimation unit, an initial iteration module, an initial iteration correction module, a multiplexer, an operation iteration unit, a leading zero detection module 1, a mantissa rounding compensation unit, a rounding processing module and an operation combination module; The floating point number preprocessing unit is used to split the floating point number into three parts, namely, a sign, an exponent and a mantissa; The sign-exponent processing unit is used to receive the sign and exponent sent by the floating-point number preprocessing unit, and judge whether it is a non-negative single-precision floating-point number and a non-standard number according to the sign. If it is non-negative and a non-standard number at the same time, the exponent is shifted and added to obtain the exponential result after the corresponding square root, and the sign bit is retained and sent to the operation combination module; if it is not non-negative or not a non-standard number, a data exception signal is sent to the operation combination module, so that the operation combination module selects the source of the final output result; The initial valuation unit comprises two valuation tables, which are used to receive the exponent and mantissa sent by the floating-point number preprocessing unit, and select one of the valuation tables to perform initial valuation on the mantissa according to the parity of the exponent to obtain valuation one, valuation two, valuation three and valuation four. Valuation one and valuation two are sent to the initial iteration module as initial iteration values, and valuation three and valuation four are sent to the initial iteration correction module as initial iteration values; The initial iteration module is used to receive the mantissa sent by the floating point number preprocessing unit and the estimation 1 and the estimation 2 sent by the initial estimation unit, perform an iterative operation, and output iterative values ​​x0_1, b0_1 and y0_1, as well as a correction parameter σ; The initial iterative correction module is used to receive the mantissa sent by the floating point preprocessing unit and the third and fourth estimates sent by the initial estimation unit, perform iterative correction operations, and output iterative correction values ​​x0_2, b0_2 and y0_2; The multiplexer is used to receive the iteration values ​​x0_1, b0_1 and y0_1 sent by the initial iteration module, as well as the correction parameter σ, and the iteration correction values ​​x0_2, b0_2 and y0_2 sent by the initial iteration correction module, and select and output one group thereof according to the correction parameter σ as the iteration values ​​x0, b0, y0; The operation iteration unit is used to receive the iteration values ​​x0, b0, y0 sent by the multiplexer, and perform multiplication operation to obtain a 64-bit operation result x3 and an intermediate operation result y2; The leading zero detection module 1 is used to receive the operation result x3 sent by the operation iteration unit, and perform leading zero detection on the result to ensure that the first digit of the data format output subsequently is 1; The mantissa rounding compensation unit is used to determine whether the mantissa needs to be compensated according to the intermediate operation result y2 of the operation iteration unit, and send a compensation signal to the rounding processing module; The rounding processing module: according to the compensation signal sent by the mantissa rounding compensation unit, a shift operation needs to be performed according to the output result of the leading zero detection module 1 to ensure that the first bit of the subsequent output data format is 1, and the shifted data is rounded to obtain a carry parameter; The operation combination module is used to receive the high 23 bits and carry parameter of the 64-bit mantissa result sent by the rounding processing module, the data exception signal or the sign and the exponent after square root sent by the sign exponent processing unit, and if the data exception signal is received, the result of the rounding processing module is selected for addition and data splicing processing; if the sign and the exponent after square root are received, the addition and data splicing processing are directly performed to obtain the single-precision floating-point square root operation result that finally complies with the IEEE754 format.

2. A single-precision floating-point number square root calculation device according to claim 1, characterized in that: The valuation one and valuation three are the valuations of the reciprocal square root of the mantissa; the valuation two and valuation four are the valuations of the reciprocal value of the mantissa; and the valuation three is greater than the valuation one, and the valuation four is greater than the valuation two.

3. A single-precision floating-point number square root calculation device according to claim 1, characterized in that: The initial iteration module includes a multiplier 1, a multiplier 2, a leading zero detection module 2, and a shift addition module 1; The multiplier 1 is a 24*8 multiplier, and the multiplier 1 uses Booth coding and Wallace tree to process the estimated value 2 and the mantissa to obtain an output result x0_1 and send it to the multiplexer; The second multiplier is a 24*16 multiplier, and the second multiplier uses Booth coding and Wallace tree to process the first estimate and the mantissa, and sends the processing result to the second leading zero detection module; The leading zero detection module 2 is used to perform leading zero detection processing on the result output by the multiplier 2; The shift addition module 1 is used to receive the operation result of the leading zero detection module 2, perform a shift operation to obtain the shifted result b0_1, and perform an addition truncation operation on b0_1 to obtain the result y0_1, send it to the multiplexer, and output the intermediate value of the shifted result as the correction parameter σ.

4. A single-precision floating-point number square root operation device according to claim 1, characterized in that: The initial iterative correction module includes a multiplier three, a multiplier four, a leading zero detection module three, and a shift addition module two; The multiplier three is a 24*8 multiplier, and the multiplier three uses Booth coding and Wallace tree to process the valuation four and the mantissa to obtain the output result x0_2 and send it to the multiplexer; The multiplier 4 is a 24*16 multiplier, and the multiplier 4 uses Booth coding and Wallace tree to process the estimate 3 and the mantissa, and sends the processing result to the leading zero detection module 3; The leading zero detection module three is used to perform leading zero detection processing on the result output by the multiplier four; The shift addition module 2 is used to receive the operation result of the leading zero detection module 3, perform a shift operation to obtain the shifted result b0_2, and perform an addition and truncation operation on b0_2 to obtain the result y0_2, and send it to the multiplexer.

5. The single-precision floating-point number square root calculation device according to claim 1, characterized in that: The operation iteration unit includes an operation iteration unit 1, an operation iteration unit 2 and an operation iteration unit 3; The operation iteration unit 1 is used to receive the iteration values ​​x0, b0, y0 sent by the multiplexer, perform two serial multiplication operations, and output the operation results x1, b1, y1; The operation iteration unit 2 is used to receive the operation results x1, b1, y1 sent by the operation iteration unit 1, perform two serial multiplication operations, and output the operation results x2, b2, y2; The operation iteration unit three is used to receive the operation results x2 and y2 of the operation iteration unit two, and perform a 32-bit multiplication operation to obtain a 64-bit operation result x3.

6. A single-precision floating-point number square root calculation device according to claim 5, characterized in that: The operation iteration unit 1 includes a multiplier 5, a multiplier 6, a multiplier 7, a leading zero detection module 4, a shift addition module 3 and a truncation module 1; The multiplier 5 is used to receive x0 and y0 sent by the multiplexer, perform 32-bit multiplication processing, obtain x1_r and send it to the truncation module 1; The multiplier six is ​​used to receive y0 sent by the multiplexer, perform multiplication processing of 32-bit y0 and y0, and take the high 32-bit z0 of the result and send it to the multiplier seven; The multiplier seven is used to receive b0 sent by the multiplexer and z0 sent by the multiplier six, perform 32-bit b0 and z0 multiplication processing, and send the obtained result to the leading zero detection module four; The leading zero detection module 4 is used to receive the result sent by the multiplier 7, perform 64-bit leading zero detection processing, and send the high 32 bits of the result to the shift addition module 3; The shift addition module 3 is used to receive the 32-bit width result sent by the leading zero detection module 4, perform shift and addition processing, obtain the shift result b1 and the addition result y1 respectively, and send them to the truncation module 1; The truncation module 1 is used to receive the result x1_r sent by the multiplier 5, and the results b1 and y1 sent by the shift addition module 3, intercept the high 32 bits of x1_r for processing to obtain x1, and send it together with b1 and y1 to the operation iteration unit 2.

7. The single-precision floating-point number square root calculation device according to claim 1, characterized in that: The operation iteration unit 2 includes a multiplier 8, a multiplier 9, a multiplier 10, a leading zero detection module 5, a shift addition module 4 and a truncation module 2; The multiplier eight is used to receive x1 and y1 sent by the truncation module one, perform 32-bit multiplication processing, obtain x2_r and send it to the truncation module two; The multiplier nine is used to receive y1 sent by the truncation module one, perform multiplication processing of 32-bit y1 and y1, and take the high 32 bits z1 of the result and send it to the multiplier ten; The multiplier 10 is used to receive b1 sent by the truncation module 1 and z1 sent by the multiplier 6, perform 32-bit b1 and z1 multiplication processing, and send the obtained result to the leading zero detection module 5; The leading zero detection module five is used to receive the result sent by the multiplier ten, perform 64-bit leading zero detection processing, and send the high 32 bits of the result to the shift addition module four; The shift addition module 4 is used to receive the 32-bit width result sent by the leading zero detection module 5, perform shift and addition processing, obtain the shift result b2 and the addition result y2 respectively, and send them to the truncation module 2; The truncation module 2 is used to receive the result x2_r sent by the multiplier 5, and the results b2 and y2 sent by the shift addition module 3, intercept the high 32 bits of x2_r for processing to obtain x2, and send it together with b2 and y2 to the operation iteration unit 3.

8. The single-precision floating-point number square root calculation device according to claim 1, characterized in that: The operation iteration unit three includes a multiplier eleven, which is used to perform a 32-bit multiplication operation on the operation results x2 and y2 of the operation iteration unit two to obtain a 64-bit operation result x3.

9. A single-precision floating-point number square root calculation method, using a single-precision floating-point number square root calculation device as claimed in any one of claims 1 to 8, characterized in that: The steps include: (1) The single-precision floating-point number is input into the floating-point preprocessing unit and is split into three parts: sign, exponent, and mantissa; (2) The sign and exponent are input into the sign exponent processing unit, which determines whether it is a non-negative single-precision floating-point number and a non-standard number according to the sign. If it is non-negative and a non-standard number at the same time, the exponent is shifted and added to obtain the corresponding exponent result after square root, and the sign bit is retained and sent to the operation combination module; if it is not non-negative or not a non-standard number, a data abnormality signal is sent to the operation combination module for the operation combination module to select the source of the final output result; (3) The exponent and mantissa are input into the initial valuation unit. One of the valuation tables is selected according to the parity of the exponent to perform initial valuation on the mantissa, and valuation one, valuation two, valuation three and valuation four are obtained. Valuation one and valuation two are sent to the initial iteration module as initial iteration values, and valuation three and valuation four are sent to the initial iteration correction module as initial iteration values. (4) The initial iteration module receives the mantissa sent by the floating point preprocessing unit and the estimation 1 and estimation 2 sent by the initial estimation unit, performs an iterative operation, and outputs the iterative values ​​x0_1, b0_1 and y0_1, as well as the correction parameter σ; The initial iterative correction module receives the mantissa sent by the floating point preprocessing unit and the third and fourth estimates sent by the initial estimation unit, performs an iterative correction operation, and outputs iterative correction values ​​x0_2, b0_2 and y0_2; (5) The multiplexer receives the iteration values ​​x0_1, b0_1 and y0_1 and the correction parameter σ sent by the initial iteration module, and the iteration correction values ​​x0_2, b0_2 and y0_2 sent by the initial iteration correction module, and selects and outputs one of the sets according to the correction parameter σ, and sends it to the operation iteration unit 1 as the iteration values ​​x0, b0, y0; (6) The operation iteration unit performs a multiplication operation on the iteration values ​​x0, b0, y0 sent by the multiplexer to obtain a 64-bit operation result x3 and an intermediate operation result y2; (7) The leading zero detection module 1 receives the operation result x3 sent by the operation iteration unit, and performs a leading zero detection on the result to ensure that the first digit of the data format output subsequently is 1; (8) The mantissa rounding compensation unit determines whether the mantissa needs to be compensated according to the intermediate operation result y2 of the operation iteration unit, and sends a compensation signal to the rounding processing module; (9) The rounding processing module shifts the number of bits from the first bit to the first occurrence of 0 output by the leading zero detection module 1 according to the compensation signal sent by the mantissa rounding compensation unit to ensure that the first bit of the data format output subsequently is 1, and rounds the shifted data to obtain a carry parameter; (10) The operation combination module receives the high 23 bits of the 64-bit mantissa result and the carry parameter sent by the rounding processing module, and the data exception signal or the sign and the exponent after the square root sent by the sign-exponent processing unit. If a data exception signal is received, the result of the rounding processing module is selected for addition and data splicing processing. If a sign and the exponent after the square root are received, addition and data splicing processing are directly performed to obtain the final single-precision floating-point square root operation result that conforms to the IEEE754 format.

10. A single-precision floating-point number square root calculation method according to claim 9, characterized in that: The operations performed in the operation iteration unit include: Operation iteration unit one performs two serial multiplication operations on the iteration values ​​x0, b0, y0 sent from the multiplexer, and outputs operation results x1, b1, y1; operation iteration unit two performs two serial multiplication operations on the operation results x1, b1, y1 sent from operation iteration unit one, and outputs operation results x2, b2, y2; operation iteration unit three performs 32-bit multiplication operation on the operation results x2 and y2 of operation iteration unit two to obtain a 64-bit operation result x3.

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