Bytecode instruction execution method, virtual machine, equipment and medium

Abstract

The invention discloses a bytecode instruction execution method, a virtual machine, equipment and a medium, and the method comprises the steps: determining a first target address from the storage address of each bytecode in a bytecode instruction execution request, and storing the first target address in a first register; the interpreter reads a first target address of the first register, and stores a first target byte code corresponding to the first target address to the second register; the interpreter adds 1 to the first target address stored in the first register to obtain a second target address; the interpreter executes the first target bytecode in the second register. According to the application, a program counter is mapped to a physical register, an interpreter executes a previous byte code, an address value stored in the physical register is changed to point to a next byte code to be executed, and the byte code is stored in another register, so that the interpreter directly reads and executes the byte code from the register; compared with the scheme of repeatedly accessing the program counter value from the RAM to execute the bytecode, the execution efficiency of the bytecode instruction is improved.

Description

Technical Field

[0001] The present application relates to but is not limited to the field of computer technology, and in particular to a bytecode instruction execution method, virtual machine, device, and medium. Background Art

[0002] When a virtual machine receives a bytecode instruction loading request, it needs to trigger the operation of the interpreter by running the program counter to complete the translation of the bytecode into the target machine code. Specifically, after the interpreter executes an instruction, it will update the value of the program counter according to the execution result of the current instruction and the program logic to determine the next instruction to be executed. Since the program counter of the existing virtual machine is stored in the random access memory RAM, the program counter records the current virtual machine running address. Each time the interpreter is executed, it is necessary to read the value of the program counter from the RAM in real time before performing the bytecode translation operation. When the number of bytecode instructions in the bytecode instruction loading request is large, the RAM needs to be accessed frequently, and the operation efficiency of the interpreter is low, resulting in low bytecode execution efficiency. Summary of the invention

[0003] The embodiments of the present application provide a bytecode instruction execution method, a virtual machine, a device, and a medium, which can effectively improve the operating efficiency of the virtual machine interpreter, thereby improving the execution efficiency of the bytecode instructions.

[0004] In a first aspect, an embodiment of the present application provides a bytecode instruction execution method, the method is applied to a virtual machine, the virtual machine also includes a controller, a memory, an interpreter, a first register and a second register, the method comprising:

[0005] When the controller receives a bytecode instruction execution request, the controller saves a plurality of bytecodes to be executed in the bytecode instruction execution request to the memory;

[0006] The controller determines a storage address corresponding to each of the bytecodes, determines a first target address from the storage addresses, and stores the first target address in a first register, wherein the target address is a storage address corresponding to a first bytecode in a bytecode instruction execution request;

[0007] The interpreter reads the first target address from the first register, reads the first target bytecode corresponding to the first target address from the memory, and saves the first target bytecode to the second register;

[0008] The interpreter adds 1 to the first target address stored in the first register to obtain a second target address, wherein the second target address points to one of the storage addresses corresponding to the bytecodes in all the bytecodes except the first target bytecode;

[0009] The interpreter executes the first target bytecode stored in the second register.

[0010] In some embodiments, after the interpreter executes the first target bytecode stored in the second register, the method further includes:

[0011] The interpreter determines the reference number of bytecodes in the bytecode instruction execution request, and records the current number of bytecodes executed by the interpreter in real time;

[0012] The interpreter reads the second target address from the first register, reads the second target bytecode corresponding to the second target address from the memory, and saves the second target bytecode to the second register;

[0013] The interpreter adds 1 to the second target address stored in the first register to obtain a third target address, wherein the third target address points to one of the storage addresses corresponding to the bytecodes other than the first target bytecode and the second target bytecode in all the bytecodes;

[0014] The interpreter executes the second target bytecode stored in the second register until the current bytecode execution quantity is equal to the reference quantity.

[0015] In some embodiments, the interpreter executes the first target bytecode stored in the second register, including:

[0016] Reading the first target bytecode from the second register, and determining a target bytecode instruction set corresponding to the first target bytecode;

[0017] The first target bytecode is distributed to the target bytecode instruction set to execute the first target bytecode.

[0018] In some embodiments, the method further comprises:

[0019] After the interpreter reads the second target address from the first register, if the memory cannot match the bytecode corresponding to the second target address, determine a reference bytecode set from the memory, the reference bytecode set including the remaining bytecodes in the bytecode corresponding to the bytecode instruction execution request except the first target bytecode;

[0020] The interpreter redetermines a new second target bytecode from the reference bytecode set, and saves a new second target address corresponding to the new second target bytecode to the first register.

[0021] In a second aspect, an embodiment of the present application provides a virtual machine, including a controller, a memory, an interpreter, a first register and a second register, wherein the controller includes a first data saving module and a second data saving module, and the interpreter includes a third data saving module, a first data processing module and a first bytecode execution module;

[0022] The first data saving module is used for saving a plurality of bytecodes to be executed in the bytecode instruction execution request to the memory when receiving the bytecode instruction execution request;

[0023] The second data saving module is used to determine the storage address corresponding to each of the bytecodes, determine a first target address from the storage address, and store the first target address in a first register, wherein the target address is the storage address corresponding to the first bytecode in the bytecode instruction execution request;

[0024] The third data saving module is used for reading the first target address from the first register, reading the first target bytecode corresponding to the first target address from the memory, and saving the first target bytecode to the second register;

[0025] The first data processing module is used for adding 1 to the first target address stored in the first register to obtain a second target address, wherein the second target address points to one of the storage addresses corresponding to the bytecodes in all the bytecodes except the first target bytecode;

[0026] The first bytecode instruction execution module is used to execute the first target bytecode stored in the second register.

[0027] In some embodiments, the interpreter further comprises:

[0028] A second data processing module, used to determine the reference number of bytecodes in the bytecode instruction execution request, and record the current number of bytecodes executed by the interpreter in real time;

[0029] a third data processing module, configured to read the second target address from the first register, read the second target bytecode corresponding to the second target address from the memory, and save the second target bytecode to the second register;

[0030] a fourth data processing module, configured to add 1 to the second target address stored in the first register to obtain a third target address, wherein the third target address points to one of the storage addresses corresponding to the bytecodes other than the first target bytecode and the second target bytecode in all the bytecodes;

[0031] The second bytecode instruction execution module is used to execute the second target bytecode stored in the second register until the current bytecode execution quantity is equal to the reference quantity.

[0032] In some embodiments, the first bytecode instruction execution module includes:

[0033] a target bytecode instruction set determining module, configured to read the first target bytecode from the second register and determine a target bytecode instruction set corresponding to the first target bytecode;

[0034] A bytecode distribution module is used to distribute the first target bytecode to the target bytecode instruction set to execute the first target bytecode.

[0035] In some embodiments, the interpreter further comprises:

[0036] A fifth data processing module is used to determine a reference bytecode set from the memory if no bytecode corresponding to the second target address is matched in the memory after the second target address is read from the first register, the reference bytecode set including the remaining bytecodes in the bytecode corresponding to the bytecode instruction execution request except the first target bytecode, re-determine a new second target bytecode from the reference bytecode set, and save a new second target address corresponding to the new second target bytecode to the first register.

[0037] In a third aspect, an embodiment of the present application also provides an electronic device, comprising at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions that can be executed by the at least one control processor, and the instructions are executed by the at least one control processor so that the at least one control processor can execute the bytecode instruction execution method described in the first aspect.

[0038] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the bytecode instruction execution method as described in the first aspect.

[0039] The embodiment of the present application provides a bytecode instruction execution method, a virtual machine, a device, and a medium, the method comprising: when the controller receives a bytecode instruction execution request, saving multiple bytecodes to be executed in the bytecode instruction execution request to the memory; the controller determines the storage address corresponding to each of the bytecodes, determines a first target address from the storage address, and stores the first target address to a first register, wherein the target address is the storage address corresponding to the first bytecode in the bytecode instruction execution request; the interpreter reads the first target address from the first register, reads the first target bytecode corresponding to the first target address from the memory, and saves the first target bytecode to the second register; the interpreter adds 1 to the first target address stored in the first register to obtain a second target address, wherein the second target address is the storage address corresponding to the bytecode in all the bytecodes except the first target bytecode; the interpreter executes the first target bytecode stored in the second register. According to the solution provided in the embodiment of the present application, the program counter is mapped in the physical register of the virtual machine so that the physical register stores the value of the program counter. During the execution of the bytecode instruction, after the interpreter executes the previous bytecode, it automatically changes the address value stored in the physical register to point to the next bytecode to be executed, and saves the bytecode to another register so that the interpreter can read and execute it directly from the register. Compared with the existing solution of storing the program counter value in RAM and repeatedly accessing the program counter value from RAM to execute the bytecode, the step of repeatedly accessing the program counter value from RAM can be omitted during the bytecode execution process of the present application, which can effectively improve the operating efficiency of the virtual machine interpreter and improve the execution efficiency of the bytecode instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a flowchart of the steps of a bytecode instruction execution method provided by an embodiment of the present application;

[0041] Figure 2 It is a structural diagram of an electronic device provided in another embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0043] It is understood that although the functional modules are divided in the device schematic diagram and the logical order is shown in the flow chart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flow chart. The terms "first", "second", etc. in the specification, claims or the above drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0044] When a virtual machine receives a bytecode instruction loading request, it needs to trigger the operation of the interpreter by running the program counter to complete the translation of the bytecode into the target machine code. Specifically, after the interpreter executes an instruction, it will update the value of the program counter according to the execution result of the current instruction and the program logic to determine the next instruction to be executed. Since the program counter of the existing virtual machine is stored in the random access memory RAM, the program counter records the current virtual machine running address. Each time the interpreter is executed, it is necessary to read the value of the program counter from the RAM in real time before performing the bytecode translation operation. When the number of bytecode instructions in the bytecode instruction loading request is large, the RAM needs to be accessed frequently, and the operation efficiency of the interpreter is low, resulting in low bytecode execution efficiency.

[0045] To solve the above-mentioned problems, an embodiment of the present application provides a bytecode instruction execution method, a virtual machine, a device, and a medium, the method comprising: when the controller receives a bytecode instruction execution request, saving multiple bytecodes to be executed in the bytecode instruction execution request to the memory; the controller determines the storage address corresponding to each of the bytecodes, determines a first target address from the storage address, and stores the first target address to a first register, wherein the target address is the storage address corresponding to the first bytecode in the bytecode instruction execution request; the interpreter reads the first target address from the first register, reads the first target bytecode corresponding to the first target address from the memory, and saves the first target bytecode to the second register; the interpreter adds 1 to the first target address stored in the first register to obtain a second target address, wherein the second target address is the storage address corresponding to the bytecode in all the bytecodes except the first target bytecode; the interpreter executes the first target bytecode stored in the second register. According to the solution provided in the embodiment of the present application, the program counter is mapped in the physical register of the virtual machine so that the physical register stores the value of the program counter. During the execution of the bytecode instruction, after the interpreter executes the previous bytecode, it automatically changes the address value stored in the physical register to point to the next bytecode to be executed, and saves the bytecode to another register so that the interpreter can read and execute it directly from the register. Compared with the existing solution of storing the program counter value in RAM and repeatedly accessing the program counter value from RAM to execute the bytecode, the step of repeatedly accessing the program counter value from RAM can be omitted during the bytecode execution process of the present application, which can effectively improve the operating efficiency of the virtual machine interpreter and improve the execution efficiency of the bytecode instructions.

[0046] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0047] refer to Figure 1 , Figure 1 1 is a flowchart of the steps of a bytecode instruction execution method provided by an embodiment of the present application. The embodiment of the present application provides a bytecode instruction execution method, which is applied to a virtual machine, and the virtual machine also includes a controller, a memory, an interpreter, a first register and a second register. The method includes but is not limited to the following steps:

[0048] Step S10, when the controller receives a bytecode instruction execution request, it saves a plurality of bytecodes to be executed in the bytecode instruction execution request to a memory;

[0049] Step S20, the controller determines the storage address corresponding to each bytecode, determines a first target address from the storage address, and stores the first target address in a first register, wherein the target address is the storage address corresponding to the first bytecode in the bytecode instruction execution request;

[0050] Step S30, the interpreter reads the first target address from the first register, reads the first target bytecode corresponding to the first target address from the memory, and saves the first target bytecode to the second register;

[0051] Step S40, the interpreter increases the first target address stored in the first register by 1 to obtain a second target address, wherein the second target address points to one of the storage addresses corresponding to the bytecodes in all the bytecodes except the first target bytecode;

[0052] Step S50, the interpreter executes the first target bytecode stored in the second register.

[0053] Specifically, the virtual machine of this embodiment is a RISC architecture virtual machine.

[0054] Specifically, the memory used to store the bytecode in the bytecode instruction execution request in this embodiment can be a cache or a RAM, which can be determined by those skilled in the art according to actual conditions and is not limited here.

[0055] Specifically, the first register of this embodiment is a physical register mapped to the program counter JPC, and the mapping method is to use the register keyword to configure the mapping relationship between the storage address corresponding to the bytecode to be executed and the first register, so that the controller can store the first target address in the first register after determining the first target address, and after the interpreter executes the bytecode corresponding to the first target address stored in the second register, trigger the first register to automatically change the stored address value, increase the current first target address by 1, and obtain one of the storage addresses corresponding to the bytecode other than the first target bytecode in the bytecode instruction execution request, that is, the value stored in the first register points to the code segment area corresponding to the bytecode instruction request, and the first register is used as a program counter. During the process of the interpreter executing bytecode instructions, each time the interpreter only needs to directly read the first register to obtain the target address (i.e., the program counter value) of the next bytecode to be executed. The next bytecode to be executed here is based on the actual situation. For example, the corresponding target address can be the target address corresponding to the next bytecode sorted after the currently executed bytecode, or, when the currently executed bytecode is a jump bytecode, the current first target address is increased by 1 to point to the storage address corresponding to the target bytecode after the jump. When the next target bytecode (i.e., the second target bytecode) is not executed, the second target bytecode is recorded in the first register in advance. This can save the steps of repeatedly storing and retrieving the program counter value from the RAM in the existing solution, effectively improve the operating efficiency of the virtual machine interpreter, and improve the execution efficiency of the bytecode instructions.

[0056] Specifically, the bytecode instruction execution request of this embodiment is equivalent to a bytecode file, which is obtained by compiling the source code into bytecode by the compiler.

[0057] Specifically, the second register of this embodiment is used to store the specific value of the bytecode corresponding to the previous storage address stored in the current first register, providing effective support for the current interpreter to execute the bytecode.

[0058] Specifically, the specific number of the second registers in this embodiment is determined by the compiler and is not limited here.

[0059] Specifically, in some embodiments, Figure 1 The step S50 shown includes but is not limited to the following steps:

[0060] Step S51, reading the first target bytecode from the second register, and determining the target bytecode instruction set corresponding to the first target bytecode;

[0061] Step S52: distribute the first target bytecode to the target bytecode instruction set to execute the first target bytecode.

[0062] It can be understood that the steps for the interpreter to execute the first target bytecode stored in the second register in this embodiment are as follows: read the first target bytecode from the second register, determine the target bytecode instruction set corresponding to the first target bytecode, and distribute the first target bytecode to the target bytecode instruction set, thereby providing an effective basis for triggering the address value +1 stored in the first register.

[0063] In addition, in some embodiments, when executing Figure 1 After step S50, the bytecode instruction execution method of the embodiment of the present application further includes but is not limited to the following steps:

[0064] Step S61, the interpreter determines the reference number of bytecodes in the bytecode instruction execution request, and records the current number of bytecodes executed by the interpreter in real time;

[0065] Step S62, the interpreter reads the second target address from the first register, reads the second target bytecode corresponding to the second target address from the memory, and saves the second target bytecode to the second register;

[0066] Step S63, the interpreter increases the second target address stored in the first register by 1 to obtain a third target address, wherein the third target address points to one of the storage addresses corresponding to the bytecodes in all the bytecodes except the first target bytecode and the second target bytecode;

[0067] Step S64, the interpreter executes the second target bytecode stored in the second register until the current bytecode execution quantity is equal to the reference quantity.

[0068] It can be understood that, in this embodiment, after the interpreter executes the first target bytecode stored in the second register, it determines the reference number of bytecodes in the bytecode instruction execution request, and records the current bytecode execution number of the interpreter in real time; reads the second target address from the first register, reads the second target bytecode corresponding to the second target address from the memory, and saves the second target bytecode to the second register; adds 1 to the second target address stored in the first register to obtain the third target address; the interpreter executes the second target bytecode stored in the second register until the current bytecode execution number is equal to the reference number. At this point, all bytecodes corresponding to the bytecode instruction execution request have been executed, and the interpreter does not need to obtain a new target address from the first register.

[0069] In a specific example, for example, the memory stores 3 bytecodes (i.e., reference number): A1 bytecode 1, A2 bytecode 2, A3 bytecode 3, wherein A1, A2, and A3 are the storage addresses of the corresponding bytecodes 1, bytecode 2, and bytecode 3 in the memory; A1 is stored in the first register R12, the interpreter obtains A1 from R12, and reads bytecode 1 from the memory through A1, and stores bytecode 1 in the second register R0. Since R12 is used as a program counter, at this time, the address value stored in R12 is set +1 to point to A3 in the memory, and the address stored in the first register is changed to A3. At this time, the interpreter executes bytecode 1 in R0, records the number of bytecode executions as 1, and returns to the first register after the execution is completed. Step 1, that is, the interpreter obtains A3 from R12, and reads bytecode 3 from the memory through A3, stores bytecode 3 in R0, sets the address value stored in R12 + 1, points to A2 in the memory, changes the address stored in the first register to A2, and then the interpreter executes bytecode 3 in R0, records the number of bytecode executions as 2, and returns to the first step after the execution is completed. The interpreter obtains A2 from R12, and reads bytecode 2 from the memory through A2, stores bytecode 2 in R0, sets the address value stored in R12 + 1, and the address value is invalid. At this time, the interpreter executes bytecode 2 in R0, records the number of bytecode executions as 3 to reach the reference number, and the interpreter has completed all bytecodes corresponding to the bytecode instruction execution request.

[0070] In addition, in some embodiments, the bytecode instruction execution method of the embodiment of the present application further includes but is not limited to the following steps:

[0071] Step S65, after the interpreter reads the second target address from the first register, if the memory cannot match the bytecode corresponding to the second target address, determine a reference bytecode set from the memory, the reference bytecode set including the remaining bytecodes in the bytecode corresponding to the bytecode instruction execution request except the first target bytecode;

[0072] Step S66, the interpreter redetermines a new second target bytecode from the reference bytecode set, and saves a new second target address corresponding to the new second target bytecode to the first register.

[0073] It can be understood that after the interpreter reads the second target address from the first register, if the memory cannot match the bytecode corresponding to the second target address, it means that the address value currently stored in the first register is an invalid value. At this time, the interpreter determines a reference bytecode set from the memory, and the reference bytecode set includes the remaining bytecodes in the bytecode corresponding to the bytecode instruction execution request except the executed first target bytecode, and re-determines a new second target bytecode from the reference bytecode set, and saves the new second target address corresponding to the new second target bytecode to the first register, thereby improving the fault tolerance rate of the interpreter's execution of bytecode instructions.

[0074] In addition, this embodiment further provides a virtual machine, including a controller, a memory, an interpreter, a first register and a second register, the controller including a first data saving module and a second data saving module, the interpreter including a third data saving module, a first data processing module and a first bytecode execution module;

[0075] The first data saving module is used for saving a plurality of bytecodes to be executed in the bytecode instruction execution request to a memory when receiving the bytecode instruction execution request;

[0076] The second data saving module is used to determine the storage address corresponding to each bytecode, determine the first target address from the storage address, and store the first target address in the first register, wherein the target address is the storage address corresponding to the first bytecode in the bytecode instruction execution request;

[0077] The third data saving module is used for reading the first target address from the first register, reading the first target byte code corresponding to the first target address from the memory, and saving the first target byte code to the second register;

[0078] The first data processing module is used for adding 1 to the first target address stored in the first register to obtain a second target address, wherein the second target address points to one of the storage addresses corresponding to the bytecodes in all the bytecodes except the first target bytecode;

[0079] The first bytecode instruction execution module is used to execute the first target bytecode stored in the second register.

[0080] In some embodiments, the interpreter further comprises:

[0081] A second data processing module is used to determine the reference number of bytecodes in the bytecode instruction execution request and record the current bytecode execution number of the interpreter in real time;

[0082] a third data processing module, configured to read the second target address from the first register, read the second target bytecode corresponding to the second target address from the memory, and save the second target bytecode to the second register;

[0083] a fourth data processing module, configured to add 1 to the second target address stored in the first register to obtain a third target address, wherein the third target address points to one of the storage addresses corresponding to the bytecodes other than the first target bytecode and the second target bytecode in all the bytecodes;

[0084] The second bytecode instruction execution module is used to execute the second target bytecode stored in the second register until the current bytecode execution quantity is equal to the reference quantity.

[0085] In some embodiments, the first bytecode instruction execution module includes:

[0086] a target bytecode instruction set determination module, configured to read the first target bytecode from the second register and determine a target bytecode instruction set corresponding to the first target bytecode;

[0087] The bytecode distribution module is used to distribute the first target bytecode to the target bytecode instruction set to execute the first target bytecode.

[0088] In some embodiments, the interpreter further comprises:

[0089] The fifth data processing module is used to determine a reference bytecode set from the memory when no bytecode corresponding to the second target address is matched in the memory after the second target address is read from the first register, the reference bytecode set including the remaining bytecodes in the bytecode corresponding to the bytecode instruction execution request except the first target bytecode, re-determine a new second target bytecode from the reference bytecode set, and save a new second target address corresponding to the new second target bytecode to the first register.

[0090] It should be noted that the specific implementation of the virtual machine in this embodiment is basically the same as the specific implementation of the above-mentioned bytecode instruction execution method, and will not be repeated here.

[0091] like Figure 2 As shown, Figure 2 2 is a structural diagram of an electronic device provided by an embodiment of the present application. The present invention also provides an electronic device 200, including:

[0092] The processor 210 may be implemented by a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0093] The memory 220 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 220 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 220, and the processor 210 calls and executes the bytecode instruction execution method of the embodiment of this application;

[0094] Input / output interface 230, used to implement information input and output;

[0095] Communication interface 240, used to realize communication interaction between the apparatus and other devices, which can be realized by wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.);

[0096] bus 250 , which transmits information between the various components of the device (e.g., processor 210 , memory 220 , input / output interface 230 , and communication interface 240 );

[0097] The processor 210 , the memory 220 , the input / output interface 230 , and the communication interface 240 are connected to each other in communication within the device via the bus 250 .

[0098] In addition, an embodiment of the present application further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the above-mentioned bytecode instruction execution method is implemented.

[0099] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0100] It will be appreciated by those skilled in the art that all or some of the steps and systems in the disclosed method above may be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0101] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions under the shared conditions without violating the spirit of the present invention. These equivalent deformations or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A bytecode instruction execution method, characterized in that: Applied to a virtual machine, the virtual machine further includes a controller, a memory, an interpreter, a first register and a second register, the method comprising: When the controller receives a bytecode instruction execution request, the controller saves a plurality of bytecodes to be executed in the bytecode instruction execution request to the memory; The controller determines a storage address corresponding to each of the bytecodes, determines a first target address from the storage addresses, and stores the first target address in a first register, wherein the target address is a storage address corresponding to a first bytecode in a bytecode instruction execution request; The interpreter reads the first target address from the first register, reads the first target bytecode corresponding to the first target address from the memory, and saves the first target bytecode to the second register; The interpreter adds 1 to the first target address stored in the first register to obtain a second target address, wherein the second target address points to one of the storage addresses corresponding to the bytecodes in all the bytecodes except the first target bytecode; The interpreter executes the first target bytecode stored in the second register.

2. The bytecode instruction execution method according to claim 1, characterized in that: After the interpreter executes the first target bytecode stored in the second register, the method further includes: The interpreter determines the reference number of bytecodes in the bytecode instruction execution request, and records the current number of bytecodes executed by the interpreter in real time; The interpreter reads the second target address from the first register, reads the second target bytecode corresponding to the second target address from the memory, and saves the second target bytecode to the second register; The interpreter adds 1 to the second target address stored in the first register to obtain a third target address, wherein the third target address points to one of the storage addresses corresponding to the bytecodes other than the first target bytecode and the second target bytecode in all the bytecodes; The interpreter executes the second target bytecode stored in the second register until the current bytecode execution quantity is equal to the reference quantity.

3. The bytecode instruction execution method according to claim 1, characterized in that: The interpreter executes the first target bytecode stored in the second register, including: Reading the first target bytecode from the second register, and determining a target bytecode instruction set corresponding to the first target bytecode; The first target bytecode is distributed to the target bytecode instruction set to execute the first target bytecode.

4. The bytecode instruction execution method according to claim 2, characterized in that: The method further comprises: After the interpreter reads the second target address from the first register, if the memory cannot match the bytecode corresponding to the second target address, determine a reference bytecode set from the memory, the reference bytecode set including the remaining bytecodes in the bytecode corresponding to the bytecode instruction execution request except the first target bytecode; The interpreter redetermines a new second target bytecode from the reference bytecode set, and saves a new second target address corresponding to the new second target bytecode to the first register.

5. A virtual machine, characterized in that: It includes a controller, a memory, an interpreter, a first register and a second register, wherein the controller includes a first data saving module and a second data saving module, and the interpreter includes a third data saving module, a first data processing module and a first bytecode execution module; The first data saving module is used for saving a plurality of bytecodes to be executed in the bytecode instruction execution request to the memory when receiving the bytecode instruction execution request; The second data saving module is used to determine the storage address corresponding to each of the bytecodes, determine the first target address from the storage address, and store the first target address in the first register, wherein the target address is the storage address corresponding to the first bytecode in the bytecode instruction execution request; The third data saving module is used for reading the first target address from the first register, reading the first target bytecode corresponding to the first target address from the memory, and saving the first target bytecode to the second register; The first data processing module is used for adding 1 to the first target address stored in the first register to obtain a second target address, wherein the second target address points to one of the storage addresses corresponding to the bytecodes in all the bytecodes except the first target bytecode; The first bytecode instruction execution module is used to execute the first target bytecode stored in the second register.

6. The virtual machine according to claim 5, characterized in that: The interpreter also includes: A second data processing module, used to determine the reference number of bytecodes in the bytecode instruction execution request, and record the current number of bytecodes executed by the interpreter in real time; a third data processing module, configured to read the second target address from the first register, read the second target bytecode corresponding to the second target address from the memory, and save the second target bytecode to the second register; a fourth data processing module, configured to add 1 to the second target address stored in the first register to obtain a third target address, wherein the third target address points to one of the storage addresses corresponding to the bytecodes other than the first target bytecode and the second target bytecode in all the bytecodes; The second bytecode instruction execution module is used to execute the second target bytecode stored in the second register until the current bytecode execution quantity is equal to the reference quantity.

7. The virtual machine according to claim 5, characterized in that: The first bytecode instruction execution module comprises: a target bytecode instruction set determining module, configured to read the first target bytecode from the second register and determine a target bytecode instruction set corresponding to the first target bytecode; A bytecode distribution module is used to distribute the first target bytecode to the target bytecode instruction set to execute the first target bytecode.

8. The virtual machine according to claim 5, characterized in that: The interpreter also includes: A fifth data processing module is used to determine a reference bytecode set from the memory if no bytecode corresponding to the second target address is matched in the memory after the second target address is read from the first register, the reference bytecode set including the remaining bytecodes in the bytecode corresponding to the bytecode instruction execution request except the first target bytecode, re-determine a new second target bytecode from the reference bytecode set, and save a new second target address corresponding to the new second target bytecode to the first register.

9. An electronic device, characterized in that: It includes at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions that can be executed by the at least one control processor, and the instructions are executed by the at least one control processor so that the at least one control processor can execute the bytecode instruction execution method as described in any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the bytecode instruction execution method as described in any one of claims 1 to 4.

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