Lock step circuit, chip and electronic equipment
By introducing a comparison module into the lock step circuit, comparing the output data of the redundant processing module and the verification module, the reliability problem caused by data flip during the lock step process is solved, and the correct alarm signal output is achieved.
Patent Information
- Application Number
- CN202510023786.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-07
- Publication Date
- 2025-05-06
AI Technical Summary
During the lock step process, due to physical factors such as line aging or particle flip, the data may be flipped, causing the slave to not recognize errors, reducing the reliability of the lock step.
A lock step circuit is designed, including a main processing module, a redundant processing module, a verification module and a comparison module. The comparison module compares the data output by the redundant processing module with the data output by the verification module and outputs an alarm signal. In this way, even if the data output by the main processing module is flipped before the verification module, the comparison module can still compare the flipped data, thereby outputting the correct alarm signal.
Improves the reliability of the lock step, ensuring that the alarm signal can be correctly identified and output even if the data is flipped during transmission.
Smart Images
Figure CN119938413A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of lockstep processing technology, and in particular to a lockstep circuit, a chip and an electronic device. Background Art
[0002] During the lock-step process, during the transmission from the host to the slave, the data may be flipped due to physical factors such as line aging and particle flipping, making it impossible for the slave to identify the error even if it decodes the data.
[0003] However, the data compared by the comparison module may be correct, which makes it impossible for the comparison module to warn the erroneous data received by the slave, thereby reducing the reliability of the lock-step. Summary of the invention
[0004] In view of the above problems, the embodiments of the present application provide a lockstep circuit, a chip and an electronic device to at least partially solve the above technical problems.
[0005] In a first aspect, an embodiment of the present application provides a lock-step circuit, which includes a main processing module, a redundant processing module, a verification module and a comparison module. The main processing module is used to output first data according to input data; the redundant processing module is used to output second data according to the input data; the verification module is used to output corresponding third data and verification data according to the first data; and the comparison module is used to output an alarm signal according to the comparison result of the second data and the third data.
[0006] In a second aspect, an embodiment of the present application further provides a chip, which includes the above-mentioned lockstep circuit.
[0007] In a third aspect, an embodiment of the present application further provides an electronic device, which includes a device body and the above-mentioned chip disposed in the device body.
[0008] The lockstep circuit, chip and electronic device provided in the embodiments of the present application output an alarm signal according to the comparison result of the second data and the third data through the comparison module. Compared with outputting the alarm signal according to the comparison result of the first data and the second data, even if the first data is flipped before being input into the verification module, the comparison module compares the third data after the flipping, rather than the first data before the flipping. Therefore, a correct alarm signal can be output when the first data is flipped, which improves the reliability of the lockstep.
[0009] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0011] Figure 1 A first principle block diagram of a lockstep circuit provided in an embodiment of the present application is shown.
[0012] Figure 2 A first principle block diagram of a comparison module is shown.
[0013] Figure 3 A functional block diagram of a decoding logic unit is shown.
[0014] Figure 4 A principle block diagram of a first logic unit is shown.
[0015] Figure 5 A principle block diagram of a second logic unit is shown.
[0016] Figure 6 A second principle block diagram of the comparison module is shown.
[0017] Figure 7 A third principle block diagram of the lockstep circuit provided in an embodiment of the present application is shown.
[0018] Figure 8 An application schematic diagram of the lockstep circuit provided in an embodiment of the present application is shown.
[0019] Fig. 9 The structure diagram of the chip provided in the embodiment of the present application is shown.
[0020] Fig.10 A structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0021] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.
[0022] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.
[0023] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.
[0024] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.
[0025] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.
[0026] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.
[0027] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.
[0028] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.
[0029] In the lockstep circuit in the related art, the first input end of the comparison module is connected between the main processing module and the verification module, and the second input end of the comparison module is connected to the output end of the redundant processing module. Before the first data output by the main processing module according to the input data is sent to the verification module, it may be caused to flip due to physical factors such as line aging and particle flipping. In this case, the first data accessed by the verification module is the data that has been flipped. Even if the first data that has been flipped is input to the slave machine for decoding through the verification module, it is impossible to effectively identify the error that occurred before the verification module.
[0030] Among them, the verification module is used to implement end-to-end (E2E) communication protection, which can protect the exchange of safety-related data during the data transmission from the host to the slave to prevent the impact of faults on the communication link. One of the implementation methods of E2E protection is error detection and correction (ECC). ECC technology can detect errors in data transmission and correct them when possible to ensure safe and reliable transmission of data between the host and the slave.
[0031] In this case, the data input to the slave is erroneous data after flipping, but the first data input to the comparison module is not flipped. The comparison module compares the correct data, and therefore cannot generate an error alarm.
[0032] Based on this, the embodiment of the present application provides a lockstep circuit 100, such as Figure 1As shown, the lock-step circuit 100 is applied to a bus bridge, and the lock-step circuit 100 includes a main processing module 10, a redundant processing module 20, a verification module 30, and a comparison module 40. The input end of the main processing module 10 is connected to the input end of the redundant processing module 20, the output end of the main processing module 10 is connected to the input end of the verification module 30, the two input ends of the comparison module 40 are respectively connected to the output end of the verification module 30 and the output end of the redundant processing module 20, and the comparison module 40 outputs an alarm signal ALM. The lock-step circuit 100 outputs the alarm signal ALM according to the comparison result of the second data and the third data through the comparison module 40. Compared with outputting the alarm signal ALM according to the comparison result of the first data and the second data, even if the first data is flipped before being input to the verification module 30, the comparison module 40 compares the third data after the flip, rather than the first data before the flip, so that the correct alarm signal ALM can be output when the first data is flipped, which improves the reliability of the lock-step.
[0033] The present application embodiment provides a lockstep circuit 100, see Figures 1 to 8 ,like Figure 1 As shown, the lockstep circuit 100 includes a main processing module 10, a redundant processing module 20, a verification module 30 and a comparison module 40. The main processing module 10 is used to output first data according to input data; the redundant processing module 20 is used to output second data according to the input data; the verification module 30 is used to output corresponding third data and verification data according to the first data; and the comparison module 40 is used to output an alarm signal ALM according to the comparison result between the second data and the third data.
[0034] It can be understood that the lock-step circuit 100 provided in the embodiment of the present application outputs the alarm signal ALM according to the comparison result of the second data and the third data through the comparison module 40. Compared with outputting the alarm signal ALM according to the comparison result of the first data and the second data, even if the first data is flipped before being input into the verification module 30, the comparison module 40 compares the third data after the flipping, rather than the first data before the flipping, so that the correct alarm signal ALM can be output when the first data is flipped, which improves the reliability of the lock-step.
[0035] It should be noted that the verification module 30 may be, but is not limited to, a module for implementing error checking and correction (ECC) technology, and may specifically be an ECC encoding circuit, which is used to generate a corresponding verification code (verification data) according to the first data. In other embodiments, the verification module 30 may also be a module for implementing other verification technologies besides the ECC technology.
[0036] If the first data is not flipped, the first data and the third data are the same; if the first data is flipped, the first data and the third data are different. The structure of the main processing module 10 is the same as that of the redundant processing module 20.
[0037] When the lockstep circuit 100 is applied to a bus bridge, the main processing module 10 or the redundant processing module 20 may include an interface conversion circuit or a data format conversion circuit. In some other embodiments, the main processing module 10 or the redundant processing module 20 may both be a processing core or a controller.
[0038] Alternatively, if Figure 2 As shown, the comparison module 40 includes a decoding logic unit 41, a first logic unit 42, a second logic unit 43 and a comparison unit 44. The decoding logic unit 41 is used to generate first enable data and second enable data according to first configuration data and second configuration data; the first logic unit 42 is used to output first logic data according to the operation result of third data and first enable data; the second logic unit 43 is used to output second logic data according to the operation result of second data and second enable data; the comparison unit 44 is used to output an alarm signal ALM according to the comparison result of whether the first logic data is equal to the second logic data.
[0039] It should be noted that pri_en_cfg[4:0] is used to represent the first configuration data, which can be stored in a register. The number of bits of the first configuration data is 5 bits as an example here, and other number of bits can be configured as needed. shw_en_cfg[4:0] is used to represent the second configuration data, which can be stored in a register. The number of bits of the second configuration data is 5 bits as an example here, and other number of bits can be configured as needed.
[0040] pri_en[i] represents a single-bit first enable data. shw_en[i] represents a single-bit second enable data. pri_bit[i] represents a single-bit third data. shw_bit[i] represents a single-bit second data.
[0041] Alternatively, if Figure 3 As shown, the decoding logic unit 41 includes a first decoding unit 411 and a second decoding unit 412. The first decoding unit 411 is used to generate first enabling data according to first configuration data. The number of bits of the first configuration data is N1, and the number of the first enabling data is 2. N1 , N1 is an integer greater than 0; the second decoding unit 412 is used to generate second enabling data according to the second configuration data, the number of bits of the second configuration data is N2, and the number of the second enabling data is 2 N2 , N2 is an integer greater than 0.
[0042] It should be noted that if the first configuration data is 5-bit pri_en_cfg[4:0], the first decoding unit 411 can output 32 different first enable data, such as pri_en[0], pri_en[1], pri_en[2]...pri_en
[30] and pri_en
[31] . In this way, more types of first enable data can be output by using a register with a smaller capacity, which reduces the number of bits of the register, thereby effectively reducing the occupied area of the register, and further reducing the area of the lockstep circuit 100. Similarly, the number of bits of the register storing the second configuration data can also be reduced, thereby effectively reducing the occupied area of the register, and further reducing the area of the lockstep circuit 100. Optionally, N1 is equal to N2.
[0043] Alternatively, if Figure 4 As shown, the first logic unit 42 includes an XOR gate 421, a first input terminal of the XOR gate 421 is connected to the third data, a second input terminal of the XOR gate 421 is connected to the first enable data, and an output terminal of the XOR gate 421 outputs the first logic data.
[0044] It should be noted that when pri_en[i] is 0, the output of XOR gate 421 can be the same as pri_bit[i]; when pri_en[i] is 1, the output of XOR gate 421 can be the inversion of pri_bit[i]. Therefore, after power-on, the reset value of pri_en[i] should be 0, and pri_bit[i] does not self-check by default.
[0045] Alternatively, if Figure 5 As shown, the second logic unit 43 includes an XOR gate 431, a first input terminal of the XOR gate 431 is connected to the second data, a second input terminal of the XOR gate 431 is connected to the second enable data, and an output terminal of the XOR gate 431 outputs the second logic data.
[0046] It should be noted that when shw_en[i] is 0, the output of the XOR gate 431 can be the inversion of shw_bit[i]; when shw_en[i] is 1, the output of the XOR gate 431 can be the same as shw_bit[i]. Therefore, after power-on, the reset value of shw_en[i] should be 1, and shw_bit[i] does not self-check by default.
[0047] Specifically, pri_en[i] is 0, the output of XOR gate 421 is the same as pri_bit[i]; shw_en[i] is 1, the output of XOR gate 431 is the same as shw_bit[i]. When comparing pri_bit[i]!=shw_bit[i], an alarm pulse appears in the alarm signal ALM.
[0048] pri_en[i] is 0, the output of XOR gate 421 is the same as pri_bit[i]; shw_en[i] input is 0, the output of XOR gate 431 is the inversion of shw_bit[i]. This situation can be used to test whether the comparison logic of lockstep circuit 100 is correct.
[0049] When pri_en[i] is 1, the output of XOR gate 421 is the inversion of pri_bit[i]; when shw_en[i] is 0, the output of XOR gate 431 is the inversion of shw_bit[i]. This situation can be used to compare the second data with the third data to generate an alarm pulse.
[0050] pri_en[i] is 1, the output of XOR gate 421 is the inversion of pri_bit[i]; shw_en[i] is 1, the output of XOR gate 431 is the same as shw_bit[i]. This situation can be used to test whether the comparison logic of lockstep circuit 100 is correct.
[0051] Alternatively, if Figure 6 As shown, the comparison module 40 further includes an edge detection unit 45 , and the edge detection unit 45 is configured to output an alarm signal ALM when an edge of the comparison result output by the comparison unit 44 is detected.
[0052] It should be noted that the edge may be at least one of a rising edge and a falling edge. Compared with the level-triggered output alarm signal ALM, the edge-triggered output alarm signal ALM is more timely or accurate.
[0053] Alternatively, if Figure 7 As shown, the lockstep circuit 100 further includes a first delay module 50 and a second delay module 60 . The first delay module 50 is used to delay the third data transmitted to the comparison module 40 ; the second delay module 60 is used to delay the input data transmitted to the redundancy processing module 20 .
[0054] It should be noted that the first delay module 50 may be connected between the checking module 30 and the comparing module 40 . The second delay module 60 may be connected between the input terminal for receiving input data and the redundancy processing module 20 .
[0055] Alternatively, if Figure 7 As shown, the lockstep circuit 100 also includes a configuration bus PL1 and a branch bus ZL1. The configuration bus PL1 is used to transmit the third data and the verification data; the branch bus ZL1 is used to transmit the third data from the configuration bus PL1 to the comparison module 40; wherein the first delay module 50 is connected to the branch bus ZL1.
[0056] It should be noted that the configuration bus PL1 is used to transmit the third data and the verification data. The branch bus ZL1 is connected to the configuration bus PL1, and the first delay module 50 is connected in series with the branch bus ZL1, so that the first delay module 50 can avoid delaying the data in the configuration bus PL1.
[0057] Figure 8 The application schematic diagram of the lockstep circuit 100 provided in an embodiment of the present application is shown. The slave is connected to the configuration bus PL1 to receive the third data and the check data. An ECC decoding module can also be set before the slave, and the ECC decoding module can perform error detection and correction on the third data according to the check data to improve the reliability of data transmission.
[0058] The present application embodiment also provides a chip 200, such as Fig. 9 As shown, the chip 200 includes the lockstep circuit 100. The chip 200 is also called an integrated circuit (IC), and the chip 200 can be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip.
[0059] It can be understood that since the chip 200 provided in the embodiment of the present application includes the lockstep circuit 100, it can also output the alarm signal ALM according to the comparison result of the second data and the third data through the comparison module 40. Compared with outputting the alarm signal ALM according to the comparison result of the first data and the second data, even if the first data is flipped before being input into the verification module 30, the comparison module 40 compares the third data after the flipping, rather than the first data before the flipping, so that the correct alarm signal ALM can be output when the first data is flipped, which improves the reliability of the lockstep.
[0060] The present application embodiment also provides an electronic device 300, such as Fig.10As shown, the electronic device 300 includes a device body and the above-mentioned lock-step circuit 100 or chip 200 provided in the device body. The electronic device 300 can be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.
[0061] It can be understood that since the electronic device 300 provided in the embodiment of the present application includes the above-mentioned lockstep circuit 100 or chip 200, it can also output the alarm signal ALM according to the comparison result of the second data and the third data through the comparison module 40. Compared with outputting the alarm signal ALM according to the comparison result of the first data and the second data, even if the first data is flipped before being input into the verification module 30, the comparison module 40 compares the third data after the flipping, rather than the first data before the flipping, so that the correct alarm signal ALM can be output when the first data is flipped, which improves the reliability of the lockstep.
[0062] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as a preferred embodiment as above, it is not intended to limit the present application. Any technical personnel in this field can use the technical contents disclosed above to make some changes or modify them into equivalent embodiments with equivalent changes without departing from the scope of the technical solution of the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.
Claims
1. A lockstep circuit, characterized in that: The lockstep circuit comprises: A main processing module, the main processing module is used to output first data according to input data; A redundancy processing module, the redundancy processing module is used to output second data according to the input data; A verification module, the verification module is used to output corresponding third data and verification data according to the first data; A comparison module, wherein the comparison module is used to output an alarm signal according to a comparison result between the second data and the third data.
2. The lockstep circuit according to claim 1, characterized in that: The comparison module comprises: a decoding logic unit, the decoding logic unit being configured to generate first enabling data and second enabling data according to first configuration data and second configuration data; a first logic unit, the first logic unit being configured to output first logic data according to a calculation result of the third data and the first enable data; a second logic unit, the second logic unit being configured to output second logic data according to a calculation result of the second data and the second enable data; A comparison unit, wherein the comparison unit is used to output the alarm signal according to a comparison result of whether the first logic data is equal to the second logic data.
3. The lockstep circuit according to claim 2, characterized in that: The decoding logic unit comprises: A first decoding unit, the first decoding unit is used to generate the first enabling data according to the first configuration data, the number of bits of the first configuration data is N1, and the number of the first enabling data is 2 N1 , N1 is an integer greater than 0; A second decoding unit, the second decoding unit is used to generate the second enabling data according to the second configuration data, the number of bits of the second configuration data is N2, and the number of the second enabling data is 2 N2 , N2 is an integer greater than 0.
4. The lockstep circuit according to claim 2, characterized in that: The first logic unit includes an XOR gate, a first input terminal of the XOR gate is connected to the third data, a second input terminal of the XOR gate is connected to the first enable data, and an output terminal of the XOR gate outputs the first logic data.
5. The lockstep circuit according to claim 2, characterized in that: The second logic unit includes an XNOR gate, a first input terminal of the XNOR gate is connected to the second data, a second input terminal of the XNOR gate is connected to the second enable data, and an output terminal of the XNOR gate outputs the second logic data.
6. The lockstep circuit according to claim 2, characterized in that: The comparison module further includes an edge detection unit, and the edge detection unit is used to output the alarm signal when an edge of the comparison result output by the comparison unit is detected.
7. The lockstep circuit according to any one of claims 1 to 6, characterized in that: The lockstep circuit further comprises: a first delay module, the first delay module being used for delaying the third data transmitted to the comparison module; A second delay module, wherein the second delay module is used to delay the input data transmitted to the redundancy processing module.
8. The lockstep circuit according to claim 7, characterized in that: The lockstep circuit further comprises: A configuration bus, wherein the configuration bus is used to transmit the third data and the verification data; a branch bus, the branch bus being used to transmit the third data from the configuration bus to the comparison module; Wherein, the first delay module is connected to the branch bus.
9. A chip, characterized in that: The chip comprises the lockstep circuit as claimed in any one of claims 1 to 8.
10. An electronic device, characterized in that: The electronic device comprises a device body and the chip according to claim 9 disposed in the device body.