Universal distributed test system
By introducing a distributed testing system in the automatic testing machine, using edge computing modules and star or chain topology, the problems of limited depth and low testing efficiency in the traditional ATE testing machine are solved, and efficient and low-cost chip testing is achieved.
Patent Information
- Application Number
- CN202510004385.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-05-06
AI Technical Summary
The existing automatic test machine ATE has problems such as limited logic vector depth, high testing cost, excessive data channel usage, low data centralized processing efficiency, and long iteration time for test programs, which is difficult to meet the needs of complex chip testing.
A general distributed testing system is proposed. By combining test computers, N edge computing modules and N DUT arrays, a star or chain topology is adopted to realize the decomposition, distribution and parallel processing of test data, breaking through the limitation of the depth of the logical test vector, and improving the testing efficiency.
It realizes infinite expansion of the depth of logical test vectors, reduces testing costs, improves testing efficiency, simplifies the testing process, and reduces the overall system requirements.
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Figure CN119938425A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip testing technology, and in particular to a universal distributed testing technology. Background Art
[0002] This section is intended to provide a background or context for the embodiments of the present application as stated in the claims. The contents in this section are for reference only and do not constitute an admission or confirmation that they are prior art that has been disclosed.
[0003] Chip automated testing generally uses automatic test equipment ATE, which is an instrument used to test integrated circuits. It applies test vectors to integrated circuits according to pre-set test signals, and compares the observed response with the expected result to determine whether the integrated circuit has defects. It is necessary to select a suitable ATE platform according to different chip specifications. For example, digital chips generally use SoC testers, and common ones include Teradyne's J750-HD platform and Advantest's 93K platform; memory chips generally use storage testers, and common ones include Teradyne's Magnum platform and Advantest's T58xx series platform, etc.
[0004] The ATE platform is versatile and stable. Test engineers can develop test programs based on the data specifications of the chip to be tested and on each platform to implement functional and performance testing of the chip to be tested.
[0005] Existing automatic test machines ATE have the shortcomings of limited logic vector depth and difficulty in expansion. At the same time, the depth of logic vectors is proportional to the test cost. The deeper the logic vector depth, the higher the corresponding software license fee, and the higher the test cost per chip. When testing complex digital chips, if the logic vector depth is not enough, if some test vectors are discarded, the test coverage will be insufficient, and the chip screening quality will be low, and there is a risk of missed detection; if sufficient test coverage is retained, it will be necessary to split multiple test processes, which will increase the difficulty of test control and test costs, and reduce overall yield; if a higher-configuration test machine is selected, the test cost will also increase significantly, and the difficulty of finding a high-configuration machine in OSAT will also increase.
[0006] In addition, the existing automatic test equipment ATE adopts a centralized processing mode, which collects the response of each data channel and returns it to the computer for processing. Although the data information is complete, there are problems such as too many data channels being occupied, high uplink and downlink duplex transmission bandwidth occupancy, and low data centralized processing efficiency.
[0007] In addition, the existing automatic test equipment ATE uses a pre-compiled method to store test programs. Each update iteration of the digital test vector requires recompilation of the complete test program, which is time-consuming. At the same time, the test program code part and the digital test vector part are highly coupled, which leads to the disadvantage of difficulty in debugging.
[0008] Therefore, there is an urgent need for a test system that can break through the limitation of LVM vector depth in traditional ATE test machines and has higher test efficiency. Summary of the invention
[0009] The purpose of this application is to provide a universal distributed testing system that can break through the limitation of logic test vector depth and has higher testing efficiency.
[0010] To solve the above technical problems, an embodiment of the present invention discloses a universal distributed test system, comprising: a test computer, N edge computing modules and N DUT arrays, wherein N is an integer greater than or equal to 2;
[0011] The test computer is used to store a test database and provide a test interface, the test interface is communicatively connected with the N edge computing modules, and the test interface is used to send the test data in the test database to the N edge computing modules and collect the test results uploaded by the N edge computing modules;
[0012] The N edge computing modules are communicatively connected to the N DUT arrays in a one-to-one correspondence, and the N edge computing modules are used to send the test vectors contained in the test data to the N DUT arrays, receive the test response signals uploaded by the N DUT arrays, calculate the test results according to the test response signals, and upload the test results to the test interface;
[0013] The N DUT arrays are used to test the corresponding DUT according to the test vector and upload the test response signal to the N edge computing modules.
[0014] In another preferred example, the test interface is communicatively connected to each of the N edge computing modules respectively, and the N edge computing modules are independent of each other and have no connection channels with each other, thereby forming a star topology.
[0015] In another preferred example, when the parallelism requirement for test data transmission is not high, the universal distributed test system adopts the star topology.
[0016] In another preferred example, the test interface is only communicatively connected to any one of the N edge computing modules, and the N edge computing modules are communicatively connected to each other, thereby forming a chain topology structure.
[0017] In another preferred example, when the parallelism requirement for test data transmission is high, the universal distributed test system adopts the chain topology.
[0018] In another preferred example, the edge computing module includes the following submodules: a data receiving module, a data decoding module, a data storage module, an excitation module, a sampling module, a logic judgment module, a result storage module, a data coordination module, a selection module and a data sending module;
[0019] The data receiving module is used to receive test data from the test interface or an adjacent edge computing module;
[0020] The data decoding module is used to decode the test data corresponding to the edge computing module in the test data received by the data receiving module to obtain the test vector;
[0021] The data storage module is used to store the test vector decoded by the data decoding module;
[0022] The stimulus module is used to send the stimulus signal contained in the test vector stored in the data storage module to the DUT array corresponding to the edge computing module;
[0023] The sampling module is used to sample the test response signal uploaded by the DUT array;
[0024] The logic judgment module is used to perform a logic comparison based on the expected signal contained in the test vector stored in the data storage module and the test response signal sampled by the sampling module to obtain a test result corresponding to the test response signal;
[0025] The result storage module is used to store the test results obtained by the logic decision module;
[0026] There is a data transparent transmission path between the data collaboration module and the data receiving module, which is used to send the test data received by the data receiving module that does not correspond to the current edge computing module to the data receiving module of the adjacent edge computing module, and receive the test results uploaded by the adjacent edge computing module;
[0027] The selection module is used to select the test result stored in the result storage module or the data collaboration module;
[0028] The data sending module is used to upload the test result selected by the selection module to the test interface or the data coordination module of the adjacent edge computing module.
[0029] In another preferred example, an asymmetric transmission method is adopted between the test interface and the N edge computing modules, and the test data sent by the test interface to the N edge computing modules is transmitted preferentially.
[0030] In another preferred example, the test data sent to the N edge computing modules through the test interface is transmitted in real time.
[0031] In another preferred example, the test interface includes: USB, network port and / or PCIe port.
[0032] In another preferred embodiment, the test database is formed by classifying and encoding the test vectors in a standard format and then compressing and encrypting them.
[0033] In the implementation mode of the present application, the original logic test vectors are decomposed and integrated into a universal test data format, a test database is formed by compression and encryption, and stored in the universal storage space of the test computer, breaking through the limitation of the LVM vector depth in the traditional ATE test machine and improving the test efficiency.
[0034] Furthermore, when the parallelism requirement for test data transmission is not high, the star topology is adopted, and each parallel module is relatively independent and does not interfere with each other.
[0035] Furthermore, when the parallelism requirement for test data transmission is high, the chain topology structure can be used to arbitrarily expand parallel modules without affecting the connection mode of the test interface.
[0036] Furthermore, the test stimulus, sampling, and judgment functions are delegated to the edge computing module. Through edge computing, the requirements for the entire system are reduced, and high-concurrency testing can be achieved at a low cost.
[0037] Furthermore, an asymmetric transmission method is adopted between the test interface and the N edge computing modules, and the test data sent by the test interface to the N edge computing modules is transmitted preferentially, so that the downlink bandwidth is fully utilized and the efficiency is improved.
[0038] Furthermore, the test interface transmits a database that has been encoded, compressed and encrypted, with a unified data format, no additional overhead, and higher efficiency.
[0039] Furthermore, during the test process, the test database is transmitted in real time, and does not use the specific limited LVM space used in the ATE machine, thereby achieving a nearly infinite test vector space.
[0040] Each technical feature disclosed in the above invention content, each technical feature disclosed in each implementation mode and example below, and each technical feature disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should be deemed to have been recorded in this specification), unless such combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, while the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] Figure 1 It is a structural schematic diagram of a star topology structure of a universal distributed test system according to an embodiment of the present application;
[0042] Figure 2 It is a schematic diagram of a chain topology structure of a universal distributed test system according to an embodiment of the present application;
[0043] Figure 3 It is a schematic diagram of a test database generation process of a general distributed test system according to an embodiment of the present application;
[0044] Figure 4 It is a structural diagram of an edge computing module of a general distributed testing system according to an implementation scheme of the present application. DETAILED DESCRIPTION
[0045] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.
[0046] Description of some concepts:
[0047] ATE (Automated Test Equipment), an automatic test machine, is an automated mass production test equipment for logic chips, memory chips, digital-analog hybrid chips and other chip products.
[0048] OSAT (Outsourced Semiconductor Assembly and Testing), an outsourced semiconductor packaging and testing service provider, provides third-party outsourcing services to design companies and is a key production link in the entire semiconductor industry chain.
[0049] LVM (Logic Vector Memory), a logic vector storage block, is a storage block for storing logic test vectors in ATE machines. It is generally limited in depth, ranging from 16M to 256M.
[0050] DUT (Device Under Test), device under test, chip under test.
[0051] Correspondence: refers to the corresponding relationship between two or more data, which is usually stored in storage devices (such as storage servers, hard disks, memory, etc.). The specific storage form can be various, for example, it can be a file representing the correspondence, or a table in a database, and so on.
[0052] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.
[0053] The embodiment of the present application relates to a universal distributed test system, the structural block diagram of which is as follows: Figure 1 and Figure 2 shown.
[0054] Specifically, if Figure 1 and Figure 2 As shown, the universal distributed test system includes:
[0055] A test computer, N edge computing modules, and N DUT arrays, where N is an integer greater than or equal to 2.
[0056] The test computer is used to store a test database and provide a test interface. The test interface is communicatively connected to the N edge computing modules. The test interface is used to send the test data in the test database to the N edge computing modules and collect the test results uploaded by the N edge computing modules.
[0057] In this embodiment, preferably, the test database is formed by classifying and encoding the test vectors in a standard format and then compressing and encrypting them.
[0058] Specifically, if Figure 3 As shown, the test database is formed by decomposing and integrating the original logic test vectors with standard test vector formats into a universal test data format, and compressing and encrypting the format to form a database, which is stored in the universal storage space of the test computer, such as a hard disk, memory, etc., and has basically no upper limit on usage. Among them, the standard test vector formats include: AVC, ATP, WGL, VEC, etc.
[0059] The general test data formats include the following three:
[0060] a) The test vector only contains the stimulus itself and only downlink data;
[0061] b) The test vector contains stimulus and expected output, which is decomposed into three parts: stimulus, expectation and mask;
[0062] c) Timing requirements of test vectors.
[0063] In addition, the test data sent from the test interface to the N edge computing modules is transmitted in real time. That is to say, during the test process, the test database is transmitted in real time, and does not use the specific limited LVM space used in traditional ATE machines, realizing a nearly infinite test vector space.
[0064] Furthermore, preferably, an asymmetric transmission method is adopted between the test interface and the N edge computing modules, and the test data sent by the test interface to the N edge computing modules is transmitted preferentially.
[0065] It should be noted that the asymmetric transmission here means that the test data sent from the test interface to the N edge computing modules is transmitted first, and then the uplink data uploaded to the test interface by the N edge computing modules is transmitted after the downlink data sent to the N edge computing modules are transmitted.
[0066] The test interface of this embodiment is mainly used to send the test database and collect the test results. Due to the asymmetric transmission, and the need to wait for the result of the uplink data to decide the next action, the downlink bandwidth can be fully utilized to improve efficiency. The test interface transmits the database after encoding, compression and encryption, and the format is unified. For the interface, it processes the data in a unified format, and no additional overhead is required, which is more efficient.
[0067] Furthermore, preferably, the test interface includes: USB, network port and / or PCIe port. That is to say, in this embodiment, a high-speed communication port such as USB, network port, PCIe port commonly used on a computer can be used as the test interface.
[0068] The N edge computing modules are communicatively connected to the N DUT arrays in a one-to-one correspondence. The N edge computing modules are used to send the test vectors contained in the test data to the N DUT arrays, receive the test response signals uploaded by the N DUT arrays, calculate the test results according to the test response signals, and upload the test results to the test interface.
[0069] The N DUT arrays are used to test the corresponding DUT according to the test vector and upload the test response signal to the N edge computing modules.
[0070] In a preferred embodiment of this embodiment, Figure 1 As shown, the test interface is respectively communicated with each of the N edge computing modules, and the N edge computing modules are independent of each other and there is no connection channel between them, thereby forming a star topology.
[0071] When the parallelism requirement for test data transmission is not high, the universal distributed test system adopts the star topology.
[0072] In another preferred embodiment of this embodiment, Figure 2 As shown, the test interface is only connected to any one of the N edge computing modules, and the N edge computing modules are connected to each other, thereby forming a chain topology. When the parallelism requirement for test data transmission is high, the universal distributed test system adopts the chain topology.
[0073] It should be noted that the degree of parallelism here refers to the maximum number of instructions or data executed in parallel, and a low degree of parallelism requirement means that the maximum number of instructions or data executed in parallel is small, and a high degree of parallelism requirement means that the maximum number of instructions or data executed in parallel is large. That is to say, when N is a small integer, the star topology structure is preferably used; when N is a large integer, the chain topology structure is preferably used.
[0074] The universal distributed test system of this embodiment can adopt two transmission connection methods: star topology and chain topology. When the parallelism requirement is not high, the star topology can be adopted, and each parallel module is relatively independent and does not interfere with each other; when the parallelism requirement is high, the chain topology can be adopted, and the parallel modules can be expanded arbitrarily without affecting the connection method of the test interface.
[0075] In this embodiment, by setting up an edge computing module, the test stimulus, sampling, and judgment functions are decentralized to the edge side. Through the processing power of the coprocessor (which can be a computing chip such as MCU, FPGA, DSP, etc.), a hierarchical mechanism is adopted to pre-determine the test results of the DUT, and then summarize the overall test results and feed them back to the test host.
[0076] Specifically, if Figure 4 As shown, the edge computing module includes the following submodules: data receiving module, data decoding module, data storage module, excitation module, sampling module, logic decision module, result storage module, data coordination module, selection module and data sending module;
[0077] The data receiving module is used to receive test data from the test interface or an adjacent edge computing module;
[0078] The data decoding module is used to decode the test data corresponding to the edge computing module in the test data received by the data receiving module to obtain the test vector;
[0079] The data storage module is used to store the test vector decoded by the data decoding module;
[0080] The stimulus module is used to send the stimulus signal contained in the test vector stored in the data storage module to the DUT array corresponding to the edge computing module;
[0081] The sampling module is used to sample the test response signal uploaded by the DUT array;
[0082] The logic judgment module is used to perform a logic comparison based on the expected signal contained in the test vector stored in the data storage module and the test response signal sampled by the sampling module to obtain a test result corresponding to the test response signal;
[0083] The result storage module is used to store the test results obtained by the logic decision module;
[0084] There is a data transparent transmission path between the data collaboration module and the data receiving module, which is used to send the test data received by the data receiving module that does not correspond to the current edge computing module to the data receiving module of the adjacent edge computing module, and receive the test results uploaded by the adjacent edge computing module;
[0085] The selection module is used to select the test result stored in the result storage module or the data collaboration module;
[0086] The data sending module is used to upload the test result selected by the selection module to the test interface or the data coordination module of the adjacent edge computing module.
[0087] The data coordination module is arranged to correspond to the chain topology of the universal distributed test system.
[0088] By setting up a distributed edge computing module, the test stimulus, sampling, and judgment functions are delegated to the edge computing module. The edge computing method reduces the requirements of the entire system and achieves high-concurrency testing at a low cost.
[0089] In summary, compared with the prior art, the universal distributed test system of the present application has the following advantages:
[0090] (1) The logic test vectors are extracted from the test platform and packaged into a dynamically mountable and real-time transmission test database in a designed compression format through interface definition. This eliminates the need for the use of LVM in traditional ATE test machines and breaks through the limitation of vector depth.
[0091] (2) Through the decoupling design of key processes, an innovative distributed architecture is proposed. By implementing functions such as data decompression, providing incentives, response sampling, and logical comparison in the edge computing module, an automated testing system is realized by finally transmitting the test results back. The test system is easy to expand and can achieve high-concurrency testing.
[0092] (3) The test interface uses asymmetric transmission and distributed edge computing modules to complete the underlying operations, reducing the requirements of the entire system and achieving high-concurrency testing at low cost.
[0093] (4) During the test process, the test database is transmitted in real-time data compression, with no limit on the depth of logical test vectors, which simplifies the test process, replaces the investment in high-end test equipment, and reduces test costs.
[0094] (5) The universal distributed test system is modular in design with standardized interface definitions, making it easy to switch interfaces according to different chip types under test and highly reusable.
[0095] (6) This universal distributed test system is a universal test platform that adopts an expandable star or chain topology structure, is suitable for a variety of test scenarios, has good scalability, modular platform design, and high reuse rate.
[0096] (7) This universal distributed test system has no restrictions on hardware implementation. It can be used with commonly used production sorting machines such as Pick&Place robots, turret robots, SLT robots, etc., and can also be used as a laboratory R&D test platform.
[0097] It should be noted that the modules mentioned in the various device implementations of the present invention are all logical modules. Physically, a logical module can be a physical module, or a part of a physical module, or can be implemented as a combination of multiple physical modules. The physical implementation of these logical modules themselves is not the most important. The combination of functions implemented by these logical modules is the key to solving the technical problems proposed by the present invention. In addition, in order to highlight the innovative part of the present invention, the above-mentioned device implementations of the present invention do not introduce modules that are not closely related to solving the technical problems proposed by the present invention, which does not mean that there are no other modules in the above-mentioned device implementations.
[0098] It should be noted that in the claims and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.
[0099] This specification includes combinations of the various embodiments described herein. Individual references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") are not mutually exclusive unless indicated as mutually exclusive or it is clear to a person skilled in the art that they are mutually exclusive. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.
[0100] While the present invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
Claims
1. A universal distributed testing system, characterized in that: include: A test computer, N edge computing modules, and N DUT arrays, where N is an integer greater than or equal to 2; The test computer is used to store a test database and provide a test interface, the test interface is communicatively connected with the N edge computing modules, and the test interface is used to send the test data in the test database to the N edge computing modules and collect the test results uploaded by the N edge computing modules; The N edge computing modules are communicatively connected to the N DUT arrays in a one-to-one correspondence, and the N edge computing modules are used to send the test vectors contained in the test data to the N DUT arrays, receive the test response signals uploaded by the N DUT arrays, calculate the test results according to the test response signals, and upload the test results to the test interface; The N DUT arrays are used to test the corresponding DUT according to the test vector and upload the test response signal to the N edge computing modules.
2. The universal distributed test system according to claim 1, characterized in that: The test interface is respectively communicatively connected with each of the N edge computing modules, and the N edge computing modules are independent of each other and have no connection channels with each other, thereby forming a star topology.
3. The universal distributed test system according to claim 2, characterized in that: When the parallelism requirement for test data transmission is not high, the universal distributed test system adopts the star topology.
4. The universal distributed test system according to claim 1, characterized in that: The test interface is only communicatively connected to any one of the N edge computing modules, and the N edge computing modules are communicatively connected to each other, thereby forming a chain topology structure.
5. The universal distributed test system according to claim 4, characterized in that: When the parallelism requirement for test data transmission is high, the universal distributed test system adopts the chain topology.
6. The universal distributed test system according to claim 1, characterized in that: The edge computing module includes the following submodules: data receiving module, data decoding module, data storage module, excitation module, sampling module, logic decision module, result storage module, data coordination module, selection module and data sending module; The data receiving module is used to receive test data from the test interface or an adjacent edge computing module; The data decoding module is used to decode the test data corresponding to the edge computing module in the test data received by the data receiving module to obtain the test vector; The data storage module is used to store the test vector decoded by the data decoding module; The stimulus module is used to send the stimulus signal contained in the test vector stored in the data storage module to the DUT array corresponding to the edge computing module; The sampling module is used to sample the test response signal uploaded by the DUT array; The logic judgment module is used to perform a logic comparison based on the expected signal contained in the test vector stored in the data storage module and the test response signal sampled by the sampling module to obtain a test result corresponding to the test response signal; The result storage module is used to store the test results obtained by the logic decision module; There is a data transparent transmission path between the data collaboration module and the data receiving module, which is used to send the test data received by the data receiving module that does not correspond to the current edge computing module to the data receiving module of the adjacent edge computing module, and receive the test results uploaded by the adjacent edge computing module; The selection module is used to select the test result stored in the result storage module or the data collaboration module; The data sending module is used to upload the test result selected by the selection module to the test interface or the data coordination module of the adjacent edge computing module.
7. The universal distributed test system according to claim 1, characterized in that: An asymmetric transmission method is adopted between the test interface and the N edge computing modules, and the test data sent by the test interface to the N edge computing modules is transmitted preferentially.
8. The universal distributed test system according to claim 7, characterized in that: The test data sent by the test interface to the N edge computing modules is transmitted in real time.
9. The universal distributed test system according to claim 1, characterized in that: The test interface includes: USB, network port and / or PCIe port.
10. The universal distributed test system according to any one of claims 1 to 9, characterized in that: The test database is formed by classifying and encoding the test vectors in a standard format and compressing and encrypting them.