Multi-core processor-oriented reconfigurable interconnection circuit, implementation method and chip

Abstract

The invention discloses a reconfigurable interconnection circuit for a multi-core processor, an implementation method and a chip, and belongs to the technical field of chips. The circuit comprises a multi-master and multi-slave routing arbitration structure and an interconnection component, a multi-core processor is connected with the multi-master and multi-slave routing arbitration structure, the multi-master and multi-slave routing arbitration structure is connected with an embedded FPGA through the interconnection component, and the multi-master and multi-slave routing arbitration structure is connected with the embedded FPGA through the interconnection component. The interconnection module is used for performing identification and routing arbitration on data transmission inside the multi-core processor or between the multi-core processor and the embedded FPGA, and allocating corresponding interconnection resources for the data transmission, and the interconnection resources are realized based on the interconnection module; the interconnection component is used for managing and transmitting communication between the interfaces connected with the interconnection component, and the interfaces are the interface on the multi-core processor side and / or the interface on the embedded FPGA side. Real-time, reliable and efficient interconnection between the multi-core processor and the embedded FPGA is achieved, the requirement for hardware resources can be lowered, and the size of a system-level chip is reduced.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and in particular relates to a reconfigurable interconnection circuit, implementation method and chip for a multi-core processor. Background Art

[0002] Single-core processors have performance bottlenecks when handling complex tasks, and multi-core processors have become a solution to improve computing power. Multi-core processors can achieve higher parallel processing capabilities and stronger computing performance by integrating multiple CPU cores. In the system-on-chip (SoC) design, multi-core processors can be closely integrated with embedded field programmable gate arrays (FPGAs) to form a heterogeneous computing platform, in which multi-core processors are responsible for performing general computing tasks, while embedded FPGAs can be used for specific hardware acceleration tasks. The two work together to improve system performance and efficiency. How to achieve communication and interconnection between multi-core processors and embedded FPGAs is a problem that needs to be solved. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the related art. To this end, the present application proposes a reconfigurable interconnection circuit, implementation method and chip for a multi-core processor, which dynamically allocates interconnection resources through routing arbitration to form a reconfigurable interconnection circuit, realizes real-time, reliable and efficient interconnection between the multi-core processor and the embedded FPGA, can reduce the demand for hardware resources, and reduce the size of the system-level chip.

[0004] In a first aspect, the present application provides a reconfigurable interconnect circuit for a multi-core processor, the circuit comprising:

[0005] A multi-master multi-slave routing arbitration structure and an interconnection component, wherein the multi-core processor is connected to the multi-master multi-slave routing arbitration structure, and the multi-master multi-slave routing arbitration structure is connected to the embedded FPGA through the interconnection component.

[0006] The multi-master and multi-slave routing arbitration structure is used to identify and route data transmission within the multi-core processor or between the multi-core processor and the embedded FPGA, and allocate corresponding interconnection resources for the data transmission, and the interconnection resources are implemented based on the interconnection components;

[0007] The interconnection component is used to manage and transfer communications between interfaces connected to the interconnection component, wherein the interface is an interface on the multi-core processor side and / or an interface on the embedded FPGA side;

[0008] The multi-master and multi-slave routing arbitration structure or the interconnection component adopts an island-type interconnection architecture, and the interconnection resources under the island-type interconnection architecture include global interconnection resources and local interconnection resources;

[0009] The global interconnection resources include interconnection channels and switch boxes, and the local interconnection resources include connection boxes, wherein:

[0010] The interconnection channel is composed of a preset number of interconnection line segments and is used to realize signal transmission between logic function blocks;

[0011] The switch box includes a preset number of programmable switches for implementing jumps between different interconnected line segments;

[0012] The connection box comprises an input connection module and an output connection module, which are used to realize signal transmission between the logic function block and the interconnection channel.

[0013] In the above technical scheme, the reconfigurable interconnection circuit for multi-core processors includes a multi-master and multi-slave routing arbitration structure and an interconnection component. The multi-master and multi-slave routing arbitration structure is used to identify and arbitrate data transmission inside or outside the multi-core processor and between the processor and the embedded FPGA, and allocate interconnection resources based on the interconnection component. The interconnection component manages and transmits the communication between the multi-core processor and the embedded FPGA interface. The interconnection resources are dynamically allocated through routing arbitration to form a reconfigurable interconnection circuit, which realizes real-time, reliable and efficient interconnection between the multi-core processor and the embedded FPGA, and can reduce the demand for hardware resources and reduce the size of the system-level chip. The multi-master and multi-slave routing arbitration structure or interconnection component is an island-type interconnection architecture, and divides the interconnection resources into global interconnection resources and local interconnection resources. The global interconnection resources include interconnection channels and switch boxes, which are used to transmit signals between logic function blocks, and control the direction and path of signal transmission through programmable switches in the switch box. Local interconnection resources include connection boxes, which realize signal transmission between logic function blocks and interconnection channels. Through the connection and expansion of logic function blocks, a complete interconnection circuit function is formed to meet the user's interconnection needs. Through the isolated interconnection architecture, the multi-master and multi-slave routing arbitration structure and interconnection components can expand more processors or peripherals to adapt to different communication needs. Different types of interconnection channels and switch boxes help to more effectively utilize hardware resources and reduce the size of reconfigurable interconnection circuits for multi-core processors, thereby reducing the size of system-level chips.

[0014] According to an embodiment of the present application, the types of interconnect components include slave interconnect components, host interconnect components, storage interconnect components, system application interconnect components and control interconnect components, wherein:

[0015] The slave interconnection component is used to realize the interconnection between at least one processor in the multi-core processor and the embedded FPGA, wherein the at least one processor serves as a slave and the embedded FPGA serves as a host;

[0016] The host interconnection component is used to realize the interconnection between at least one processor in the multi-core processor and the embedded FPGA, wherein the at least one processor serves as a host and the embedded FPGA serves as a slave;

[0017] The storage interconnection component is used to realize the interconnection of storage resources;

[0018] The system application interconnection component is used to realize the interconnection of system-level applications;

[0019] The control interconnection component is used to realize the transmission of control signals.

[0020] In the above technical solution, the interconnection components include slave interconnection components, host interconnection components, storage interconnection components, system application interconnection components and control interconnection components. Different types of interconnection components cooperate with each other to realize data transmission and control signal transmission between the multi-core processor and the embedded FPGA or between other resources. The processor in the multi-core processor and the instantiated programmable logic device in the embedded FPGA can be configured as a host or a slave to improve data transmission efficiency. Different types of interconnection components can adapt to different communication requirements. By dynamically allocating interconnection resources, the demand for hardware resources can be effectively reduced, and the volume of the reconfigurable interconnection circuit can be reduced, thereby reducing the volume of the system-level chip.

[0021] According to one embodiment of the present application, the embedded FPGA as a host includes at least one programmable logic device instantiated by the embedded FPGA as a host.

[0022] In the above technical solution, the embedded FPGA instantiates at least one programmable logic device as a host. The FPGA as a host can communicate and exchange data with other parts of the system-level chip, thereby improving the data processing capability and response speed of the embedded FPGA.

[0023] According to an embodiment of the present application, the embedded FPGA as a slave includes at least one programmable logic device instantiated by the embedded FPGA as a slave.

[0024] In the above technical solution, the embedded FPGA instantiates at least one programmable logic device as a slave, which can respond to requests from a multi-core processor or other host. The embedded FPGA as a slave can execute specific tasks or requests initiated by the host, so that the host can effectively use the embedded FPGA.

[0025] According to one embodiment of the present application, the host interconnection component is also used to realize the interconnection between processors in the multi-core processor, at least one processor serves as a host and at least another processor serves as a slave.

[0026] In the above technical solution, the host interconnection component supports communication within the multi-core processor, allowing different processors to communicate without going through other external devices, thereby improving the communication efficiency between processors and improving the data processing capability of the multi-core processor.

[0027] According to one embodiment of the present application, the host interconnection component is also used to realize the interconnection between at least one processor in the multi-core processor and the embedded FPGA and at least another processor, wherein at least one processor in the multi-core processor serves as a host, and at least one programmable logic device instantiated by the embedded FPGA and the at least another processor serve as slaves.

[0028] In the above technical solution, the host interconnection component can be used to realize the interconnection between the host and the slave inside the multi-core processor, and can also be used to use at least one programmable logic device instantiated by the embedded FPGA as a slave, that is, the host interconnection component can manage the communication inside the multi-core processor and the communication between the multi-core processor and external devices (such as embedded FPGA), so that the multi-core processor can use the embedded FPGA more effectively and realize closer collaboration between processors inside the multi-core processor.

[0029] According to an embodiment of the present application, the type of the interface includes: at least one of an AMBA general interface, an AMBA high-performance interface, an AMBA_ACP interface and a CTRL_IO_SIG interface.

[0030] In the above technical solution, the multiple interface types used in the reconfigurable interconnection circuit for multi-core processors include at least one of the AMBA general interface, the AMBA high-performance interface, the AMBA_ACP interface and the CTRL_IO_SIG interface. The AMBA general interface supports the communication between the multi-core processor and the embedded FPGA in the role of the host or the slave, while the AMBA high-performance interface improves the data transmission rate through the FIFO buffer, the ACP interface realizes cache consistency and can be used to optimize the memory access of the accelerator, and the CTRL_IO_SIG interface is used to transmit control signals. Through the configuration of different interfaces, the interface is dynamically selected according to the communication requirements, and the efficiency of data transmission is improved. The design of multiple interface types and interconnection components enables the reconfigurable interconnection circuit for multi-core processors to adapt to different communication requirements, effectively reducing the demand for hardware resources, reducing the volume of the reconfigurable interconnection circuit for multi-core processors, and thus reducing the volume of the system-level chip.

[0031] According to an embodiment of the present application, all interfaces except the acceleration consistency interface on the multi-core processor side are connected to the multi-master and multi-slave routing arbitration structure, and then connected to the embedded FPGA through the interconnection component.

[0032] In the above technical solution, all interfaces except the acceleration consistency interface on the multi-core processor side are connected to the multi-master and multi-slave routing arbitration structure, and then connected to the embedded FPGA through the interconnection component. The interconnection resources are dynamically allocated through routing arbitration to form a reconfigurable interconnection circuit, thereby realizing the interconnection between the multi-core processor and the embedded FPGA, which can reduce the demand for hardware resources and reduce the size of the system-level chip. The acceleration consistency interface is not connected to the multi-master and multi-slave routing arbitration structure, avoiding possible additional competition and waiting time, and improving the data transmission efficiency between the multi-core processor and the embedded FPGA.

[0033] According to one embodiment of the present application, the acceleration consistency interface on the multi-core processor side is directly connected to the system application interconnection component in the interconnection component, and the system application interconnection component is a consistency control unit in the acceleration processor.

[0034] In the above technical solution, the acceleration consistency interface on the multi-core processor side is directly connected to the system application interconnection component in the interconnection component. This component is a consistency control unit inside the acceleration processor, which can simplify the data transmission path and improve the data transmission efficiency between the multi-core processor and the embedded FPGA.

[0035] According to one embodiment of the present application, the interface on the embedded FPGA side includes: at least one of a host AMBA general interface, a slave AMBA general interface, a host AMBA high-performance interface, a slave AMBA_ACP interface, and a CTRL_IO_SIG interface;

[0036] The slave interconnection component is connected to the host AMBA universal interface, the host interconnection component is connected to the slave AMBA universal interface, the storage interconnection component is connected to the host AMBA high-performance interface, the system application interconnection component is connected to the slave AMBA_ACP interface, and the control interconnection component is connected to the CTRL_IO_SIG interface.

[0037] In the above technical scheme, the slave interconnection component is connected to the host AMBA universal interface, the host interconnection component is connected to the slave AMBA universal interface, the storage interconnection component is connected to the host AMBA high-performance interface, the system application interconnection component is connected to the slave AMBA_ACP interface, and the control interconnection component is connected to the CTRL_IO_SIG interface. This explains the interface configuration on the embedded FPGA side and its connection method with different interconnection components, realizes communication and data transmission between multi-core processors and embedded FPGAs, and can meet the data transmission requirements in different application scenarios.

[0038] According to one embodiment of the present application, the allocation of corresponding interconnection resources for the data transmission includes: determining the connection relationship of the interconnection segments in the interconnection component and the jump relationship between the interconnection segments according to the number of interfaces, interface types, and circuit application requirements of the multi-master and multi-slave routing arbitration structure, and generating a reconfigurable configuration file, wherein the reconfigurable configuration file is used to realize the configuration of turning on or off the programmable switch in the switch box and the input connection module and the output connection module in the connection box.

[0039] In the above technical scheme, according to the number of interfaces, interface types and circuit application requirements of the multi-master and multi-slave routing arbitration structure, the connection relationship of the interconnection segments in the interconnection component and the jump relationship between the interconnection segments are determined, a reconfigurable configuration file is generated, and corresponding interconnection resources are allocated for data transmission according to the reconfigurable configuration file, so that the reconfigurable interconnection circuit for multi-core processors can adapt to different data transmission requirements, thereby improving the flexibility of the reconfigurable interconnection circuit for multi-core processors.

[0040] According to an embodiment of the present application, the local interconnection resource further includes: an input cross-interconnection module, the input cross-interconnection module is used to realize signal interconnection between logic units and connect the input pins of the logic function block to each logic unit;

[0041] Among them, a plurality of the logic units constitute the logic function block.

[0042] In the above technical solution, the local interconnection resources also include an input cross-interconnection module, which can be used to realize signal interconnection between logic units and connect the input pins of the logic function block to each logic unit, and further can be used to realize the interconnection between the multi-core processor and the embedded FPGA.

[0043] According to an embodiment of the present application, the horizontal channel and the vertical channel of the programmable interconnect on the embedded FPGA side provide the global interconnection resource, and the global interconnection resource performs signal interaction with the interconnection bus on the multi-core processor side through the local interconnection resource;

[0044] The signal output of the multi-core processor side is sent to the interconnection component through the local interconnection resource and processed by the corresponding logic unit, or the signal output of the multi-core processor side is sent to the adjacent logic unit through the horizontal channel for processing.

[0045] In the above technical solution, the horizontal channels and vertical channels of the programmable interconnection on the embedded FPGA side provide global interconnection resources. The global interconnection resources exchange signals with the interconnection bus on the multi-core processor side through local interconnection resources. The signal output on the multi-core processor side is sent to the interconnection component through the local interconnection resources and processed by the corresponding logic unit, or sent to the adjacent logic unit through the horizontal channel for processing. The interconnection between the multi-core processor and the embedded FPGA is realized through the global interconnection resources and the local interconnection resources, thereby improving the flexibility of the reconfigurable interconnection circuit for the multi-core processor.

[0046] According to one embodiment of the present application, the types of the interconnection segments include long interconnection segments, short interconnection segments, local interconnection segments and direct connection segments. The long interconnection segments are used to meet the signal path requirements between logic function blocks that are far apart, the short interconnection segments are used to achieve interconnection between adjacent logic function blocks, and the local interconnection segments are used to achieve signal sharing and feedback between logic units within each logic function block; the direct connection segments are used for signal transmission between adjacent logic function blocks.

[0047] In the above technical solution, the design of the interconnection segment adopts a multi-level combined interconnection system, including long interconnection segments, short interconnection segments, local interconnection segments and direct connection segments, so as to meet the interconnection requirements of different distances and different complexities, adapt to the layout and signal transmission of different logical function blocks in the multi-master and multi-slave routing arbitration structure and interconnection components, and improve the flexibility of the reconfigurable interconnection circuit for multi-core processors.

[0048] According to one embodiment of the present application, the interconnection channel is a unidirectional channel or a bidirectional channel.

[0049] In the above technical solution, the interconnection channel is a unidirectional channel or a bidirectional channel. By selecting different interconnection channels to adapt to various signal transmission requirements, the data transmission efficiency of the reconfigurable interconnection circuit for multi-core processors is improved.

[0050] According to an embodiment of the present application, the switch box is implemented by combining a bidirectional interconnection switch with a unidirectional interconnection switch.

[0051] In the above technical solution, the switch box is implemented by combining a bidirectional interconnection switch with a unidirectional interconnection switch. By selecting different interconnection switches to adapt to various signal transmission requirements, the data transmission efficiency of the reconfigurable interconnection circuit for multi-core processors is improved.

[0052] According to an embodiment of the present application, the topology type of the programmable switches in the switch box includes at least one of subset interconnection, global interconnection and vertical interconnection.

[0053] In the above technical solution, the topological structure type of the programmable switch in the switch box includes at least one of subset interconnection, global interconnection and vertical interconnection. By reasonably selecting and applying the topological structure type of the programmable switch in the switch box, the flexibility and scalability of the reconfigurable interconnection circuit for multi-core processors can be improved.

[0054] According to one embodiment of the present application, the parameters of the multi-master and multi-slave routing arbitration structure or interconnection component include: the number of routing wires that can be connected to the input or output of each logical function block, the number of other routing wires that each routing wire can be connected to, the length of the routing segment, the mode of the routing switch, the electrical design of the wires and programmable switches, and the number of routing segments for each channel.

[0055] In the above technical solution, the parameters of the multi-master and multi-slave routing arbitration structure or interconnection component include the number of routing wires that can be connected to the input or output of each logical function block, the number of other routing wires that each routing wire can be connected to, the length of the routing segment, the mode of the routing switch, the electrical design of the routing wires and the programmable switches, and the number of routing segments of each channel. These parameters jointly determine the configuration method of the data transmission path of the reconfigurable interconnection circuit for multi-core processors, so as to realize the ability to dynamically adjust the routing path according to different data transmission requirements, adapt to different application scenarios, and help to make more efficient use of hardware resources.

[0056] According to an embodiment of the present application, the programmable switch is implemented using a multiplexer and a tri-state buffer.

[0057] In the above technical solution, the programmable switch is implemented using a multiplexer and a three-state buffer, which improves the flexibility and controllability of the programmable switch and can be dynamically adjusted according to real-time data transmission requirements and routing decisions, thereby improving the flexibility of reconfigurable interconnect circuits for multi-core processors.

[0058] According to an embodiment of the present application, the multi-master and multi-slave routing arbitration structure includes an AMBA bus matrix, and the AMBA bus matrix is ​​used to connect all AMBA bus interfaces of the multi-core processor.

[0059] In the above technical solution, the multi-master and multi-slave routing arbitration structure includes an AMBA bus matrix for connecting all AMBA bus interfaces of the multi-core processor. By centrally connecting all AMBA bus interfaces of the multi-core processor, the efficiency of data transmission is improved, the use of hardware resources is optimized, and the flexibility of the reconfigurable interconnection circuit for the multi-core processor is improved.

[0060] In a second aspect, the present application provides a method for implementing a reconfigurable interconnect circuit for a multi-core processor, the method comprising:

[0061] Generate the code of the reconfigurable interconnection circuit for the multi-core processor according to the interconnection requirements, the interconnection parameters on the multi-core processor side, and the interconnection parameters on the embedded FPGA side;

[0062] Generate an FPGA configuration file according to the code;

[0063] The FPGA configuration file is downloaded to the embedded FPGA to form the reconfigurable interconnection circuit for the multi-core processor.

[0064] In the above technical scheme, according to the interconnection requirements, the interconnection parameters on the multi-core processor side and the interconnection parameters on the embedded FPGA side, the code of the reconfigurable interconnection circuit for the multi-core processor is generated, and the code is converted into an FPGA configuration file, and the FPGA configuration file is downloaded to the embedded FPGA, thereby realizing the reconfigurable interconnection circuit for the multi-core processor, improving the flexibility of realizing the reconfigurable interconnection circuit for the multi-core processor, and the realized reconfigurable interconnection circuit for the multi-core processor can meet different interconnection requirements, thereby enhancing the scalability and adaptability of the reconfigurable interconnection circuit for the multi-core processor.

[0065] According to one embodiment of the present application, the interconnection parameters on the multi-core processor side include at least one of the following: the number of CPU cores, the data bit width of each CPU, the number of CPU masters and slaves, the access address space of each CPU, the CPU interface type, the number of interfaces of the multi-master and multi-slave routing arbitration structure, and the interface type of the multi-master and multi-slave routing arbitration structure;

[0066] The interconnection parameters on the embedded FPGA side include at least one of the following: the number of embedded FPGA masters and slaves, the type of AMBA bus interface, the number of interconnection component signals, the type of interconnection components, and the number of each type of interconnection components.

[0067] In the above technical scheme, according to the interconnection requirements, at least one of the number of CPU cores, the data bit width of each CPU, the number of CPU masters and slaves, the access address space of each CPU, the CPU interface type, the number of interfaces of the multi-master and multi-slave routing arbitration structure and the interface type of the multi-master and multi-slave routing arbitration structure, and at least one of the number of masters and slaves of the embedded FPGA, the AMBA bus interface type, the number of interconnection component signals, the interconnection component type, and the number of each interconnection component type, the code of the reconfigurable interconnection circuit for the multi-core processor is generated, which improves the flexibility of realizing the reconfigurable interconnection circuit for the multi-core processor. The realized reconfigurable interconnection circuit for the multi-core processor can meet different interconnection requirements, and enhances the scalability and adaptability of the reconfigurable interconnection circuit for the multi-core processor.

[0068] According to an embodiment of the present application, the code for generating the reconfigurable interconnection circuit for the multi-core processor according to the interconnection requirements, the interconnection parameters on the multi-core processor side, and the interconnection parameters on the embedded FPGA side includes:

[0069] Determine the data transmission within the multi-core processor or between the multi-core processor and the embedded FPGA according to the interconnection requirements;

[0070] According to the interconnection parameters on the multi-core processor side and the interconnection parameters on the embedded FPGA side, a code of the reconfigurable interconnection circuit for the multi-core processor is generated for the data transmission.

[0071] In the above technical scheme, according to the interconnection requirements, the data transmission inside the multi-core processor or between the multi-core processor and the embedded FPGA is determined, and according to the interconnection parameters on the multi-core processor side and the interconnection parameters on the embedded FPGA side, the code of the reconfigurable interconnection circuit for the multi-core processor is generated for the data transmission, and for the data transmission inside the multi-core processor or between the multi-core processor and the embedded FPGA, the corresponding reconfigurable interconnection circuit for the multi-core processor is implemented, thereby enhancing the scalability and adaptability of the reconfigurable interconnection circuit for the multi-core processor.

[0072] In a third aspect, the present application provides a chip, which includes a multi-core processor and an embedded FPGA, and also includes a reconfigurable interconnect circuit for the multi-core processor as described in the first aspect above.

[0073] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0075] Figure 1 It is a schematic diagram of the structure of a reconfigurable interconnection circuit for a multi-core processor provided in some embodiments of the present application;

[0076] Figure 2 is a schematic diagram of interconnection resources under an island-type interconnection architecture provided in some embodiments of the present application;

[0077] Figure 3 is a schematic diagram of a switch box provided in some embodiments of the present application;

[0078] Figure 4 is a schematic diagram of a connection box provided in some embodiments of the present application;

[0079] Figure 5 is a schematic diagram of configuring interconnected resources provided by some embodiments of the present application;

[0080] Figure 6 is a schematic diagram of the structure of the interconnection channel provided in some embodiments of the present application;

[0081] Figure 7 is a schematic diagram of a programmable switch topology structure provided by some embodiments of the present application;

[0082] Figure 8 is a schematic diagram of the structure of a bidirectional interconnection switch provided in some embodiments of the present application;

[0083] Fig. 9 is a schematic diagram of the structure of a unidirectional interconnection switch provided in some embodiments of the present application;

[0084] Fig.10 It is a schematic diagram of a multi-master and multi-slave routing arbitration structure or interconnection component provided by some embodiments of the present application;

[0085] Fig.11 is a schematic diagram of a programmable switch structure provided by some embodiments of the present application;

[0086] Fig.12 is a schematic diagram of a multiplexer provided in some embodiments of the present application;

[0087] Fig.13 is a schematic diagram of an AMBA bus matrix provided in some embodiments of the present application;

[0088] Fig.14 It is a flowchart of a method for implementing a reconfigurable interconnect circuit for a multi-core processor provided in some embodiments of the present application.

[0089] Description of reference numerals:

[0090] 10: Reconfigurable interconnect circuits for multi-core processors;

[0091] 101: multi-master and multi-slave routing arbitration structure; 1011: AMBA bus matrix;

[0092] 102: interconnection component; 1021: slave interconnection component; 1022: host interconnection component;

[0093] 1023: storage interconnection component; 1024: system application interconnection component; 1025: control interconnection component. DETAILED DESCRIPTION

[0094] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0095] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0096] As computing demands grow, the performance bottleneck of single-core processors in handling complex tasks has prompted multi-core processors to become a key technology to improve computing capabilities. Multi-core processors can achieve higher parallel processing capabilities and stronger computing performance by integrating multiple CPU cores. However, the performance of multi-core processors depends not only on the processing power of the cores, but also on the efficiency of inter-core communication, which directly affects data transmission speed, system latency, and overall system performance.

[0097] In a multi-core processor, inter-core communication usually adopts two modes: pipeline operation and shared memory. In pipeline operation mode, data is transferred between different cores through private cache areas. For example, after CPU0 processes the data, it passes the data to CPU1, and then CPU1 passes it to CPU2, and so on. Although this method can achieve continuous processing of tasks, data transmission across core caches will bring long delays. On the other hand, although inter-core data transmission based on shared memory can be realized, the clock cycles consumed by accessing shared memory are far more than accessing private caches, resulting in performance limitations.

[0098] In the design of System on Chip (SoC), multi-core processors can be tightly integrated with embedded Field Programmable Gate Arrays (FPGA) to form a heterogeneous computing platform, in which the multi-core processor is responsible for performing general computing tasks, while the embedded FPGA can be used for specific hardware acceleration tasks. The two working together can improve system performance and efficiency. The embedded FPGA can also be called eFPGA. How to achieve communication and interconnection between the multi-core processor and eFPGA is a problem that needs to be solved.

[0099] In conjunction with the accompanying drawings, the reconfigurable interconnect circuit, implementation method and chip for a multi-core processor provided in the embodiments of the present application are described in detail through specific embodiments and their application scenarios.

[0100] Figure 1 Schematic diagram of a reconfigurable interconnect circuit for a multi-core processor provided in some embodiments of the present application. Figure 1 As shown, the reconfigurable interconnection circuit 10 for multi-core processors includes: a multi-master multi-slave routing arbitration structure 101 and an interconnection component 102, the multi-core processor is connected to the multi-master multi-slave routing arbitration structure 101, and the multi-master multi-slave routing arbitration structure 101 is connected to the embedded FPGA through the interconnection component 102.

[0101] The multi-master and multi-slave routing arbitration structure 101 is used to identify and route data transmission within the multi-core processor or between the multi-core processor and the embedded FPGA, and allocate corresponding interconnection resources for the data transmission, and the interconnection resources are implemented based on the interconnection component 102;

[0102] The interconnection component 102 is used to manage and transfer the communication between the interfaces connected to the interconnection component, and the interface is the interface on the multi-core processor side and / or the interface on the embedded FPGA side;

[0103] The multi-master and multi-slave routing arbitration structure or the interconnection component adopts an island-type interconnection architecture, and the interconnection resources under the island-type interconnection architecture include global interconnection resources and local interconnection resources;

[0104] The global interconnection resources include interconnection channels and switch boxes, and the local interconnection resources include connection boxes, wherein:

[0105] The interconnection channel is composed of a preset number of interconnection line segments and is used to realize signal transmission between logic function blocks;

[0106] The switch box includes a preset number of programmable switches for implementing jumps between different interconnected line segments;

[0107] The connection box includes an input connection module and an output connection module, which are used to realize signal transmission between the logic function block and the interconnection channel;

[0108] The complete interconnected circuit function required by the user is formed by connecting and expanding the functions realized by multiple logic function blocks.

[0109] It can be understood that the multi-master and multi-slave routing arbitration structure 101 allows multiple master devices (such as multiple processors) and multiple slave devices (such as embedded FPGAs or other devices) to transmit data, and identifies, arbitrates and makes routing decisions on these data transmission requests, so that data can be transmitted between devices through the correct path, and interconnection resources based on interconnection components are allocated for data transmission.

[0110] The interconnection component 102 connects the multi-master and multi-slave routing arbitration structure 101 and the embedded FPGA, and is used to manage and transfer the communication between the interfaces to which the interconnection component is connected.

[0111] Optionally, the communication between the interfaces may be the communication between the interface on the multi-core processor side and the interface on the embedded FPGA side, or the communication between the interfaces on the multi-core processor side, or the communication between the interfaces on the embedded FPGA side.

[0112] The interconnection component 102 realizes the interconnection resources allocated by the multi-master and multi-slave routing arbitration structure 101 by managing and transmitting the communication between the interfaces to which it is connected, that is, it realizes the connection relationship between different interfaces and interconnection segments and the jump relationship between interconnection segments, which can meet different computing needs and application scenarios.

[0113] The multi-master and multi-slave routing arbitration structure 101 identifies, arbitrates and makes routing decisions for data transmission. The interconnection component 102 manages and transmits the communication between the interfaces connected to the interconnection component based on the routing decision of the multi-master and multi-slave routing arbitration structure 101, and realizes the corresponding interconnection resources. The multi-master and multi-slave routing arbitration structure 101 and the interconnection component 102 are combined to form a reconfigurable interconnection circuit to realize real-time, reliable and efficient interconnection between multi-core processors and embedded FPGAs.

[0114] It should be noted that the multi-master and multi-slave routing arbitration structure 101 identifies and arbitrates data transmission based on the address space, that is, when a data transmission request occurs, the multi-master and multi-slave routing arbitration structure determines the data transmission address based on the target address or source address of the transmission request, and further determines the routing path and allocates corresponding interconnection resources, thereby realizing real-time, reliable and efficient interconnection between the multi-core processor and the embedded FPGA.

[0115] like Figure 1As shown, in the system-level chip, the multi-master and multi-slave routing arbitration structure 101 and the interconnection component 102 act as switches to achieve communication between the multi-core processor and the embedded FPGA.

[0116] Optionally, the interface communicates based on an Advanced Microcontroller Bus Architecture (AMBA) protocol and may be referred to as an AMBA interface.

[0117] AMBA protocols include Advanced High-performance Bus (AHB), Advanced Peripheral Bus (APB) and Advanced eXtensible Interface (AXI), which can be used to achieve connections between processors, memories and peripherals with different performance and power consumption requirements.

[0118] In a processor system (a multi-core processor constitutes a processor system), AMBA is used inside the APU to connect the processor core, the SCU, cache memory or OCM, and various interconnections within the FPGA. These connections complement the connections on the CPU-eFPGA boundary.

[0119] In some embodiments, the reconfigurable interconnection circuit for a multi-core processor may include multiple interconnection components 102 with different functions, a portion of the interconnection components 102 is directly connected to the embedded FPGA, and is used for data exchange between the central processing unit (CPU) in the multi-core processor and the embedded FPGA. The central processing unit may be referred to as a processor, and the multi-core processor includes at least one processor, while another portion of the interconnection components 102 is used for connection between CPUs or within the embedded FPGA. The connection between the interconnection components 102 may also be based on the AMBA protocol, so that data can be transmitted between the interconnection components, thereby enabling the SoC to achieve efficient data processing to meet various complex computing requirements.

[0120] Figure 2 Schematic diagram of interconnection resources under an island-type interconnection architecture provided by some embodiments of the present application. Figure 2As shown, the island-type multi-master and multi-slave routing arbitration structure includes interconnection channels, switch boxes, connection boxes, input cross-interconnection modules and logic function blocks (also called logic function modules, or logic clusters) composed of multiple logic units, and also includes IP function modules. IP function modules (Intellectual Property Core) refer to pre-designed and verified integrated circuit design modules with specific functions. Logic function blocks can also be expressed as configurable logic blocks (Configurable Logic Block, CLB). Multiple configurable logic blocks constitute programmable logic resources.

[0121] In the island-type interconnection architecture, the multi-master and multi-slave routing arbitration structure or interconnection components are divided into several independent functional units, namely "islands". The islands are divided into global interconnection resources and local interconnection resources to support signal transmission and logic control within the SoC.

[0122] Global interconnection resources include interconnection channels and switch boxes (SB). Interconnection channels use preset interconnection segments to achieve signal transmission between logic function blocks. Switch boxes include a preset number of programmable switches. Figure 3 Schematic diagram of a switch box provided in some embodiments of the present application. The switch box is used to implement jumps between different interconnection segments, perform path selection and jump control between different interconnection segments, and thus manage the direction and routing of signal transmission.

[0123] Among them, the interconnection channel is composed of a preset number of regular wiring units. Most of the signal transmission between logic function blocks is realized through these wiring units, including long interconnection segments and short interconnection segments. Among them, short interconnection segments are used to realize the interconnection between adjacent logic function blocks, and long interconnection segments are used to meet the signal path requirements between logic function blocks that are far apart. The number, direction, length, composition ratio and distribution of the interconnection channels affect the delay characteristics and signal quality of the circuit, and also directly determine the routing rate and resource utilization of the embedded FPGA.

[0124] The local interconnection resources include a connection box (CB), which includes an input connection module and an output connection module, and is used to realize signal transmission between logic function blocks and interconnection channels, and is also used to realize the connection between interconnection segments and programmable logic resources. Figure 4 is a schematic diagram of a connection box provided in some embodiments of the present application.

[0125] The interconnection segments in the chip layout are actually some horizontal or vertical metal wires. These metal wires are bidirectional, but since all the interconnection segments are connected through the interconnection switches in the SB, the direction of the switching circuit in the interconnection resource determines the direction of the interconnection segment.

[0126] In some embodiments, the local interconnection resource further includes: an input cross-interconnection module, the input cross-interconnection module is used to realize signal interconnection between logic units and connect the input pins of the logic function block to each logic unit;

[0127] Among them, a plurality of the logic units constitute the logic function block.

[0128] The input cross-connection module is used to realize signal interconnection between logic units and connect the input pins of the logic function block with the corresponding logic unit. Specifically, it may include the allocation and sharing of input pin connections, cascading between logic units, feedback of output signals, etc.

[0129] In the above technical scheme, the reconfigurable interconnection circuit for multi-core processors includes a multi-master and multi-slave routing arbitration structure and an interconnection component. The multi-master and multi-slave routing arbitration structure is used to identify and arbitrate data transmission inside or outside the multi-core processor and between the processor and the embedded FPGA, and allocate interconnection resources based on the interconnection component. The interconnection component manages and transmits the communication between the multi-core processor and the embedded FPGA interface. The interconnection resources are dynamically allocated through routing arbitration to form a reconfigurable interconnection circuit, which realizes real-time, reliable and efficient interconnection between the multi-core processor and the embedded FPGA, and can reduce the demand for hardware resources and reduce the size of the system-level chip. The multi-master and multi-slave routing arbitration structure or interconnection component is an island-type interconnection architecture, and divides the interconnection resources into global interconnection resources and local interconnection resources. The global interconnection resources include interconnection channels and switch boxes, which are used to transmit signals between logic function blocks, and control the direction and path of signal transmission through programmable switches in the switch box. Local interconnection resources include connection boxes, which realize signal transmission between logic function blocks and interconnection channels. By connecting and expanding the functions realized by logic function blocks, a complete application circuit function required by users can be formed to meet the user's interconnection needs. Through the isolated interconnection architecture, the multi-master and multi-slave routing arbitration structure and interconnection components can expand more processors or peripherals to adapt to different communication needs. Different types of interconnection channels and switch boxes help to more effectively utilize hardware resources and reduce the volume of reconfigurable interconnection circuits for multi-core processors, thereby reducing the volume of system-level chips.

[0130] In one embodiment of the present application, the types of the interconnection components 102 include a slave interconnection component 1021, a host interconnection component 1022, a storage interconnection component 1023, a system application interconnection component 1024 and a control interconnection component 1025, wherein:

[0131] The slave interconnection component 1021 is used to realize the interconnection between at least one processor in the multi-core processor and the embedded FPGA, wherein the at least one processor serves as a slave and the embedded FPGA serves as a host;

[0132] The host interconnection component 1022 is used to realize the interconnection between at least one processor in the multi-core processor and the embedded FPGA, wherein the at least one processor serves as a host and the embedded FPGA serves as a slave;

[0133] The storage interconnection component 1023 is used to realize the interconnection of storage resources;

[0134] The system application interconnection component 1024 is used to realize the interconnection of system-level applications;

[0135] The control interconnection component 1025 is used to realize the transmission of control signals.

[0136] like Figure 1 As shown, the slave interconnection component 1021 is used to realize the interconnection of at least one CPU in the multi-core processor as a slave and the eFPGA as a host, that is, through the slave interconnection component 1021, the CPU in the multi-core processor can respond to the request of the eFPGA and execute the corresponding task; the host interconnection component 1022 is used to realize the interconnection of at least one CPU in the multi-core processor as a host and the eFPGA as a slave, that is, through the host interconnection component 1022, the multi-core processor can control the eFPGA and send instructions and data to it; the storage interconnection component 1023 is used to realize the interconnection of storage resources, that is, to manage the access of the multi-core processor and the eFPGA to storage resources (such as memory, hard disk, etc.) to realize data access; the system application interconnection component 1024 is used to realize the interconnection of system-level applications, for example, it can be used for data exchange and communication between different applications; the control interconnection component 1025 is used to realize the transmission of control signals, manage the control signals (such as synchronization signals, interrupt signals, etc.) between the multi-core processor and the FPGA, so that the SoC can run stably.

[0137] Different types of interconnected components collaborate with each other to enable communication and data transmission between multi-core processors and embedded FPGAs or other resources to adapt to different computing needs and application scenarios.

[0138] In some embodiments, the embedded FPGA as a host includes at least one programmable logic device instantiated by the embedded FPGA as a host.

[0139] In some embodiments, the embedded FPGA as a slave includes at least one programmable logic device instantiated by the embedded FPGA as a slave.

[0140] eFPGA is an FPGA embedded in SoC. Instantiation refers to creating an instance of a specific hardware design, which can be a logic module, a processor core, or any other predefined hardware structure. Programmable logic devices are hardware components whose internal logic can be reconfigured after manufacturing. In embedded FPGAs, programmable logic devices are usually composed of programmable logic units (such as lookup tables, triggers, etc.) and programmable resources (such as switch boxes, wiring resources, etc.).

[0141] When the embedded FPGA acts as a host, the embedded FPGA instantiates at least one programmable logic device as a host, that is, the FPGA can actively initiate communication requests, control data transmission or logic processing, and the FPGA as a host can directly communicate and exchange data with other parts of the SoC.

[0142] When the embedded FPGA acts as a slave, the embedded FPGA instantiates at least one programmable logic device as a slave to respond to requests from the CPU or other hosts. The embedded FPGA as a slave can execute specific tasks or requests initiated by the host, so that the host can effectively utilize the embedded FPGA.

[0143] In some embodiments, the host interconnect component 1022 is also used to implement interconnection between processors in the multi-core processor, with at least one processor acting as a host and at least another processor acting as a slave.

[0144] It can be understood that the host interconnection component 1022 can be used to realize the interconnection of at least one processor in the multi-core processor as a host and the embedded FPGA as a slave, and can also be used to realize the interconnection of at least one processor inside the multi-core processor as a host and at least another processor as a slave, that is, the host interconnection component 1022 can support communication within the multi-core processor, allowing different CPUs to communicate without going through other external devices, thereby improving the communication efficiency within the multi-core processor, reducing communication delays, and improving the processing power of the SoC.

[0145] In some embodiments, the host interconnect component 1022 is also used to implement interconnection between at least one processor in the multi-core processor and the embedded FPGA and at least another processor, wherein at least one processor in the multi-core processor serves as a host, and at least one programmable logic device instantiated by the embedded FPGA and the at least another processor serve as slaves.

[0146] It can be understood that the host interconnection component 1022 can be used to realize the interconnection between the host and the slave within the multi-core processor, and can also be used to communicate with at least one programmable logic device instantiated by the eFPGA as a slave, that is, the host interconnection component can simultaneously manage the communication within the multi-core processor and the communication between the multi-core processor and the eFPGA, so that the multi-core processors and the multi-core processors and the embedded FPGA can cooperate more closely to meet the corresponding computing needs and application scenarios.

[0147] In the above technical solution, the interconnection components include slave interconnection components, host interconnection components, storage interconnection components, system application interconnection components and control interconnection components. Different types of interconnection components cooperate with each other to realize data transmission and control signal transmission between the multi-core processor and the embedded FPGA or between other resources. The processor in the multi-core processor and the instantiated programmable logic device in the embedded FPGA can be configured as a host or a slave to improve data transmission efficiency. Different types of interconnection components can adapt to different communication requirements. By dynamically allocating interconnection resources, the demand for hardware resources can be effectively reduced, and the volume of the reconfigurable interconnection circuit can be reduced, thereby reducing the volume of the system-level chip.

[0148] In one embodiment of the present application, the type of the interface includes: at least one of an AMBA general interface, an AMBA high-performance interface, an AMBA_ACP interface and a CTRL_IO_SIG interface.

[0149] The AMBA universal interface is a standardized interface used to connect various components in multi-core processors and eFPGAs, supports basic data transmission and communication requirements, and is applicable to a variety of different devices and application scenarios. In some embodiments, the AMBA universal interface is designed as a 32-bit or 64-bit data bus for medium and low-speed data communication between the multi-core processor and the eFPGA. The interface is transparent, that is, data is directly transmitted from one device to another without additional buffering. Two AMBA universal interfaces are configured to achieve bidirectional communication: one interface allows the CPU to control communication as a host, and the other interface allows the PL (programmable logic device, instantiated by the eFPGA) to control communication as a host, supporting the CPU and eFPGA to play the role of host or slave as needed in different scenarios, thereby improving the flexibility and communication efficiency of the SoC.

[0150] The AMBA high-performance interface is designed to meet the needs of high-performance computing, providing higher data transmission rates and lower latency. In some embodiments, the AMBA high-performance interface has a FIFO (first-in, first-out) buffer, allowing batch read and write operations to further improve the efficiency of data transmission, and can support high-speed data communication between eFPGA and multi-core processors. The data bus width is 32 bits or 64 bits to meet different data transmission requirements.

[0151] The AMBA_ACP interface is an interface designed for accelerators that supports a cache consistency protocol, allowing the accelerator to directly access the SoC memory and maintain consistency with the processor cache, which can be used to improve data processing efficiency and reduce latency.

[0152] The CTRL_IO_SIG interface is used to transmit control signals between the multi-core processor and the eFPGA, and can be used to achieve synchronous operation and correct data transmission control between SoC components.

[0153] In the above technical solution, the multiple interface types used in the reconfigurable interconnection circuit for multi-core processors include at least one of the AMBA general interface, the AMBA high-performance interface, the AMBA_ACP interface and the CTRL_IO_SIG interface. The AMBA general interface supports the communication between the multi-core processor and the embedded FPGA in the role of the host or the slave, while the AMBA high-performance interface improves the data transmission rate through the FIFO buffer, the ACP interface realizes cache consistency and can be used to optimize the memory access of the accelerator, and the CTRL_IO_SIG interface is used to transmit control signals. Through the configuration of different interfaces, the interface is dynamically selected according to the communication requirements, and the efficiency of data transmission is improved. The design of multiple interface types and interconnection components enables the reconfigurable interconnection circuit for multi-core processors to adapt to different communication requirements, effectively reducing the demand for hardware resources, reducing the volume of the reconfigurable interconnection circuit for multi-core processors, and thus reducing the volume of the system-level chip.

[0154] In one embodiment of the present application, all interfaces except the acceleration consistency interface on the multi-core processor side are connected to the multi-master and multi-slave routing arbitration structure, and then connected to the embedded FPGA through the interconnection component.

[0155] The Accelerator Coherency Port (ACP) is a dedicated interface that can be used for cache coherence access between multi-core processors and embedded FPGAs. It supports all standard read and write transactions without the need for additional coherence management.

[0156] It is understandable that the ACP interface already has the ability to handle consistency transactions, so there is no need to perform additional consistency management through a multi-master and multi-slave routing arbitration structure. It also avoids the additional contention and waiting time that may occur in the multi-master and multi-slave routing arbitration structure, and can improve the data transmission efficiency between multi-core processors and embedded FPGAs.

[0157] In the above technical solution, all interfaces except the acceleration consistency interface on the multi-core processor side are connected to the multi-master and multi-slave routing arbitration structure, and then connected to the embedded FPGA through the interconnection component. The interconnection resources are dynamically allocated through routing arbitration to form a reconfigurable interconnection circuit, thereby realizing the interconnection between the multi-core processor and the embedded FPGA, which can reduce the demand for hardware resources and reduce the size of the system-level chip. The acceleration consistency interface is not connected to the multi-master and multi-slave routing arbitration structure, avoiding possible additional competition and waiting time, and improving the data transmission efficiency between the multi-core processor and the embedded FPGA.

[0158] In one embodiment of the present application, the acceleration consistency interface on the multi-core processor side is directly connected to the system application interconnection component in the interconnection component, and the system application interconnection component is a consistency control unit in the acceleration processor.

[0159] The System Coherency Unit (SCU) in the Accelerated Processing Unit (APU) is used to maintain the cache consistency within the multi-core processor.

[0160] It can be understood that the acceleration consistency interface is directly connected to the consistency control unit in the acceleration processor. This connection method allows the acceleration consistency interface to be directly connected to the system application interconnection component in the interconnection component instead of being connected to the multi-master and multi-slave routing arbitration structure. This can simplify the data transmission path and improve the data transmission efficiency between the multi-core processor and the embedded FPGA.

[0161] In the above technical solution, the acceleration consistency interface on the multi-core processor side is directly connected to the system application interconnection component in the interconnection component. This component is a consistency control unit inside the acceleration processor, which can simplify the data transmission path and improve the data transmission efficiency between the multi-core processor and the embedded FPGA.

[0162] In one embodiment of the present application, the interface on the embedded FPGA side includes: at least one of a host AMBA general interface, a slave AMBA general interface, a host AMBA high-performance interface, a slave AMBA_ACP interface, and a CTRL_IO_SIG interface;

[0163] The slave interconnection component is connected to the host AMBA universal interface, the host interconnection component is connected to the slave AMBA universal interface, the storage interconnection component is connected to the host AMBA high-performance interface, the system application interconnection component is connected to the slave AMBA_ACP interface, and the control interconnection component is connected to the CTRL_IO_SIG interface.

[0164] On the embedded FPGA side, the host AMBA general interface is used to connect when the embedded FPGA is the host and the processor is the slave. The host AMBA high-performance interface is used to achieve high-speed data transmission, the slave AMBA_ACP interface is used to connect high-speed data transmission that supports cache coherence, and the CTRL_IO_SIG interface is used to transmit control signals and input / output signals.

[0165] The host interconnect component is connected to the slave AMBA general interface, allowing the embedded FPGA to respond to the processor's request as a slave. The storage interconnect component is connected to the host AMBA high-performance interface for high-speed data transmission of storage resources. The system application interconnect component is connected to the slave AMBA_ACP interface for high-speed data transmission of system-level applications. The control interconnect component is connected to the CTRL_IO_SIG interface for transmitting control signals and input / output signals.

[0166] Table 1

[0167]

[0168] Table 1 is an interface description table provided in some embodiments of the present application. As shown in Table 1, in some embodiments, the interface type also includes an AHB_HP interface and an AHB_GP interface. When the interface name in Table 1 starts with M, the processor is the host and the embedded FPGA is the slave. When the interface name in Table 1 starts with S, the processor is the slave and the embedded FPGA is the host.

[0169] The AHB_HP interface implements a high-bandwidth data path from the FPGA bus host to the OCM and DDR memory, with two read and write communication FIFO buffers. The storage interconnect component connects the high-speed AXI_HP interface to two DDR memory interfaces or OCM. The AXI_HP interface has a 32-bit or 64-bit data host interface, each interface can be independently programmed, and can automatically expand unaligned 32-bit transmissions to 64 bits. The AXI_HP interface also has a programmable write command threshold to support cross-domain operations at asynchronous clock frequencies. The interface also contains read and write FIFOs, and the command and communication data FIFO fill level counts are visible to the FPGA, allowing the eFPGA to dynamically monitor and manage data.

[0170] The AHB_GP interface is a direct interface. Unlike the AHB_HP interface, the AHB_GP interface has no additional buffering, so its performance is mainly limited by the host interface and the slave interconnection. The AHB_GP interface is more suitable for general rather than high-performance tasks. Each interface of the AHB_GP interface can support multiple peripherals. The AHB_GP interface supports 32-bit or 64-bit data bus width, with a 12-bit bus interface ID width and a 6-bit slave interface ID width. Each host and slave interface can accept 8 read and 8 write operations at a time.

[0171] In the above technical scheme, the slave interconnection component is connected to the host AMBA universal interface, the host interconnection component is connected to the slave AMBA universal interface, the storage interconnection component is connected to the host AMBA high-performance interface, the system application interconnection component is connected to the slave AMBA_ACP interface, and the control interconnection component is connected to the CTRL_IO_SIG interface. This explains the interface configuration on the embedded FPGA side and its connection method with different interconnection components, realizes communication and data transmission between multi-core processors and embedded FPGAs, and can meet the data transmission requirements in different application scenarios.

[0172] In one embodiment of the present application, the allocating corresponding interconnection resources for the data transmission includes: determining the connection relationship of the interconnection segments in the interconnection component and the jump relationship between the interconnection segments according to the number of interfaces, interface types and circuit application requirements of the multi-master and multi-slave routing arbitration structure, and generating a reconfigurable configuration file, wherein the reconfigurable configuration file is used to realize the configuration of turning on or off the programmable switch in the switch box and the input connection module and the output connection module in the connection box.

[0173] It is understandable that in a multi-master multi-slave routing arbitration structure, in order to efficiently perform data transmission, it is necessary to allocate corresponding interconnection resources for data transmission, and the allocation process is determined based on the number of interfaces, interface types, and circuit application requirements of the multi-master multi-slave routing arbitration structure. Due to the complexity of the interface logic between the processor and the embedded FPGA, a large number of interfaces and dedicated interconnection resources are required to realize data transmission. Therefore, in some embodiments, a multi-level combined interconnection structure is used to design the connection relationship of the interconnection segments in the interconnection components and the jump relationship between the interconnection segments.

[0174] The number of interfaces in the multi-master and multi-slave routing arbitration structure determines the number of channels that can be used for data transmission, while the interface type determines the type of data transmitted. Circuit application requirements refer to the different requirements of different application scenarios for data transmission, including data transmission rate, delay, bandwidth, etc. These requirements will directly affect the allocation and configuration of interconnection resources.

[0175] Interconnection segments are the basis of interconnection components. They connect different logical function blocks in interconnection components. By determining the connection relationship between interconnection segments, a data transmission path is formed to achieve effective data transmission. In an interconnection component, data may need to jump between multiple interconnection segments. The jump relationship determines the routing path of data in the interconnection circuit and how to select the path through interconnection components such as switch boxes. After determining the connection relationship of interconnection segments in the interconnection component and the jump relationship between interconnection segments, a reconfigurable configuration file can be generated.

[0176] Figure 5 Schematic diagram of configuring interconnected resources provided by some embodiments of the present application. Figure 5 As shown, the multi-master multi-slave routing arbitration structure or interconnection component adopts an island-type interconnection architecture, and the interconnection resources under the island-type interconnection architecture include global interconnection resources and local interconnection resources; the global interconnection resources include interconnection channels and switch boxes, the interconnection channels are composed of a preset number of interconnection segments, which are used to realize signal transmission between logic function blocks, and the switch boxes include a preset number of programmable switches, which are used to realize jumps between different interconnection segments; the local interconnection resources include connection boxes, including input connection modules and output connection modules, and the input connection modules and the output connection modules are connected in Figure 5 Not shown in the figure, it can be realized by a programmable switch, and the connection box is used to realize the signal transmission between the logic function block and the interconnection channel. Among them, the reconfigurable configuration file is used to realize the configuration of the programmable switch in the switch box and the input connection module and the output connection module in the connection box.

[0177] In the above technical scheme, according to the number of interfaces, interface types and circuit application requirements of the multi-master and multi-slave routing arbitration structure, the connection relationship of the interconnection segments in the interconnection component and the jump relationship between the interconnection segments are determined, a reconfigurable configuration file is generated, and corresponding interconnection resources are allocated for data transmission according to the reconfigurable configuration file, so that the reconfigurable interconnection circuit for multi-core processors can adapt to different data transmission requirements, thereby improving the flexibility of the reconfigurable interconnection circuit for multi-core processors.

[0178] In one embodiment of the present application, the horizontal channel and the vertical channel of the programmable interconnect on the embedded FPGA side provide the global interconnection resource, and the global interconnection resource performs signal interaction with the interconnection bus on the multi-core processor side through the local interconnection resource;

[0179] The signal output of the multi-core processor side is sent to the interconnection component through the local interconnection resource and processed by the corresponding logic unit, or the signal output of the multi-core processor side is sent to the adjacent logic unit through the horizontal channel for processing.

[0180] The horizontal and vertical channels of programmable interconnect on the embedded FPGA side provide global interconnect resources, which allow signals to be transmitted between different logic units. Global interconnect resources include interconnect channels and switch boxes. Interconnect channels are used to transmit signals between logic function blocks. Switch boxes contain programmable switches to control the direction and path of signal transmission, thereby achieving flexible signal routing.

[0181] The signal output on the multi-core processor side can be sent to the interconnect components through local interconnect resources. These signals can also be directly sent to adjacent logic units for processing through horizontal channels, thereby reducing the delay of data transmission.

[0182] The local interconnection resources include a connection box and an input cross-connection module. The connection box includes an input connection module and an output connection module, which are used to realize signal transmission between the logic function block and the interconnection channel. The input cross-connection module realizes the signal interconnection between the logic units. The module can also connect the input pins of the logic function block to each logic unit. It should be noted that multiple logic units constitute a logic function block.

[0183] In the above technical solution, the horizontal channels and vertical channels of the programmable interconnection on the embedded FPGA side provide global interconnection resources. The global interconnection resources exchange signals with the interconnection bus on the multi-core processor side through local interconnection resources. The signal output on the multi-core processor side is sent to the interconnection component through the local interconnection resources and processed by the corresponding logic unit, or sent to the adjacent logic unit through the horizontal channel for processing. The interconnection between the multi-core processor and the embedded FPGA is realized through the global interconnection resources and the local interconnection resources, thereby improving the flexibility of the reconfigurable interconnection circuit for the multi-core processor.

[0184] In one embodiment of the present application, the interconnection channel is a unidirectional channel or a bidirectional channel.

[0185] Figure 6 Schematic diagram of the structure of the interconnection channel provided by some embodiments of the present application. Figure 6 As shown in (a), a unidirectional channel uses a unidirectional inverter or buffer at the end of the connection to determine the direction of the channel signal transmission. Signals can only be transmitted from the A and C ends to the B and D ends respectively, and the reverse direction is not possible. Figure 6 As shown in (b), at the end of the bidirectional channel connection, a bidirectional selector is usually used to select the direction of channel signal transmission. The bidirectional selector is often implemented by a buffer or a three-state buffer. The A and B ends in the figure can be configured to achieve bidirectional transmission of signals.

[0186] In the above technical solution, the interconnection channel is a unidirectional channel or a bidirectional channel. By selecting different interconnection channels to adapt to various data transmission requirements, the data transmission efficiency of the reconfigurable interconnection circuit for multi-core processors is improved.

[0187] In one embodiment of the present application, the topology type of the programmable switches in the switch box includes at least one of subset interconnection, global interconnection and vertical interconnection.

[0188] Figure 7 Schematic diagram of a programmable switch topology structure provided by some embodiments of the present application. Figure 7 As shown, the topological structure types of the programmable switch include at least one of subset interconnection, global interconnection and vertical interconnection.

[0189] Subset interconnection refers to the configuration of programmable switches to connect certain specific circuit elements or modules to form a smaller, localized subset of connections. This connection method is suitable for scenarios where local communication between circuit modules that need to implement specific functions is required.

[0190] Global interconnect refers to the configuration of programmable switches to allow extensive, global connections between circuit elements or modules. This type of connection is often used to implement complex circuit functions and system-level integration.

[0191] Vertical interconnection refers to the connection between different layers or different circuit boards, allowing signals to be transmitted between different layers. This connection is usually achieved through through-holes, conductive columns or other vertical connection structures.

[0192] By properly selecting and applying the topological structure type of the programmable switch in the switch box, it is possible to achieve jumps between different interconnection segments, perform path selection and jump control between different interconnection segments, and thus manage the direction and routing of signal transmission.

[0193] In the above technical solution, the topological structure type of the programmable switch in the switch box includes at least one of subset interconnection, global interconnection and vertical interconnection. By reasonably selecting and applying the topological structure type of the programmable switch in the switch box, the flexibility and scalability of the reconfigurable interconnection circuit for multi-core processors can be improved.

[0194] In one embodiment of the present application, the switch box is implemented by combining a bidirectional interconnection switch with a unidirectional interconnection switch.

[0195] Figure 8 Schematic diagram of the structure of a bidirectional interconnection switch provided in some embodiments of the present application. Figure 8As shown in FIG. 1 , the interconnection line segments in the horizontal (x) direction can transmit signals from left to right or from right to left; the interconnection line segments in the vertical (y) direction can transmit signals from top to bottom or from bottom to top. Figure 8 If the bidirectional interconnection switch is shown, then the interconnection line segment it drives is bidirectional.

[0196] Fig. 9 is a schematic diagram of the structure of a unidirectional interconnection switch provided in some embodiments of the present application. Fig. 9 As shown, the unidirectional interconnection switch only allows the signal to flow in one direction and is suitable for scenarios where signal transmission has a clear directionality.

[0197] By combining the bidirectional interconnection switch and the unidirectional interconnection switch, the transmission path can be flexibly configured to meet different signal transmission requirements.

[0198] In some embodiments, the number of interconnection switches and jump relationships are set as follows: the connectivity (Fc) between the function block (CLB) pin and the connection is set to 10%, that is, among the connections passing through a certain pin of the CLB, 10% of the connections have switches that reach the input pin, and the number of other interconnection segments that can be connected at the end of the interconnection segment (Fs) is at least 3, and covers the three directions of left turn, right turn and forward. The logic function block allows direct data exchange between the input and output of the logic unit, that is, adding direct connection signals. By utilizing these flexibilities and considering all the options provided by the multi-level programmable interconnection network, the layout and routing tool can achieve a higher routing rate even when the Fc and Fs values ​​are low.

[0199] In the above technical solution, the switch box is implemented by combining a bidirectional interconnection switch with a unidirectional interconnection switch. By selecting different interconnection switches to adapt to various signal transmission requirements, the data transmission efficiency of the reconfigurable interconnection circuit for multi-core processors is improved.

[0200] In one embodiment of the present application, the types of the interconnection segments include long interconnection segments, short interconnection segments, local interconnection segments and direct connection segments. The long interconnection segments are used to meet the signal path requirements between logic function blocks that are far apart, the short interconnection segments are used to achieve interconnection between adjacent logic function blocks, the local interconnection segments are used to achieve signal sharing and feedback between logic units within each logic function block, and the direct connection segments are used for signal transmission between adjacent logic function blocks.

[0201] It can be understood that long interconnection segments are used to meet the signal path requirements between logic function blocks that are far apart. In reconfigurable interconnection circuits for multi-core processors, logic function blocks may be distributed in different locations. Long interconnection segments can span a large spatial distance, so that signals can be accurately transmitted to the target logic function block. Short interconnection segments are used to achieve a large amount of signal flow and fast interconnection between adjacent logic function blocks. Since adjacent logic function blocks are relatively close in space, short interconnection segments can reduce signal transmission delays and power consumption, thereby improving data transmission efficiency. Local interconnection segments are used to achieve signal sharing and feedback between logic units within each logic function block, which helps to enhance the signal processing capabilities within the logic function block. Direct connection segments are used for signal transmission between adjacent logic function blocks, which can reduce signal transmission delays and power consumption.

[0202] In the embodiment of the present application, the interconnection line segments adopt a multi-level combined interconnection system, namely "long line-short line-local interconnection line-direct line", which provides different types of rich interconnection resources for the interconnection needs of different applications, and can efficiently and flexibly realize user circuits.

[0203] Creating a good interconnect architecture involves many complex tradeoffs, including enough programmable switches and interconnect segments to make most circuits feasible and achieve good routing efficiency; however, too many interconnect segments and programmable switches waste area. Close connections use short interconnect segments to reduce capacitance and layout area, while long interconnect segments can be used to avoid the extra delay caused by passing through multiple programmable switches.

[0204] In the above technical solution, the design of the interconnection segment adopts a multi-level combined interconnection system, including long interconnection segments, short interconnection segments, local interconnection segments and direct connection segments, so as to meet the interconnection requirements of different distances and different complexities, adapt to the layout and signal transmission of different logical function blocks in the multi-master and multi-slave routing arbitration structure and interconnection components, and improve the flexibility of the reconfigurable interconnection circuit for multi-core processors.

[0205] In one embodiment of the present application, the parameters of the multi-master and multi-slave routing arbitration structure or interconnection component include: the number of routing wires that can be connected to the input or output of each logical function block, the number of other routing wires that each routing wire can be connected to, the length of the routing segment, the mode of the routing switch, the electrical design of the routing wires and the programmable switches, and the number of routing segments for each channel.

[0206] The number of routing wires that can be connected to the input or output of each logic function block determines how many routing wires the logic function block can be connected to, which affects the ability and flexibility of signal transmission. The number of other routing wires that each routing wire can connect to involves the cross-connection capability between routing wires, affecting the routing selection and traffic management of signals on different paths. The length of the routing segment affects the delay of signal transmission and the integrity of the signal, and in physical design, it is directly related to the layout and wiring of the circuit. The mode of the routing switch determines how the signal transmission path is configured, including unidirectional or bidirectional transmission, and how the path selection is performed through the switch box.

[0207] Fig.10 Schematic diagram of a multi-master and multi-slave routing arbitration structure or interconnection component provided in some embodiments of the present application. Fig.10 For example, the number of routing wires that can be connected to the input or output of each logic function block is 3, the number of other routing wires that each routing wire can be connected to is 3, and the number of routing line segments of each channel is 4.

[0208] Fig.11 Schematic diagram of a programmable switch structure provided by some embodiments of the present application. Fig.11 As shown in Figure 1, eFPGA can use transmission tubes controlled by SRAM cells to connect interconnects. Although transmission tubes can bring the smallest area, this structure brings a square increase in delay when more transmission tubes are connected in series, which makes this structure slow when implementing large FPGAs.

[0209] In some embodiments, the programmable switch is implemented using a multiplexer and a tri-state buffer. To reduce latency at the expense of increased area, the eFPGA uses a multiplexer composed of transmission tubes, and the output of the multiplexer is buffered by a tri-state buffer.

[0210] A multiplexer (MUX) is a logic circuit with multiple input lines and one output line, which can select one of the multiple inputs as the output according to a selection signal. In a reconfigurable interconnect circuit, a MUX is used to select the signal path that should be activated.

[0211] Fig.12 Schematic diagram of a multiplexer provided in some embodiments of the present application. The transmission tube size of the structure is small and the buffer size is large, which can compromise the area and driving capability. The structure has excellent electrical characteristics, reduces the area and improves the speed. The present application can adopt Fig.12 The multiplexer shown is used as the basic implementation structure of the programmable switch.

[0212] A tristate buffer is a buffer that can be in three states, namely high level, low level and high impedance (disabled state). The high impedance state allows other parts of the circuit to take over the bus, so that multiple devices can share the same communication path without interfering with each other. In reconfigurable interconnect circuits, tristate buffers are used to disable paths when signal transmission is not required, or to coordinate access when multiple devices share the same bus.

[0213] Programmable switches implemented using multiplexers and tri-state buffers improve the flexibility and control capabilities of multi-master and multi-slave routing arbitration structures or interconnect components, and can be dynamically adjusted according to real-time data transmission requirements and routing decisions.

[0214] In the above technical solution, the parameters of the multi-master and multi-slave routing arbitration structure or interconnection component include the number of routing wires that can be connected to the input or output of each logical function block, the number of other routing wires that each routing wire can be connected to, the length of the routing segment, the mode of the routing switch, the electrical design of the routing wires and the programmable switches, and the number of routing segments of each channel. These parameters jointly determine the configuration method of the data transmission path of the reconfigurable interconnection circuit for multi-core processors, so as to realize the ability to dynamically adjust the routing path according to different data transmission requirements, adapt to different application scenarios, and help to make more efficient use of hardware resources.

[0215] In one embodiment of the present application, the multi-master and multi-slave routing arbitration structure includes an AMBA bus matrix 1011, and the AMBA bus matrix 1011 is used to connect all AMBA bus interfaces of the multi-core processor.

[0216] Fig.13 is a schematic diagram of an AMBA bus matrix provided by some embodiments of the present application, such as Fig.13 As shown, in some embodiments, the multi-master multi-slave routing arbitration structure further includes an AMBA bus matrix 1011, which is used to connect all AMBA bus interfaces of the multi-core processor. In a multi-core processor, different processors may need to access the same resources, such as memory or peripherals. The AMBA bus matrix provides a shared communication path, and implements resource allocation and flow control by centrally managing the AMBA bus interfaces, thereby optimizing the overall performance of the reconfigurable interconnect circuit for the multi-core processor.

[0217] In the above technical solution, the multi-master and multi-slave routing arbitration structure includes an AMBA bus matrix for connecting all AMBA bus interfaces of the multi-core processor. By centrally connecting all AMBA bus interfaces of the multi-core processor, the efficiency of data transmission is improved, the use of hardware resources is optimized, and the flexibility of the reconfigurable interconnection circuit for the multi-core processor is improved.

[0218] Fig.14 1 is a flowchart of a method for implementing a reconfigurable interconnect circuit for a multi-core processor provided in some embodiments of the present application. Fig.14 As shown, the implementation method of the reconfigurable interconnect circuit for a multi-core processor includes: step 1410, step 1420 and step 1430.

[0219] Step 1410: Generate code for the reconfigurable interconnection circuit for the multi-core processor according to the interconnection requirements, the interconnection parameters on the multi-core processor side, and the interconnection parameters on the embedded FPGA side;

[0220] The complete interconnected circuit function required by the user is formed by connecting and expanding the functions realized by multiple logic function blocks. The interconnection requirements reflect the complete interconnected circuit function required by the user. According to the interconnection requirements, it can be determined which logic function blocks need to be connected and expanded.

[0221] In some embodiments, the interconnection parameters on the multi-core processor side include at least one of the following: the number of CPU cores, the data bit width of each CPU, the number of CPU masters and slaves, the access address space of each CPU, the CPU interface type, the number of interfaces of the multi-master and multi-slave routing arbitration structure, and the interface type of the multi-master and multi-slave routing arbitration structure;

[0222] The interconnection parameters on the embedded FPGA side include at least one of the following: the number of embedded FPGA masters and slaves, the type of AMBA bus interface, the number of interconnection component signals, the type of interconnection components, and the number of each type of interconnection components.

[0223] In some embodiments, the code for generating the reconfigurable interconnection circuit for the multi-core processor according to the interconnection requirements, the interconnection parameters on the multi-core processor side, and the interconnection parameters on the embedded FPGA side includes:

[0224] Determine the data transmission within the multi-core processor or between the multi-core processor and the embedded FPGA according to the interconnection requirements;

[0225] According to the interconnection parameters on the multi-core processor side and the interconnection parameters on the embedded FPGA side, a code of the reconfigurable interconnection circuit for the multi-core processor is generated for the data transmission.

[0226] It can be understood that the code of the reconfigurable interconnection circuit for multi-core processors is generated based on the interconnection requirements, the number of CPU cores, the data bit width of each CPU, the number of CPU masters and slaves, the access address space of each CPU, the CPU interface type, the number of interfaces of the multi-master and multi-slave routing arbitration structure, at least one of the interface types of the multi-master and multi-slave routing arbitration structure, the number of masters and slaves of the embedded FPGA, the AMBA bus interface type, the number of interconnection component signals, the interconnection component type and at least one of the number of each interconnection component type, with the purpose of enabling the generated code to meet the communication and data transmission requirements of the multi-core processor and the embedded FPGA. The generated code defines in detail the structure, function and interconnection relationship of the multi-master and multi-slave routing arbitration structure and interconnection components in the reconfigurable interconnection circuit for multi-core processors.

[0227] Step 1420: Generate an FPGA configuration file according to the code.

[0228] Create an FPGA configuration file based on the code generated in step 1410. The configuration file contains information that will be downloaded to the embedded FPGA for configuration. The generation of the configuration file may involve code compilation, synthesis and optimization, so that the configuration file can be correctly understood and executed by the embedded FPGA.

[0229] Step 1430: Download the FPGA configuration file to the embedded FPGA to form the reconfigurable interconnection circuit for the multi-core processor.

[0230] The FPGA configuration file generated in step 1420 is downloaded to the embedded FPGA so that it can implement the preset reconfigurable interconnection circuit for the multi-core processor according to the instructions in the configuration file.

[0231] In the above technical scheme, according to the interconnection requirements, the interconnection parameters on the multi-core processor side and the interconnection parameters on the embedded FPGA side, the code of the reconfigurable interconnection circuit for the multi-core processor is generated, and the code is converted into an FPGA configuration file, and the FPGA configuration file is downloaded to the embedded FPGA, thereby realizing the reconfigurable interconnection circuit for the multi-core processor, improving the flexibility of realizing the reconfigurable interconnection circuit for the multi-core processor, and the realized reconfigurable interconnection circuit for the multi-core processor can meet different interconnection requirements, thereby enhancing the scalability and adaptability of the reconfigurable interconnection circuit for the multi-core processor.

[0232] An embodiment of the present application further provides a chip, which includes a multi-core processor and an embedded FPGA, and also includes a reconfigurable interconnect circuit for the multi-core processor. For an understanding of the reconfigurable interconnect circuit for the multi-core processor, reference can be made to the description in the aforementioned embodiment, which will not be repeated here.

[0233] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0234] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0235] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the relevant technology, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0236] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

[0237] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0238] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A reconfigurable interconnect circuit for a multi-core processor, characterized in that: include: A multi-master multi-slave routing arbitration structure and an interconnection component, wherein a multi-core processor is connected to the multi-master multi-slave routing arbitration structure, and the multi-master multi-slave routing arbitration structure is connected to an embedded field programmable gate array FPGA through the interconnection component. The multi-master and multi-slave routing arbitration structure is used to identify and route data transmission within the multi-core processor or between the multi-core processor and the embedded FPGA, and allocate corresponding interconnection resources for the data transmission, and the interconnection resources are implemented based on the interconnection components; The interconnection component is used to manage and transfer communications between interfaces connected to the interconnection component, wherein the interface is an interface on the multi-core processor side and / or an interface on the embedded FPGA side; The multi-master and multi-slave routing arbitration structure or the interconnection component adopts an island-type interconnection architecture, and the interconnection resources under the island-type interconnection architecture include global interconnection resources and local interconnection resources; The global interconnection resources include interconnection channels and switch boxes, and the local interconnection resources include connection boxes, wherein: The interconnection channel is composed of a preset number of interconnection line segments and is used to realize signal transmission between logic function blocks; The switch box includes a preset number of programmable switches for implementing jumps between different interconnected line segments; The connection box comprises an input connection module and an output connection module, which are used to realize signal transmission between the logic function block and the interconnection channel.

2. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that: The types of interconnect components include slave interconnect components, host interconnect components, storage interconnect components, system application interconnect components and control interconnect components, wherein: The slave interconnection component is used to realize the interconnection between at least one processor in the multi-core processor and the embedded FPGA, wherein the at least one processor serves as a slave and the embedded FPGA serves as a host; The host interconnection component is used to realize the interconnection between at least one processor in the multi-core processor and the embedded FPGA, wherein the at least one processor serves as a host and the embedded FPGA serves as a slave; The storage interconnection component is used to realize the interconnection of storage resources; The system application interconnection component is used to realize the interconnection of system-level applications; The control interconnection component is used to realize the transmission of control signals.

3. The reconfigurable interconnect circuit for multi-core processors according to claim 2, characterized in that: The embedded FPGA as a host includes at least one programmable logic device instantiated by the embedded FPGA as a host.

4. The reconfigurable interconnect circuit for multi-core processors according to claim 2, characterized in that: The embedded FPGA as a slave includes at least one programmable logic device instantiated by the embedded FPGA as a slave.

5. The reconfigurable interconnect circuit for multi-core processors according to claim 2, characterized in that: The host interconnection component is also used to realize the interconnection between processors in the multi-core processor, at least one processor serves as a host and at least another processor serves as a slave.

6. The reconfigurable interconnect circuit for multi-core processors according to claim 2, characterized in that: The host interconnection component is also used to realize the interconnection between at least one processor in the multi-core processor and the embedded FPGA and at least another processor, wherein at least one processor in the multi-core processor serves as the host, and at least one programmable logic device instantiated by the embedded FPGA and the at least another processor serve as slaves.

7. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that: The types of the interface include: at least one of an Advanced Microcontroller Bus Architecture AMBA general interface, an AMBA high performance interface, an AMBA_ACP interface and a CTRL_IO_SIG interface.

8. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that: All interfaces on the multi-core processor side except the acceleration consistency interface are connected to the multi-master and multi-slave routing arbitration structure, and then connected to the embedded FPGA through the interconnection component.

9. The reconfigurable interconnect circuit for multi-core processors according to claim 2, characterized in that: The acceleration consistency interface on the multi-core processor side is directly connected to the system application interconnection component in the interconnection component, and the system application interconnection component is a consistency control unit in the acceleration processor.

10. The reconfigurable interconnect circuit for multi-core processors according to claim 2, characterized in that: The interface on the embedded FPGA side includes: at least one of a host AMBA general interface, a slave AMBA general interface, a host AMBA high-performance interface, a slave AMBA_ACP interface, and a CTRL_IO_SIG interface; The slave interconnection component is connected to the host AMBA universal interface, the host interconnection component is connected to the slave AMBA universal interface, the storage interconnection component is connected to the host AMBA high-performance interface, the system application interconnection component is connected to the slave AMBA_ACP interface, and the control interconnection component is connected to the CTRL_IO_SIG interface.

11. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that: The allocating corresponding interconnection resources for the data transmission includes: determining the connection relationship of the interconnection segments in the interconnection component and the jump relationship between the interconnection segments according to the number of interfaces, interface types and circuit application requirements of the multi-master and multi-slave routing arbitration structure, and generating a reconfigurable configuration file, wherein the reconfigurable configuration file is used to realize the configuration of turning on or off the programmable switch in the switch box and the input connection module and the output connection module in the connection box.

12. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that: The local interconnection resources further include: an input cross-interconnection module, the input cross-interconnection module is used to realize signal interconnection between logic units and connect the input pins of the logic function block to each logic unit; Among them, a plurality of the logic units constitute the logic function block.

13. The reconfigurable interconnect circuit for a multi-core processor according to any one of claims 1 to 12, characterized in that: The horizontal channel and the vertical channel of the programmable interconnection on the embedded FPGA side provide the global interconnection resource, and the global interconnection resource performs signal interaction with the interconnection bus on the multi-core processor side through the local interconnection resource; The signal output of the multi-core processor side is sent to the interconnection component through the local interconnection resource and processed by the corresponding logic unit, or the signal output of the multi-core processor side is sent to the adjacent logic unit through the horizontal channel for processing.

14. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that: The types of the interconnection segments include long interconnection segments, short interconnection segments, local interconnection segments and direct connection segments. The long interconnection segments are used to meet the signal path requirements between logic function blocks that are far apart. The short interconnection segments are used to achieve interconnection between adjacent logic function blocks. The local interconnection segments are used to achieve signal sharing and feedback between logic units within each logic function block. The direct connection segments are used for signal transmission between adjacent logic function blocks.

15. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that: The interconnection channel is a one-way channel or a two-way channel.

16. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that: The switch box is implemented by combining a bidirectional interconnection switch with a unidirectional interconnection switch.

17. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that: The topological structure type of the programmable switches in the switch box includes at least one of subset interconnection, global interconnection and vertical interconnection.

18. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that: The parameters of the multi-master and multi-slave routing arbitration structure or interconnection component include: the number of routing wires to which the input or output of each logic function block can be connected, the number of other routing wires to which each routing wire can be connected, the length of the routing segment, the mode of the routing switch, the electrical design of the wires and programmable switches, and the number of routing segments for each channel.

19. The reconfigurable interconnect circuit for multi-core processors according to claim 1, characterized in that: The programmable switch is implemented by a multiplexer and a tri-state buffer.

20. The reconfigurable interconnect circuit for multi-core processors according to any one of claims 1-12 and 14-19, characterized in that: The multi-master and multi-slave routing arbitration structure includes an AMBA bus matrix, and the AMBA bus matrix is ​​used to connect all AMBA bus interfaces of the multi-core processor.

21. A method for implementing a reconfigurable interconnect circuit for a multi-core processor according to any one of claims 1 to 20, characterized in that: include: Generate the code of the reconfigurable interconnection circuit for the multi-core processor according to the interconnection requirements, the interconnection parameters on the multi-core processor side, and the interconnection parameters on the embedded FPGA side; Generate an FPGA configuration file according to the code; The FPGA configuration file is downloaded to the embedded FPGA to form the reconfigurable interconnection circuit for the multi-core processor.

22. The method according to claim 21, characterized in that The interconnection parameters on the multi-core processor side include at least one of the following: the number of CPU cores, the data bit width of each CPU, the number of CPU masters and slaves, the access address space of each CPU, the CPU interface type, the number of interfaces of the multi-master and multi-slave routing arbitration structure, and the interface type of the multi-master and multi-slave routing arbitration structure; The interconnection parameters on the embedded FPGA side include at least one of the following: the number of embedded FPGA masters and slaves, the type of AMBA bus interface, the number of interconnection component signals, the type of interconnection components, and the number of each type of interconnection components.

23. The method according to claim 21, characterized in that The code for the reconfigurable interconnection circuit for the multi-core processor is generated according to the interconnection requirements, the interconnection parameters on the multi-core processor side, and the interconnection parameters on the embedded FPGA side, including: Determine the data transmission within the multi-core processor or between the multi-core processor and the embedded FPGA according to the interconnection requirements; According to the interconnection parameters on the multi-core processor side and the interconnection parameters on the embedded FPGA side, a code of the reconfigurable interconnection circuit for the multi-core processor is generated for the data transmission.

24. A chip, characterized in that: The invention comprises a multi-core processor and an embedded FPGA, and also comprises a reconfigurable interconnection circuit for the multi-core processor as claimed in any one of claims 1 to 20.

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