Voltage-insensitive FPGA clock network and control method

Abstract

The invention relates to the technical field of clock networks, in particular to a voltage-insensitive FPGA (Field Programmable Gate Array) clock network and a control method, the FPGA clock network comprises a plurality of time delay adjustable clock buffers; the clock buffer receives local feedback information of the current clock buffer or global feedback information of a backward clock buffer corresponding to a backward node, and dynamically adjusts transmission delay according to the local feedback information or the global feedback information; the clock buffer comprises a local feedback module and a global feedback module. The local feedback module adaptively adjusts circuit parameters of the current clock buffer based on local feedback information to balance local supply voltage fluctuations. The global feedback module adaptively adjusts circuit parameters of the current clock buffer based on global feedback information to balance global supply voltage fluctuations. The transmission delay of the clock network can be dynamically adjusted, and the influence of power supply voltage fluctuation on the clock network is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of clock networks, and in particular to a voltage-insensitive FPGA clock network and a control method thereof. Background Art

[0002] In modern electronic systems, Field-Programmable Gate Array (FPGA) is widely used in various high-speed computing and digital signal processing fields due to its flexibility and reconfigurability. One of the core performance of FPGA is its clock network, such as Figure 1 As shown, it is responsible for providing a synchronous clock signal for the entire chip to ensure that data is transmitted correctly and efficiently between different parts.

[0003] In traditional FPGA clock network design, Figure 2 As shown in Figure 1, the clock buffer is usually composed of a cascade of inverters. This design is simple and low-cost. However, this design is very sensitive to power supply fluctuations. Figure 3 As shown in the figure (vdd represents the power supply voltage of the FPGA chip, clock buffer delay represents the delay time of the clock buffer, and clock output represents the output waveform of the clock signal), due to the change of the power supply voltage, the transmission delay of the clock buffer will fluctuate accordingly. This fluctuation accumulates on the clock network of the FPGA, resulting in clock jitter. Clock jitter can seriously affect the performance of the FPGA, especially in high-speed data transmission and processing applications, where clock jitter may cause data errors and system instability.

[0004] As FPGAs grow in size, the complexity of the clock network also increases, and the impact of voltage fluctuations on the clock network becomes more significant. This not only limits the performance improvement of FPGAs, but also places higher design requirements on designers to ensure the stability and accuracy of the clock network under different power supply conditions. Summary of the invention

[0005] In view of this, the present invention provides a voltage-insensitive FPGA clock network and control method to solve the problem that the traditional clock buffer is affected by the chip power supply voltage, resulting in transmission delay fluctuations and accumulating clock jitter in the clock network.

[0006] In a first aspect, the present invention provides a voltage-insensitive FPGA clock network, the FPGA clock network comprising a plurality of clock buffers with adjustable delays, the clock buffers being distributed at grid nodes of the FPGA clock network; the clock buffers being used to receive local feedback information of a current clock buffer or global feedback information of a backward clock buffer corresponding to a backward node, and dynamically adjust transmission delay according to the local feedback information or the global feedback information;

[0007] The clock buffer includes a local feedback module and a global feedback module in one-to-one correspondence;

[0008] The local feedback module is used to obtain local feedback information of the current clock buffer and adaptively adjust the circuit parameters of the current clock buffer according to the local feedback information to balance the local power supply voltage fluctuation;

[0009] The global feedback module is used to receive global feedback information of the backward clock buffer through a clock tree between the current clock buffer and the backward clock buffer, and adaptively adjust circuit parameters of the current clock buffer according to the global feedback information to balance global power supply voltage fluctuations.

[0010] In an optional implementation, the clock buffer is further provided with a one-to-one corresponding local delay module;

[0011] The local delay module is connected to the path between the input end and the output end of the clock buffer; the local delay module is used to fine-tune the local clock signal delay of the clock buffer.

[0012] In an optional implementation, in the current clock buffer, the input end of the current local feedback module corresponding to the current clock buffer is connected to the output end of the current local delay module corresponding to the current clock buffer; the output end of the current local feedback module is connected to the local feedback end of the current clock buffer;

[0013] The input end of the current global feedback module corresponding to the current clock buffer is connected to the output end of the backward local delay module corresponding to the backward clock buffer; the output end of the current global feedback module is connected to the global feedback end of the current clock buffer.

[0014] In an optional implementation, the local feedback module includes:

[0015] A delay monitoring unit, used for monitoring the local delay information of the current clock buffer in real time and transmitting the monitoring result to the comparison unit;

[0016] The comparison unit is used to compare the local delay information with the pre-stored expected delay information, and generate a local adjustment signal according to the comparison result, and transmit it to the local feedback end of the current clock buffer to adjust the circuit parameters of the current clock buffer.

[0017] In an optional implementation, the global feedback module includes:

[0018] A backward node information acquisition unit, used to acquire global feedback information of a backward clock buffer of the clock tree, wherein the global feedback information includes clock signal status, delay information, and supply voltage information of the backward clock buffer;

[0019] An information processing unit is used to analyze and process the collected global feedback information, generate a global adjustment signal, and transmit the global adjustment signal to the global feedback end of the current clock buffer to uniformly coordinate and adjust the circuit parameters of the current clock buffer and balance the global power supply voltage fluctuations of the FPGA clock network.

[0020] In an optional implementation, a delay unit is provided inside each of the clock buffers, and the delay unit is used to adjust the transmission delay of the clock signal of the clock buffer.

[0021] In a second aspect, the present invention provides a control method for a voltage-insensitive FPGA clock network, the control method being applied to a clock buffer of a voltage-insensitive FPGA clock network as described above, the method comprising:

[0022] Based on the local feedback module, local feedback information of the current clock buffer is obtained, and circuit parameters of the current clock buffer are adaptively adjusted according to the local feedback information to balance local power supply voltage fluctuations;

[0023] Based on the global feedback module, global feedback information of the backward clock buffer is received through the clock tree between the current clock buffer and the backward clock buffer, and circuit parameters of the current clock buffer are adaptively adjusted according to the global feedback information to balance global power supply voltage fluctuations.

[0024] In an optional implementation, the adaptively adjusting the circuit parameters of the current clock buffer according to the local feedback information includes:

[0025] If the local delay information of the current clock buffer exceeds the expected delay information, reducing the output delay of the current clock buffer;

[0026] If the local delay information of the current clock buffer is lower than the expected delay information, the output delay of the current clock buffer is increased.

[0027] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to execute a method for controlling a voltage-insensitive FPGA clock network according to the first aspect or any corresponding embodiment thereof.

[0028] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute a method for controlling a voltage-insensitive FPGA clock network according to the first aspect or any corresponding embodiment thereof.

[0029] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, wherein the computer instructions are used to enable a computer to execute a method for controlling a voltage-insensitive FPGA clock network according to the first aspect or any corresponding embodiment thereof.

[0030] The technical solution provided by the present invention may include the following beneficial effects:

[0031] The present invention provides a voltage-insensitive FPGA clock network, which includes a plurality of adjustable-delay clock buffers, which are distributed at the grid nodes of the FPGA clock network; the clock buffer is used to receive local feedback information of the current clock buffer or global feedback information of the backward clock buffer corresponding to the backward node, and dynamically adjust the transmission delay according to the local feedback information or the global feedback information; the clock buffer includes a one-to-one corresponding local feedback module and a global feedback module; the local feedback module is used to obtain the local feedback information of the current clock buffer, and adaptively adjust the circuit parameters of the current clock buffer according to the local feedback information to balance the local power supply voltage fluctuation; the global feedback module is used to receive the global feedback information of the backward clock buffer through a clock tree between the current clock buffer and the backward clock buffer, and adaptively adjust the circuit parameters of the current clock buffer according to the global feedback information to balance the global power supply voltage fluctuation. The present invention can dynamically adjust the transmission delay of the clock network by introducing a time-delay adjustable clock buffer and a two-stage adaptive feedback mechanism, effectively reducing the influence of power supply voltage fluctuation on the clock network, thereby significantly improving the stability and accuracy of the clock. Moreover, the present invention can effectively reduce clock jitter caused by voltage fluctuations by accurately controlling the delay of the clock buffer, improve the clock performance and voltage fluctuation resistance of the FPGA, and thus enhance the reliability of the entire system. In addition, the design method of the present invention has strong scalability and can adapt to FPGA chips of different sizes and complexities. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 is a schematic diagram of a grid structure of an FPGA clock network according to an embodiment of the present invention;

[0034] Figure 2 is a schematic structural diagram of a clock buffer composed of cascaded inverters according to an embodiment of the present invention;

[0035] Figure 3 is a wave line diagram showing the effect of voltage fluctuation on clock buffer delay according to an embodiment of the present invention;

[0036] Figure 4 is a schematic diagram of a voltage-insensitive FPGA clock network according to an embodiment of the present invention;

[0037] Figure 5 is a schematic diagram of the structure of a clock buffer according to an embodiment of the present invention;

[0038] Figure 6 It is a flowchart of a method for controlling a voltage-insensitive FPGA clock network according to an embodiment of the present invention;

[0039] Figure 7 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0041] In this embodiment, a voltage-insensitive FPGA clock network is provided. Figure 4 The schematic diagram of the structure of a voltage-insensitive FPGA clock network is shown, and the FPGA clock network includes multiple clock buffers with adjustable delays ( Figure 4 Each box in represents a clock buffer, i.e. Figure 4 Three connected clock buffers are provided, and this connection mode constitutes a transmission path of the clock signal in the network. The clock buffers are distributed at the grid nodes of the FPGA clock network; the clock buffers are used to receive local feedback information of the current clock buffer or global feedback information of the backward clock buffer corresponding to the backward node, and dynamically adjust the transmission delay according to the local feedback information or the global feedback information;

[0042] See also Figure 5 The clock buffer shown in FIG. 1 includes a local feedback module and a global feedback module corresponding to each other (the clock buffer also includes a local feedback terminal and a global feedback terminal, and the local feedback module is connected to the local feedback terminal of the clock buffer, that is, Figure 5 The global feedback module is connected to the global feedback terminal of the clock buffer, that is, Figure 5 The clock buffers are key components of the entire clock network. They are responsible for receiving and transmitting clock signals and dealing with voltage fluctuations by adjusting transmission delays.

[0043] The local feedback module is used to obtain local feedback information of the current clock buffer and adaptively adjust the circuit parameters of the current clock buffer according to the local feedback information to balance the local power supply voltage fluctuation;

[0044] The global feedback module is used to receive global feedback information of the backward clock buffer through the clock tree between the current clock buffer and the backward clock buffer, and adaptively adjust the circuit parameters of the current clock buffer according to the global feedback information to balance the global power supply voltage fluctuation.

[0045] Furthermore, firstly, the present embodiment proposes a clock buffer design with adjustable delay. Different from the traditional inverter cascade structure, the circuit parameters of the clock buffer with adjustable delay can be adjusted in real time. The present embodiment fine-tunes the delay of the clock buffer through feedback circuit signals; at the grid nodes, the circuit parameters of the clock buffer are adaptively adjusted through local feedback, so as to balance the influence of local power supply voltage fluctuations; between the grid nodes, the circuit parameters of the clock buffer are adaptively adjusted through clock tree backward node feedback information, so as to balance the influence of global power supply voltage fluctuations; through the two-level adaptive feedback mechanism, the present embodiment can reduce the influence of the overall clock network on the fluctuation of the power supply voltage and improve the overall performance of the clock network.

[0046] In an optional embodiment, if Figure 4 As shown, the clock buffer is also provided with a one-to-one corresponding local delay module (the local delay module is Figure 4 local delay unit in the

[0047] The local delay module is connected to the path between the input end and the output end of the clock buffer; the local delay module is used to fine-tune the local clock signal delay of the clock buffer.

[0048] Furthermore, each clock buffer is also provided with a local delay module (local delay unit), which is connected to the path between the input and output ends of the clock buffer. Its main function is to fine-tune the local clock signal delay of the clock buffer. During the clock signal transmission process, it may be necessary to make a more precise delay adjustment to the clock signal due to factors such as slight differences in the local circuit environment, and the local delay module can play such a role. For example, in some areas with more complex local wiring, the clock signal may need to increase the delay appropriately to ensure synchronization with other parts, and the local delay module can be fine-tuned according to the actual situation.

[0049] In an optional implementation, in the current clock buffer, the input end (i.e. Figure 5 IN in the current clock buffer) is connected to the output of the current local delay module corresponding to the current clock buffer (i.e. Figure 5 OUT in the current local feedback module); the output end of the current local feedback module is connected to the local feedback end of the current clock buffer;

[0050] The input end of the current global feedback module corresponding to the current clock buffer is connected to the output end of the backward local delay module corresponding to the backward clock buffer; the output end of the current global feedback module is connected to the global feedback end of the current clock buffer.

[0051] In an optional implementation, the local feedback module includes:

[0052] A delay monitoring unit, used for monitoring the local delay information of the current clock buffer in real time and transmitting the monitoring result to the comparison unit;

[0053] The comparison unit is used to compare the local delay information with the pre-stored expected delay information, and generate a local adjustment signal according to the comparison result, and transmit it to the local feedback end of the current clock buffer to adjust the circuit parameters of the current clock buffer.

[0054] Further, the clock buffer of the present embodiment is equipped with a local feedback module, which is connected to the local feedback terminal (vadj_local). The module first obtains the local feedback information of the current clock buffer, which may include the transmission status of the clock signal within the local range of the current buffer, etc. Then, the local delay information of the current clock buffer is monitored in real time by the delay monitoring unit, and transmitted to the comparison unit. The comparison unit compares the local delay information with the pre-stored expected delay information. If there is a deviation between the local delay and the expected delay, the comparison unit generates a local adjustment signal according to the comparison result, and transmits it to the local feedback terminal of the current clock buffer, thereby adjusting the circuit parameters of the current clock buffer, so as to balance the influence of the local power supply voltage fluctuation on the clock signal transmission. For example, if the local power supply voltage fluctuation causes the clock signal to be transmitted too fast, so that the local delay is less than the expected delay, the comparison unit may generate a signal to increase the delay of the clock buffer, otherwise it will reduce the delay.

[0055] In an optional implementation, the global feedback module includes:

[0056] A backward node information acquisition unit, used to acquire global feedback information of a backward clock buffer of the clock tree, the global feedback information including clock signal status, delay information and supply voltage information of the backward clock buffer;

[0057] The information processing unit is used to analyze and process the collected global feedback information, generate a global adjustment signal, and transmit the global adjustment signal to the global feedback end of the current clock buffer to uniformly coordinate and adjust the circuit parameters of the current clock buffer and balance the global power supply voltage fluctuations of the FPGA clock network.

[0058] Furthermore, the global feedback module is connected to the global feedback end (vadj_backward) of the clock buffer. It receives the global feedback information of the backward clock buffer through the clock tree between the current clock buffer and the backward clock buffer. This information covers the clock signal status, delay information, and power supply voltage information of the backward clock buffer. The information processing unit will conduct in-depth analysis and processing of the collected global feedback information, generate a global adjustment signal based on this information, and transmit it to the global feedback end of the current clock buffer, and then coordinate and adjust the circuit parameters of the current clock buffer in a unified manner to balance the global power supply voltage fluctuation of the entire FPGA clock network. For example, when the power supply voltage fluctuation in a certain area of ​​the network affects the clock signal of the backward clock buffer, this impact can be transmitted to the current clock buffer through the global feedback module, and corresponding adjustments can be made to ensure the clock stability of the entire network.

[0059] In an optional embodiment, if Figure 4 As shown, each clock buffer is provided with a delay unit (the local delay module is Figure 4 The delay unit in the clock buffer is used to adjust the transmission delay of the clock signal of the clock buffer.

[0060] Furthermore, each clock buffer is provided with a delay unit ( Figure 4 The internal delay unit is mainly used to adjust the transmission delay of the clock signal of the clock buffer. Different from the fine-tuning function of the local delay module, the internal delay unit can adjust the transmission delay of the clock signal at a more macro level to adapt to different working conditions and voltage fluctuations, ensuring that the clock signal can maintain a relatively stable transmission time when passing through the clock buffer.

[0061] Furthermore, this embodiment uses a clock buffer with adjustable delay on the FPGA clock network, which can accept local or backward feedback information from the clock network node to dynamically adjust the transmission delay. At the clock network node, this embodiment adaptively adjusts the circuit parameters of the clock buffer clock buffer through local feedback to balance the impact of local power supply voltage fluctuations; if the local delay exceeds the expected delay, the clock buffer output delay is reduced; otherwise, the clock buffer output delay is increased; and, between grid nodes, this embodiment adaptively adjusts the circuit parameters of the clock buffer clock buffer through clock tree backward node feedback information to balance the impact of global power supply voltage fluctuations.

[0062] This embodiment uses a two-level adaptive feedback mechanism to reduce the impact of the overall clock network on power supply voltage fluctuations and improve the overall performance of the clock network; this delay adjustment method is adaptive and does not require FPGA users to make specific configurations or designs. This embodiment has strong scalability. As the scale of the FPGA increases, it can significantly reduce the impact of local / overall voltage fluctuations on the clock network and improve the performance of the clock network;

[0063] In summary, this embodiment provides a voltage-insensitive FPGA clock network, which includes multiple adjustable-delay clock buffers, which are distributed at the grid nodes of the FPGA clock network; the clock buffer is used to receive local feedback information of the current clock buffer or global feedback information of the backward clock buffer corresponding to the backward node, and dynamically adjust the transmission delay according to the local feedback information or the global feedback information; the clock buffer includes a one-to-one corresponding local feedback module and a global feedback module; the local feedback module is used to obtain the local feedback information of the current clock buffer, and adaptively adjust the circuit parameters of the current clock buffer according to the local feedback information to balance the local power supply voltage fluctuation; the global feedback module is used to receive the global feedback information of the backward clock buffer through the clock tree between the current clock buffer and the backward clock buffer, and adaptively adjust the circuit parameters of the current clock buffer according to the global feedback information to balance the global power supply voltage fluctuation. This embodiment can dynamically adjust the transmission delay of the clock network by introducing a clock buffer with adjustable delay and a two-level adaptive feedback mechanism, effectively reducing the impact of power supply voltage fluctuations on the clock network, thereby significantly improving the stability and accuracy of the clock. Moreover, by precisely controlling the delay of the clock buffer, this embodiment can effectively reduce the clock jitter caused by voltage fluctuations, improve the clock performance and voltage fluctuation resistance of the FPGA, and thus enhance the reliability of the entire system. In addition, the design method of this embodiment has strong scalability and can adapt to FPGA chips of different sizes and complexities.

[0064] According to an embodiment of the present invention, an embodiment of a control method for a voltage-insensitive FPGA clock network is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0065] In this embodiment, a control method for a voltage-insensitive FPGA clock network is provided. The control method is applied to Figure 4 A voltage-insensitive FPGA clock network clock buffer is shown, as Figure 6 As shown, the process includes the following steps:

[0066] Step S601 : obtaining local feedback information of the current clock buffer based on the local feedback module, and adaptively adjusting circuit parameters of the current clock buffer according to the local feedback information to balance local power supply voltage fluctuations.

[0067] Furthermore, this embodiment uses a local feedback module to obtain local feedback information of the current clock buffer. These local feedback information contain relevant information about the clock signal in the local area where the current clock buffer is located, and may include the transmission time and signal quality of the clock signal, etc., which reflects the state of the clock signal in the local area. The local feedback module will continuously monitor the working state of the current clock buffer to obtain local feedback information. Then, the circuit parameters of the current clock buffer are adaptively adjusted according to the local feedback information obtained. The circuit parameters here may involve the bias voltage and current size of various transistors in the clock buffer, etc. Changes in these parameters will affect the transmission characteristics of the clock signal.

[0068] In an optional implementation, the step S601 includes:

[0069] If the local delay information of the current clock buffer exceeds the expected delay information, reducing the output delay of the current clock buffer;

[0070] If the local delay information of the current clock buffer is lower than the expected delay information, the output delay of the current clock buffer is increased.

[0071] Furthermore, if the local delay information of the current clock buffer exceeds the expected delay information, the output delay of the current clock buffer is reduced. This means that when the monitored local clock signal transmission delay is longer than expected, it may be due to the local power supply voltage being too high, resulting in too fast signal transmission speed. In order to return the local clock signal to a normal state, the output delay needs to be reduced. If the local delay information of the current clock buffer is lower than the expected delay information, the output delay of the current clock buffer is increased. On the contrary, when the local clock signal transmission delay is shorter than expected, it may be due to the local power supply voltage being too low, causing the signal transmission to slow down. At this time, the output delay needs to be increased.

[0072] Step S602, based on the global feedback module, global feedback information of the backward clock buffer is received between the current clock buffer and the backward clock buffer through the clock tree, and circuit parameters of the current clock buffer are adaptively adjusted according to the global feedback information to balance the global power supply voltage fluctuation.

[0073] Furthermore, the global feedback module receives the global feedback information of the backward clock buffer through the clock tree between the current clock buffer and the backward clock buffer. The clock tree is a network structure connecting the various clock buffers, through which clock signals and feedback information can be transmitted between different clock buffers. The global feedback information of the backward clock buffer contains a wider range of clock network information, which may involve the overall status of multiple clock buffers and their regions, including clock signal status, delay information, and power supply voltage information. This embodiment adaptively adjusts the circuit parameters of the current clock buffer based on the received global feedback information. Through the above-mentioned steps S601 and S602, this embodiment can dynamically adjust the circuit parameters of the clock buffer at both the local and global levels to cope with power supply voltage fluctuations in different ranges, thereby realizing a voltage-insensitive FPGA clock network and improving the performance and reliability of the entire FPGA clock network.

[0074] In summary, this embodiment can dynamically adjust the transmission delay of the clock network by introducing a clock buffer with adjustable delay and a two-level adaptive feedback mechanism, effectively reducing the impact of power supply voltage fluctuations on the clock network, thereby significantly improving the stability and accuracy of the clock. In addition, this embodiment can effectively reduce the clock jitter caused by voltage fluctuations by accurately controlling the delay of the clock buffer, improve the clock performance of the FPGA and its ability to resist voltage fluctuations, thereby enhancing the reliability of the entire system. In addition, the design method of this embodiment has strong scalability and can adapt to FPGA chips of different sizes and complexities.

[0075] The embodiment of the present invention also provides a computer device, see Figure 7 , Figure 7 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 7 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0076] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0077] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0078] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0079] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0080] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0081] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0082] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0083] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the defined scope.

Claims

1. A voltage-insensitive FPGA clock network, characterized in that: The FPGA clock network includes a plurality of clock buffers with adjustable delays, and the clock buffers are distributed at the grid nodes of the FPGA clock network; the clock buffers are used to receive local feedback information of the current clock buffer or global feedback information of the backward clock buffer corresponding to the backward node, and dynamically adjust the transmission delay according to the local feedback information or the global feedback information; The clock buffer includes a local feedback module and a global feedback module in one-to-one correspondence; The local feedback module is used to obtain local feedback information of the current clock buffer and adaptively adjust the circuit parameters of the current clock buffer according to the local feedback information to balance the local power supply voltage fluctuation; The global feedback module is used to receive global feedback information of the backward clock buffer through the clock tree between the current clock buffer and the backward clock buffer, and adaptively adjust the circuit parameters of the current clock buffer according to the global feedback information to balance the global power supply voltage fluctuation.

2. The FPGA clock network according to claim 1, characterized in that: The clock buffer is also provided with a one-to-one corresponding local delay module; The local delay module is connected to the path between the input end and the output end of the clock buffer; the local delay module is used to fine-tune the local clock signal delay of the clock buffer.

3. The FPGA clock network according to claim 2, characterized in that: In the current clock buffer, an input end of a current local feedback module corresponding to the current clock buffer is connected to an output end of a current local delay module corresponding to the current clock buffer; an output end of the current local feedback module is connected to a local feedback end of the current clock buffer; The input end of the current global feedback module corresponding to the current clock buffer is connected to the output end of the backward local delay module corresponding to the backward clock buffer; the output end of the current global feedback module is connected to the global feedback end of the current clock buffer.

4. The FPGA clock network according to claim 3, characterized in that: The local feedback module comprises: A delay monitoring unit, used for monitoring the local delay information of the current clock buffer in real time and transmitting the monitoring result to the comparison unit; The comparison unit is used to compare the local delay information with the pre-stored expected delay information, and generate a local adjustment signal according to the comparison result, and transmit it to the local feedback end of the current clock buffer to adjust the circuit parameters of the current clock buffer.

5. The FPGA clock network according to claim 3, characterized in that: The global feedback module comprises: A backward node information acquisition unit, used to acquire global feedback information of a backward clock buffer of the clock tree, wherein the global feedback information includes clock signal status, delay information, and supply voltage information of the backward clock buffer; An information processing unit is used to analyze and process the collected global feedback information, generate a global adjustment signal, and transmit the global adjustment signal to the global feedback end of the current clock buffer to uniformly coordinate and adjust the circuit parameters of the current clock buffer and balance the global power supply voltage fluctuations of the FPGA clock network.

6. The FPGA clock network according to claim 1, characterized in that: A delay unit is disposed inside each of the clock buffers, and the delay unit is used to adjust the transmission delay of the clock signal of the clock buffer.

7. A method for controlling a voltage-insensitive FPGA clock network, characterized in that: The control method is applied to a clock buffer of a voltage-insensitive FPGA clock network according to any one of claims 1 to 6, and the method comprises: Based on the local feedback module, local feedback information of the current clock buffer is obtained, and circuit parameters of the current clock buffer are adaptively adjusted according to the local feedback information to balance local power supply voltage fluctuations; Based on the global feedback module, global feedback information of the backward clock buffer is received through the clock tree between the current clock buffer and the backward clock buffer, and circuit parameters of the current clock buffer are adaptively adjusted according to the global feedback information to balance global power supply voltage fluctuations.

8. The control method according to claim 7, characterized in that: The step of adaptively adjusting the circuit parameters of the current clock buffer according to the local feedback information comprises: If the local delay information of the current clock buffer exceeds the expected delay information, reducing the output delay of the current clock buffer; If the local delay information of the current clock buffer is lower than the expected delay information, the output delay of the current clock buffer is increased.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the control method of a voltage-insensitive FPGA clock network as described in claim 7 or 8 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the control method of a voltage-insensitive FPGA clock network as described in claim 7 or 8.

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