Layout file generation method of standard cell library and electronic equipment

Abstract

The invention provides a layout file generation method of a standard cell library and electronic equipment, and relates to the technical field of standard cell library migration. The layout file generation method of the standard cell library comprises the steps that a feature evaluation function corresponding to a design rule of a target standard cell library is obtained through a target LLM, the feature evaluation function is embedded into a heuristic layout optimization algorithm, and the target LLM is obtained by training LLM through a training set generated based on layout file information; and generating a target layout file according to a heuristic layout optimization algorithm and the layout wiring template of the target standard cell library. According to the method, the LLM is specially trained by utilizing the training set generated based on the data in the field of the standard cell library, so that the LLM can quickly understand and adapt to design rule texts of different materials, different structures and different process nodes, the adaptability of the LLM to different process nodes is effectively improved, the migration capability is good, the efficiency is high, and the implementation is easy. And the adaptive development period of the standard cell library is greatly reduced.

Description

Technical Field

[0001] The present application relates to the technical field of standard cell library migration, and in particular to a method for generating a layout file of a standard cell library and an electronic device. Background Art

[0002] DTCO (Design Technology Co Optimization) can help semiconductor fabs reduce costs and time-to-market processes in advanced process development. Therefore, DTCO is used in every link of PDK (Process Design Kit) development. In DTCO applications, the layout file generation of the Stand Cell (standard cell library) is required to quickly adapt to changes in process nodes and efficiently complete cross-node migration. However, the current layout file generation method can only realize layout file generation for specific process nodes. When facing new process nodes, it often shows problems of poor adaptability and insufficient migration capabilities, making it difficult to effectively achieve cross-node migration. Summary of the invention

[0003] The embodiments of the present application provide a layout file generation method for a standard cell library and an electronic device, which can solve the problems of poor adaptability and insufficient migration capability of the existing layout file generation method when facing new process nodes.

[0004] In order to achieve this purpose, the embodiments of the present application provide the following solutions.

[0005] According to one aspect of an embodiment of the present application, a method for generating a layout file of a standard cell library is provided, the method comprising:

[0006] Using the target LLM to obtain a feature evaluation function corresponding to the design rule of the target standard cell library, and embedding the feature evaluation function into the heuristic layout optimization algorithm, wherein the target LLM is obtained by training the LLM using a training set generated based on layout file information, and the layout file information includes at least one of a process design rule file, a strategy file, and a heuristic algorithm script corresponding to the standard cell library;

[0007] A target layout file is generated according to the heuristic layout optimization algorithm and the layout and routing template of the target standard cell library.

[0008] In a possible implementation, the layout file information includes a process design rule file, a strategy file, and a heuristic algorithm script, and the acquisition of the training set includes:

[0009] Obtaining a process design rule file of a process node corresponding to a standard cell library, and constructing a rule data set according to layout and wiring rule parameters in the process design rule file;

[0010] Using the strategy file to obtain a simplified strategy description of the layout and routing corresponding to the standard cell library, and generating a strategy data set through the simplified strategy description;

[0011] Generate a script data set using the heuristic algorithm script for layout and routing;

[0012] The rule data set, the strategy data set and the script data set are combined according to a preset ratio to obtain the training set.

[0013] In one possible implementation, training the LLM includes:

[0014] Determine an LLM to be trained, train the LLM using the training set, and adjust the LLM during the training process, wherein the adjustment of the LLM includes adjusting parameters of the LLM, integrating data in a knowledge base of a standard cell library into the LLM, and optimizing a generation strategy of the LLM according to feedback information, wherein the feedback information is generated based on a generation result of the LLM.

[0015] In a possible implementation, adjusting the parameters of the LLM includes:

[0016] The attention weight matrix in the attention layer is modified using the low-rank decomposition matrix, and the low-rank decomposition matrix is ​​updated during the training process.

[0017] In a possible implementation, integrating data in a knowledge base of a standard cell library into the LLM includes:

[0018] Constructing the knowledge base, wherein the knowledge base includes process specifications, design manuals, and layout and wiring libraries;

[0019] The knowledge base is used to obtain associated data of the query information, and the associated data is injected into the LLM.

[0020] In a possible implementation, the optimizing the LLM generation strategy according to the feedback information includes:

[0021] A reward function is constructed according to the feedback information, and a generation strategy of the LLM is updated based on an optimization target, wherein the optimization target is determined based on a policy gradient algorithm and a KL divergence regularization term.

[0022] In a possible implementation, the step of using the target LLM to obtain a feature evaluation function corresponding to a design rule of a target standard cell library includes:

[0023] Obtaining a design rule text of a process node corresponding to the target standard cell, and using the target LLM to obtain key parameter information in the design rule text, wherein the key parameter information includes wiring width, spacing, and through-hole rules;

[0024] The feature evaluation function is generated according to the key parameter information.

[0025] In a possible implementation, embedding the feature evaluation function into a heuristic layout optimization algorithm includes:

[0026] The embedding method of the feature evaluation function is determined according to the type of the heuristic layout optimization algorithm, and the feature evaluation function is embedded based on the embedding method. The heuristic layout optimization algorithm includes at least one of an algorithm based on energy minimization, an algorithm based on fitness selection, and an algorithm based on reward feedback.

[0027] In a possible implementation, generating a target layout file according to the heuristic layout optimization algorithm and the layout and routing template of the target standard cell library includes:

[0028] Constructing a search space according to the layout and routing feature vector of the layout and routing template, and determining the feature evaluation function as the objective function;

[0029] A heuristic layout optimization algorithm embedded in the feature evaluation function is determined, and the target layout file is acquired using the heuristic layout optimization algorithm, the search space, and the objective function.

[0030] According to one aspect of an embodiment of the present application, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method described above.

[0031] The beneficial effects of the technical solution provided by the embodiment of the present application are:

[0032] The layout file generation method provided by the present application includes using the target LLM to obtain the feature evaluation function corresponding to the design rule of the target standard cell library, embedding the feature evaluation function into the heuristic layout optimization algorithm, the target LLM is obtained by training the LLM using the training set generated based on the layout file information, and the layout file information includes at least one of the process design rule file, strategy file, and heuristic algorithm script corresponding to the standard cell library; generating the target layout file according to the heuristic layout optimization algorithm and the layout and routing template of the target standard cell library. The present application implements the special training of the LLM using the training set generated based on the data in the field of the standard cell library, so that it can quickly understand and adapt the design rule text of different materials, different structures and different process nodes, so that when generating the layout file, it can automatically use the feature function suitable for the current process node, so as to facilitate the use of the feature evaluation function to quickly obtain the target layout file, effectively improve the adaptability facing different process nodes, have good migration ability, high migration efficiency, and greatly reduce the adaptation development cycle of the standard cell library. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in describing the embodiments of the present application.

[0034] Figure 1 A flowchart of a method for generating a layout file of a standard cell library provided in an embodiment of the present application;

[0035] Figure 2 A workflow diagram of a layout file generation method provided in an embodiment of the present application;

[0036] Figure 3 A flowchart of the training set construction provided in the embodiment of the present application;

[0037] Figure 4 A flowchart of the feature evaluation function generated by the embodiment of the present application;

[0038] Figure 5 A flowchart of LLM training provided in an embodiment of the present application;

[0039] Figure 6 A flowchart of generating a layout file using a characteristic function provided in an embodiment of the present application;

[0040] Figure 7 A layout file of a standard cell library obtained based on a layout file generation method provided in an embodiment of the present application;

[0041] Figure 8 A structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0043] It will be understood by those skilled in the art that, unless specifically stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the terms "including" and "comprising" used in the embodiments of the present application refer to that the corresponding features can be implemented as the presented features, information, data, steps, operations, elements and / or components, but do not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the present technical field. It should be understood that when we say that an element is "connected" or "coupled" to another element, the one element may be directly connected or coupled to the other element, or it may refer to that the one element and the other element establish a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein indicates at least one of the items defined by the term, for example, "A and / or B" indicates that it is implemented as "A", or is implemented as "A", or is implemented as "A and B".

[0044] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0045] The following describes several exemplary embodiments to illustrate the technical solutions of the embodiments of the present invention and the technical effects produced by the technical solutions of the present invention. It should be noted that the following embodiments can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different embodiments will not be described repeatedly.

[0046] The layout file generation method of the standard cell library and the electronic device provided in the present application are intended to solve at least one technical problem existing in the prior art.

[0047] The present application provides a method for generating a layout file of a standard cell library, such as Figure 1-Figure 7 As shown, the layout file generation method of the standard cell library includes:

[0048] S101: using a target LLM (Large Language Model) to obtain a feature evaluation function corresponding to a design rule of a target standard cell library, and embedding the feature evaluation function into a heuristic layout optimization algorithm, wherein the target LLM is obtained by training the LLM using a training set generated based on layout file information.

[0049] Optionally, the layout file information includes at least one of a process design rule file, a strategy file, and a heuristic algorithm script corresponding to the standard cell library.

[0050] Optionally, the layout file information includes a process design rule file, a strategy file, and a heuristic algorithm script. The acquisition of the training set includes: acquiring the process design rule file of the process node corresponding to the standard cell library, and constructing a rule data set according to the layout and wiring rule parameters in the process design rule file; using the strategy file to obtain a simplified strategy description of the layout and wiring corresponding to the standard cell library, and generating a strategy data set through the simplified strategy description; using the heuristic algorithm script of the layout and wiring to generate a script data set; and combining the rule data set, strategy data set, and script data set according to a preset ratio to obtain a training set.

[0051] Optionally, the process design rule file can be a PDK design rule file of a process node related to a standard cell library, and key layout and wiring rule parameters are extracted therein, including wiring width, spacing, number of metal layers and other parameters related to the layout and wiring of the standard cell library, and these parameters are used to form a rule data set Where N r is the number of process design rule files, Dr represents the rule data set, and D i i represents the i-th data of the i-th parameter in the rule data set.

[0052] Optionally, the strategy file includes a commonly used simplified strategy description for Stand Cell placement and routing, which includes description information such as symmetry, regularized grid, and pin alignment, and the simplified strategy description is used to form a strategy data set. Where N t is the number of policy files, Dt represents the policy data set, T j j represents the jth description information of the jth simplified policy description in the policy data set.

[0053] Optionally, the heuristic algorithm script for layout and routing can be a commonly used heuristic algorithm script for StandCell layout and routing, which includes layout optimization based on simulated annealing, layout and routing search based on A*, etc. These algorithm scripts are used to form a script data set. Where N s is the number of scripts, Ds represents the script dataset, S k k represents the kth script of the kth heuristic algorithm script in the script dataset.

[0054] Optionally, the rule dataset D r , Strategy Dataset D t and script dataset D s According to a certain ratio, random combination is used to form the LLM training set D = (Di , T j , S k ), where the ratio can be adjusted according to the training requirements and the rule data set D r , Strategy Dataset D t and script dataset D s Each sample (D i , T j , S k ) contains heterogeneous information in three dimensions: rules, strategies, and scripts. This heterogeneous information corresponds to the key elements in the Stand Cell migration optimization process. Among them, the layout and routing rule parameters D i Defines the hard constraints that the layout file needs to meet, simplifying the strategy description T j Provides soft guidance for layout file optimization, heuristic algorithm script S k The specific algorithm implementation for solving the optimization problem is given. By organizing these three types of information into a unified training set in a structured form, the powerful semantic understanding and generation capabilities of LLM can be used to establish an end-to-end mapping from rule text to layout and routing strategy and then to optimization script, laying the data foundation for subsequent Stand Cell automated migration.

[0055] Optionally, in order to improve the coverage and balance of the data set, data augmentation technology can be used to expand the samples in the training set, such as increasing the number of samples by randomly combining the parameters of the process design rule files in the samples, synonymously rewriting the strategy files, and generating code variants of the heuristic algorithm scripts.

[0056] In one embodiment, Figure 3As shown, the Stand Cell process design rule file, strategy file and heuristic algorithm script of the 180-55nm node of the CMOS process are obtained, and the training data set of the LLM is obtained by using these data. Specifically, key layout and wiring rule parameters such as wiring width, spacing, number of metal layers, etc. are extracted from the process design rule file to form a rule data set. The strategy file is a further explanation of the process design rules. For example, the PMOS tube and the NMOS tube are placed horizontally in two rows, the PMOS row is in the upper half of the standard cell, and the NMOS row is in the lower half of the standard cell, and the gates of the PMOS tube and the NMOS tube are aligned. When the PMOS tube and the NMOS tube share, they are connected with vertical metal; the two wide metals connected to VDD / VSS pass horizontally above the active area of ​​the PMOS tube and the active area of ​​the NMOS tube respectively; if the source and drain areas of the connected MOS tubes in the circuit are also adjacent in the layout, they are connected through the active area; if they are not adjacent, they are connected with metal wires; some MOS tubes in the unit circuit are very large in size. If they are placed without processing, they will exceed the unit boundary, so such large-size tubes need to be folded. When folding, the connectivity of the active area is considered, and the number of folds is guaranteed to be an odd number. The heuristic algorithm script is a python language script file based on the rules and simplification strategies of the 180-55nm node of the CMOS process.

[0057] Optionally, training the LLM includes: determining the LLM to be trained, training the LLM using a training set, and adjusting the LLM during the training process, wherein the adjustment of the LLM includes adjusting the parameters of the LLM, integrating data in a knowledge base of a standard cell library into the LLM, and optimizing the generation strategy of the LLM according to feedback information, and the feedback information is generated based on the generation result of the LLM.

[0058] Optionally, the LLM to be trained can be a pre-trained open source LLM M, which can be a large language model such as GPT-3, BERT, RoBERTa, etc. These models are pre-trained on large-scale general corpus, have strong natural language understanding and generation capabilities, and can serve as a good starting point for Stand Cell field adaptation.

[0059] Optionally, adjusting the parameters of the LLM includes: modifying the attention weight matrix in the attention layer using a low-rank decomposition matrix (LoRA, Low-Rank Adaptation), and updating the low-rank decomposition matrix during training.

[0060] In one embodiment, LoRA technology is used to efficiently fine-tune the parameters of LLM M. Specifically, for each attention layer of M, a low-rank decomposition matrix ΔW with rank r is introduced q , ΔW k , ΔW v , ΔWo ∈R d×r , d is the dimension of the attention weight matrix, r<<d, so as to modify the attention weight matrix in the attention layer, and the relevant expression is:

[0061] W′ q =W q +ΔW q ;

[0062] W′ k =W k +ΔW k ;

[0063] W′ o =W o +ΔW o ;

[0064] Among them, W′ q , W′ k , W′ o is the modified attention weight matrix, W q , W k , W o is the attention weight matrix before modification. During the training process, only the low-rank decomposition matrix ΔW is updated q , ΔW k , ΔW v ΔW, while keeping the original weight matrix W q , W k , W o Fixed. In this way, the amount of fine-tuning parameters can be significantly reduced and the training efficiency can be improved without changing the original model structure. At the same time, a reasonable setting of the rank r can maximize the model performance while reducing the storage and calculation overhead of the fine-tuning parameters. The specific size of the rank r can be determined based on the efficiency of model training and the accuracy of the trained model.

[0065] Optionally, data in a knowledge base of the standard cell library is integrated into the LLM, including: constructing a knowledge base, the knowledge base including process specifications, design manuals, and a layout and wiring library; using the knowledge base to obtain associated data of the query information, and injecting the associated data into the LLM.

[0066] In one embodiment, the RRRAG (Retrieval-Augmented Generation) technology can be used to integrate dynamic retrieval of data in the knowledge base into LLM. Specifically, a Stand Cell knowledge base K is constructed, which contains structured data in the Stand Cell field such as process specifications, design manuals, and layout and wiring libraries. Given an input query q, retrieve the K data most relevant to q from K. Where q is the query information of the standard cell library to be designed, c i is the i-th relevant data, p i c i The correlation score of (q,c1,...,c k ) and the spliced ​​data is used as the input of LLM to generate the target information y:

[0067] y=M(q,c1,...,c k )

[0068] During LLM training, by injecting relevant information from the knowledge base K into the LLM, the problem of insufficient coverage of pre-training corpus and annotated data in the Stand Cell field can be effectively compensated, and the LLM's professional knowledge understanding and application capabilities can be improved. The number of relevant data K to be retrieved from the knowledge base can be determined based on the size of the knowledge base and query efficiency.

[0069] Optionally, optimizing the LLM generation strategy according to the feedback information includes: constructing a reward function according to the feedback information, updating the LLM generation strategy based on an optimization target, and the optimization target is determined based on a policy gradient algorithm and a KL divergence regularization term.

[0070] In one embodiment, the feedback information can be a feedback score, and the RLHF (Reinforcement Learning from Human Feedback) technology can be used to optimize the LLM generation strategy. Collect the feedback score q of the Stand Cell expert on the LLM generation result y, q∈[0,1], and construct the reward function R(q,y) based on the feedback score q. Use the policy gradient algorithm to update the LLM generation strategy π θ , θ is the strategy parameter, and the function of the optimization objective can be:

[0071] Among them, E stands for expectation.

[0072] By maximizing the expected reward of expert feedback based on the function of this optimization objective, the LLM generation strategy can be made more in line with the actual needs and preferences of Stand Cell design.

[0073] Optionally, to avoid excessive policy updates, the optimization objective function can also introduce a KL divergence regularization term to ensure the stability of the training process. Accordingly, the optimization objective function is:

[0074]

[0075] in is the strategy before update, π θis the updated strategy, β is the regularization coefficient, D KL The design of the reward function and the adjustment of the hyperparameters are determined based on the quality of expert feedback, the efficiency of sampling, and the stability of the policy update.

[0076] Optionally, when training LLM, the training set D can be used to perform end-to-end joint training on LLM, and the advantages of LoRA, RAG and RLHF technologies can be combined to obtain the target LLM M suitable for the Stand Cell field. SC The entire training process adopts an alternating optimization approach. While updating the LLM parameters, the RAG retriever and RLHF reward model can also be fine-tuned to achieve coordinated adaptation of the three modules. During the training process, the LLM M can also be monitored by setting a validation set. SC performance, using early stopping, model integration and other methods to prevent overfitting and improve the generalization ability of the model.

[0077] The target LLM M obtained after training in the above steps SC It combines the hard constraints of process design rules, the soft guidance of layout strategies in simplified strategy files, and the algorithm implementation of optimization solutions (heuristic algorithm scripts), so that the target LLM can fully understand and apply the professional knowledge of Stand Cell. Compared with the LLM pre-trained on general corpus, M SC It has significant advantages in StandCell layout and routing migration tasks, and can generate layout and routing that meets the requirements of the new process more accurately and efficiently. At the same time, thanks to the use of LoRA and knowledge base, M SC The computational overhead during training and inference is also effectively controlled, with good practicality and scalability.

[0078] In one embodiment, Figure 4As shown in the figure, the LLM training phase mainly uses three advanced technologies, LoRA, RAG and RLHF, to improve the performance of the model in the StandCell placement and routing migration optimization task. First, the Llama open source LLM model can be selected as the local large language model, and the LoRA technology can be used to efficiently fine-tune the model parameters. Specifically, for each attention layer in the LLM, a low-rank decomposition matrix is ​​introduced to modify the attention weight matrix. During the training process, only these low-rank decomposition matrices are updated, while the original weight matrix is ​​kept fixed. This parameterized adaptation method can significantly improve the fine-tuning efficiency and generalization ability of LLM in new fields without increasing the model size. Secondly, the RAG technology is used to enhance the LLM model's understanding and application of Stand Cell domain knowledge. A Stand Cell knowledge base containing process specifications, design manuals, placement and routing libraries, etc. is constructed. In the process of generating placement and routing, given an input query (such as process nodes and cell types related to the standard cell library), the most relevant entries are retrieved from the knowledge base and integrated into the input representation of the LLM, thereby providing rich domain knowledge support for subsequent placement and routing generation. Through the RAG mechanism, LLM can flexibly utilize external structured knowledge to make up for the lack of its own training data and improve the accuracy and reliability of generated layout and routing. Finally, the RLHF technology is used to optimize the generation strategy of the LLM model. The feedback scores of Stand Cell domain experts on the layout and routing generated by LLM are collected, a reward function is constructed, and the policy gradient algorithm is used to update the generation strategy of LLM to maximize the expected reward of expert feedback. At the same time, the KL divergence regularization term is introduced to ensure the stability of strategy updates. Through RLHF, LLM can learn from the preferences and judgments of human experts, continuously adjust and improve its generation strategy, so that the content it generates is more consistent with the thinking mode and aesthetic standards of human designers (that is, it conforms to the fitness function syntax), and finally generates higher quality and more reliable Stand Cell layout and routing.

[0079] Optionally, a target LLM is used to obtain a feature evaluation function corresponding to the design rules of a target standard cell library, including: obtaining a design rule text of a process node corresponding to the target standard cell, obtaining key parameter information in the design rule text using the target LLM, the key parameter information including wiring width, spacing, and through-hole rules; and generating a feature evaluation function based on the key parameter information.

[0080] Optionally, the design rule text may be the design rule text of the new process node to which the standard cell library is to be migrated. new Input to the target LLMM SCIn the design rule text, the target LLM is used to extract key parameter information, including wiring width, spacing, through-hole rules, etc., and the key parameter information is used to form a constraint condition set. m represents the number of constraints in the set, c i represents the i-th constraint, which is formed based on key parameter information. SC The natural language understanding and generation capabilities of , map the constraint set C to the feature evaluation function A(x) in mathematical form.

[0081] Optionally, the constraint set can be filled into a mathematical template, which is used to describe the layout and routing characteristics and constraint relationships, such as routing length, line width, line spacing, etc. Specifically, the constraint set C is filled into a predefined mathematical template to generate A(x), and the analytical expression of A(x) can be:

[0082]

[0083] Where x is the characteristic vector of Stand Cell layout and routing, f i (x,c i ) is the i-th constraint condition c i The corresponding feature evaluation component.

[0084] Optionally, f i (x,c i ) can vary depending on the type of constraint, which includes indicator function, distance function, ratio function, and other types of constraints. When the constraint type is an indicator function: i (x,c i )=1(g i (x)≤c i ), where g i (x) is the i-th eigenvalue of the layout X, c i g i (x) corresponds to the constraint threshold. When the constraint type is distance function, f i (x,c i )=exp(-a i .|g i (x)-c i |), where a i is the distance scale coefficient. When the constraint type is proportional function, f i (x,c i )=min(g i (x) / c i ,1), at this time, f i (x,c i) is used to describe the degree to which a placement and routing characteristic exceeds or falls below a threshold.

[0085] Optionally, the value range of A(x) is [0,1], and a larger value indicates a higher evaluation of the layout and routing X on the new process design rule. By flexibly combining different types of feature evaluation components, a composite, multi-objective evaluation function can be obtained to comprehensively evaluate the performance of the layout and routing of the standard cell library in different constraint dimensions.

[0086] Optionally, embedding the feature evaluation function into the heuristic layout optimization algorithm includes: determining an embedding method of the feature evaluation function according to the type of the heuristic layout optimization algorithm, and embedding the feature evaluation function based on the embedding method, wherein the heuristic layout optimization algorithm includes at least one of an algorithm based on energy minimization, an algorithm based on fitness selection, and an algorithm based on reward feedback.

[0087] In one embodiment, for different heuristic layout optimization algorithms, the embedding method of the feature evaluation function A(x) of the layout and routing x is also different. For energy minimization-based algorithms such as simulated annealing, A(x) can be directly embedded as the energy function to be minimized, and the expression can be: E(x) represents the energy function. For algorithms based on fitness selection, such as genetic algorithms, A(x) can be embedded as the individual fitness evaluation function. The expression can be: fitness(x) = A(x), where fitness(x) represents the fitness evaluation function. For algorithms based on reward feedback, such as reinforcement learning, A(x) can be used as the immediate reward for the layout and routing generation action: r(x) = A(x)-A(x prev ), where r(x) represents the immediate reward, A(x prev ) represents the feature evaluation function before the layout and routing x is generated, and A(x) represents the feature evaluation function after the layout and routing x is generated.

[0088] Optionally, the embedding of the feature evaluation function can be achieved by writing it into the script of the heuristic layout optimization algorithm. Specifically, the target LLM automatically generates the Python code implementation of the feature evaluation function A(x) and writes it into the code template of the heuristic layout optimization algorithm, and finally obtains the complete, automatically generated code of the heuristic layout optimization algorithm, which can be directly compiled and executed to guide the optimization search of the Stand Cell layout and routing. The entire step realizes the end-to-end automatic mapping from the new process rule text to the layout and routing optimization objective function and then to the heuristic algorithm code, which greatly reduces the burden of manual analysis and programming.

[0089] In one embodiment, Figure 5As shown in the figure, a template-based structured mathematical modeling method is used in the automatic generation stage of feature evaluation function to map the process design rule constraints of the new process node to the objective function of layout and routing optimization. First, the process design rule text of the new process node is input into the customized Stand Cell LLM model, and the key parameter information, such as wiring width, spacing, through-hole rules, etc., is extracted to form a structured set of constraints. Then, the extracted constraints are filled into the predefined mathematical template to automatically generate the analytical expression of the feature evaluation function. The function is composed of multiple feature fitness components, each component corresponds to a constraint condition, and the type of constraint condition can be different mathematical forms such as indicator function, distance function, and proportional function. By flexibly combining these components, a composite, multi-objective layout and routing evaluation function can be obtained to comprehensively measure the advantages and disadvantages of layout and routing in different constraint dimensions. Finally, the mathematical expression of the evaluation function is converted into executable Python code by using the powerful natural language understanding and logical reasoning capabilities of the LLM model. The automatically generated evaluation function can be seamlessly embedded in the objective function interface of the heuristic optimization algorithm. In this way, an automated mapping relationship is established between process rule constraints and layout and routing optimization goals, greatly reducing the burden of manual analysis and coding.

[0090] S102: Generate a target layout file according to the heuristic layout optimization algorithm and the layout and routing template of the target standard cell library.

[0091] Optionally, a target layout file is generated according to a heuristic layout optimization algorithm and a layout and routing template of a target standard cell library, including: constructing a search space according to a layout and routing feature vector of the layout and routing template, and determining a feature evaluation function as a target function; determining a heuristic layout optimization algorithm that embeds the feature evaluation function, and obtaining a target layout file using the heuristic layout optimization algorithm, the search space, and the target function.

[0092] Optionally, the layout and routing template is the Stand Cell layout and routing template of the new process node to be migrated. Specifically, the Stand Cell layout and routing template x0 of the new process node is used as the initial solution for the optimization search, and the layout and routing feature vector thereof is extracted. The layout and routing feature vector includes the wiring topology, the pin position, etc., and the search space X is constructed using the layout and routing feature vector. The feature evaluation function A(x) is used as the objective function of the search to evaluate the quality of the layout and routing solution x, x∈X. Moreover, when performing the optimization search, different heuristic layout optimization algorithms adopt different search methods.

[0093] In one embodiment, A(x) based on energy minimization can be embedded in a simulated annealing algorithm and searched using the simulated annealing algorithm. The relevant search process is:

[0094] a) Initialize the current solution x = x0, the initial temperature T = T max , T max is the maximum temperature;

[0095] b) Randomly perturb the neighborhood of x to generate a new solution x new According to the Metropolis criterion, we accept x with probability P = min(1, exp(-ΔA / T)) new As the new current solution, where ΔA is the estimated change, ΔA = A(x new )-A(x);

[0096] c) Cooling based on the formula T=αT, where α∈(0,1) is the annealing coefficient;

[0097] d) Repeat b) and c) until T < T min Or if the new solution cannot be accepted after N consecutive iterations, the current layout and routing solution x is output, and the target layout file is obtained using the current solution.

[0098] When A(x) is a feature evaluation function based on fitness selection, A(x) can be embedded in a genetic algorithm and searched using the genetic algorithm. The relevant search process is:

[0099] a) Initialize the population Each individual x i Corresponding to a placement and routing solution;

[0100] b) Calculate the fitness of the current population according to A(x) and select individuals with higher fitness as parents;

[0101] c) Perform genetic operations such as crossover and mutation on parent individuals to generate new offspring individuals;

[0102] d) The offspring individuals and the parent individuals form a new population, and return to b);

[0103] e) After G generations of evolution, the individual X with the highest fitness in the population is output, and the target layout file is obtained according to the layout and routing solution corresponding to the individual x.

[0104] For A(x) based on reward feedback, it can be embedded in the reinforcement learning algorithm. The search process using the reinforcement learning algorithm is:

[0105] a) Initialize the layout and routing generation strategy π θ (x|s), where s is the placement and routing state and θ is the strategy parameter;

[0106] b) Under a given layout and routing state s, generate a layout and routing strategy π θ Generate a series of placement and routing actions xt For the tth placement and routing action;

[0107] c) Calculate the instant reward of each placement and routing action based on A(x), which is calculated as r t =A(x t )-A(x t-1 );

[0108] d) Use the policy gradient algorithm to update the policy parameters θ to maximize the cumulative reward R is the cumulative reward;

[0109] e) Repeat b), c), and d) until the strategy converges and output the optimized layout and routing generation strategy A target layout file is obtained according to the layout and routing generation strategy.

[0110] Optionally, a corresponding layout and routing solution is generated based on the feature vector of the layout and routing solution x and combined with the Stand Cell template library. SC The natural language generation capability of x is used to convert the structured feature description of x into human-readable layout and routing description text, which can include data such as the coordinates of each pin, the line width and layer of each wiring.

[0111] like Figure 6 As shown, the present application uses an automatically generated feature evaluation function as the optimization target in the heuristic layout and routing search optimization stage to perform intelligent search on the layout and routing solutions of the Stand Cell. First, the Stand Cell layout and routing template of the new process node is used as the initial solution for the optimization search, and the key layout and routing feature vectors are extracted to form a high-dimensional search space. The automatically generated feature evaluation function is used as the target function of the search to evaluate the pros and cons of each layout and routing solution in the search space. According to the mathematical characteristics of the evaluation function, a suitable heuristic layout optimization algorithm is selected. In the process of search and optimization, the algorithm and the feature evaluation function work closely together to continuously approach the optimal layout and routing solution through iterative optimization. Thanks to the automatically generated high-quality feature evaluation function, the search process can fully consider the design constraints of the new process node, effectively avoid design rule conflicts, and take into account multiple optimization goals such as layout and routing size, congestion, and power consumption, thereby generating a more optimized and reliable layout and routing result.

[0112] Optionally, the layout and routing description text can be converted into a layout file recognizable by EDA tools, such as GDSII, OASIS, etc. This step can utilize the API interface provided by commercial EDA software, or use an open source EDA tool chain to convert the layout and routing description text.

[0113] Optionally, after obtaining the layout and routing solution, the layout and routing corresponding to the layout and routing solution can also be verified. The verification method can be DRC (design rule check), LVS (layout corresponds to schematic) and other integrated circuit verification methods. These verification methods are used to ensure that it meets the design rule constraints of the new process node. If the verification fails, the optimization search is re-performed with the current layout and routing solution as the initial solution. If the verification passes, the layout and routing that passes the verification can be determined as the final Stand Cell layout and routing x best .

[0114] The target LLM realizes starting from a given Stand Cell rule file (layout and routing template for a new process node), using the feature evaluation function automatically generated by the LLM, guiding the heuristic layout optimization algorithm to intelligently search and optimize the layout and routing solution space, and finally obtaining the optimal layout and routing solution that meets the constraints of the new process rules. This method inherits the automatic generation mechanism of layout and routing evaluation and optimization criteria based on LLM in the process of generating the feature evaluation function, and further combines it with the mature heuristic layout optimization algorithm to form a complete Stand Cell automated migration optimization process. This application generates a feature evaluation function for the process design rule text of the new process node through the target LLM in the Stand Cell field, and writes the function into the script of the heuristic algorithm. This application can efficiently complete the automated migration and layout optimization of the Stand Cell under the new design rules, make full use of domain knowledge to guide layout and routing generation, overcome the limitations of the insufficient generalization ability of traditional methods, provide key technical support for the DTCO process, and improve the intelligence level of Stand Cell development.

[0115] In one embodiment, the target standard cell library is the Stand Cell layout and routing of the 28nm node of the CMOS process. Starting from the AN2D1 structure of the 180mm node, key features such as layout and routing topology connection and cell size are extracted, and the LLM is fine-tuned and trained using the process design rule text, simplification strategy text, and heuristic algorithm script. The LLM is used to learn expert-level knowledge of CMOS process migration and layout and routing. Then, for the 28nm node process, the target LLM is used to automatically generate a feature evaluation function, and the specific constraints of the 28nm node process on wiring width, line spacing, polysilicon spacing, placement of NMOS and PMOS tubes, through-hole layer and metal layer wiring are quantitatively considered to form a mathematical goal for layout and routing optimization. Finally, the simulated annealing algorithm is used for layout search optimization, which continuously evolves from a random layout to gradually meet various constraints such as wiring spacing, through-hole interface, PAD position, cell size, etc., while optimizing key performance. The resulting layout file is as follows: Figure 7As shown in the figure, the 28nm node AN2D1 is 36.7% smaller in area than the 180mm node AN2D1. The entire StandCell layout migration process is end-to-end automated, requiring only a brief manual confirmation of the feature functions and layout files generated by the LLM, which greatly reduces the workload of designers and shortens the development cycle of the Stand Cell library.

[0116] Compared with the prior art, the layout file generation method of the standard cell library provided in this application has the following beneficial effects:

[0117] (1) By utilizing the powerful knowledge transfer capability of LLM, StandCell can be quickly adapted and migrated under new materials, new structures, and new process nodes. Traditional deterministic algorithms and reinforcement learning methods have poor generalization capabilities and require a lot of manpower and material resources for manual adjustment and optimization when faced with new design rules. However, the present invention conducts special training on LLM in the field of StandCell, enabling it to quickly understand and adapt different design rule texts, automatically generate evaluation functions that meet new features, greatly shorten the adaptation development cycle of Stand Cell, and improve the migration efficiency across materials, structures, and process nodes.

[0118] (2) The knowledge and experience of domain experts are fully explored and utilized. Design rule files, simplified strategy texts, and corresponding heuristic algorithm scripts are used as data sets for model training. Through LoRA model adjustment, RAG data retrieval, and RLHF output alignment, the trained Stand Cell domain LLM model can well understand and apply these expert knowledge. When optimizing Stand Cell layout and routing, LLM can automatically generate an evaluation function that is highly consistent with the new features based on the new design rule text, and feed it back to the heuristic search algorithm to guide it to perform more efficient and accurate layout optimization. This method of automatically generating optimization targets using expert knowledge avoids the difficulty of manually designing complex evaluation functions and improves the optimization efficiency and layout quality of StandCell layout and routing.

[0119] (3) The end-to-end automated Stand Cell migration process highly integrates key links such as design rule understanding, layout optimization, and performance verification to form a complete set of Stand Cell development automation methods. Through the knowledge transfer and language understanding capabilities of LLM, the adaptation efficiency of Stand Cell under different materials, structures, and process nodes can be significantly improved; by automatically generating high-quality evaluation functions to guide heuristic search, the layout and routing optimization speed can be greatly accelerated; through automated performance characterization and verification processes, the Stand Cell development cycle can be shortened. This end-to-end automated migration method provides key support and enablement for the intelligence and efficiency of the DTCO process, accelerates the development progress of PDK, and has significant engineering application value.

[0120] Based on the same inventive concept, the present application also proposes an electronic device, such as Figure 8 As shown. The electronic device 4000 includes: a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, such as through a bus 4002. Optionally, the electronic device 4000 may also include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as data transmission and / or data reception. It should be noted that in actual applications, the transceiver 4004 is not limited to one, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present application.

[0121] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 4001 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0122] The bus 4002 may include a path to transmit information between the above components. The bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The bus 4002 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0123] Memory 4003 can be ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or it can be EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, optical disk storage (including compressed optical disk, laser disc, optical disk, digital versatile disc, Blu-ray disc, etc.), magnetic disk storage medium, other magnetic storage devices or any other medium that can be used to carry or store computer programs and can be read by a computer, without limitation here.

[0124] The memory 4003 is used to store the computer program for executing the embodiment of the present application, and the execution is controlled by the processor 4001. The processor 4001 is used to execute the computer program stored in the memory 4003 to implement the steps shown in the above method embodiment.

[0125] Among them, the electronic device can be any electronic product that can interact with an object, such as a personal computer, a tablet computer, a smart phone, a personal digital assistant (PDA), a game console, an interactive network television (IPTV), a smart wearable device, etc.

[0126] The electronic device may also include a network device and / or an object device, wherein the network device includes, but is not limited to, a single network server, a server group consisting of multiple network servers, or a cloud consisting of a large number of hosts or network servers based on cloud computing.

[0127] The network where the electronic device is located includes but is not limited to the Internet, a wide area network, a metropolitan area network, a local area network, a virtual private network (Virtual Private Network, VPN), etc.

[0128] The terms "first", "second", "third", "fourth", "1", "2", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that shown or described in the drawings.

[0129] It should be understood that, although each operation step is indicated by arrows in the flowchart of the embodiment of the present application, the implementation order of these steps is not limited to the order indicated by the arrows. Unless clearly stated herein, in some implementation scenarios of the embodiment of the present application, the implementation steps in each flowchart can be performed in other orders according to demand. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, and each sub-step or stage in these sub-steps or stages may also be executed at different times respectively. In different scenarios of execution time, the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiment of the present application does not limit this.

[0130] The above is only an optional implementation method for some implementation scenarios of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A method for generating a layout file of a standard cell library, characterized in that: The method comprises: Using the target LLM to obtain a feature evaluation function corresponding to the design rule of the target standard cell library, and embedding the feature evaluation function into the heuristic layout optimization algorithm, wherein the target LLM is obtained by training the LLM using a training set generated based on layout file information, and the layout file information includes at least one of a process design rule file, a strategy file, and a heuristic algorithm script corresponding to the standard cell library; A target layout file is generated according to the heuristic layout optimization algorithm and the layout and routing template of the target standard cell library.

2. The method for generating a layout file of a standard cell library according to claim 1, characterized in that: The layout file information includes a process design rule file, a strategy file, and a heuristic algorithm script. The acquisition of the training set includes: Obtaining a process design rule file of a process node corresponding to a standard cell library, and constructing a rule data set according to layout and wiring rule parameters in the process design rule file; Using the strategy file to obtain a simplified strategy description of the layout and routing corresponding to the standard cell library, and generating a strategy data set through the simplified strategy description; Generate a script data set using the heuristic algorithm script for layout and routing; The rule data set, the strategy data set and the script data set are combined according to a preset ratio to obtain the training set.

3. The method for generating a layout file of a standard cell library according to claim 1, characterized in that: Training LLM, including: Determine an LLM to be trained, train the LLM using the training set, and adjust the LLM during the training process, wherein the adjustment of the LLM includes adjusting parameters of the LLM, integrating data in a knowledge base of a standard cell library into the LLM, and optimizing a generation strategy of the LLM according to feedback information, wherein the feedback information is generated based on a generation result of the LLM.

4. The method for generating a layout file of a standard cell library according to claim 3, characterized in that: Adjust the parameters of the LLM, including: The attention weight matrix in the attention layer is modified using the low-rank decomposition matrix, and the low-rank decomposition matrix is ​​updated during the training process.

5. The method for generating a layout file of a standard cell library according to claim 3, characterized in that: The integrating the data in the knowledge base of the standard cell library into the LLM comprises: Constructing the knowledge base, wherein the knowledge base includes process specifications, design manuals, and layout and wiring libraries; The knowledge base is used to obtain associated data of the query information, and the associated data is injected into the LLM.

6. The method for generating a layout file of a standard cell library according to claim 5, characterized in that: The step of optimizing the generation strategy of the LLM according to the feedback information includes: A reward function is constructed according to the feedback information, and a generation strategy of the LLM is updated based on an optimization target, wherein the optimization target is determined based on a policy gradient algorithm and a KL divergence regularization term.

7. The method for generating a layout file of a standard cell library according to claim 1, characterized in that: The method of using the target LLM to obtain a feature evaluation function corresponding to the design rule of the target standard cell library includes: Obtaining a design rule text of a process node corresponding to the target standard cell, and using the target LLM to obtain key parameter information in the design rule text, wherein the key parameter information includes wiring width, spacing, and through-hole rules; The feature evaluation function is generated according to the key parameter information.

8. The method for generating a layout file of a standard cell library according to claim 1, characterized in that: The embedding of the feature evaluation function into the heuristic layout optimization algorithm comprises: The embedding method of the feature evaluation function is determined according to the type of the heuristic layout optimization algorithm, and the feature evaluation function is embedded based on the embedding method. The heuristic layout optimization algorithm includes at least one of an algorithm based on energy minimization, an algorithm based on fitness selection, and an algorithm based on reward feedback.

9. The method for generating a layout file of a standard cell library according to claim 7, characterized in that: The generating a target layout file according to the heuristic layout optimization algorithm and the layout and routing template of the target standard cell library includes: Constructing a search space according to a layout and routing feature vector of a layout and routing template, and determining the feature evaluation function as an objective function; A heuristic layout optimization algorithm embedded in the feature evaluation function is determined, and the target layout file is acquired using the heuristic layout optimization algorithm, the search space, and the objective function.

10. An electronic device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1-9.

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