Error correction encoding method, device and storage medium

Abstract

The application discloses an error correction coding method and device and a storage medium, and relates to the technical field of memories, and the method comprises the following steps: monitoring the running state of a storage device to obtain running state information of the storage device; when it is monitored that the running state information reaches a preset condition, obtaining a target physical address of a storage area reaching the preset condition in the storage device; when a data storage request is received, determining a target error correction coding scheme according to the target physical address; and performing error correction coding according to the target error correction coding scheme. The application can effectively improve the error correction success rate of data in a weak-keeping-capability area of the storage device, and improve the overall service life and reliability of the storage device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, in particular to an error correction coding method, device and storage medium. BACKGROUND

[0002] In 3D NAND flash, due to differences in manufacturing processes and physical properties, storage units in different layers or regions may have different endurance. Therefore, when reaching the same usage level, the edge or corner regions with poorer endurance are more prone to wear and errors.

[0003] At present, in order to reduce the error rate of 3D NAND flash during use, data is generally migrated from regions more prone to wear and errors to more stable regions through intelligent data allocation algorithms. However, in the process of data migration, additional storage and I / O resources are consumed, and the risk of data migration errors may be introduced. In addition, frequent data migration may also affect the overall performance and stability of the system.

[0004] The above content is only used to assist in understanding the technical solutions of the present application and does not represent the acknowledgement of the above content as prior art. SUMMARY

[0005] The main purpose of the present application is to provide an error correction coding method, device and storage medium, aiming to solve the technical problem of how to reduce the error rate of the storage device during use.

[0006] To achieve the above purpose, the present application provides an error correction coding method, which comprises:

[0007] Monitoring the running state of the storage device to obtain running state information of the storage device;

[0008] When it is monitored that the running state information meets a preset condition, obtaining a target physical address of a storage region in the storage device that meets the preset condition;

[0009] When receiving a data storage request, determining a target error correction coding scheme according to the target physical address;

[0010] Performing error correction coding according to the target error correction coding scheme.

[0011] In an embodiment, the running state information includes the number of erase-write times, and when it is monitored that the running state information meets a preset condition, the step of obtaining a target physical address of a storage region in the storage device that meets the preset condition comprises:

[0012] Obtaining the number of erase-write times of the storage device;

[0013] When the number of erasing and writing reaches the preset first threshold, a target physical address corresponding to each storage area in the storage device whose number of erasing and writing reaches the first threshold is obtained.

[0014] In an embodiment, before the step of monitoring the running state of the storage device to obtain the running state information of the storage device, the method further comprises:

[0015] performing an erasing and writing test on the storage device, and generating an error distribution matrix according to a test result;

[0016] calculating a weight corresponding to each error storage area according to the error distribution matrix;

[0017] determining a target error correction coding scheme according to the target physical address, comprising:

[0018] determining the error correction coding scheme of the corresponding error storage area according to the weight.

[0019] In an embodiment, the step of performing an erasing and writing test on the storage device, and generating an error distribution matrix according to a test result comprises:

[0020] obtaining the number of errors detected by the error correction coding algorithm and the logical address where the error occurs;

[0021] mapping the logical address to the physical structure of the storage device to obtain the physical address of the error storage area;

[0022] generating the error distribution matrix according to the number of errors and the physical address.

[0023] In an embodiment, the step of calculating a weight corresponding to each error storage area according to the error distribution matrix comprises:

[0024] inputting the error distribution matrix into a preset mapping function;

[0025] calculating the weight corresponding to each element in the error distribution matrix.

[0026] In an embodiment, the step of determining the error correction coding scheme of the corresponding error storage area according to the weight comprises:

[0027] grouping the error storage areas according to a preset grouping standard and the weight;

[0028] determining the error correction coding algorithm and the error correction coding check area length corresponding to each group weight according to the grouping result;

[0029] generating the error correction coding scheme according to the error correction coding algorithm and the error correction coding check area length, and there is a mapping relationship between the error correction coding scheme and the corresponding physical address.

[0030] In an embodiment, the step of error correction coding according to the target error correction coding scheme comprises:

[0031] When the target physical address receives a test storage request, the test data corresponding to the test storage request is encoded and stored according to the target error correction scheme.

[0032] In an embodiment, after the step of error correction coding according to the target error correction coding scheme, further comprising:

[0033] After reading the test data, the test data is parsed according to the target error correction scheme to obtain comparison data;

[0034] If the test data and the comparison data are inconsistent, a first error information is generated, and an error log is updated;

[0035] If the test data and the comparison data are consistent, it is determined whether the generated error cause matches a preset error pattern;

[0036] If not, a second error information is generated, and the error log is updated.

[0037] In addition, to achieve the above-mentioned purposes, the present application also provides an error correction coding device, which comprises a memory, a processor and a computer program stored on the memory and executable on the processor, and the computer program is configured to implement the steps of the error correction coding method as described above.

[0038] In addition, to achieve the above-mentioned purposes, the present application also provides a storage medium, which is a computer readable storage medium, and the storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the error correction coding method as described above.

[0039] The present application provides an error correction coding method, which continuously monitors the running state of a storage device to obtain running state information of the storage device. When it is monitored that the running state information meets a preset condition, a target physical address of a storage area in the storage device that meets the preset condition is obtained, and the target physical address can accurately locate the storage area that has a problem or meets a specific condition. When a data storage request is received, a target error correction coding scheme is determined according to the obtained target physical address, and the data to be stored is error correction coded according to the scheme.

[0040] In the present application, by triggering error correction coding according to the usage degree of the storage area, it can be avoided that due to the too high usage degree, the current error correction coding scheme cannot correct errors correctly, resulting in damaged blocks and data migration. In addition, the target error correction coding scheme is obtained according to the target physical address of the storage area, and different coding error correction schemes are configured for different storage areas, which can optimize the specific needs of each area, thereby improving the overall storage efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0041] The drawings herein are incorporated into the specification and form a part of the specification, show embodiments consistent with the present application, and together with the specification serve to explain the principles of the present application.

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0043] Figure 1 The flowchart provided for the first embodiment of the error correction coding method of the present application;

[0044] Figure 2 The detailed flowchart provided for the first embodiment of the error correction coding method of the present application;

[0045] Figure 3 The flowchart provided for the second embodiment of the error correction coding method of the present application;

[0046] Figure 4 The detailed flowchart provided for the second embodiment of the error correction coding method of the present application;

[0047] Figure 5 The flowchart provided for the third embodiment of the error correction coding method of the present application;

[0048] Figure 6 The device structure diagram of the hardware running environment involved in the error correction coding method in the embodiments of the present application. DETAILED DESCRIPTION

[0049] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application, and are not used to limit the present application.

[0050] In order to better understand the technical solutions of the present application, the following will be described in detail in conjunction with the drawings in the specification and the specific embodiments.

[0051] The main solution of the embodiment of the present application is: monitoring the running state of the storage device to obtain running state information of the storage device; when it is monitored that the running state information reaches a preset condition, obtaining a target physical address of a storage area in the storage device that reaches the preset condition; when a data storage request is received, determining a target error correction coding scheme according to the target physical address; and performing error correction coding according to the target error correction coding scheme.

[0052] At present, in order to reduce the error rate of 3D NAND flash in use, data is generally migrated from areas that are more prone to wear and error to more stable areas through an intelligent data allocation algorithm. However, in the process of data migration, additional storage and I / O resources are consumed, and the risk of data migration errors may be introduced. In addition, frequent data migration may also affect the overall performance and stability of the system.

[0053] To solve the above problems, the present application provides an error correction coding method, which continuously monitors the running state of the storage device to obtain the running state information of the storage device. When it is monitored that the running state information meets a preset condition, the target physical address of the storage area in the storage device that meets the preset condition is obtained. The target physical address can accurately locate the storage area that has a problem or meets a specific condition. When a data storage request is received, the target error correction coding scheme is determined according to the obtained target physical address, and the data to be stored is error correction coded according to the scheme.

[0054] In the present application, error correction coding is triggered according to the usage degree of the storage area, which can avoid the situation that the current error correction coding scheme cannot correctly correct errors due to high usage degree, resulting in damaged blocks and data migration. In addition, the target error correction coding scheme is determined according to the target physical address of the storage area, different coding error correction schemes are configured for different storage areas, and the specific needs of each area can be optimized, thereby improving the overall storage efficiency.

[0055] It should be noted that the execution subject of the present embodiment can be a computing service device with network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, a Nandflash (NAND flash memory) and its corresponding controller, an SSD (Solid State Disk) and its corresponding controller, etc., or an electronic device or device capable of realizing the above functions. The present embodiment and the following embodiments will be described below with the error correction coding device as an example.

[0056] Based on this, the present application provides an error correction coding method, which is described with reference to Figure 1 , Figure 1 The flowchart of the first embodiment of the error correction coding method of the present application is shown in the figure.

[0057] In this embodiment, the error correction encoding method includes steps S100-S400:

[0058] Step S100, monitor the running state of the storage device to obtain the running state information of the storage device.

[0059] It should be noted that the storage device can be a flash memory device. Flash memory, also known as flash storage or read-only memory, is a non-volatile electronic storage device. It can maintain stored data without external power supply, and has the characteristics of high information density, large amount of read and write, short random access time, etc. Flash memory changes the charge state in the floating gate by controlling the gate voltage, thereby realizing data reading and writing.

[0060] 3D NAND flash is a technology that uses three-dimensional space to stack storage cells to improve storage density. Compared with traditional 2D NAND flash, 3D NAND flash stacks multiple storage layers vertically, allowing more data to be stored in the same volume. In 3D NAND flash, high-frequency write / erase areas are more likely to reach their life limit due to frequent data operations. In a multi-layer stacked 3D NAND structure, the storage cells in the edge or corner areas may have lower durability due to manufacturing process limitations. In the storage device, the storage cells in the areas close to the heat source or poor heat dissipation are more likely to have errors and wear in high-temperature environments.

[0061] In this embodiment, the running state information is obtained by checking the system log of the operating system or the SSD (Solid State Drive) log. Performance monitors can also be used to add flash or SSD-related counters that you want to monitor. By counting the real-time data of these counters, the running state and usage of the flash memory can be evaluated. The running state information can include read / write speed, response time, amount of data written, and program / erase count. Running state information can help predict the remaining life information of the flash memory.

[0062] Step S200, when the running state information reaches the preset condition, obtain the target physical address of the storage area in the storage device that reaches the preset condition.

[0063] It should be noted that the physical address usually includes multiple parts for uniquely identifying each storage cell in the flash memory chip. These parts may include block address, page address, column address, etc.

[0064] In this embodiment, when a storage request is obtained, a logical address is allocated for the data to be stored based on the type and parameters of the storage request, the data is accessed through the logical address, the flash memory controller maps the logical address to a physical address inside the flash memory, and performs a storage operation to write the data to a specified physical address location in the flash memory. When the use stage of the target storage area changes, it indicates that the use degree of the storage area is too high and enters the late life stage, and the remaining service life is small.

[0065] Please refer to Figure 2 In a possible implementation, the running state information includes the number of erase-write times, and step S200 can include steps S210-S220.

[0066] In step S210, the number of erase-write times of the storage device is obtained.

[0067] In step S220, when the number of erase-write times reaches a preset first threshold, the target physical address corresponding to each storage area whose number of erase-write times reaches the first threshold in the storage device is obtained.

[0068] It should be noted that in the flash memory, the erase-write operation (P / E, Program / Erase) is a programming operation and an erasing operation. The programming operation (P, Program), also known as the write operation, refers to the process of writing data into a flash memory cell. The erasing operation (E, Erase) is the process of clearing the data in the flash memory cell to restore it to the initial state. The number of erase-write times refers to the fact that after a certain number of programming write and erasing operations, the performance of each storage cell will decrease significantly, and it may even be unable to reliably store data. This is due to the physical characteristics of the flash memory, which cause a certain amount of wear on the storage cell with each erase-write operation. In the flash memory, the smallest unit of the erasing operation is usually a block (Block), a sub-block (Subblock), or a deck (Deck). The smallest unit of the write operation is usually a page (Page). The complete process of a programming and an erasing of a flash memory cell is called a P / E cycle. Due to the physical characteristics of the flash memory cell, each P / E cycle causes a certain amount of wear on it. The number of P / E cycles is an important indicator of the service life of the flash memory. As the number of P / E cycles increases, the performance of the flash memory cell gradually decreases, and eventually it may no longer be able to reliably store data.

[0069] In addition, it should be noted that the physical address is a unique identifier for each storage cell inside the flash memory. When you want to access a certain data in the flash memory, you need to know which physical address the data is stored in. Then, the flash memory controller will find the corresponding storage cell according to this physical address to read or write data.

[0070] In this embodiment, the erase-write count of the storage device is monitored according to a preset period or in real time. The erase-write count is used to evaluate the usage stage and wear level of each storage area of the flash memory. The erase-write operation is monitored, and the erase-write count can be obtained according to an interface for monitoring the erase-write operation of the flash memory. The interface can include an interrupt service routine, an event callback of a file system layer, or a special flash memory management API. One or more callback functions are registered to respond to the erase-write event, and the callback functions are called each time the erase-write operation occurs. Inside the callback functions, detailed information of the erase-write event is captured, including the address of the block or page that is erased. According to the captured address information, the specific range (which can be a single block, a page, or a part of a page) that is erased is determined. Finally, according to the erase-write range, the erase-write count counter of the corresponding block or page is updated. If the erase-write operation spans multiple blocks or pages, the counters of the blocks or pages are updated respectively.

[0071] When the erase-write count of the flash memory reaches a preset first threshold, the target physical address information of the erase-write event is obtained, and all the target physical address information is recorded. Exemplarily, the expected lifetime of a 3D NAND flash memory device is 3000 erase-writes, the first threshold is 40% of the total erase-write count, i.e., 1200 erase-writes, and the second threshold is 80% of the total erase-write count, i.e., 2400 erase-writes.

[0072] In this embodiment, by setting the first threshold and dynamically adjusting the error correction coding strategy when the first threshold is reached, the success rate of error correction is improved. The number of jumps in the data stored in the storage device increases as the erase-write count increases. When the erase-write count reaches a certain threshold, the number of jumps in the data stored in the storage device increases to a degree that cannot be corrected by error coding, and thus the data cannot be read out. At this time, a new error correction coding scheme is obtained, such as upgrading from the BCH algorithm to the LDPC algorithm, and the length of the check area is increased, which can significantly enhance the error correction capability, thereby allowing the flash memory to withstand more erase-write counts without losing data.

[0073] In another possible embodiment, the usage stage of the storage device can also be evaluated according to the write amount of the flash memory unit. When the monitoring system detects that the write amount of a certain storage area reaches a preset condition, the target physical address of the storage area is recorded and obtained.

[0074] Exemplarily, it is assumed that there is an SSD with a capacity of 1 TB, which includes multiple storage areas, each with an expected size of 256 MB. When the write amount of any storage area reaches 60% of its capacity, the physical address thereof is recorded. When the write amount of any storage area reaches 80% of its capacity, the physical address thereof is recorded.

[0075] In step S300, when a data storage request is received, the target error correction coding scheme is determined according to the target physical address.

[0076] At step S400, error correction coding is performed according to the target error correction coding scheme.

[0077] It should be noted that the role of error correction coding (ECC) is to detect and correct errors in stored data. Due to various factors, data errors may occur during the process of storing data in flash memory. Error correction coding can automatically detect and correct these errors when reading data, ensuring the accuracy and reliability of the data. The length of the check area is closely related to the error correction capability of the error correction coding. The stronger the error correction capability of the error correction coding, the more check data it needs, and therefore the longer the length of the check area.

[0078] In this embodiment, the corresponding target error correction coding scheme can be determined through the mapping relationship between the physical address and the error correction scheme. An address mapping table is set up to record the mapping relationship between each physical address and the corresponding error correction coding. This mapping table can be adjusted as needed during system operation. When the target error correction scheme associated with a specific target physical address is needed, the corresponding entry of the address is searched in the address mapping table. This search process can be direct indexing (if the mapping table is arranged in physical address order), or a more complex search algorithm (if the mapping table is unordered or uses compression technology).

[0079] For example, a flash memory system contains 100 physical blocks, each block has a unique physical address. In order to optimize performance and reliability, different ECC check area lengths are set for these blocks: blocks with physical addresses 0-49 use 16-byte ECC check area. Blocks with physical addresses 50-74 use 24-byte ECC check area to improve the error correction capability of these blocks. Blocks with physical addresses 75-99 use 32-byte ECC check area because these blocks are more likely to be disturbed or damaged.

[0080] In this embodiment, by detecting the state of the target flash memory, it is determined whether the usage degree of the storage area in the target flash memory reaches the preset condition. When the storage area reaches the preset condition, the target error correction coding scheme is obtained to perform error correction coding, which can trigger the operation of error correction coding according to the usage degree of the storage area, and avoid the performance reduction of the flash memory device caused by the high usage degree. According to the preset mapping relationship, the error correction scheme corresponding to the storage area is obtained, different coding error correction schemes are configured for different storage areas, the capacity of data storage is maximized while improving the data reliability and the performance of the storage device, and the influence of the reduction of data capacity caused by the increase of the length of the check area in the coding scheme is reduced.

[0081] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as the above-mentioned embodiment one can refer to the above introduction, and the subsequent will not be described in detail. On this basis, please refer to Figure 3 Before step S100, the error correction coding method further includes steps A100-A200:

[0082] In step A100, the storage device is subjected to erasing and writing test, and an error distribution matrix is generated according to the test result.

[0083] In this embodiment, the storage device is subjected to erasing and writing test in a certain period. Alternatively, this period can be a fixed time interval, such as once a month, once a quarter or once a year. It can also be triggered based on certain conditions, such as when the error rate of a certain area exceeds the preset threshold.

[0084] In step A200, the weight corresponding to each error storage area is calculated according to the error distribution matrix.

[0085] In this embodiment, the following data is obtained and recorded during the erasing and writing test of the storage device: (1) error rate: the number of errors or error rate of each area in the last evaluation period. (2) usage frequency: the data read and write frequency of each area, which may also include writing mode (such as sequential writing, random writing, etc.) and data type (such as metadata, user data, etc.). (3) other related factors: such as environmental temperature, system load and other factors that may affect the performance and error rate of flash memory. After the collection of error information is completed, the error distribution matrix is generated according to the collected data.

[0086] In this embodiment, the weight of each area is calculated. The calculation method of the weight can be based on the combination of error rate, usage frequency and other related factors. For example, a weighted sum method can be used, and a weight coefficient is assigned to each factor, and then the weighted sum is calculated as the final weight of the area. In order to simplify the process and ensure the smooth progress of periodic evaluation and adjustment, the system management tool or script is used to periodically perform data collection, weight calculation, evaluation and adjustment tasks, and monitor the system state to detect any potential abnormalities or problems. Exemplarily, in an automated script process, cron job (Linux) or task scheduler (Windows) is used to set scripts that are executed periodically. The script collects the necessary data from the flash memory controller or system log, and calls a function or program to calculate the weight of each area.

[0087] In a possible implementation, please refer to Figure 4 Step A100 can further include steps A110-A130:

[0088] A110, obtaining the number of errors detected by the error correction coding algorithm and the logical address where the error occurs.

[0089] A120, mapping the logical address to the physical structure of the storage device to obtain the physical address of the error storage area.

[0090] In this embodiment, the number of errors and the location information can be confirmed from the statistical data generated by the ECC (Error Correction Code) mechanism. After obtaining the error information, the location information needs to be converted into a physical address in order to accurately locate the specific location of the error in the memory. The location information in the ECC error log can appear in various forms, such as memory slot number, memory channel number, memory rank number, memory bank number, etc. Different servers and memory configurations may have different memory mapping methods and address coding rules. According to different memory mapping methods and address coding rules, the address is converted, and the location information (such as slot number, channel number, etc.) is combined with the base address, offset or index value to obtain the final physical address.

[0091] Exemplarily, finding the part about memory mapping in the document, obtaining the description of the organization of the memory, can include: (1) Slot number: the number and location of each memory slot. (2) Channel number: if multi-channel technology is supported (such as dual-channel for DDR4), how each channel is allocated. (3) Rank and Bank: the organization within the memory module, how each rank and bank affects the address space. (3) Base address and size: the starting address of each slot, channel, rank, and bank and its size in the physical address space. Suppose the document states that the base address of slot 1 is 0x00000000 and the size is 2GB (i.e. 0x80000000). Each slot supports single-channel, each channel contains two ranks, and each rank has two banks. In the obtained error location information, it is pointed out that the error occurs at a certain location of "slot 1, channel 0, rank 0, bank 1". It is known from the document that the base address of slot 1 is 0x00000000. Suppose the size of each rank is 1GB (i.e. 0x40000000), and the offset between banks can be defined by the manufacturer, which is assumed to be half of the size of the rank (i.e. 0x20000000) here. Therefore, the base address of rank 0 is 0x00000000, and the offset of bank 1 is 0x20000000. Adding the base address to the offset of the rank and bank gives the starting point of the physical address. In this example, the starting point of the physical address is 0x00000000 + 0x20000000 = 0x20000000. When the error location information provides a specific byte offset (such as 0x12345678), it is added to the starting address to obtain the final physical address 0x20000000 + 0x12345678 = 0x32345678.

[0092] In a possible implementation, some server manufacturers can provide dedicated management tools or diagnostic software, which can directly display the physical address of the ECC error.

[0093] A130, generating an error distribution matrix according to the number of errors and the physical address of the error.

[0094] In this embodiment, the error distribution matrix is based on the number of errors and the physical address of the error. A hash table (or dictionary) can be used to store the key-value pair relationship between the number of errors and the physical address of the error. After obtaining each physical address and its corresponding number of errors, the data is traversed, and for each physical address and number of errors, the hash table is updated. If the address already exists, the number of errors is accumulated; if it does not exist, a new entry is created. When the error distribution is represented in the form of a matrix, first, the address range is determined, and a two-dimensional list is created according to this range, with all initial values being 0. Second, the number of errors in the hash table is distributed to the corresponding positions of the matrix, thereby obtaining the error distribution matrix.

[0095] In one possible implementation, step A200 can further include steps A210-A220:

[0096] Step A210, input the error distribution matrix into a preset mapping function.

[0097] Step A220, calculate the weight value corresponding to each element in the error distribution matrix.

[0098] In this embodiment, the weight is calculated by the preset mapping function and the specific value of the error number. First, the minimum and maximum values of the error number in your data set need to be determined. Suppose the minimum error number is min_error and the maximum error number is max_error. In the preset mapping function f(x), x is the error number and f(x) is the calculated weight. When x = min_error, f(x) = 0 (or a small value very close to 0 to avoid division by 0) When x = max_error, f(x) = 1.

[0099] Optionally, the weight is calculated using linear interpolation. Its function form is: f(x) = max_error - min_error + 2∈x - min_error + ∈. Where ∈ is a very small positive number (such as 0.001) to avoid division by 0 and ensure that when x = min_error, f(x) is close to but not equal to 0.

[0100] Optionally, the weight is calculated using a sigmoid function. Its function form is: f(x) = 1 / 1 + e-k(x-mid), where k controls the steepness of the function (i.e. the slope), and mid is the center point of the function (which can be set to (min_error + max_error) / 2). The values of mid and k can be adjusted appropriately.

[0101] In one possible implementation, determining the target error correction coding scheme according to the target physical address can include the following steps:

[0102] Grouping the error storage areas according to the preset division standard and the weight.

[0103] According to the grouping result, determine the error correction coding algorithm and the error correction coding check area length corresponding to the weight of each group.

[0104] According to the error correction coding algorithm and the error correction coding check area length, generate an error correction coding scheme, and the error correction coding scheme and the corresponding physical address have a mapping relationship.

[0105] In this embodiment, the regions can be grouped based on the size of the weight and a pre-set threshold, and different check area lengths are set for each group. First, the weight matrix is obtained, which is usually a two-dimensional array, where each element represents a specific weight value. After obtaining the weight matrix, the entire weight matrix is traversed by programming to extract each weight value. Second, the corresponding error storage area is grouped according to the pre-set range standard and the size of the weight, and the pre-set range standard can be dynamically adjusted according to actual needs. Finally, different check area lengths are set for each group of error storage areas. The check area length can be determined based on the importance of the weight value, the frequency of data update, or the limitation of storage space, etc.

[0106] In this embodiment, by setting different check area lengths for error storage areas with different weights, more check area lengths are allocated to storage areas with weak retention capabilities to improve data reliability, and fewer check area lengths are allocated to storage areas with strong retention capabilities to save storage space. In addition, by reasonable partitioning and check area length setting, the physical layout of data can be optimized, the addressing time and delay during data access can be reduced, and thus the data access speed can be improved.

[0107] In another possible implementation, grouping can be a simple division based on thresholds (for example, dividing regions with error counts higher than a certain threshold into "high error regions"), or a more complex clustering method (such as K-means clustering) to identify regions with similar error characteristics. After dividing the regions, calculate the attention weight for each region. Extract features for each region, which can include the average error count of the region, the standard deviation of the error density, the size of the region, etc. Design a model to calculate the attention weight based on the extracted features. This model can be a simple rule (such as the higher the error count, the higher the weight of the region), or a more complex machine learning model (such as a neural network). Finally, apply the calculated attention weight to the original data or the intermediate representation of the model, and the regions with high weight will be considered more carefully or given higher priority.

[0108] In this embodiment, there is an address mapping table in the flash memory system, which records the mapping relationship between each physical address and the corresponding ECC configuration (including the length of the check area). This mapping table can be adjusted as needed during system operation. When the ECC check area length related to a specific target physical address is needed, the system will look up the entry corresponding to the address in the address mapping table. This lookup process can be direct indexing (if the mapping table is arranged in physical address order), or a more complex search algorithm (if the mapping table is unordered or uses compression technology). Once the entry of the target physical address is found in the mapping table, the length of the check area stored in the entry is read.

[0109] For example, a flash memory system contains 100 physical blocks, each of which has a unique physical address. In order to optimize performance and reliability, different ECC check area lengths are set for these blocks:

[0110] The blocks with physical addresses 0-49 use a 16-byte ECC check area. The blocks with physical addresses 50-74 use a 24-byte ECC check area to improve the error correction capability of these blocks. The blocks with physical addresses 75-99 use a 32-byte ECC check area because these blocks are more likely to be disturbed or damaged.

[0111] In this embodiment, a mapping table or function is established according to the positive correlation between the region weight and the check bit length, which defines the check bit length corresponding to different weight ranges. After the mapping relationship is established, the error rate and weight of each region can be evaluated regularly, and the check bit length can be adjusted according to the evaluation results, and the mapping relationship can be updated. For example, a dynamic optimization method is used to adjust the check bit length. Machine learning algorithms are used to train historical data to predict future error rate trends and adjust the check bit length accordingly.

[0112] For example, the following mapping relationship can be set: the region with a weight lower than X1 has a check bit length of N1; the region with a weight between X1 and X2 has a check bit length of N2; the region with a weight higher than X2 has a check bit length of N3, and N3>N2>N1.

[0113] In this embodiment, by selecting different check area length gears for different storage regions, different encoding error correction schemes can be configured for different storage regions, and higher check area length can be set for regions that are more prone to wear and error. While improving data reliability and storage device performance, the capacity of data storage is maximized, and the impact of reduced data capacity due to increased check area length is minimized.

[0114] Based on the first embodiment of the present application, in the third embodiment of the present application, the same or similar contents as the above-mentioned first embodiment can be referred to the above introduction, and the following will not be repeated. On this basis, please refer to Figure 5 , after step S400, further comprising steps S500-S800:

[0115] Step S500, after reading the test data corresponding to the data storage request, the test data is parsed according to the target error correction scheme to obtain the comparison data.

[0116] Step S600, if the test data and the comparison data are inconsistent, a first error information is generated, and an error log is updated.

[0117] In this embodiment, the test data includes pre-injected specific error patterns. These error-containing data are written into the storage device. When the data are read and decoded, the decoded data can be compared with the original data to evaluate the performance of the error correction coding scheme.

[0118] In this embodiment, when a test storage request for a specific target physical address is received, the request usually contains the data to be written and the associated error correction coding scheme information. According to the test storage request, the test data is extracted from the request. The target error correction coding scheme is applied to the test data for encoding processing, and the test data is written into the target physical address. After the test data is written, the data just written is read from the target physical address. The read data is decoded using the same target error correction coding scheme to attempt to correct the possible errors in the data. The decoded data is referred to as the comparison data. The decoded comparison data is compared with the original test data to check whether the error correction coding scheme can correctly detect and correct errors. If the test data and the comparison data are found to be inconsistent during the comparison, the storage device or the associated test system should issue an error prompt. This prompt can be a simple status code, an error message, or more detailed diagnostic information to help locate the cause of the problem.

[0119] Step S700, if the test data and the comparison data are consistent, it is determined whether the generated error cause matches the pre-set error pattern;

[0120] Step S800, if the error cause does not match the pre-set error pattern, a second error information is generated, and the error log is updated.

[0121] In this embodiment, the error log or status information related to the reading and decoding process is checked. The detected error cause is matched with the pre-injected error pattern. If the decoded data is consistent with the original data, but the given error cause does not match the pre-set error pattern, a second error prompt is generated. The second error information is added to the error log for subsequent analysis and processing. The error log should contain sufficient information to track the source, time of occurrence, and context of the error.

[0122] In the embodiment, when the error correction fails and the target error correction coding scheme is considered to be updated, it can be verified whether the check bit length can meet the requirement of the number of errors. In the verification process, the theoretical error correction capability of the error correction coding in the target error correction coding scheme can be calculated. For example, in the LDPC code, the minimum code distance d of the LDPC code should satisfy d≥2t+1 to be able to correct t errors. The determined number of errors is compared with the calculated theoretical error correction capability. If the number of errors is less than or equal to the error correction capability, the error correction should be successful in theory. If the number of errors is greater than the error correction capability, the current check bit length is insufficient to correct all errors. Then the target error correction coding scheme needs to be updated, and the check bit length needs to be increased to improve the error correction capability.

[0123] Through the above steps, when the error correction fails, the target error correction coding scheme can be appropriately updated, and the reliability of the data and the stability of the system can be improved by verifying whether the check bit length meets the requirement of the number of errors.

[0124] The present application provides an error correction coding device, comprising: at least one processor; and a memory connected in communication with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the error correction coding method in the above embodiment one.

[0125] Reference will now be made to Figure 6 , which shows a structural schematic diagram of an error correction coding device suitable for implementing the embodiments of the present application. The error correction coding device in the embodiments of the present application can include, but is not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (Personal Digital Assistant), PADs (Portable Application Description), PMPs (Portable Media Player), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), and the like, and fixed terminals such as digital TVs, desktop computers, and the like. Figure 6 The error correction coding device shown is only an example, and should not bring any limitation to the functions and use range of the embodiments of the present application.

[0126] As Figure 6As shown, the error correction encoding device can include a processing apparatus 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to a program stored in a read only memory (ROM) 1002 or a program loaded from a storage apparatus 1003 into a random access memory (RAM) 1004. In the RAM 1004, various programs and data required for operation of the error correction encoding device are also stored. The processing apparatus 1001, the ROM 1002, and the RAM 1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input apparatus 1007 including, for example, a touch panel, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output apparatus 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; the storage apparatus 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication apparatus 1009. The communication apparatus 1009 can allow the error correction encoding device to communicate with other devices wirelessly or by wire to exchange data. Although the error correction encoding device having various systems is shown in the figure, it should be understood that all the shown systems are not required to be implemented or possessed. More or less systems can be alternatively implemented or possessed.

[0127] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product comprising a computer program carried on a computer readable medium, the computer program containing program codes for executing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network through the communication apparatus, or installed from the storage apparatus 1003, or installed from the ROM 1002. When the computer program is executed by the processing apparatus 1001, the above-mentioned functions defined in the methods of the embodiments disclosed in the present application are performed.

[0128] The error correction encoding device provided in the present application adopts the error correction encoding method in the above-mentioned embodiments, and can solve the technical problem of how to reduce the error rate of the storage device in use. Compared with the prior art, the error correction encoding device provided in the present application has the same beneficial effects as the error correction encoding method provided in the above-mentioned embodiments, and other technical features in the error correction encoding device are the same as the features disclosed in the previous embodiment method, which will not be repeated here.

[0129] It should be understood that various aspects of the disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any appropriate manner in any one or more embodiments or examples.

[0130] The above description is merely illustrative of the application and is not intended to limit the scope of the application. Any variations and modifications that can be made by any person skilled in the art within the spirit and scope of the application are intended to be encompassed by the application. The scope of the application is defined by the appended claims.

[0131] The application provides a computer readable storage medium having stored thereon computer readable program instructions (i.e., a computer program) for performing the error correction encoding method in the above-described embodiments.

[0132] The computer readable storage medium provided by the application may, for example, be a U disk, but is not limited to an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, system, or device, or any combination thereof. More specific examples of the computer readable storage medium can include, but are not limited to, an electrical connection having one or more conductive wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any appropriate combination thereof. In the present embodiment, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer readable storage medium can be transmitted in any appropriate medium, including but not limited to an electrical wire, an optical cable, an RF (Radio Frequency), etc., or any appropriate combination thereof.

[0133] The above computer readable storage medium can be included in an error correction encoding device; or can exist separately and not be assembled into an error correction encoding device.

[0134] The computer readable storage medium described above carries one or more programs, when the one or more programs are executed by the error correction coding device, the error correction coding device is caused to: monitor a running state of the storage device to obtain running state information of the storage device; when it is monitored that the running state information reaches a preset condition, obtain a target physical address of a storage area reaching the preset condition in the storage device; when a data storage request is received, determine a target error correction coding scheme according to the target physical address; and perform error correction coding according to the target error correction coding scheme.

[0135] Computer program code for carrying out operations of the present application can be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider).

[0136] The flow diagrams and the block diagrams in the drawings are illustrations of architectures, functionalities, and operations of possible implementations of systems, methods, and computer program products according to various embodiments of present application. In this regard, each block in the flow diagrams or block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or operations, or combinations of special purpose hardware and computer instructions.

[0137] The modules involved in the embodiments of the present application can be implemented in the manner of software or in the manner of hardware. Among them, the name of the module does not constitute a limitation to the unit itself in some cases.

[0138] The readable storage medium provided by the application is a computer readable storage medium, which stores computer readable program instructions (i.e. computer programs) for executing the error correction coding method described above, and can solve the technical problem of how to reduce the error rate of the storage device during use. Compared with the prior art, the beneficial effects of the computer readable storage medium provided by the application are the same as those of the error correction coding method provided by the above-mentioned embodiments, and are not described here.

[0139] The above is only part of the embodiments of the application, and does not limit the patent scope of the application. Any equivalent structural transformation made by using the content of the application specification and drawings, or direct / indirect application in other related technical fields is included in the patent protection scope of the application.

Claims

1. An error correction encoding method characterized by, The method comprises: performing erase-write test on the storage device, and generating an error distribution matrix according to a test result; calculating a weight corresponding to each error storage area according to the error distribution matrix; monitoring a running state of the storage device to obtain running state information of the storage device; when the running state information reaches a preset condition, obtaining a target physical address of a storage area in the storage device that reaches the preset condition; when receiving a data storage request, determining a target error correction coding scheme according to the target physical address, comprising: determining the target error correction coding scheme corresponding to the error storage area according to the weight; performing error correction coding according to the target error correction coding scheme.

2. The error correction encoding method of claim 1, wherein, The running state information comprises an erase-write number, and the step of obtaining the target physical address of the storage area in the storage device that reaches the preset condition when the running state information reaches the preset condition comprises: obtaining the erase-write number of the storage device; when the erase-write number reaches a preset first threshold, obtaining a target physical address corresponding to each storage area in the storage device whose erase-write number reaches the first threshold.

3. The error correction encoding method of claim 1, wherein The step of performing erase-write test on the storage device and generating an error distribution matrix according to a test result comprises: obtaining an error number detected by an error correction coding algorithm and a logical address where an error occurs; mapping the logical address to a physical structure of the storage device to obtain a physical address of the error storage area; generating the error distribution matrix according to the error number and the physical address.

4. The error correction encoding method of claim 1, wherein, The step of calculating a weight corresponding to each error storage area according to the error distribution matrix comprises: inputting the error distribution matrix into a preset mapping function; calculating a weight corresponding to each element in the error distribution matrix.

5. The error correction encoding method of claim 1, wherein, The step of determining an error correction coding scheme corresponding to the error storage area according to the weight comprises: grouping the error storage areas according to a preset grouping standard and the weight; determining an error correction coding algorithm and an error correction coding check area length corresponding to the weight of each group according to a grouping result; generating an error correction coding scheme according to the error correction coding algorithm and the error correction coding check area length, wherein the error correction coding scheme and the corresponding physical address have a mapping relationship.

6. The error correction encoding method of claim 1, wherein, The step of performing error correction coding according to the target error correction coding scheme comprises: when the target physical address receives a test storage request, encoding and storing test data corresponding to the test storage request according to the target error correction coding scheme.

7. The error correction encoding method according to any one of claims 1 to 6, characterized by, After the step of performing error correction coding according to the target error correction coding scheme, the error correction coding method further comprises: after reading the test data corresponding to the data storage request, analyzing the test data according to the target error correction coding scheme to obtain comparison data; if the test data and the comparison data are inconsistent, generating first error information and updating an error log; if the test data and the comparison data are consistent, determining whether a generated error cause matches a preset error mode. If not, a second error message is generated and the error log is updated.

8. An error correction encoding device characterized by comprising: The device comprises a memory, a processor and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the error correction encoding method according to any one of claims 1 to 7.

9. A storage medium, characterized by The storage medium is a computer readable storage medium, and the storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the error correction encoding method according to any one of claims 1 to 7.

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