Manufacturing method of side wall for embedded SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory

Abstract

The invention provides a method for manufacturing a side wall for an embedded SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory, which comprises the following steps of: providing a substrate, and forming a logic region with an L-shaped side wall and a gate outer layer of SONOS on the substrate; forming a metal silicide layer above the active region and the grid electrode; depositing silicon nitride as an etching stop layer; growing a sacrificial oxide layer on the surface of the etching stop layer; etching the sacrificial oxide layer to change the logic region and the gate outer layer of the SONOS into a D-type side wall from an L-type side wall; depositing an interlayer dielectric layer; and etching the interlayer dielectric layer to form a through hole, and depositing metal in the through hole. According to the invention, the logic region and the gate outer layer of the SONOS are changed from an L-shaped side wall to a D-shaped side wall, and the D-shaped side wall is stable in morphology and large in etching window, thereby facilitating the subsequent filling of the interlayer dielectric layer, avoiding the generation of cavity defects in the filling process, and improving the device yield.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to a method for manufacturing a sidewall of an embedded SONOS memory. Background Art

[0002] In the traditional embedded SONOS (flash memory) memory manufacturing process, such as Figure 1 As shown, the outer layer of the logic area and the gate of SONOS is composed of silicon nitride and silicon oxide to form an "L"-shaped side wall. Void defects will appear during the filling process of the boron phosphorus doped silicon oxide (BPSG) interlayer dielectric between adjacent gates, which is not conducive to the subsequent etching of the through hole and the deposition of tungsten metal. Summary of the invention

[0003] In view of this, the present invention provides a method for manufacturing a sidewall for an embedded SONOS memory, which is used to change the "L"-shaped sidewall of the logic area and the outer layer of the SONOS gate into a "D"-shaped sidewall. Its unique morphology is conducive to the subsequent filling of the interlayer dielectric layer and avoids the generation of void defects.

[0004] The present invention provides a method for manufacturing a sidewall of an embedded SONOS memory, comprising the following steps:

[0005] Step 1: providing a substrate, and forming a logic region with an L-shaped sidewall and a gate outer layer of SONOS on the substrate;

[0006] Step 2: forming a metal silicide layer on the active area and the gate;

[0007] Step 3, depositing silicon nitride as an etch stop layer;

[0008] Step 4: growing a sacrificial oxide layer on the surface of the etch stop layer;

[0009] Step 5, etching the sacrificial oxide layer to change the outer layer of the logic area and the gate of the SONOS from an L-shaped sidewall to a D-shaped sidewall;

[0010] Step 6: depositing an interlayer dielectric layer;

[0011] Step seven: etching the interlayer dielectric layer to form a through hole, and depositing metal in the through hole.

[0012] Preferably, the substrate in step one is a silicon substrate.

[0013] Preferably, the L-shaped sidewall in step 1 comprises an oxide layer and a silicon nitride layer.

[0014] Preferably, the metal silicide layer in step 2 is cobalt silicide.

[0015] Preferably, the sacrificial oxide layer in step 4 is a silicon oxide layer, which is formed by thermal oxygen growth.

[0016] Preferably, the etching in step five is a plasma etching process.

[0017] Preferably, the interlayer dielectric layer in step six is ​​made of BPSG.

[0018] Preferably, the metal in step seven is tungsten.

[0019] The present invention changes the morphology of the sidewalls, and changes the outer layer of the gate of the logic area and the SONOS from an L-shaped sidewall to a D-shaped sidewall. The formed D-shaped sidewall has a stable morphology and a large etching window, which is beneficial to the subsequent filling of the interlayer dielectric layer, avoids the generation of void defects during the filling process, and improves the device yield. In addition, the present invention directly improves the morphology of the gate sidewall, ensures the gate oxide integrity of the logic area and the SONOS, and the method is simple and efficient, saving manufacturing costs and development time. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0021] Figure 1 Shown is a schematic diagram of the structure of a conventional embedded SONOS memory;

[0022] Figure 2 A flow chart showing a method for manufacturing a spacer for an embedded SONOS memory according to an embodiment of the present invention;

[0023] Figures 3 to 8 It is a schematic structural diagram of each step of a method for manufacturing a sidewall of an embedded SONOS memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0025] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0026] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".

[0027] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0028] Figure 2 A flow chart showing a method for manufacturing a spacer for an embedded SONOS memory according to an embodiment of the present invention; Figures 3 to 6 The structure diagram of each step of the manufacturing method of the sidewall of the embedded SONOS memory according to the embodiment of the present invention is shown. Figure 2 As shown, the method for manufacturing the sidewall of the embedded SONOS memory according to the embodiment of the present invention comprises the following steps:

[0029] Step 1: Figure 3 As shown, a substrate is provided, and a logic region with an L-shaped sidewall and a gate outer layer of SONOS are formed on the substrate.

[0030] The material of the substrate may be silicon, germanium, silicon germanium or silicon carbide, etc., or may be silicon on insulator (SOI) or germanium on insulator (GOI), or may be other materials, such as III and V group compounds such as gallium arsenide. The substrate in the embodiment of the present invention is a silicon substrate, and further, it may be an undoped or lightly doped silicon substrate.

[0031] A logic region with an L-shaped sidewall and a SONOS gate outer layer are formed on the surface of the silicon substrate. Figure 2 As shown, a gate structure located in the logic area and a gate structure located in the SONOS area are formed on the surface of the silicon substrate. The gate structure includes a gate dielectric layer and a gate conductive material layer stacked in sequence. In a preferred embodiment, the gate dielectric layer is a gate oxide layer (GOX), and the gate conductive material layer is polysilicon (Poly). The L-shaped sidewall in the embodiment of the present invention includes an oxide layer and a silicon nitride (SIN) layer.

[0032] Step 2: Figure 4 As shown, a metal silicide layer is formed over the active area and the gate.

[0033] The Salicide (silicide) process steps are performed after the source and drain ion implantation is completed. The basic process steps for forming Salicide are to first use physical vapor deposition (PVD) to deposit a layer of metal (Ti, Co, NiPt, etc.) on the polysilicon gate and active area. Then two rapid thermal annealing processes (RTA) and a selective wet etching process are performed, and finally Salicide is formed on the surface of the polysilicon and the active area. The metal silicide includes thin films such as TiSi2, CoSi2 and NiPtSi. Metal Ti, Co or NiPt will not react with the dielectric material to form metal silicide, but will only react with the polysilicon and active area in direct contact to form metal silicide. In the embodiment of the present invention, the metal silicide layer is cobalt silicide CoSi2, which is formed by atomic layer deposition (ALD) through Co deposition and subsequent rapid thermal annealing (RTA).

[0034] Step 3: Figure 5 As shown, silicon nitride is deposited as an etch stop layer.

[0035] In the embodiment of the present invention, the silicon nitride etch stop layer is used to block the over-etching of the subsequent sacrificial oxide layer silicon oxide, and prevent the influence of the plasma gas on the gate and the active area during etching.

[0036] Step 4: Figure 6 As shown, a sacrificial oxide layer is grown on the surface of the etch stop layer.

[0037] In the embodiment of the present invention, the sacrificial oxide layer is silicon oxide and is preferably formed by thermal oxidation. Of course, other suitable methods may also be used.

[0038] Step 5: Figure 7 As shown, the sacrificial oxide layer is etched to change the outer layer of the logic area and the gate of the SONOS from an L-shaped sidewall to a D-shaped sidewall.

[0039] In the embodiment of the present invention, the sacrificial oxide layer is etched by plasma etching process. During etching, the sacrificial oxide layer on the surface of the L-shaped side wall is partially retained and not completely etched, so that the morphological profile after etching is smooth and not tortuous.

[0040] The gate sidewall between the logic area and the SONOS area is changed from L-type to D-type. The new "D"-type sidewall has a stable morphology and a large etching window, which improves the filling capacity of the subsequent dielectric layer.

[0041] Step 6: Figure 8 As shown, an interlayer dielectric layer is deposited.

[0042] In the embodiment of the present invention, the interlayer dielectric layer (ILD) is formed by using BPSG (boron phospho-silicate glass) using a chemical vapor deposition (CVD) process. Compared with the traditional process flow, it has higher requirements on the composition and filling capacity of the interlayer dielectric, such as Figure 8 As shown, the interlayer dielectric layer formed in the embodiment of the present invention has no voids, and no void defects are generated during the filling process, thereby improving the filling capacity of the interlayer dielectric layer, and will not affect the etching of the through hole and the deposition process of tungsten metal, so that the device can work normally.

[0043] Step seven: etching the interlayer dielectric layer to form a through hole, and depositing metal in the through hole.

[0044] When forming a through hole, the size of the through hole needs to be defined by patterning the interlayer dielectric layer. After the through hole is formed, metal tungsten is deposited in the through hole, and tungsten is used as a connection between the metal layer and the device.

[0045] The embodiment of the present invention changes the sidewall morphology to change the L-shaped sidewall between adjacent gates into a D-shaped sidewall. The D-shaped sidewall has a stable morphology and a large etching window, which improves the filling capacity of the subsequent interlayer dielectric layer and eliminates the voids in the interlayer dielectric layer between adjacent gates, thereby not affecting the etching of the through hole and the deposition process of tungsten metal. The device can work normally and the device yield is improved. The method of the embodiment of the present invention directly improves the morphology of the gate sidewall, ensures the gate oxide integrity of the logic area and SONOS, and the method is simple and efficient, saving manufacturing costs and development time.

[0046] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a sidewall of an embedded SONOS memory, characterized in that: The following steps are involved: Step 1: providing a substrate, and forming a logic region with an L-shaped sidewall and a gate outer layer of SONOS on the substrate; Step 2: forming a metal silicide layer on the active area and the gate; Step 3, depositing silicon nitride as an etch stop layer; Step 4: growing a sacrificial oxide layer on the surface of the etch stop layer; Step 5, etching the sacrificial oxide layer to change the outer layer of the logic area and the gate of the SONOS from an L-shaped sidewall to a D-shaped sidewall; Step 6: depositing an interlayer dielectric layer; Step seven: etching the interlayer dielectric layer to form a through hole, and depositing metal in the through hole.

2. The method for manufacturing a sidewall for an embedded SONOS memory according to claim 1, characterized in that: The substrate in step 1 is a silicon substrate.

3. The method for manufacturing a sidewall for an embedded SONOS memory according to claim 1, characterized in that: The L-shaped sidewall in step 1 includes an oxide layer and a silicon nitride layer.

4. The method for manufacturing a sidewall for an embedded SONOS memory according to claim 1, characterized in that: The metal silicide layer in step 2 is cobalt silicide.

5. The method for manufacturing a sidewall for an embedded SONOS memory according to claim 1, characterized in that: The sacrificial oxide layer in step 4 is a silicon oxide layer, which is formed by thermal oxygen growth.

6. The method for manufacturing a sidewall for an embedded SONOS memory according to claim 1, characterized in that: The etching in step five is a plasma etching process.

7. The method for manufacturing a sidewall for an embedded SONOS memory according to claim 1, characterized in that: The interlayer dielectric layer in step six adopts BPSG.

8. The method for manufacturing a sidewall for an embedded SONOS memory according to claim 1, characterized in that: The metal in step seven is tungsten.

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