Wet etching method of high-pressure-resistant polyimide and prepared wafer

Abstract

The invention discloses a wet etching method of high-pressure-resistant polyimide and a prepared wafer, and belongs to the field of semiconductor device manufacturing processes, the wet etching method comprises the following steps: coating polyimide on a SiC wafer and baking to obtain the SiC wafer with a polyimide film; performing passivation pressure point photoetching on the SiC wafer with the polyimide film to obtain a SiC wafer with a polyimide passivation film; and sequentially hardening the SiC wafer with the polyimide passivation film, coating a bottom film, carrying out wet etching and carrying out dry photoresist removal to obtain the SiC wafer with the high-voltage-resistant polyimide passivation layer. The method can solve the problem of poor corrosion morphology caused by treatment of polyimide with the thickness of 20 microns or above by an existing corrosion process.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor device manufacturing technology, and in particular relates to a wet etching method for high-voltage polyimide and a wafer obtained. Background Art

[0002] In the manufacturing process of silicon carbide (SiC) power devices, the passivation layer can not only protect the device from moisture, pollutants and physical damage in the external environment, but also effectively improve the electrical performance of the device, such as voltage resistance and insulation resistance. At present, for the passivation process in the manufacturing process of SiC devices, the commonly used terminal protection material in the industry is polyimide (PI). Generally, the thickness of the polyimide passivation layer is mostly 2μm~15μm, but when the voltage resistance requirement of SiC power devices is above 5kV, the thickness of the polyimide passivation layer often needs to be above 20μm to ensure sufficient voltage resistance and reliability.

[0003] At present, for the wet etching process of polyimide, the industry has mature etching process technology for passivation layers with a thickness of 2μm~15μm, but when the SiC passivation process is used above 20μm, there are defects such as difficult to control the corrosion rate, large side etching, and easy deformation of the pattern. Specifically, as the thickness of polyimide increases, the time for the chemical solution to penetrate into the material increases, resulting in increased uncertainty in the corrosion rate and difficulty in accurately controlling the depth of removal; side etching refers to the uneven corrosion of the chemical solution along the edge or interface of the material, which will cause the edge of the pattern to be blurred and deformed, affecting the electrical performance and reliability of the device. In the corrosion process of thick polyimide, the side etching phenomenon is particularly obvious due to the influence of solution diffusion and reaction kinetics; as the corrosion depth increases, the stress distribution inside the material changes, which may cause the pattern to be distorted or tilted during the corrosion process, further affecting the performance of the device and the degree of package integration. Therefore, it is necessary to improve the wet etching process of polyimide with a thickness of more than 20μm. Summary of the invention

[0004] The purpose of the present invention is to provide a wet etching method for high-voltage polyimide and a wafer obtained therefrom, so as to solve the problem that the existing etching process for treating polyimide with a thickness of more than 20 μm causes poor corrosion morphology.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions: In a first aspect, a wet etching method for high voltage-resistant polyimide comprises the following steps: S1, coating polyimide on a SiC wafer and baking the same to obtain a SiC wafer having a polyimide film; S2, performing passivation pressure point photolithography on the SiC wafer with the polyimide film to obtain a SiC wafer with a polyimide passivation film; S3, sequentially performing hardening, primer coating, wet etching and dry stripping on the SiC wafer with the polyimide passivation film to obtain a SiC wafer with a high withstand voltage polyimide passivation layer.

[0006] In some embodiments, in S1, polyimide is coated by spin coating using a polyimide coating liquid, and the viscosity of the polyimide coating liquid is 10000 cp to 18000 cp.

[0007] In some embodiments, in S1, the baking temperature is 80°C to 120°C, the baking time is 20 min to 50 min, and the thickness of the polyimide film is 30 μm to 60 μm.

[0008] In some embodiments, in S2, the passivation pressure point lithography uses negative resist masking.

[0009] In some embodiments, in S2, the step of performing passivation pressure point lithography on the SiC wafer having the polyimide film specifically includes: After the SiC wafer with the polyimide film is sequentially coated with glue, exposed and developed, a SiC wafer with a polyimide passivation film is obtained.

[0010] In some embodiments, the coating thickness of the glue is 1.0 μm to 2.4 μm, the exposure time of the exposure is 1.0 s to 3.0 s, and the development time is 5 s to 15 s.

[0011] In some embodiments, in S3, the temperature of the hardening film is 120° C. to 140° C., and the time of the hardening film is 15 min to 30 min.

[0012] In some embodiments, in S3, the etching solution used for the wet etching is a mixed etching solution of tetramethylammonium hydroxide and anhydrous ethanol, wherein the volume ratio of tetramethylammonium hydroxide: anhydrous ethanol is 1: (5-10), the temperature of the wet etching is 20°C-25°C, and the time of the wet etching is 22min-25min.

[0013] In some embodiments, in S3, the dry stripping adopts microwave plasma stripping, and the time of the dry stripping is 12 minutes to 20 minutes.

[0014] In a second aspect, a SiC wafer having a high-voltage polyimide passivation layer is obtained by using the high-voltage polyimide wet etching method.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a wet etching method for high-voltage polyimide and a wafer obtained. First, polyimide is coated on a SiC wafer and baked to obtain a SiC wafer with a polyimide film; then, the SiC wafer with the polyimide film is subjected to passivation point photolithography to obtain a SiC wafer with a polyimide passivation film; finally, the SiC wafer with the polyimide passivation film is subjected to hard film, primer film, wet etching and dry degumming in sequence to obtain a SiC wafer with a high-voltage polyimide passivation layer. The method enables thicker polyimide to have good corrosion morphology, can solve the problem of poor corrosion morphology caused by existing corrosion processes for polyimide with a thickness of more than 20 μm, and is used in the manufacture of SiC high-voltage power devices.

[0016] Furthermore, the present invention adopts a polyimide coating liquid with a viscosity of 10000 cp to 18000 cp and performs coating by spin coating, which can ensure the uniformity and quality of coating.

[0017] Furthermore, the baking temperature in S1 of the present invention is 80°C~120°C, and the baking time is 20min~50min, which can ensure that the curing degree of the polyimide film is moderate. At the same time, the thickness of the polyimide film is 30μm~60μm, which meets the subsequent application requirements.

[0018] Furthermore, the passivation pressure point lithography of the present invention adopts negative resist masking, which can improve the accuracy and effect of lithography and provide a better patterning basis.

[0019] Furthermore, the coating thickness of the adhesive of the present invention is 1.0 μm to 2.4 μm, the exposure amount of the exposure is 1.0 s to 3.0 s, and the development time is 5 s to 15 s, which can ensure the accuracy and integrity of the photolithography pattern and avoid pattern deformation and blur.

[0020] Furthermore, in S3, the hardening temperature is 120° C. to 140° C., and the hardening time is 15 min to 30 min, so as to ensure the stability of the polyimide passivation film.

[0021] Furthermore, in S3, the wet etching uses a mixed etching solution of tetramethylammonium hydroxide and anhydrous ethanol, which can control the etching rate and etching effect to ensure the accuracy and integrity of the pattern. The temperature of the mixed etching solution is 20°C to 25°C, and the wet etching time is 22min to 25min, which can improve the accuracy and efficiency of etching.

[0022] Furthermore, in S3, the dry debonding adopts microwave plasma debonding, and the time of the dry debonding is 12 minutes to 20 minutes, which can quickly and efficiently remove the residual adhesive layer while avoiding damage to the polyimide structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A flow chart of a wet etching preparation method of high-voltage polyimide provided in an embodiment of the present invention; Figure 2 This is a SEM image of the polyimide corrosion morphology obtained in Example 2 of the present invention. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] In the present invention, unless otherwise specified, all the embodiments and preferred implementation methods mentioned herein can be combined with each other to form a new technical solution.

[0027] In the present invention, unless otherwise specified, all technical features and preferred features mentioned herein can be combined with each other to form a new technical solution.

[0028] In the present invention, unless otherwise specified, the components or preferred components involved can be combined with each other to form a new technical solution.

[0029] In the present invention, unless otherwise specified, the numerical range "a-b" represents an abbreviation of any combination of real numbers between a and b, wherein a and b are both real numbers.

[0030] The “range” disclosed in the present invention is in the form of a lower limit and an upper limit, which can be one or more lower limits, and one or more upper limits, respectively.

[0031] In the present invention, the term "and / or" used herein refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0032] In the present invention, unless otherwise specified, each reaction or operation step can be carried out sequentially or in accordance with the sequence. Preferably, the reaction method herein is carried out sequentially.

[0033] Unless otherwise specified, the professional and scientific terms used herein have the same meanings as those familiar to those skilled in the art. In addition, any method or material similar or equivalent to the described content may also be applied to the present invention.

[0034] The present invention will be further described below in conjunction with the accompanying drawings: like Figure 1 As shown, the present invention discloses a wet etching preparation method of high-voltage polyimide, comprising the following steps: Step 1: Spin-coating polyimide on a SiC wafer using a polyimide coating liquid, and then baking to obtain a SiC wafer with a polyimide film; Step 2: performing passivation pressure point lithography on the SiC wafer with the polyimide film, wherein the passivation pressure point lithography specifically comprises the following steps: sequentially performing glue coating, exposure and development on the SiC wafer with the polyimide film to obtain a SiC wafer with a polyimide passivation film; Step 3: The SiC wafer with the polyimide passivation film is subjected to hardening, primer coating, wet etching and dry stripping in sequence to obtain a SiC wafer with a high withstand voltage polyimide passivation layer.

[0035] Preferably, in step 1, the viscosity of the polyimide coating liquid is 10000 cp~18000 cp, the baking temperature is 80°C~120°C, the baking time is 20min~50min, and the thickness of the polyimide film is 30μm~60μm.

[0036] Preferably, in step 2, the passivation pressure point lithography adopts negative resist masking, the coating thickness of the resist is 1.0 μm to 2.4 μm, the exposure amount of the exposure is 1.0 s to 3.0 s, and the development time is 5 s to 15 s.

[0037] Preferably, in step 3, the hardening temperature is 120°C~140°C, the hardening time is 15min~30min, the etching solution used in the wet etching is a mixed etching solution of tetramethylammonium hydroxide and anhydrous ethanol, wherein the volume ratio of tetramethylammonium hydroxide: anhydrous ethanol is 1:(5~10), the wet etching temperature is 20°C~25°C, the wet etching time is 22min~25min, and the dry stripping adopts microwave plasma stripping, and the dry stripping time is 12min~20min.

[0038] Embodiment 1 A wet etching preparation method for high-voltage polyimide comprises the following steps: Step 1: Spin-coat polyimide on a SiC wafer using a polyimide coating liquid, and then bake to obtain a SiC wafer with a polyimide film. The viscosity of the polyimide coating liquid is 12000 cp, the baking temperature is 90° C., the baking time is 25 min, and the thickness of the polyimide film is 30 μm. Step 2: performing passivation pressure point lithography on the SiC wafer with the polyimide film, including coating, exposure, and development, to obtain a SiC wafer with a polyimide passivation film. The passivation pressure point lithography adopts negative resist masking, the coating thickness of the coating is 1.3 μm, the exposure amount of the exposure is 1.5 s, and the development time is 8 s; Step 3: After hardening, primer coating, wet etching and dry stripping of the SiC wafer with a polyimide passivation film in sequence, a SiC wafer with a high-voltage polyimide passivation layer is obtained. The hardening temperature is 120°C, the hardening time is 20 minutes, the polyimide is wet-etched, and the etching solution used is a mixed etching solution of tetramethylammonium hydroxide and anhydrous ethanol, wherein the volume ratio of tetramethylammonium hydroxide: anhydrous ethanol is 1:5, the wet etching temperature is 20°C, the wet etching time is 22 minutes, and the dry stripping is dry stripping using a microwave plasma stripper, and the dry stripping time is 15 minutes.

[0039] Embodiment 2 A wet etching preparation method for high-voltage polyimide comprises the following steps: Step 1: Spin-coat polyimide on a SiC wafer using a polyimide coating liquid, and then bake to obtain a SiC wafer with a polyimide film. The viscosity of the polyimide coating liquid is 14000 cp, the baking temperature is 105° C., the baking time is 35 min, and the thickness of the polyimide film is 45 μm. Step 2: performing passivation pressure point lithography on the SiC wafer with the polyimide film, including coating, exposure, and development, to obtain a SiC wafer with a polyimide passivation film. The passivation pressure point lithography adopts negative resist masking, the coating thickness of the coating is 1.7 μm, the exposure amount of the exposure is 2.0 s, and the development time is 12 s; Step 3: After hardening, primer coating, wet etching and dry stripping of the SiC wafer with a polyimide passivation film in sequence, a SiC wafer with a high-voltage polyimide passivation layer is obtained. The hardening temperature is 130°C, the hardening time is 25 minutes, the polyimide is wet-etched, and the etching solution used is a mixed etching solution of tetramethylammonium hydroxide and anhydrous ethanol, wherein the volume ratio of tetramethylammonium hydroxide: anhydrous ethanol is 1:10, the wet etching temperature is 22°C, the wet etching time is 24 minutes, and the dry stripping is dry stripping using a microwave plasma stripper, and the dry stripping time is 18 minutes.

[0040] The polyimide thickness of the SiC wafer with a high withstand voltage polyimide passivation layer is 45 μm, and the thick layer of polyimide is successfully wet-etched. Figure 2 As shown, the SiC wafer with a high-voltage polyimide passivation layer has neat lines on the 45μm thick polyimide surface pattern under microscopic examination, no excess residue, and a side etching amount of less than 5μm, with good corrosion morphology, which can be used in the manufacture of SiC high-voltage power devices. Therefore, it is concluded that the method proposed in the present invention can effectively improve the poor polyimide corrosion morphology, solve the problems of pattern deformation and large side etching after corrosion, and improve the high-voltage passivation lithography corrosion morphology yield. It provides technical support for the research of high-voltage SiC devices.

[0041] Embodiment 3 A wet etching preparation method for high-voltage polyimide comprises the following steps: Step 1: Spin-coat polyimide on a SiC wafer using a polyimide coating liquid, and then bake to obtain a SiC wafer with a polyimide film. The viscosity of the polyimide coating liquid is 17000 cp, the baking temperature is 115° C., the baking time is 45 min, and the thickness of the polyimide film is 55 μm. Step 2: performing passivation pressure point lithography on the SiC wafer with the polyimide film, including coating, exposure, and development, to obtain a SiC wafer with a polyimide passivation film. The passivation pressure point lithography adopts negative resist masking, the coating thickness of the coating is 2.0 μm, the exposure amount of the exposure is 2.5 s, and the development time is 14 s; Step 3: After hardening, primer coating, wet etching and dry stripping of the SiC wafer with a polyimide passivation film in sequence, a SiC wafer with a high-voltage polyimide passivation layer is obtained. The hardening temperature is 140°C, the hardening time is 30 minutes, the polyimide is wet-etched, and the etching solution used is a mixed etching solution of tetramethylammonium hydroxide and anhydrous ethanol, wherein the volume ratio of tetramethylammonium hydroxide: anhydrous ethanol is 1:7, the wet etching temperature is 24°C, the wet etching time is 25 minutes, and the dry stripping is dry stripping using a microwave plasma stripper, and the dry stripping time is 20 minutes.

[0042] Embodiment 4 A wet etching preparation method for high-voltage polyimide comprises the following steps: Step 1: Spin-coat polyimide on a SiC wafer using a polyimide coating liquid, and then bake to obtain a SiC wafer with a polyimide film. The viscosity of the polyimide coating liquid is 10000 cp, the baking temperature is 80° C., the baking time is 20 min, and the thickness of the polyimide film is 30 μm. Step 2: performing passivation pressure point lithography on the SiC wafer with the polyimide film, including coating, exposure, and development, to obtain a SiC wafer with a polyimide passivation film. The passivation pressure point lithography adopts negative resist masking, the coating thickness of the coating is 1.0 μm, the exposure amount of the exposure is 1.0 s, and the development time is 5 s; Step 3: After hardening, primer coating, wet etching and dry stripping of the SiC wafer with a polyimide passivation film in sequence, a SiC wafer with a high-voltage polyimide passivation layer is obtained. The hardening temperature is 125°C, the hardening time is 15 minutes, the polyimide is wet-etched, and the etching solution used is a mixed etching solution of tetramethylammonium hydroxide and anhydrous ethanol, wherein the volume ratio of tetramethylammonium hydroxide: anhydrous ethanol is 1:6, the wet etching temperature is 25°C, the wet etching time is 22 minutes, and the dry stripping is dry stripping using a microwave plasma stripper, and the dry stripping time is 12 minutes.

[0043] Embodiment 5 A wet etching preparation method for high-voltage polyimide comprises the following steps: Step 1: Spin-coat polyimide on a SiC wafer using a polyimide coating liquid, and then bake to obtain a SiC wafer with a polyimide film. The viscosity of the polyimide coating liquid is 18000 cp, the baking temperature is 120° C., the baking time is 50 min, and the thickness of the polyimide film is 60 μm. Step 2: performing passivation pressure point lithography on the SiC wafer with the polyimide film, including coating, exposure, and development, to obtain a SiC wafer with a polyimide passivation film. The passivation pressure point lithography adopts negative resist masking, the coating thickness of the coating is 2.4 μm, the exposure amount of the exposure is 3.0 s, and the development time is 15 s; Step 3: After hardening, primer coating, wet etching and dry stripping of the SiC wafer with a polyimide passivation film in sequence, a SiC wafer with a high-voltage polyimide passivation layer is obtained. The hardening temperature is 135°C, the hardening time is 30 minutes, the polyimide is wet-etched, and the etching solution used is a mixed etching solution of tetramethylammonium hydroxide and anhydrous ethanol, wherein the volume ratio of tetramethylammonium hydroxide: anhydrous ethanol is 1:8, the wet etching temperature is 23°C, the wet etching time is 23 minutes, and the dry stripping is dry stripping using a microwave plasma stripper, and the dry stripping time is 17 minutes.

[0044] In summary, the present invention provides a wet etching method for high-voltage polyimide, which significantly optimizes the manufacturing process of SiC high-voltage power devices. By adopting a polyimide coating liquid with suitable viscosity and precise spin coating technology, the uniformity and high quality of the polyimide film are ensured, laying a solid foundation for subsequent processes. The temperature and time of the baking step are properly controlled so that the degree of curing of the polyimide film is moderate, while meeting the thickness requirement of 30μm to 60μm, meeting the manufacturing needs of high-voltage devices. In the photolithography stage, the negative photoresist masking technology is used to significantly improve the accuracy and effect of photolithography, providing a better foundation for the patterning of polyimide passivation film. By precisely controlling the parameters of glue coating, exposure and development, the accuracy and integrity of the photolithography pattern are ensured, and deformation and blurring of the pattern are avoided. In the wet etching stage, the present invention uses a mixed etching solution of tetramethylammonium hydroxide and anhydrous ethanol. By accurately controlling the temperature and etching time of the solution, the etching rate and etching effect are well controlled, and the accuracy and integrity of the pattern are ensured. This step not only improves the accuracy and efficiency of the etching, but also provides favorable conditions for the subsequent dry degumming step. Finally, the microwave plasma degumming technology is used for dry degumming, which not only quickly and efficiently removes the residual glue layer, but also avoids damage to the polyimide structure, thereby ensuring the performance and reliability of the SiC high-voltage power device.

[0045] The above contents are only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A wet etching method for high-voltage polyimide, characterized in that: The following steps are involved: S1, coating polyimide on a SiC wafer and baking the same to obtain a SiC wafer having a polyimide film; S2, performing passivation pressure point photolithography on the SiC wafer with the polyimide film to obtain a SiC wafer with a polyimide passivation film; S3, sequentially performing hardening, primer coating, wet etching and dry stripping on the SiC wafer with the polyimide passivation film to obtain a SiC wafer with a high withstand voltage polyimide passivation layer.

2. A wet etching method for high voltage-resistant polyimide according to claim 1, characterized in that: In S1, polyimide is coated by spin coating using a polyimide coating liquid, wherein the viscosity of the polyimide coating liquid is 10000 cp to 18000 cp.

3. The wet etching method of high voltage-resistant polyimide according to claim 1, characterized in that: In S1, the baking temperature is 80° C. to 120° C., the baking time is 20 min to 50 min, and the thickness of the polyimide film is 30 μm to 60 μm.

4. The wet etching method of high voltage-resistant polyimide according to claim 1, characterized in that: In S2, the passivation pressure point lithography adopts negative resist masking.

5. The wet etching method of high voltage-resistant polyimide according to claim 1, characterized in that: In S2, the step of performing passivation pressure point lithography on the SiC wafer having the polyimide film specifically comprises: After the SiC wafer with the polyimide film is sequentially coated with glue, exposed and developed, a SiC wafer with a polyimide passivation film is obtained.

6. A wet etching method for high voltage-resistant polyimide according to claim 5, characterized in that: The coating thickness of the glue is 1.0 μm to 2.4 μm, the exposure amount of the exposure is 1.0 s to 3.0 s, and the development time is 5 s to 15 s.

7. The wet etching method of high voltage-resistant polyimide according to claim 1, characterized in that: In S3, the temperature of the hardening film is 120° C. to 140° C., and the time of the hardening film is 15 min to 30 min.

8. The wet etching method of high voltage-resistant polyimide according to claim 1, characterized in that: In S3, the etching solution used for the wet etching is a mixed etching solution of tetramethylammonium hydroxide and anhydrous ethanol, wherein the volume ratio of tetramethylammonium hydroxide: anhydrous ethanol is 1: (5-10), the temperature of the wet etching is 20°C-25°C, and the time of the wet etching is 22min-25min.

9. The wet etching method of high voltage-resistant polyimide according to claim 1, characterized in that: In S3, the dry debonding adopts microwave plasma debonding, and the time of the dry debonding is 12 minutes to 20 minutes.

10. A SiC wafer having a high withstand voltage polyimide passivation layer, characterized in that: The high-voltage-resistant polyimide is obtained by the wet etching method of any one of claims 1 to 9.

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