A method for evaluating a damage layer of a wafer backside thinning process

Abstract

The present application relates to the technical field of semiconductor, in particular to a kind of about wafer back thinning processing damage layer evaluation method.It includes the following steps: S1, form several array distribution's PN junction on the surface of each chip of wafer;PN junction includes N-type well, P-type well, and N-type well and P-type well are respectively arranged on chip substrate, and P-type well is located in N-type well;Power connection terminal one is arranged on chip substrate, power connection terminal two is arranged on N-type well, and power connection terminal three is arranged on P-type well;S2, chip is thinned;S3, between power connection terminal one and power connection terminal two, reverse voltage is connected, and the change curve of leakage current is measured;S4, through leakage current curve, the condition of wafer damage layer is analyzed.Compared with prior art, a kind of wafer with simple PN junction structure is designed.When grinding processing damage affects the depletion layer of PN junction in wafer, leakage current will occur, and the condition of damage layer in the whole wafer is evaluated by testing leakage current.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, in particular to a method for evaluating damage layer of wafer back thinning processing. BACKGROUND

[0002] To improve the performance of semiconductor devices, reduce their power consumption size and cost, the demand for extreme thinning of chip thickness is becoming higher and higher. In particular, this year, wafer back thinning technology is advancing in the direction of thinning the final thickness of Si substrate to tens of microns or even a few microns. As shown in FIG. 1, wafer back thinning is generally achieved by mechanical grinding processing technology, but mechanical grinding processing will produce a damage layer on the back of the wafer. When the damage layer approaches the doping layer or functional layer near the surface of the semiconductor device wafer, it will affect the performance of the semiconductor device. Figure 1

[0003] Currently, the main means of evaluating the damage layer is to observe the crack depth of the wafer after thinning processing by electron microscope (SEM). However, there are two limitations of this technology: 1) Only visible parts can be evaluated (incompleteness). As shown in FIG. 2, the damage layer that affects the performance of the semiconductor device is not only the depth of the visible crack, but also the lattice dislocation and stress field at a deeper position than the crack. The latter two are difficult to characterize by SEM. 2) Only a small part of the wafer can be evaluated (regional limitation). SEM is evaluated by observing the morphology of the Si substrate cross section. The observable range is generally a few microns to a few hundred microns, so it is difficult to evaluate the distribution of the damage layer on the entire wafer. Figure 2 SUMMARY

[0004] The present application overcomes the shortcomings of the prior art and provides a method for evaluating the damage layer of wafer back thinning processing, which can effectively evaluate the influence range of the damage layer and the distribution of the damage layer on the entire wafer.

[0005] To achieve the above purpose, a method for evaluating the damage layer of wafer back thinning processing is designed, which includes the following steps:

[0006] S1, forming a plurality of array distributed PN junctions on the surface of each chip of the wafer;

[0007] The PN junction includes an N-type well and a P-type well, and the chip substrate is respectively provided with the N-type well and the P-type well, and the P-type well is located in the N-type well;

[0008] The chip substrate is provided with a power connection terminal one, the N-type well is provided with a power connection terminal two, and the P-type well is provided with a power connection terminal three; ​​

[0009] S2, thinning the chip;

[0010] S3, connecting a reverse voltage between the power connection terminal one and the power connection terminal two, measuring the change curve of the leakage current;

[0011] S4, analyzing the condition of the damage layer of the wafer through the leakage current curve.

[0012] The chip substrate is a P-type Si substrate.

[0013] The depth of the N-type well is greater than that of the P-type well, and the P-type well is contained in the N-type well.

[0014] An isolation groove is arranged between the adjacent PN junctions.

[0015] In the step S4, the relationship between the leakage current and the PN junction depletion layer defect is shown in the following formula:

[0016] I leakeage ∝N def =ρ def ×S

[0017] Where Ileakage is the leakage current intensity, ρdef is the area density of the defect, and S is the area.

[0018] In the step S4, the difference of the damage layer of the wafer is obtained by comparing the difference of different leakage current curves.

[0019] Further comprising a step S5, connecting a reverse voltage between the power connection terminal two and the power connection terminal three, measuring the change curve of the leakage current, and analyzing the condition of the damage layer of the wafer through the leakage current curve.

[0020] Compared with the prior art, the wafer with a simple PN junction structure is designed. When the grinding processing damage affects the depletion layer of the PN junction in the wafer, the leakage current occurs, and the condition of the damage layer in the whole wafer is evaluated by testing the leakage current. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 It is a schematic diagram of the wafer thinning in the prior art.

[0022] Figure 2 It is a schematic diagram of the processing damage layer in the prior art.

[0023] Figure 3 It is a schematic diagram of the principle of the PN junction leakage current of the present application.

[0024] Figure 4 It is a schematic diagram of the wafer in the step S1 of the present application.

[0025] Figure 5This is a schematic diagram of the chip and PN junction of the present invention.

[0026] Figure 6 for Figure 5 A magnified view of a portion of point A in the middle.

[0027] Figure 7 This is a test schematic diagram in an embodiment of the present invention.

[0028] Figure 8 This is a graph showing the evaluation results in an embodiment of the present invention.

[0029] Figure 9 This is a schematic diagram illustrating the specific use of the present invention. Detailed Implementation

[0030] The present invention will now be further described with reference to the accompanying drawings.

[0031] like Figure 3 As shown, when a reverse voltage is applied across a PN junction (positive voltage for the N-type junction and negative voltage for the P-type junction), the depletion layer in the middle of the PN junction thickens. Since there are very few carriers in the depletion layer, the leakage current between the PN junctions is very weak. However, when defects exist in the depletion layer, these defects act as carriers, leading to an increase in leakage current.

[0032] Based on this, the method for evaluating the damage layer during wafer backside thinning in this embodiment includes the following steps:

[0033] like Figures 4 to 5 As shown in Figure S1, several arrayed PN junctions 2 are formed on the surface of each chip 1 of the wafer, and several test pads 5 are also provided on the chip.

[0034] like Figure 6 As shown, the PN junction 2 includes an N-type well 2-1 and a P-type well 2-2. The chip substrate 1-1 is provided with an N-type well 2-1 and a P-type well 2-2, and the P-type well 2-2 is located inside the N-type well 2-1.

[0035] A power connector terminal Pin1 is provided on the chip substrate 1-1, a power connector terminal Pin2 is provided on the N-type well 2-1, and a power connector terminal Pin3 is provided on the P-type well 2-2.

[0036] S2, thinning chip 1;

[0037] S3. Apply a reverse voltage between power connector terminal 1 (Pin1) and power connector terminal 2 (Pin2), and measure the leakage current change curve.

[0038] S4. Analyze the condition of wafer damage layer 3 using the leakage current curve.

[0039] S5. Apply a reverse voltage between power connector terminal 2 (Pin2) and power connector terminal 3 (Pin3), and measure the leakage current change curve. Analyze the condition of the deeper wafer damage layer 3 through the leakage current curve.

[0040] The chip substrate 1-1 is a P-type Si substrate. The depth of the N-type well 2-1 is greater than that of the P-type well 2-2, and the P-type well 2-2 is contained within the N-type well 2-1.

[0041] An isolation slot 2-3 is provided between adjacent PN junctions 2 to isolate adjacent PN junctions 2 and ensure that they do not interfere with each other.

[0042] In step S3, when a reverse voltage is applied between power connector pin 1 and power connector pin 2, the depletion layer 4 between the N-type well 2-1 and the chip substrate 1-1 thickens, and the leakage current between the N-type well 2-1 and the chip substrate 1-1 will be very small. However, when the thinning process damage layer enters the depletion layer 4 and causes a defect, the leakage current will increase, such as... Figure 7 As shown. Similarly, when a reverse voltage is applied between Pin2 and Pin3, and the grinding damage layer enters its depletion layer, the leakage current between the N-type well and the P-type well will increase.

[0043] Therefore, in this embodiment, after the thinning process, by evaluating the correlation between the thickness of the chip substrate 1-1 and the leakage current between the power connector terminals 1-1 and 2-2, and between the power connector terminals 2-2 and 3-3 on the wafer, the depth, density, and distribution of the damaged layer on the wafer can be obtained.

[0044] In step S4, the relationship between leakage current and the defects in the PN junction depletion layer 4 is shown in the following equation:

[0045] I leakage ∝N def =ρ def ×S

[0046] Where Ileakage is the leakage current intensity, ρdef is the surface density of the defect, and S is the area.

[0047] In step S4, the differences in the damage layers 3 of different wafers can also be obtained by comparing the differences in different leakage current curves.

[0048] like Figure 9 As shown, in this embodiment, before the thinning process, a pre-test is performed using a probe to measure the initial leakage current and the chip substrate thickness (1-1). Then, a temporary bonding process is used for thinning. Finally, the thinned chip is tested according to steps S1 to S5. A schematic diagram of the test is shown below.Figure 7 As shown, the evaluation results are as follows: Figure 8 As shown, initially, as the chip substrate 1-1 thins (in this embodiment, the initial thickness of the chip substrate 1-1 is >10µm), the leakage current does not change significantly. However, when the chip substrate 1-1 is thinned to a certain thickness (<3µm in this embodiment), the leakage current increases sharply, and a leakage current curve can be obtained. The characteristics of the damaged layer can be evaluated by measuring three data points on the leakage current curve, such as... Figure 8 As shown in the figure, ① represents the starting point of the leakage current rise, which is related to the maximum depth of the damaged layer. ② represents the slope of the leakage current rise, which is related to the depth distribution of the damaged layer. ③ represents the saturation value of the leakage current rise, which is related to the density of the damaged layer.

[0049] In practical applications, different grinding processes can yield different leakage current curves. By comparing the differences in leakage current curves, the differences in the damaged layer can be determined.

Claims

1. A method for evaluating damage layers during wafer backside thinning, characterized in that: Includes the following steps: S1, Several arrayed PN junctions (2) are formed on the surface of each chip (1) of the wafer. The PN junction (2) includes an N-type well (2-1) and a P-type well (2-2). The chip substrate (1-1) is provided with an N-type well (2-1) and a P-type well (2-2), and the P-type well (2-2) is located inside the N-type well (2-1). A power connector terminal 1 (Pin1) is provided on the chip substrate (1-1), a power connector terminal 2 (Pin2) is provided on the N-type well (2-1), and a power connector terminal 3 (Pin3) is provided on the P-type well (2-2). S2, thinning the chip (1); S3. Apply a reverse voltage between power connector terminal 1 (Pin1) and power connector terminal 2 (Pin2) and measure the leakage current change curve. S4, analyze the condition of the wafer damage layer (3) by using the leakage current curve; S5, apply a reverse voltage between power connector terminal 2 (Pin2) and power connector terminal 3 (Pin3), measure the leakage current change curve, and analyze the wafer damage layer (3) through the leakage current curve.

2. The method for evaluating the damage layer during wafer backside thinning as described in claim 1, characterized in that: The chip substrate (1-1) is a P-type Si substrate.

3. The method for evaluating the damage layer during wafer backside thinning as described in claim 1, characterized in that: The depth of the N-type well (2-1) is greater than that of the P-type well (2-2), and the P-type well (2-2) is contained within the N-type well (2-1).

4. The method for evaluating the damage layer during wafer backside thinning as described in claim 1, characterized in that: An isolation groove (2-3) is provided between adjacent PN junctions (2).

5. The method for evaluating the damage layer during wafer backside thinning as described in claim 1, characterized in that: In step S4, the relationship between leakage current and defects in the PN junction depletion layer (4) is shown in the following equation: I leakage ∝ N def = p def × S Among them I leakage ρ is the leakage current intensity. def It is the areal density of the defect, and S is the area.

6. The method for evaluating the damage layer during wafer backside thinning as described in claim 1, characterized in that: In step S4, the differences in different wafer damage layers (3) are obtained by comparing the differences in different leakage current curves.

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