Method for monitoring pollution of semiconductor device by residual halogen elements

Abstract

The invention provides a method for monitoring pollution of a semiconductor device by residual halogen elements, and the method comprises the steps: firstly forming a PN junction conduction loop, a first conductive plug, a middle metal layer and a third conductive plug which are connected with one end of the PN junction conduction loop, and a second conductive plug, a middle metal layer and a fourth conductive plug which are connected with the other end of the PN junction conduction loop; the method comprises the steps of firstly obtaining a defect graph of a semiconductor device, finally obtaining a contact condition and a filling condition of a contact hole according to the defect graph, and diagnosing whether halogen element residues exist or not and whether the semiconductor device is polluted or not according to the contact condition and the filling condition. The PN junction conduction loop is matched with the conductive plug in the contact hole, and the contact condition and the filling condition of the contact hole are diagnosed according to the defect graph, so that the residual condition of the halogen elements can be effectively monitored in real time, the chip quality can be directly responded, and sensitive feedback can be made for the trace change of the halogen elements.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for monitoring the contamination of semiconductor devices by residual halogen elements. Background Art

[0002] In the back-end process of semiconductor devices, different layers of copper metal layers and aluminum metal layers are usually connected to each other through conductive plugs (also called metal plugs) to form a metal interconnection structure. The material of the conductive plug is usually Ti / TiN / W, that is, the copper metal layer, the conductive plug and the aluminum metal layer (CU->Ti / TiN / W->Al) constitute the metal interconnection structure. In the conductive plug, the Ti layer plays the role of gluing the upper and lower layers, and the TiN layer plays the role of blocking / inhibiting the diffusion of metal ions.

[0003] If the Ti layer and the TiN layer are contaminated by halogen elements during or after the deposition process, it will cause poor subsequent W (metal tungsten) filling, resulting in tungsten metal missing on the copper metal wire, affecting the reliability and yield of the final product. In addition, the transfer box that has been loaded with wafers that have been processed by halogen elements will also cause the wafers of other operation procedures to be contaminated by halogen elements when used in other procedures, resulting in the risk of low yield. Therefore, a method for online monitoring of halogen element contamination of semiconductor devices is needed, which can monitor online whether there are halogen element residues inside and on the surface of semiconductor devices and whether they cause contamination. Summary of the invention

[0004] The present application provides a method for monitoring the contamination of semiconductor devices by residual halogen elements, which can solve the problem that the metal interconnect structure is contaminated by halogen elements, affecting the reliability and yield of the final product, but the residual halogen elements cannot be effectively monitored.

[0005] The embodiment of the present application provides a method for monitoring contamination of a semiconductor device by residual halogen elements, comprising: providing a substrate; A semiconductor structure is formed on the substrate, wherein a PN junction conduction loop, a first conductive plug connected to one end of the PN junction conduction loop, a second conductive plug connected to the other end of the PN junction conduction loop, and a first insulating dielectric layer covering the first conductive plug and the second conductive plug are formed in the semiconductor structure; wherein a plurality of grooves are formed in the first insulating dielectric layer, and the grooves respectively expose the top of the first conductive plug and the top of the second conductive plug; forming an intermediate metal layer, wherein the intermediate metal layer fills the trench; forming a second insulating dielectric layer, wherein the second insulating dielectric layer covers the first insulating dielectric layer and the intermediate metal layer; Etching the second insulating dielectric layer to form a plurality of contact holes arranged in an array in the second insulating dielectric layer; Filling a metal material layer in the contact hole to form a third conductive plug and a fourth conductive plug, wherein the third conductive plug is connected to the first conductive plug, and the fourth conductive plug is connected to the second conductive plug through the intermediate metal layer; Removing the metal material layer on the surface of the second insulating dielectric layer by a grinding process; Scanning the semiconductor device after the grinding process by a defect detection machine to obtain a defect map of the semiconductor device; According to the defect map of the semiconductor device, the contact condition at the bottom of the contact hole and the filling condition of the contact hole are obtained. If the contact condition at the bottom of the contact hole and / or the filling condition of the contact hole are abnormal, it is diagnosed that the residual halogen elements have caused contamination to the semiconductor device.

[0006] In the method for monitoring the contamination of a semiconductor device by residual halogen elements, the step of scanning the semiconductor device after the grinding process by a defect detection machine to obtain a defect map of the semiconductor device includes: Scanning the semiconductor device after the grinding process by an electron beam scanning machine to obtain a first defect map of the semiconductor device; The semiconductor device after the grinding process is scanned by a surface defect detection machine to obtain a second defect map of the semiconductor device.

[0007] In the method for monitoring the contamination of a semiconductor device by residual halogen elements, the step of obtaining the contact condition at the bottom of the contact hole and the filling condition of the contact hole according to the defect map of the semiconductor device, and if the contact condition at the bottom of the contact hole and / or the filling condition of the contact hole are abnormal, then diagnosing that the semiconductor device is contaminated by residual halogen elements includes: According to the first defect map, the contact condition between the metal material layer in the contact hole and the intermediate metal layer at the bottom is obtained. If the contact between the metal material layer in the contact hole and the intermediate metal layer at the bottom is abnormal, it is diagnosed that the bottom of the contact hole is contaminated by residual halogen elements. According to the second defect map, the filling condition of the metal material layer in the contact hole is obtained. If the filling condition of the metal material layer in the contact hole is abnormal, it is diagnosed that the surface of the semiconductor device is contaminated by halogen elements.

[0008] In the method for monitoring the contamination of a semiconductor device by residual halogen elements, in the first defect map, if the brightness value of the contact hole area is lower than a preset brightness value, it is confirmed that the contact condition at the bottom of the contact hole is abnormal; In the second defect map, if the upper surface of the metal material layer in the contact hole is lower than the upper surface of the second insulating dielectric layer, it is confirmed that the filling condition of the contact hole is abnormal.

[0009] In the method for monitoring the contamination of a semiconductor device by residual halogen elements, the number of rows of contact holes arranged in an array is at least 3, and the number of columns is at least 3.

[0010] In the method for monitoring the contamination of a semiconductor device by residual halogen elements, the ratio of the total area of ​​all the contact hole patterns to the plane area of ​​the semiconductor structure is greater than 3%.

[0011] In the method for monitoring the contamination of a semiconductor device by residual halogen elements, after forming a plurality of contact holes arranged in an array and before filling a metal material layer in the contact holes to form a third conductive plug and a fourth conductive plug, the method for monitoring the contamination of a semiconductor device by residual halogen elements further includes: A diffusion suppression layer is formed, the diffusion suppression layer covering the sidewalls and the bottom wall of the contact hole.

[0012] In the method for monitoring the contamination of a semiconductor device by residual halogen elements, the diffusion suppression layer comprises a titanium layer and a titanium nitride layer, the titanium layer covers the sidewalls and bottom wall of the contact hole, and the titanium nitride layer covers the titanium layer.

[0013] In the method for monitoring the contamination of a semiconductor device by residual halogen elements, the halogen elements include at least chlorine.

[0014] The technical solution of this application has at least the following advantages: The present application provides a method for monitoring the contamination of a semiconductor device by residual halogen elements. First, a PN junction conduction loop, a first conductive plug connected to one end of the PN junction conduction loop, an intermediate metal layer and a third conductive plug, and a second conductive plug connected to the other end of the PN junction conduction loop, an intermediate metal layer and a fourth conductive plug are formed. Then, after a grinding process, the semiconductor device is scanned by a defect detection machine to obtain a defect map of the semiconductor device. Finally, according to the defect map of the semiconductor device, the contact condition and filling condition of the contact hole are obtained. If the contact condition and / or filling condition of the contact hole are abnormal, it is diagnosed that there is residual halogen element, and the residual halogen element causes contamination to the semiconductor device. The present application cooperates with the conductive plug in the contact hole through the PN junction conduction loop, and can diagnose the contact condition and filling condition of the contact hole according to the defect map, so as to monitor the residual halogen element in real time and effectively. In this way, a direct response can be made to the chip quality, and a keen feedback can be made to the trace changes of the halogen element, thereby improving the monitoring accuracy and monitoring efficiency. In addition, based on the feedback from the above-mentioned monitoring method, a reasonable cleaning frequency can be set for the wafer transfer box in the future, so as to avoid the situation where halogen elements remain on the transfer box and cause the wafer to be contaminated. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 is a flow chart of a method for monitoring contamination of a semiconductor device by residual halogen elements according to an embodiment of the present invention; Figure 2 is a schematic diagram of a semiconductor structure after forming a third conductive plug and a fourth conductive plug according to an embodiment of the present invention; The reference numerals are described as follows: 10-substrate, 11-shallow trench isolation structure, 12-first well region, 13-second well region, 14-first lightly doped drain region, 15-second lightly doped drain region, 21-gate oxide layer 1, 22-gate oxide layer 2, 31-source region 1, 32-drain region 1, 33-source region 2, 34-drain region 2, 41-gate 1, 42-gate 2, 43-sidewall 1, 44-sidewall 2, 45-sidewall 3, 46-first dielectric layer, 51-second dielectric layer, 52-first conductive plug, 53-second conductive plug, 54-third conductive plug, 55-fourth conductive plug, 60-intermediate metal layer, 61-first insulating dielectric layer, 70-second insulating dielectric layer. DETAILED DESCRIPTION

[0017] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0018] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0019] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0020] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0021] The present application embodiment provides a method for monitoring the contamination of a semiconductor device by residual halogen elements, referring to Figure 1 and Figure 2 , Figure 1 is a flow chart of a method for monitoring contamination of a semiconductor device by residual halogen elements according to an embodiment of the present invention, Figure 2 is a schematic diagram of a semiconductor structure after forming a third conductive plug and a fourth conductive plug according to an embodiment of the present invention. The method for monitoring the contamination of a semiconductor device by residual halogen elements includes: First, step S1 is performed: providing a substrate 10, wherein the substrate 10 at least includes a PMOS device region and an NMOS device region, wherein the PMOS device region and the NMOS device region are isolated by a shallow trench isolation structure 11, and a first well region (N well) 12 is formed in the substrate 10 of the PMOS device region; and a second well region (P well) 13 is formed in the substrate 10 of the NMOS device region.

[0022] Then, step S2 is performed: a semiconductor structure is formed on the substrate 10, wherein a PN junction conduction loop, a first conductive plug 52 connected to one end of the PN junction conduction loop, a second conductive plug 53 connected to the other end of the PN junction conduction loop, and a first insulating dielectric layer 61 covering the first conductive plug 52 and the second conductive plug 53 are formed in the semiconductor structure; wherein a plurality of grooves are formed in the first insulating dielectric layer 61, and the grooves expose the top of the first conductive plug 52 and the top of the second conductive plug 53, respectively.

[0023] Specifically, the semiconductor structure on the substrate 10 at least includes: a gate oxide layer 1 21, a gate oxide layer 22, a gate 1 41, a gate 2 42, a sidewall 1 43, a sidewall 2 44, a sidewall 3 45, a first dielectric layer 46, and a second dielectric layer 51. The gate oxide layer 1 21 is located on the substrate 10 of the PMOS device region, the gate 1 41 is located on the gate oxide layer 1 21, the gate 2 42 is located on the gate oxide layer 22, and the sidewall 1 43, the sidewall 2 44, and the sidewall 3 45 are located on both sides of the gate 1 41 and the gate 2 42, respectively. Further, the first dielectric layer 46 covers the gate 1 41, the gate 2 42 and the sidewall 3 45, the second dielectric layer 51 covers the first dielectric layer 46, the first conductive plug 52 penetrates the second dielectric layer 51 and the first dielectric layer 46 and contacts the source region 1 31 of the PMOS device region, the second conductive plug 53 penetrates the second dielectric layer 51 and the first dielectric layer 46 and contacts the drain region 1 32 of the PMOS device region, the first conductive plug 52 also penetrates the second dielectric layer 51 and the first dielectric layer 46 and contacts the source region 2 33 of the NMOS device region, and the second conductive plug 53 also penetrates the second dielectric layer 51 and the first dielectric layer 46 and contacts the drain region 2 34 of the NMOS device region.

[0024] In this embodiment, the first conductive plug 52 and the second conductive plug 53 both include: a titanium layer, a titanium nitride layer and a tungsten metal material layer, the titanium layer covers the side walls and bottom walls of the contact hole where the first conductive plug 52 and the second conductive plug 53 are located, the titanium nitride layer covers the titanium layer, and the tungsten metal material layer fills the remaining space of the contact hole where the first conductive plug 52 and the second conductive plug 53 are located.

[0025] It is worth noting that in the contact holes at the positions of the first conductive plug 52 and the second conductive plug 53, a reaction gas is required during the deposition of the titanium layer and the titanium nitride layer: TDMAT (tetrakis dimethylaminotitanium). The halogen content in the TDMAT gas is prone to exceed the standard, resulting in the deposited titanium nitride layer being contaminated by halogen elements.

[0026] Wherein, the halogen elements at least include: chlorine.

[0027] Preferably, the first dielectric layer 46 is a silicon nitride layer, and the second dielectric layer 51 is a silicon dioxide layer.

[0028] Furthermore, the material of the first insulating dielectric layer 61 is silicon dioxide.

[0029] Next, step S3 is performed: forming an intermediate metal layer 60 , wherein the intermediate metal layer 60 fills the trench.

[0030] In this embodiment, the middle metal layer 60 is made of copper.

[0031] Further, step S4 is performed: forming a second insulating dielectric layer 70 , wherein the second insulating dielectric layer 70 covers the first insulating dielectric layer 61 and the intermediate metal layer 60 .

[0032] In this embodiment, the second insulating dielectric layer 70 is made of silicon dioxide.

[0033] Next, step S5 is performed: etching the second insulating dielectric layer 70 to form a plurality of contact holes arranged in an array in the second insulating dielectric layer 70 .

[0034] Preferably, the number of rows of the contact holes arranged in an array is at least 3, and the number of columns is at least 3.

[0035] Preferably, the ratio of the total area of ​​all the contact hole patterns to the plane area of ​​the semiconductor structure is greater than 3%.

[0036] Furthermore, after forming a plurality of contact holes arranged in an array, and before filling a metal material layer in the contact holes to form a third conductive plug 54 and a fourth conductive plug 55, the method for monitoring contamination of a semiconductor device by residual halogen elements may also include: forming a diffusion inhibition layer, which covers the side walls and bottom walls of the contact holes.

[0037] In this embodiment, the diffusion suppression layer includes: a titanium layer and a titanium nitride layer, the titanium layer covers the sidewall and the bottom wall of the contact hole, and the titanium nitride layer covers the titanium layer.

[0038] Similarly, it is worth noting that in the contact holes at the positions of the third conductive plug 54 and the fourth conductive plug 55, a reaction gas is required during the deposition of the titanium layer and the titanium nitride layer: TDMAT (tetrakis dimethylaminotitanium). The halogen content in the TDMAT gas is prone to exceed the standard, causing the deposited titanium nitride layer to be contaminated by halogen elements. This type of contamination belongs to raw material contamination, which will subsequently cause the bottom of the contact hole to be contaminated by residual halogen elements.

[0039] Next, step S6 is performed: a metal material layer is filled in the contact hole to form a third conductive plug 54 and a fourth conductive plug 55 , wherein the third conductive plug 54 is connected to the first conductive plug 52 , and the fourth conductive plug 55 is connected to the second conductive plug 53 through the intermediate metal layer 60 .

[0040] In this embodiment, the material of the intermediate metal layer 60 is tungsten metal.

[0041] It is worth noting that in the process of forming the third conductive plug 54 and the fourth conductive plug 55 , processes such as tungsten metal deposition and tungsten metal back etching are inevitably performed, wherein the etching gas in the tungsten metal etching process needs to use a gas containing halogen elements.

[0042] Among them, a metal material layer is filled in the contact holes arranged in an array to form a plurality of third conductive plugs 54 and a plurality of fourth conductive plugs 55, each third conductive plug 54 is connected to each first conductive plug 52, each fourth conductive plug 55 is connected to each second conductive plug 53, and as many PN junction conduction circuits as possible are formed, thereby improving the systematicness and reliability of the method for monitoring the contamination of semiconductor devices by residual halogen elements.

[0043] Furthermore, after the deposition of the intermediate metal layer 60 is completed, the wafer transfer box A is first loaded with a batch of wafers that need to undergo a tungsten metal back-etching process. Since the etching gas in the tungsten metal etching process needs to use a gas containing halogen elements, after the tungsten metal back-etching operation is completed, a small amount of halogen elements are brought into the wafer transfer box A by the wafers, and then this batch of wafers will be replaced and placed in the wafer transfer box B. Next, the replaced wafer transfer box A will be used to place another batch of wafers that have completed the titanium nitride layer deposition step. Since the halogen elements brought by the previous batch of wafers remaining in the slots at both ends of the wafer transfer box A are difficult to volatilize, the wafers of another batch at both ends of the slots are more likely to be contaminated by halogen elements. This pollution situation belongs to environmental pollution, which will cause the surface of the semiconductor device to be contaminated by halogen elements.

[0044] Further, step S7 is performed: removing the metal material layer on the surface of the second insulating dielectric layer 70 by a grinding process.

[0045] Next, step S8 is performed: the semiconductor device after the grinding process is scanned by a defect detection machine to obtain a defect map of the semiconductor device.

[0046] Preferably, the step S8 of obtaining a defect map of the semiconductor device by scanning the semiconductor device after the grinding process by a defect detection machine may specifically include: Apply a certain voltage to each PN junction conduction loop for electrical testing; Scanning the semiconductor device after the grinding process by an electron beam scanning machine to obtain a first defect map of the semiconductor device; The semiconductor device after the grinding process is scanned by a surface defect detection machine to obtain a second defect map of the semiconductor device.

[0047] The electron migration conditions in each PN junction conduction loop are obtained through the first defect map and the second defect map.

[0048] Finally, execute step S9: according to the defect map of the semiconductor device, obtain the contact condition at the bottom of the contact hole and the filling condition of the contact hole. If the contact condition at the bottom of the contact hole and / or the filling condition of the contact hole are abnormal, it is diagnosed that the residual halogen element has caused contamination to the semiconductor device.

[0049] Preferably, according to the defect map of the semiconductor device, the contact condition at the bottom of the contact hole and the filling condition of the contact hole are obtained. If the contact condition at the bottom of the contact hole and / or the filling condition of the contact hole are abnormal, the step S9 of diagnosing that the semiconductor device is contaminated by the residual halogen element may specifically include: According to the first defect map, the contact condition between the metal material layer in the contact hole and the intermediate metal layer at the bottom is obtained. If the contact between the metal material layer in the contact hole and the intermediate metal layer at the bottom is abnormal, it is diagnosed that the bottom of the contact hole is contaminated by residual halogen elements. Wherein, in the first defect map, if the brightness value of the contact hole area is lower than a preset brightness value, it is confirmed that the contact condition at the bottom of the contact hole is abnormal. The abnormal contact condition at the bottom of the contact hole is caused by the titanium nitride layer at the bottom of the contact hole being contaminated by the residual halogen elements and causing damage, thereby causing abnormal contact between the metal material layer in the contact hole and the intermediate metal layer at the bottom. According to the second defect map, the filling condition of the metal material layer in the contact hole is obtained. If the filling of the metal material layer in the contact hole is abnormal, it is diagnosed that the surface of the semiconductor device is contaminated by halogen elements. Wherein, in the second defect map, if the upper surface of the metal material layer in the contact hole is lower than the upper surface of the second insulating dielectric layer, that is, if the second defect map shows that the metal material layer in the contact hole is not filled, it is confirmed that the filling condition of the contact hole is abnormal. The abnormal filling condition of the contact hole is caused by the contamination of the wafer conveying box by the residual halogen elements, so that the wafer conveying box continues to contaminate the surface of the subsequent batches of wafers. The surface of the wafer is stained with halogen residues, which will cause the second defect map to be a special map, and its defect is manifested in that the metal material layer in the contact hole is not fully filled.

[0050] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for monitoring the contamination of semiconductor devices by residual halogen elements, characterized in that: include: providing a substrate; A semiconductor structure is formed on the substrate, wherein a PN junction conduction loop, a first conductive plug connected to one end of the PN junction conduction loop, a second conductive plug connected to the other end of the PN junction conduction loop, and a first insulating dielectric layer covering the first conductive plug and the second conductive plug are formed in the semiconductor structure; wherein a plurality of grooves are formed in the first insulating dielectric layer, and the grooves respectively expose the top of the first conductive plug and the top of the second conductive plug; forming an intermediate metal layer, wherein the intermediate metal layer fills the trench; forming a second insulating dielectric layer, wherein the second insulating dielectric layer covers the first insulating dielectric layer and the intermediate metal layer; Etching the second insulating dielectric layer to form a plurality of contact holes arranged in an array in the second insulating dielectric layer; Filling a metal material layer in the contact hole to form a third conductive plug and a fourth conductive plug, wherein the third conductive plug is connected to the first conductive plug, and the fourth conductive plug is connected to the second conductive plug through the intermediate metal layer; Removing the metal material layer on the surface of the second insulating dielectric layer by a grinding process; Scanning the semiconductor device after the grinding process by a defect detection machine to obtain a defect map of the semiconductor device; According to the defect map of the semiconductor device, the contact condition at the bottom of the contact hole and the filling condition of the contact hole are obtained. If the contact condition at the bottom of the contact hole and / or the filling condition of the contact hole are abnormal, it is diagnosed that the residual halogen elements have caused contamination to the semiconductor device.

2. The method for monitoring the contamination of semiconductor devices by residual halogen elements according to claim 1, characterized in that: The step of scanning the semiconductor device after the grinding process by a defect detection machine to obtain a defect map of the semiconductor device includes: Scanning the semiconductor device after the grinding process by an electron beam scanning machine to obtain a first defect map of the semiconductor device; The semiconductor device after the grinding process is scanned by a surface defect detection machine to obtain a second defect map of the semiconductor device.

3. The method for monitoring the contamination of semiconductor devices by residual halogen elements according to claim 2, characterized in that: According to the defect map of the semiconductor device, the contact condition at the bottom of the contact hole and the filling condition of the contact hole are obtained. If the contact condition at the bottom of the contact hole and / or the filling condition of the contact hole are abnormal, the step of diagnosing that the semiconductor device is contaminated by the residual halogen element comprises: According to the first defect map, the contact condition between the metal material layer in the contact hole and the intermediate metal layer at the bottom is obtained. If the contact between the metal material layer in the contact hole and the intermediate metal layer at the bottom is abnormal, it is diagnosed that the bottom of the contact hole is contaminated by residual halogen elements. According to the second defect map, the filling condition of the metal material layer in the contact hole is obtained. If the filling condition of the metal material layer in the contact hole is abnormal, it is diagnosed that the surface of the semiconductor device is contaminated by halogen elements.

4. The method for monitoring the contamination of semiconductor devices by residual halogen elements according to claim 3, characterized in that: In the first defect image, if the brightness value of the contact hole area is lower than the preset brightness value, it is confirmed that the contact condition of the bottom of the contact hole is abnormal; In the second defect map, if the upper surface of the metal material layer in the contact hole is lower than the upper surface of the second insulating dielectric layer, it is confirmed that the filling condition of the contact hole is abnormal.

5. The method for monitoring the contamination of semiconductor devices by residual halogen elements according to claim 1, characterized in that: The number of rows of the contact holes arranged in an array is at least 3, and the number of columns is at least 3.

6. The method for monitoring the contamination of semiconductor devices by residual halogen elements according to claim 1, characterized in that: The ratio of the total area of ​​all the contact hole patterns to the plane area of ​​the semiconductor structure is greater than 3%.

7. The method for monitoring the contamination of semiconductor devices by residual halogen elements according to claim 1, characterized in that: After forming a plurality of contact holes arranged in an array and before filling a metal material layer in the contact holes to form a third conductive plug and a fourth conductive plug, the method for monitoring contamination of a semiconductor device by residual halogen elements further includes: A diffusion suppression layer is formed, the diffusion suppression layer covering the sidewalls and the bottom wall of the contact hole.

8. The method for monitoring the contamination of semiconductor devices by residual halogen elements according to claim 7, characterized in that: The diffusion suppression layer includes a titanium layer and a titanium nitride layer, the titanium layer covers the sidewall and the bottom wall of the contact hole, and the titanium nitride layer covers the titanium layer.

9. The method for monitoring the contamination of semiconductor devices by residual halogen elements according to claim 1, characterized in that: The halogen elements include at least chlorine.

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