Methods for monitoring semiconductor devices contamination by residual halogen elements

Abstract

This application provides a method for monitoring semiconductor devices contaminated by residual halogen elements. First, a PN junction conduction loop is formed, along with a first conductive plug connected to one end of the PN junction conduction loop, an intermediate metal layer, and a third conductive plug. Then, a second conductive plug, an intermediate metal layer, and a fourth conductive plug are connected to the other end of the PN junction conduction loop. Subsequently, a defect map of the semiconductor device is obtained. Finally, based on the defect map, the contact and filling conditions of the contact holes are obtained, and the presence of residual halogen elements and whether they have contaminated the semiconductor device are diagnosed based on the contact and filling conditions. This application, through the cooperation of the PN junction conduction loop and the conductive plugs in the contact holes, and by diagnosing the contact and filling conditions of the contact holes based on the defect map, enables real-time and effective monitoring of residual halogen elements. This allows for a direct response to chip quality and provides sensitive feedback on minute changes in halogen levels.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and more specifically to a method for monitoring semiconductor devices contaminated by residual halogen elements. Background Technology

[0002] In the back-end processes of semiconductor devices, different copper and aluminum metal layers are typically interconnected using conductive plugs (also called metal plugs) to form a metal interconnect structure. The conductive plugs are usually made of Ti / TiN / W, meaning the copper metal layer, conductive plug, and aluminum metal layer (Cu->Ti / TiN / W->Al) constitute the metal interconnect structure. In the conductive plug, the Ti layer acts as a glue between the upper and lower layers, while the TiN layer blocks / suppresses the diffusion of metal ions.

[0003] If Ti and TiN layers are contaminated by halogens during or after deposition, it can lead to poor subsequent tungsten (W) filling, resulting in tungsten metal defects on the copper wires and affecting the reliability and yield of the final product. Furthermore, using a transport container that has handled halogen-contaminated wafers for other processes can also contaminate wafers for those processes, leading to low yields. Therefore, a method for online monitoring of halogen contamination in semiconductor devices is needed to monitor the presence of halogen residues and contamination issues both inside and on the surface of the semiconductor device. Summary of the Invention

[0004] This application provides a method for monitoring semiconductor devices contaminated by residual halogen elements, which can solve the problem that halogen contamination of metal interconnect structures affects the reliability and yield of the final product, but the residual halogen elements cannot be effectively monitored.

[0005] This application provides a method for monitoring semiconductor devices contaminated by residual halogen elements, including:

[0006] Provide a substrate;

[0007] A semiconductor structure is formed on the substrate, wherein a PN junction conduction loop, a first conductive plug connected to one end of the PN junction conduction loop, a second conductive plug connected to the other end of the PN junction conduction loop, and a first insulating dielectric layer covering the first conductive plug and the second conductive plug are formed; wherein a plurality of trenches are formed in the first insulating dielectric layer, and the trenches expose the top ends of the first conductive plug and the second conductive plug respectively;

[0008] An intermediate metal layer is formed, which fills the trench;

[0009] A second insulating dielectric layer is formed, which covers the first insulating dielectric layer and the intermediate metal layer;

[0010] The second insulating dielectric layer is etched to form a plurality of contact holes arranged in an array in the second insulating dielectric layer;

[0011] A metal material layer is filled into the contact hole to form a third conductive plug and a fourth conductive plug, wherein the third conductive plug is connected to the first conductive plug and the fourth conductive plug is connected to the second conductive plug through the intermediate metal layer;

[0012] The metal material layer on the surface of the second insulating dielectric layer is removed by a grinding process;

[0013] The semiconductor device after the polishing process is scanned by a defect inspection machine to obtain a defect map of the semiconductor device;

[0014] Based on the defect diagram of the semiconductor device, the contact condition at the bottom of the contact hole and the filling condition of the contact hole are obtained. If the contact condition at the bottom of the contact hole and / or the filling condition of the contact hole are abnormal, it is diagnosed that halogen residue has caused contamination to the semiconductor device.

[0015] In the method for monitoring semiconductor devices contaminated by residual halogen elements, the step of obtaining a defect map of the semiconductor device by scanning the semiconductor device after the polishing process using a defect inspection machine includes:

[0016] The semiconductor device after the polishing process is performed is scanned using an electron beam scanning machine to obtain a first defect map of the semiconductor device;

[0017] A second defect map of the semiconductor device is obtained by scanning the semiconductor device after the polishing process using a surface defect inspection machine.

[0018] In the method for monitoring semiconductor devices contaminated by residual halogen elements, the contact condition at the bottom of the contact hole and the filling condition of the contact hole are obtained based on the defect map of the semiconductor device. If the contact condition at the bottom of the contact hole and / or the filling condition of the contact hole are abnormal, the step of diagnosing contamination of the semiconductor device by residual halogen elements includes:

[0019] Based on the first defect diagram, the contact condition between the metal material layer in the contact hole and the bottom intermediate metal layer is obtained. If the contact between the metal material layer in the contact hole and the bottom intermediate metal layer is abnormal, it is diagnosed that the bottom of the contact hole is contaminated by residual halogen elements.

[0020] Based on the second defect diagram, the filling status of the metal material layer in the contact hole is obtained. If the filling of the metal material layer in the contact hole is abnormal, the semiconductor device surface is diagnosed as being contaminated by halogen elements.

[0021] In the method for monitoring semiconductor devices contaminated by residual halogen elements, if the brightness value of the contact hole area is lower than a preset brightness value in the first defect diagram, it is confirmed that the contact condition at the bottom of the contact hole is abnormal.

[0022] In the second defect diagram, if the upper surface of the metal material layer in the contact hole is lower than the upper surface of the second insulating dielectric layer, then the filling condition of the contact hole is confirmed to be abnormal.

[0023] In the method for monitoring semiconductor devices contaminated by residual halogen elements, the number of rows of contact holes arranged in an array is at least 3, and the number of columns is at least 3.

[0024] In the method for monitoring semiconductor devices for contamination by residual halogen elements, the ratio of the total area of ​​all the contact hole patterns to the planar area of ​​the semiconductor structure is >3%.

[0025] In the method for monitoring semiconductor device contamination by residual halogen elements, after forming a plurality of contact holes arranged in an array, and before filling the contact holes with a layer of metal material to form a third conductive plug and a fourth conductive plug, the method further includes:

[0026] A diffusion inhibition layer is formed, which covers the sidewalls and bottom wall of the contact hole.

[0027] In the method for monitoring semiconductor devices contaminated by residual halogen elements, the diffusion suppression layer comprises a titanium layer and a titanium nitride layer, wherein the titanium layer covers the sidewalls and bottom wall of the contact hole, and the titanium nitride layer covers the titanium layer.

[0028] In the method for monitoring semiconductor devices for contamination by residual halogen elements, the halogen elements include at least chlorine.

[0029] The technical solution of this application has at least the following advantages:

[0030] This application provides a method for monitoring semiconductor devices contaminated by residual halogen elements. First, a PN junction conducting loop is formed, along with a first conductive plug connected to one end of the PN junction conducting loop, an intermediate metal layer, and a third conductive plug. Then, a second conductive plug, an intermediate metal layer, and a fourth conductive plug are connected to the other end of the PN junction conducting loop. Following a polishing process, the semiconductor device is scanned using a defect inspection machine to obtain a defect map. Finally, based on the defect map, the contact and filling conditions of the contact holes are determined. If the contact and / or filling conditions of the contact holes are abnormal, it is diagnosed that residual halogen elements are present and that these halogen elements are contaminating the semiconductor device. This application, through the cooperation of the PN junction conducting loop and the conductive plugs in the contact holes, and by diagnosing the contact and filling conditions of the contact holes based on the defect map, enables real-time and effective monitoring of residual halogen elements. This allows for a direct response to chip quality issues and provides sensitive feedback on minute changes in halogen elements, improving monitoring accuracy and efficiency. Furthermore, based on feedback from the aforementioned monitoring methods, a reasonable cleaning frequency can be established for the wafer transfer box to prevent halogen elements from remaining on the transfer box and causing wafer contamination. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0032] Figure 1 This is a flowchart of a method for monitoring semiconductor devices contaminated by residual halogen elements according to an embodiment of the present invention;

[0033] Figure 2 This is a schematic diagram of the semiconductor structure after the formation of the third conductive plug and the fourth conductive plug according to an embodiment of the present invention;

[0034] The reference numerals in the attached figures are explained as follows:

[0035] 10-Substrate, 11-Shallow trench isolation structure, 12-First well region, 13-Second well region, 14-First lightly doped drain region, 15-Second lightly doped drain region, 21-Gate oxide layer one, 22-Gate oxide layer two, 31-Source region one, 32-Drain region one, 33-Source region two, 34-Drain region two, 41-Gate gate one, 42-Gate gate two, 43-Sidewall one, 44-Sidewall two, 45-Sidewall three, 46-First dielectric layer, 51-Second dielectric layer, 52-First conductive plug, 53-Second conductive plug, 54-Third conductive plug, 55-Fourth conductive plug, 60-Intermediate metal layer, 61-First insulating dielectric layer, 70-Second insulating dielectric layer. Detailed Implementation

[0036] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0038] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0039] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0040] This application provides a method for monitoring semiconductor devices contaminated by residual halogen elements, referring to... Figure 1 and Figure 2 , Figure 1This is a flowchart of a method for monitoring semiconductor devices contaminated by residual halogen elements according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the semiconductor structure after the formation of the third and fourth conductive plugs according to an embodiment of the present invention. The method for monitoring the semiconductor device for contamination by residual halogen elements includes:

[0041] First, step S1 is performed: a substrate 10 is provided, the substrate 10 including at least a PMOS device region and an NMOS device region, wherein the PMOS device region and the NMOS device region are separated by a shallow trench isolation structure 11, a first well region (N-well) 12 is formed in the substrate 10 of the PMOS device region, and a second well region (P-well) 13 is formed in the substrate 10 of the NMOS device region.

[0042] Then, step S2 is performed: a semiconductor structure is formed on the substrate 10, wherein a PN junction conduction loop, a first conductive plug 52 connected to one end of the PN junction conduction loop, a second conductive plug 53 connected to the other end of the PN junction conduction loop, and a first insulating dielectric layer 61 covering the first conductive plug 52 and the second conductive plug 53 are formed in the semiconductor structure; wherein, a plurality of trenches are formed in the first insulating dielectric layer 61, and the trenches expose the top ends of the first conductive plug 52 and the second conductive plug 53 respectively.

[0043] Specifically, the semiconductor structure on the substrate 10 includes at least: a first gate oxide layer 21, a second gate oxide layer 22, a first gate 41, a second gate 42, a first sidewall 43, a second sidewall 44, a third sidewall 45, a first dielectric layer 46, and a second dielectric layer 51. The first gate oxide layer 21 is located on the substrate 10 of the PMOS device region, the first gate 41 is located on the first gate oxide layer 21, the second gate 42 is located on the second gate oxide layer 22, and the first sidewall 43, the second sidewall 44, and the third sidewall 45 are located on opposite sides of the first gate 41 and the second gate 42, respectively. Furthermore, the first dielectric layer 46 covers the gate 1 41, gate 2 42 and sidewall 3 45, the second dielectric layer 51 covers the first dielectric layer 46, the first conductive plug 52 penetrates the second dielectric layer 51 and the first dielectric layer 46 and contacts the source region 1 31 of the PMOS device region, the second conductive plug 53 penetrates the second dielectric layer 51 and the first dielectric layer 46 and contacts the drain region 1 32 of the PMOS device region, the first conductive plug 52 also penetrates the second dielectric layer 51 and the first dielectric layer 46 and contacts the source region 2 33 of the NMOS device region, and the second conductive plug 53 also penetrates the second dielectric layer 51 and the first dielectric layer 46 and contacts the drain region 2 34 of the NMOS device region.

[0044] In this embodiment, both the first conductive plug 52 and the second conductive plug 53 include: a titanium layer, a titanium nitride layer, and a tungsten metal material layer. The titanium layer covers the sidewalls and bottom walls of the contact holes at the locations of the first conductive plug 52 and the second conductive plug 53. The titanium nitride layer covers the titanium layer, and the tungsten metal material layer fills the remaining space of the contact holes at the locations of the first conductive plug 52 and the second conductive plug 53.

[0045] It is worth noting that a reaction gas, TDMAT (tetramethylaminotitanium), is required during the deposition of titanium and titanium nitride layers in the contact holes at the positions of the first conductive plug 52 and the second conductive plug 53. The halogen content in TDMAT gas is prone to exceed the standard, which can lead to contamination of the deposited titanium nitride layer with halogen elements.

[0046] The halogens include at least chlorine.

[0047] Preferably, the first dielectric layer 46 is a silicon nitride layer, and the second dielectric layer 51 is a silicon dioxide layer.

[0048] Furthermore, the first insulating dielectric layer 61 is made of silicon dioxide.

[0049] Next, step S3 is performed: an intermediate metal layer 60 is formed, which fills the trench.

[0050] In this embodiment, the intermediate metal layer 60 is made of copper.

[0051] Further, step S4 is performed: forming a second insulating dielectric layer 70, which covers the first insulating dielectric layer 61 and the intermediate metal layer 60.

[0052] In this embodiment, the second insulating dielectric layer 70 is made of silicon dioxide.

[0053] Next, step S5 is performed: etching the second insulating dielectric layer 70 to form a plurality of contact holes arranged in an array in the second insulating dielectric layer 70.

[0054] Preferably, the number of rows of contact holes arranged in an array is at least 3 and the number of columns is at least 3.

[0055] Preferably, the ratio of the total area of ​​all the contact hole patterns to the planar area of ​​the semiconductor structure is >3%.

[0056] Furthermore, after forming a plurality of contact holes arranged in an array, and before filling the contact holes with a layer of metal material to form a third conductive plug 54 and a fourth conductive plug 55, the method for monitoring semiconductor devices for contamination by residual halogen elements may further include: forming a diffusion inhibition layer that covers the sidewalls and bottom wall of the contact holes.

[0057] In this embodiment, the diffusion suppression layer includes a titanium layer and a titanium nitride layer, wherein the titanium layer covers the sidewalls and bottom wall of the contact hole, and the titanium nitride layer covers the titanium layer.

[0058] Similarly, it is worth noting that in the contact holes at the positions of the third conductive plug 54 and the fourth conductive plug 55, a reaction gas, TDMAT (tetramethylaminotitanium), is required during the deposition of the titanium layer and the titanium nitride layer. The halogen content in TDMAT gas is prone to exceed the standard, which will cause the deposited titanium nitride layer to be contaminated by halogen elements. This contamination is a raw material contamination, which will subsequently cause the bottom of the contact hole to be contaminated by residual halogen elements.

[0059] Next, step S6 is performed: a metal material layer is filled into the contact hole to form a third conductive plug 54 and a fourth conductive plug 55, wherein the third conductive plug 54 is connected to the first conductive plug 52 and the fourth conductive plug 55 is connected to the second conductive plug 53 through the intermediate metal layer 60.

[0060] In this embodiment, the intermediate metal layer 60 is made of tungsten metal.

[0061] It is worth noting that during the formation of the third conductive plug 54 and the fourth conductive plug 55, tungsten metal deposition and tungsten metal etching processes are inevitably involved. In particular, the etching gas used in the tungsten metal etching process needs to contain halogens.

[0062] In this method, a metal material layer is filled into the contact holes arranged in an array to form multiple third conductive plugs 54 and multiple fourth conductive plugs 55. Each third conductive plug 54 is connected to each first conductive plug 52, and each fourth conductive plug 55 is connected to each second conductive plug 53. This forms as many PN junction conduction loops as possible, improving the systematicness and reliability of the method for monitoring semiconductor devices contaminated by residual halogen elements.

[0063] Furthermore, after the intermediate metal layer 60 is deposited, wafer transfer box A first contains a batch of wafers that need to undergo the tungsten metal back etching process. Since the etching gas used in the tungsten metal etching process requires a gas containing halogen elements, a small amount of halogen elements is carried into wafer transfer box A after the tungsten metal back etching operation is completed. This batch of wafers is then replaced and placed in wafer transfer box B. Next, the removed wafer transfer box A is used to place another batch of wafers that have completed the titanium nitride layer deposition step. Because the halogen elements remaining at the slots at both ends of wafer transfer box A from the previous batch are difficult to volatilize, the other batch of wafers at the slots are more easily contaminated by halogen elements. This contamination is considered environmental pollution and will cause halogen contamination of the semiconductor device surface.

[0064] Further, step S7 is performed: the metal material layer on the surface of the second insulating dielectric layer 70 is removed by a grinding process.

[0065] Next, step S8 is executed: the semiconductor device after the polishing process is performed is scanned by a defect inspection machine to obtain a defect map of the semiconductor device.

[0066] Preferably, step S8, which involves scanning the semiconductor device after the polishing process using a defect inspection machine to obtain a defect map of the semiconductor device, may specifically include:

[0067] A certain voltage is applied to each PN junction conduction loop to perform electrical tests;

[0068] The semiconductor device after the polishing process is performed is scanned using an electron beam scanning machine to obtain a first defect map of the semiconductor device;

[0069] A second defect map of the semiconductor device is obtained by scanning the semiconductor device after the polishing process using a surface defect inspection machine.

[0070] The electron migration in the conduction loop of each PN junction is obtained by using the first defect map and the second defect map.

[0071] Finally, step S9 is executed: based on the defect diagram of the semiconductor device, the contact condition at the bottom of the contact hole and the filling condition of the contact hole are obtained. If the contact condition at the bottom of the contact hole and / or the filling condition of the contact hole are abnormal, it is diagnosed that halogen residue has caused contamination to the semiconductor device.

[0072] Preferably, based on the defect map of the semiconductor device, the contact condition at the bottom of the contact hole and the filling condition of the contact hole are obtained. If the contact condition at the bottom of the contact hole and / or the filling condition of the contact hole are abnormal, then step S9, which diagnoses the contamination of the semiconductor device by residual halogen elements, may specifically include:

[0073] Based on the first defect diagram, the contact condition between the metal material layer in the contact hole and the bottom intermediate metal layer is obtained. If the contact between the metal material layer in the contact hole and the bottom intermediate metal layer is abnormal, it is diagnosed that the bottom of the contact hole is contaminated by residual halogen elements. In the first defect diagram, if the brightness value of the contact hole area is lower than a preset brightness value, it is confirmed that the contact condition at the bottom of the contact hole is abnormal. The abnormal contact condition at the bottom of the contact hole is caused by damage to the titanium nitride layer at the bottom of the contact hole due to contamination by residual halogen elements, thereby causing abnormal contact between the metal material layer in the contact hole and the bottom intermediate metal layer.

[0074] Based on the second defect map, the filling status of the metal material layer in the contact hole is obtained. If the filling of the metal material layer in the contact hole is abnormal, it is diagnosed that the semiconductor device surface is contaminated by halogen elements. Specifically, in the second defect map, if the upper surface of the metal material layer in the contact hole is lower than the upper surface of the second insulating dielectric layer, that is, if the second defect map shows that the metal material layer in the contact hole is not fully filled, it is confirmed that the filling status of the contact hole is abnormal. The abnormal filling status of the contact hole is caused by residual halogen elements contaminating the wafer transfer box, which in turn continues to contaminate the surface of subsequent batches of wafers. The residual halogen elements on the wafer surface will cause the second defect map to be a special map, the defect manifestation of which is that the metal material layer in the contact hole is not fully filled.

[0075] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for monitoring contamination of semiconductor devices by residual halogen elements, characterized in that, include: Provide a substrate; A semiconductor structure is formed on the substrate, wherein a PN junction conduction loop, a first conductive plug connected to one end of the PN junction conduction loop, a second conductive plug connected to the other end of the PN junction conduction loop, and a first insulating dielectric layer covering the first conductive plug and the second conductive plug are formed; wherein a plurality of trenches are formed in the first insulating dielectric layer, and the trenches expose the top ends of the first conductive plug and the second conductive plug respectively; An intermediate metal layer is formed, which fills the trench; A second insulating dielectric layer is formed, which covers the first insulating dielectric layer and the intermediate metal layer; The second insulating dielectric layer is etched to form a plurality of contact holes arranged in an array in the second insulating dielectric layer; A metal material layer is filled into the contact hole to form a third conductive plug and a fourth conductive plug, wherein the third conductive plug is connected to the first conductive plug and the fourth conductive plug is connected to the second conductive plug through the intermediate metal layer; The metal material layer on the surface of the second insulating dielectric layer is removed by a grinding process; The semiconductor device after the polishing process is performed is scanned using an electron beam scanning machine to obtain a first defect map of the semiconductor device; A second defect map of the semiconductor device is obtained by scanning the semiconductor device after the polishing process using a surface defect inspection machine. Based on the first defect diagram, the contact condition between the metal material layer in the contact hole and the bottom intermediate metal layer is obtained. If the contact between the metal material layer in the contact hole and the bottom intermediate metal layer is abnormal, it is diagnosed that the bottom of the contact hole is contaminated by residual halogen elements. Based on the second defect diagram, the filling status of the metal material layer in the contact hole is obtained. If the filling of the metal material layer in the contact hole is abnormal, the semiconductor device surface is diagnosed as being contaminated by halogen elements.

2. The method for monitoring semiconductor devices contaminated by residual halogen elements according to claim 1, characterized in that, In the first defect diagram, if the brightness value of the contact hole area is lower than the preset brightness value, it is confirmed that the contact condition at the bottom of the contact hole is abnormal. In the second defect diagram, if the upper surface of the metal material layer in the contact hole is lower than the upper surface of the second insulating dielectric layer, then the filling condition of the contact hole is confirmed to be abnormal.

3. The method for monitoring semiconductor devices contaminated by residual halogen elements according to claim 1, characterized in that, The number of rows and columns of the contact holes arranged in an array shall be at least 3.

4. The method for monitoring semiconductor devices contaminated by residual halogen elements according to claim 1, characterized in that, The ratio of the total area of ​​all the contact hole patterns to the planar area of ​​the semiconductor structure is >3%.

5. The method for monitoring semiconductor devices contaminated by residual halogen elements according to claim 1, characterized in that, After forming a plurality of contact holes arranged in an array, and before filling the contact holes with a layer of metal material to form a third conductive plug and a fourth conductive plug, the method for monitoring semiconductor devices for contamination by residual halogen elements further includes: A diffusion inhibition layer is formed, which covers the sidewalls and bottom wall of the contact hole.

6. The method for monitoring semiconductor devices contaminated by residual halogen elements according to claim 5, characterized in that, The diffusion suppression layer comprises a titanium layer and a titanium nitride layer, wherein the titanium layer covers the sidewalls and bottom wall of the contact hole, and the titanium nitride layer covers the titanium layer.

7. The method for monitoring semiconductor devices contaminated by residual halogen elements according to claim 1, characterized in that, The halogens include at least chlorine.

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