Wiring structure and amplifier

Abstract

The invention relates to a wiring structure and an amplifier. A wiring structure is provided with an MIM capacitor and a spiral wiring. This wiring structure is provided with: a substrate having a main surface and a back surface; and a plurality of wiring layers sequentially laminated on the main surface. The plurality of wiring layers includes: a first wiring layer which is a wiring layer closest to the substrate; the second wiring layer is arranged on the first wiring layer; and a third wiring layer disposed on the second wiring layer. The MIM capacitor is configured to include: a first electrode included in a second wiring layer; a second electrode included in the third wiring layer; and a first insulating layer disposed between the first electrode and the second electrode. The spiral wiring is configured to include: a first wiring included in a first wiring layer; a second wiring included in the second wiring layer; and a third wiring included in the third wiring layer.

Description

Technical Field

[0001] The present disclosure relates to wiring structures and amplifiers. Background Art

[0002] Patent Document 1 discloses an inductor formed of a plurality of wiring layers on a substrate. The inductor is formed by connecting a plurality of C-shaped wirings included in the plurality of wiring layers to each other.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2008 / 016089

[0006] For example, in semiconductor devices such as semiconductor amplifiers, multiple wiring layers on a substrate are sometimes used to form MIM (Metal-Insulator-Metal) capacitors and spiral wirings that serve as inductors. In this case, when the first wiring layer is used to form the lower electrode of the MIM capacitor, the flatness of the lower electrode is sometimes impaired. When the flatness of the lower electrode is impaired, the unevenness of the thickness of the insulating layer formed between the lower electrode and the upper electrode becomes larger, and the electric field in the part where the thickness of the insulating layer is small becomes locally larger. This will lead to uneven characteristics of the semiconductor device and a decrease in the reliability of the semiconductor device. In addition, when there are many spiral wirings as inductors, more wiring layers are required compared to MIM capacitors, but when the number of wiring layers increases, the time required for manufacturing becomes longer, so it is desirable to reduce the overall number of wiring layers. Summary of the invention

[0007] The present disclosure has been made in view of such problems, and an object of the present disclosure is to suppress a local increase in an electric field in a MIM capacitor and reduce the number of overall wiring layers in a wiring structure and an amplifier including a MIM capacitor and a spiral wiring.

[0008] In order to solve the above-mentioned problems, the wiring structure disclosed in the present invention has a MIM capacitor and a spiral wiring, wherein the wiring structure has: a substrate having a main surface and a back surface; and a plurality of wiring layers stacked in sequence on the main surface. The plurality of wiring layers include: a first wiring layer, which is the wiring layer closest to the substrate; a second wiring layer, which is arranged on the first wiring layer; and a third wiring layer, which is arranged on the second wiring layer. The MIM capacitor is constructed to include: a first electrode, which is included in the second wiring layer; a second electrode, which is included in the third wiring layer; and a first insulating layer, which is arranged between the first electrode and the second electrode. The spiral wiring is constructed to include: a first wiring, which is included in the first wiring layer; a second wiring, which is included in the second wiring layer; and a third wiring, which is included in the third wiring layer.

[0009] Effects of the Invention

[0010] According to the wiring structure and amplifier of the present disclosure, in a wiring structure including a MIM capacitor and a spiral wiring, local increase of the electric field in the MIM capacitor can be suppressed and the number of overall wiring layers can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a diagram showing a cross-sectional structure of the wiring structure according to the first embodiment.

[0012] Figure 2 It is a perspective view showing the three-dimensional structure of an inductor.

[0013] Figure 3 This is a circuit diagram showing the configuration of an amplifier having a wiring structure.

[0014] Figure 4 This is a graph showing the relationship between the number of wiring layers and the area in the inductor and the relationship between the number of wiring layers and the film formation time of the insulating layer in the inductor.

[0015] Figure 5 It is a circuit diagram of a passive element according to the second embodiment.

[0016] Figure 6 This is a top view of the wiring structure of the passive components.

[0017] Figure 7 It is a diagram showing a cross-sectional structure of a wiring structure.

[0018] Figure 8 It is a diagram showing a cross-sectional structure of a wiring structure of a comparative example.

[0019] Description of Reference Numerals

[0020] 1: Amplifier;

[0021] 2: Passive components;

[0022] 10A, 10B: wiring structure;

[0023] 11: Transistor;

[0024] 12: Wiring part;

[0025] 13, 13A, 13B: MIM capacitors;

[0026] 14: Inductor;

[0027] 16: Reference potential line;

[0028] 20: substrate;

[0029] 21: Main side;

[0030] 22: back;

[0031] 23: hole;

[0032] 31: insulating layer (second insulating layer);

[0033] 32: insulating layer (first insulating layer);

[0034] 33, 34: insulation layer;

[0035] 40: Insulation film;

[0036] 41: source electrode;

[0037] 42: drain electrode;

[0038] 43: gate electrode;

[0039] 44: Field plate;

[0040] 50: first wiring layer;

[0041] 51: source wiring;

[0042] 52: drain wiring;

[0043] 53: Wiring;

[0044] 54: Wiring (fourth wiring);

[0045] 55: Wiring (first wiring);

[0046] 60: second wiring layer;

[0047] 61: Wiring;

[0048] 62: lower electrode (first electrode);

[0049] 63: Wiring (second wiring);

[0050] 70: third wiring layer;

[0051] 71: Wiring;

[0052] 72: upper electrode (second electrode);

[0053] 73: Wiring (third wiring);

[0054] 80: fourth wiring layer;

[0055] 81: Wiring;

[0056] 82: Wiring (sixth wiring);

[0057] 83: Wiring (fifth wiring);

[0058] 84: Wiring;

[0059] 91: Metal film;

[0060] 92: via (second via);

[0061] 101: via;

[0062] 102: via (first via);

[0063] 103, 111: vias;

[0064] 112: via (third via);

[0065] 121, 122: vias;

[0066] 131, 132, 133, 134, 135, 136: capacitors;

[0067] 141, 142, 143, 144: inductors;

[0068] 151, 152: bias power supply;

[0069] 191, 201: input terminals;

[0070] 192, 203: output terminals;

[0071] 202: node;

[0072] 631, 731: gap;

[0073] 552, 632, 732, 733, 832: end;

[0074] G1, G2: Straight line. DETAILED DESCRIPTION

[0075] [Description of Embodiments of the Present Disclosure]

[0076] First, the contents of the embodiments of the present disclosure are listed for explanation. [1] A wiring structure of one aspect of the present disclosure includes a MIM capacitor and a spiral wiring, wherein the wiring structure includes: a substrate having a main surface and a back surface; and a plurality of wiring layers stacked in sequence on the main surface. The plurality of wiring layers include: a first wiring layer, which is the wiring layer closest to the substrate; a second wiring layer, which is arranged on the first wiring layer; and a third wiring layer, which is arranged on the second wiring layer. The MIM capacitor is configured to include: a first electrode, which is included in the second wiring layer; a second electrode, which is included in the third wiring layer; and a first insulating layer, which is arranged between the first electrode and the second electrode. The spiral wiring is configured to include: a first wiring, which is included in the first wiring layer; a second wiring, which is included in the second wiring layer; and a third wiring, which is included in the third wiring layer.

[0077] In this wiring structure, the first electrode (lower electrode) of the MIM capacitor is not included in the first wiring layer as the lowest layer among the multiple wiring layers on the substrate, but is included in the second wiring layer provided on the first wiring layer. Usually, an insulating layer is sandwiched between the first wiring layer and the second wiring layer. The surface unevenness of the first wiring layer is gradually eliminated on the surface of the insulating layer when the insulating layers are stacked. Therefore, by including the first electrode in the second wiring layer, the surface of the first electrode can be flattened compared to the case where the first electrode is included in the first wiring layer. As a result, the unevenness of the thickness of the first insulating layer formed between the first electrode and the second electrode becomes smaller, which can suppress the local increase of the electric field in the MIM capacitor. In addition, the spiral wiring (inductor) is configured to include: a first wiring of the first wiring layer as the lowest layer among the multiple wiring layers; and a second wiring and a third wiring, respectively included in the second wiring layer and the third wiring layer also used for the MIM capacitor. Therefore, the overall number of wiring layers can be reduced.

[0078] [2] Alternatively, the wiring structure of [1] may further include: a fourth wiring provided between the MIM capacitor and the substrate and included in the first wiring layer; and one or more first vias connecting the first electrode to the fourth wiring. In this case, the first electrode can be electrically connected to the fourth wiring included in the first wiring layer with low inductance.

[0079] [3] Alternatively, the wiring structure of [2] above may further include: a metal film disposed on the back surface; and a second via hole disposed between the main surface and the back surface of the substrate to connect the metal film to the fourth wiring. Alternatively, when viewed from a direction perpendicular to the main surface, the second via hole overlaps with the MIM capacitor and the fourth wiring. In this case, the first electrode of the MIM capacitor can be electrically connected to the metal film (e.g., a reference potential line) disposed on the back surface. In addition, compared to a case where the second via hole is disposed at a position that does not overlap with the MIM capacitor when viewed from a direction perpendicular to the main surface, the area on the main surface required for the wiring structure can be reduced, and the wiring structure can be miniaturized.

[0080] [4] In the wiring structures of [1] to [3] above, the spiral wiring may also include a plurality of third vias, which are dispersedly arranged throughout the entire area of ​​the second wiring and the third wiring, connecting the second wiring to the third wiring. In this case, the potential of the second wiring is uniformly close to the potential of the third wiring throughout the entire area. Therefore, the inter-wiring capacitance generated by the potential difference between the second wiring and the third wiring can be reduced, thereby reducing the capacitance component (parasitic capacitance) of the spiral wiring (inductor). Not only that, the deviation of the flow of current can be reduced between the second wiring and the third wiring. Moreover, by integrating the second wiring and the third wiring, even if the thickness of the second wiring and the thickness of the third wiring are reduced, the decrease in allowable current density and the increase in wiring resistance can be suppressed.

[0081] [5] In the wiring structure of [4] above, the thickness of the second wiring and the thickness of the third wiring may be smaller than the thickness of the first wiring. In this case, by connecting the second wiring and the third wiring via a plurality of third vias as in [4] above, it is possible to suppress a partial increase in the current density of the spiral wiring (inductor). In addition, by reducing the thickness of the second wiring and the thickness of the third wiring, it is possible to shorten the wiring formation time.

[0082] [6] In the wiring structure of [5] above, the thickness of the wiring in the second wiring layer may be smaller than the thickness of the wiring in the third wiring layer. In this case, the possibility of disconnection of the wiring in the third wiring layer extending from the second electrode of the MIM capacitor can be reduced, and the wiring in the second wiring layer can be thinned to shorten the formation time of the second wiring layer.

[0083] [7] In the wiring structure of [5] above, the sum of the thickness of the second wiring and the thickness of the third wiring may be equal to the thickness of the first wiring. In this case, the current density of the spiral wiring (inductor) can be made uniform.

[0084] [8] In the wiring structure of [4] above, the plurality of wiring layers may further include a fourth wiring layer stacked on the third wiring layer. Alternatively, the spiral wiring may further include a fifth wiring included in the fourth wiring layer. In this case, it is possible to facilitate the design of a spiral wiring (inductor) having a larger inductance.

[0085] [9] In the wiring structure of [8] above, the thickness of the fifth wiring may be equal to or greater than the thickness of the first wiring. The fifth wiring is included in the fourth wiring layer which is the uppermost layer, so even if the fifth wiring is formed thick, the time required to form the insulating layer does not increase. By forming the fifth wiring thick, the current density of the fifth wiring can be sufficiently reduced.

[0086]

[10] In the wiring structure of [8] above, the first wiring, the second wiring, the third wiring, and the fifth wiring may each be in a ring shape having a gap in a portion, and the first wiring, the second wiring, the third wiring, and the fifth wiring may be arranged in a manner such that the center of the ring is located on a common axis perpendicular to the main surface, and the gap of the second wiring and the gap of the third wiring are arranged in a direction perpendicular to the main surface. Alternatively, the wiring structure may further include: a fourth via hole connecting the end of the first wiring with the end of the second wiring; and a fifth via hole connecting the second end of the third wiring with the end of the fifth wiring, wherein the second end of the third wiring is located on the side opposite to the first end of the third wiring located on the end of the second wiring. For example, with such a structure, a spiral wiring can be formed.

[0087]

[11] In the wiring structures of [1] to [7] above, the plurality of wiring layers may further include a fourth wiring layer stacked on the third wiring layer. Alternatively, the fourth wiring layer may include a sixth wiring provided on the MIM capacitor. For example, by providing the wiring in the fourth wiring layer on the MIM capacitor, the area on the main surface required for the wiring structure can be reduced, and the wiring structure can be miniaturized.

[0088]

[12] Alternatively, the wiring structure of [1] to

[11] above may further include: a second insulating layer sandwiched between the first wiring layer and the second wiring layer; and a third insulating layer sandwiched between the second wiring layer and the third wiring layer. Alternatively, the thickness of the first insulating layer may be smaller than the thickness of the second insulating layer and the thickness of the third insulating layer. Alternatively, the dielectric constant of the first insulating layer may be larger than the dielectric constant of the second insulating layer and the dielectric constant of the third insulating layer. In this case, the capacitance of the MIM capacitor per unit area can be increased. Thus, the area on the main surface required for the wiring structure can be reduced, and the wiring structure can be miniaturized.

[0089]

[13] An amplifier according to one aspect of the present disclosure includes: any one of the wiring structures described in [1] to

[12] ; and a transistor provided on a substrate common to the wiring structure. According to the amplifier, by including any one of the wiring structures described above, it is possible to suppress the local increase of the electric field in the MIM capacitor and reduce the number of overall wiring layers.

[0090] [Details of the embodiments of the present disclosure]

[0091] Hereinafter, specific examples of the wiring structure and amplifier disclosed in the present invention will be described with reference to the accompanying drawings. It should be noted that the present invention is not limited to these examples, but is shown by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims. In the following description, in the description of the drawings, the same reference numerals are marked on the same elements, and repeated descriptions are omitted.

[0092] [First embodiment]

[0093] Figure 1 1 is a diagram showing a cross-sectional structure of a wiring structure 10A according to the present embodiment. Figure 1 As shown, the wiring structure 10A includes: a substrate 20 having a main surface 21 and a back surface 22; and an insulating film 40. The substrate 20 is, for example, a semiconductor substrate. The substrate 20 is, for example, a III-V compound semiconductor substrate or a substrate capable of growing a III-V compound semiconductor. The main surface 21 and the back surface 22 are parallel to each other and both are flat. The substrate 20 has a hole 23 that penetrates the substrate 20 from the main surface 21 to the back surface 22.

[0094] The insulating film 40 is provided on the main surface 21 of the substrate 20 and is in contact with the main surface 21. The insulating film 40 is mainly composed of a silicon compound such as SiO2 or SiN. The insulating film 40 has an opening communicating with the hole 23.

[0095] The wiring structure 10A further includes a plurality of wiring layers including a first wiring layer 50, a second wiring layer 60, a third wiring layer 70, and a fourth wiring layer 80. In the illustrated example, the plurality of wiring layers are composed of the first wiring layer 50, the second wiring layer 60, the third wiring layer 70, and the fourth wiring layer 80. In other words, the wiring structure 10A does not include any wiring layer other than the first wiring layer 50, the second wiring layer 60, the third wiring layer 70, and the fourth wiring layer 80. The first wiring layer 50 is the wiring layer closest to the substrate 20 among the plurality of wiring layers. The insulating film 40 is sandwiched between the first wiring layer 50 and the main surface 21, and is in contact with both the first wiring layer 50 and the main surface 21. The second wiring layer 60 is provided on the first wiring layer 50. The third wiring layer 70 is provided on the second wiring layer 60. The fourth wiring layer 80 is provided on the third wiring layer 70. The wiring within the first wiring layer 50, the wiring within the second wiring layer 60, the wiring within the third wiring layer 70, and the wiring within the fourth wiring layer 80 are constructed to contain at least one metal material of Au, Ti, Al, Ta, W, Cu, Pt, Mo, Ni, Pd, and Cr, for example.

[0096] The thickness TA2 of the wiring in the second wiring layer 60 is the same as or smaller than the thickness TA3 of the wiring in the third wiring layer 70. The ratio (TA2 / TA3) of the thickness TA2 of the wiring in the second wiring layer 60 to the thickness TA3 of the wiring in the third wiring layer 70 is, for example, 1 / 2 or more and 1 or less. In one embodiment, the thickness TA2 is 1 μm or 2 μm, and the thickness TA3 is 2 μm.

[0097] In addition, the thickness TA2 of the wiring in the second wiring layer 60 and the thickness TA3 of the wiring in the third wiring layer 70 are smaller than the thickness TA1 of the wiring in the first wiring layer 50. The ratio (TA2 / TA1) of the thickness TA2 of the wiring in the second wiring layer 60 to the thickness TA1 of the wiring in the first wiring layer 50 is, for example, greater than 1 / 4 and less than 1 / 2. The ratio (TA3 / TA1) of the thickness TA3 of the wiring in the third wiring layer 70 to the thickness TA1 of the wiring in the first wiring layer 50 is, for example, greater than 1 / 2 and less than 2 / 3. In one embodiment, the thickness TA1 is 3 μm or 4 μm. The sum (TA2+TA3) of the thickness TA2 of the wiring in the second wiring layer 60 and the thickness TA3 of the wiring in the third wiring layer 70 may also be equal to the thickness TA1 of the wiring in the first wiring layer 50. The thickness TA4 of the fourth wiring layer 80 is greater than or equal to the thickness TA1 of the first wiring layer 50.

[0098] The wiring structure 10A further includes an insulating layer 31 (second insulating layer), an insulating layer 32 (first insulating layer), an insulating layer 33, and an insulating layer 34. The insulating layer 32 is provided on the insulating layer 31, the insulating layer 33 is provided on the insulating layer 32, and the insulating layer 34 is provided on the insulating layer 33. The insulating layer 31 is interposed between the first wiring layer 50 and the second wiring layer 60. In the portion of the first wiring layer 50 where no wiring is provided, the insulating layer 31 is in contact with the insulating film 40. The insulating layer 32 and the insulating layer 33 are interposed between the second wiring layer 60 and the third wiring layer 70. In the portion of the second wiring layer 60 where no wiring is provided, the insulating layer 32 is in contact with the insulating layer 31. The insulating layer 33 is provided on the insulating layer 32 and is in contact with the insulating layer 32. The insulating layer 34 is interposed between the third wiring layer 70 and the fourth wiring layer 80. In the portion of the third wiring layer 70 where no wiring is provided, the insulating layer 34 is in contact with the insulating layer 33.

[0099] The dielectric constant of the insulating layer 32 is greater than the dielectric constants of the insulating layer 31, the insulating layer 33, and the insulating layer 34. The insulating layer 31, the insulating layer 33, and the insulating layer 34 are, for example, formed as dielectrics including insulating materials containing Si such as SiO2, SiN, and SiON, or resin materials such as polyimide. The insulating layer 32 is, for example, formed as dielectrics including insulating materials containing Si such as SiO2, SiN, and SiON, resin materials such as polyimide, or metal oxides such as hafnium oxide (HfO2) or aluminum oxide (Al2O3). In addition, the thickness TB2 of the insulating layer 32 is less than the thickness TB1, thickness TB3, and thickness TB4 of the insulating layer 31, the insulating layer 33, and the insulating layer 34. The thickness TB1 of the insulating layer 31 is greater than the thickness TB2, thickness TB3, and thickness TB4 of the insulating layer 32, the insulating layer 33, and the insulating layer 34. The ratio of thickness TB2 of insulating layer 32 to thickness TB1 of insulating layer 31 (TB2 / TB1) is, for example, 0.001 or more and 0.5 or less. In one embodiment, thicknesses TB1, TB2, TB3, and TB4 are 6 μm, 0.23 μm, 3 μm, and 4 μm, respectively.

[0100] The wiring structure 10A includes a wiring portion 12, a MIM capacitor 13, and an inductor 14 which is a spiral wiring. In addition, a transistor 11 is provided separately from the wiring structure 10A. When viewed from a direction perpendicular to the main surface 21, the transistor 11, the wiring portion 12, the MIM capacitor 13, and the inductor 14 are provided in different regions.

[0101] The transistor 11 of this embodiment is a HEMT (High Electron Mobility Transistor). The transistor 11 has a source electrode 41, a drain electrode 42, a gate electrode 43, and a field plate 44. In addition, the substrate 20 has a channel layer and an electron supply layer not shown. The source electrode 41 and the drain electrode 42 are respectively arranged in the source opening and the drain opening formed in the insulating film 40, and form an ohmic contact with the channel layer or the electron supply layer of the substrate 20. The gate electrode 43 is arranged in the gate opening formed in the insulating film 40, and forms a Schottky contact with the substrate 20. The field plate 44 is insulated from the gate electrode 43, and is arranged on the gate electrode 43 and between the gate electrode 43 and the drain electrode 42.

[0102] The transistor 11 further includes a source wiring 51 and a drain wiring 52. Both the source wiring 51 and the drain wiring 52 are included in the first wiring layer 50. The source wiring 51 is provided on the source electrode 41 and is in contact with the source electrode 41. The drain wiring 52 is provided on the drain electrode 42 and is in contact with the drain electrode 42.

[0103] The wiring portion 12 includes wiring 53, wiring 61, wiring 71, and wiring 81, one or more vias 101, one or more vias 111, and one or more vias 121. Wiring 53 is included in the first wiring layer 50. Wiring 61 is included in the second wiring layer 60. Via 101 penetrates the insulating layer 31 and connects wiring 61 to wiring 53. Wiring 71 is included in the third wiring layer 70. Via 111 penetrates the insulating layer 32 and the insulating layer 33 and connects wiring 71 to wiring 61. Wiring 81 is included in the fourth wiring layer 80. Via 121 penetrates the insulating layer 34 and connects wiring 81 to wiring 71. It should be noted that Figure 1 The wiring portion 12 shown schematically shows the wiring of other portions except the transistor 11 , the MIM capacitor 13 , and the inductor 14 in the wiring structure 10A.

[0104] The MIM capacitor 13 is configured to include a lower electrode 62 (first electrode), an upper electrode 72 (second electrode), and an insulating layer 32. The lower electrode 62 is included in the second wiring layer 60. The upper electrode 72 is included in the third wiring layer 70. The insulating layer 32 is provided between the lower electrode 62 and the upper electrode 72. The capacitance of the MIM capacitor 13 depends on the facing area of ​​the lower electrode 62 and the upper electrode 72, the dielectric constant of the insulating layer 32, and the thickness of the insulating layer 32.

[0105] The upper electrode 72 is formed integrally with the wiring 71 included in the third wiring layer 70. Specifically, an opening is formed in the region above the lower electrode 62 in the insulating layer 33, and the upper electrode 72 is formed on the side surface of the opening and the bottom surface of the opening, that is, on the insulating layer 32 exposed from the insulating layer 33. In addition, the wiring 71 covers a portion of the upper electrode 72, and a portion of the upper electrode 72 is in contact with the wiring 71. Therefore, the upper electrode 72 protrudes from the wiring 71 toward the substrate 20 and is provided at the same height as the insulating layer 33, but since the upper electrode 72 is connected to the wiring 71, it is assumed that the upper electrode 72 is included in the third wiring layer 70.

[0106] The wiring structure 10A of the present embodiment further includes a wiring 54 (fourth wiring), one or more vias 102 (first vias), a wiring 82 (sixth wiring), a metal film 91 , and a via 92 (second via).

[0107] The wiring 54 is included in the first wiring layer 50. The wiring 54 is provided between the MIM capacitor 13 and the substrate 20. The via 102 penetrates the insulating layer 31 between the lower electrode 62 and the wiring 54, and connects the lower electrode 62 to the wiring 54. When viewed from a direction perpendicular to the main surface 21 of the substrate 20, the via 102 overlaps with the lower electrode 62 and the wiring 54.

[0108] The metal film 91 is provided on the back side 22 of the substrate 20. The metal film 91 is bonded to a reference wire on the wiring substrate on which the wiring structure 10A is mounted, for example, by a conductive bonding material (e.g., silver paste), and is set to a reference potential. The via 92 is provided to pass through between the main surface 21 and the back side 22 of the substrate 20. In the illustrated example, the via 92 is provided on the side of the hole 23 formed in the substrate 20 and in the opening of the insulating film 40 connected to the hole 23. The via 92 extends from the back side 22 of the substrate 20 to the surface of the insulating film 40. One end of the via 92 is connected to the wiring 54 by contacting with the wiring 54, and the other end of the via 92 is connected to the metal film 91 by contacting with the metal film 91. Thus, the via 92 connects the metal film 91 to the wiring 54. When viewed from a direction perpendicular to the main surface 21, the via 92 is provided at a position overlapping with the MIM capacitor 13 and the wiring 54.

[0109] The wiring 82 is included in the fourth wiring layer 80. The wiring 82 is a part of many wirings for connecting various circuit elements provided in the wiring structure 10A. The wiring 82 is provided on the MIM capacitor 13. In other words, when viewed from a direction perpendicular to the main surface 21, the wiring 82 is provided at a position overlapping with the MIM capacitor 13.

[0110] The inductor 14 is configured to include a wiring 55 (first wiring), a wiring 63 (second wiring), a wiring 73 (third wiring), and a wiring 83 (fifth wiring). The wiring 55 is included in the first wiring layer 50. The wiring 63 is included in the second wiring layer 60. The wiring 73 is included in the third wiring layer 70. The wiring 73 has the same planar shape as the planar shape of the wiring 63, and when viewed from a direction perpendicular to the main surface 21, the wiring 73 overlaps with the wiring 63. The wiring 83 is included in the fourth wiring layer 80. Therefore, the thickness TA2 of the wiring 63 is the same as or smaller than the thickness TA3 of the wiring 73. In addition, the thickness TA2 of the wiring 63 and the thickness TA3 of the wiring 73 are smaller than the thickness TA1 of the wiring 55. The sum of the thickness TA2 of the wiring 63 and the thickness TA3 of the wiring 73 (TA2+TA3) may be equal to the thickness TA1 of the wiring 55. The thickness TA4 of the wiring 83 is equal to or greater than the thickness TA1 of the wiring 55. The thickness of each of the wiring 55 , the wiring 63 , the wiring 73 , and the wiring 83 is determined according to the frequency used.

[0111] The inductor 14 further includes one or more vias 103, a plurality of vias 112 (third vias), and one or more vias 122. The via 103 penetrates the insulating layer 31 between the wiring 63 and the wiring 55. The via 103 connects one end of the wiring 63 to one end of the wiring 55. The via 122 penetrates the insulating layer 34 between the wiring 83 and the wiring 73. The via 122 connects one end of the wiring 83 to one end of the wiring 73. The plurality of vias 112 are dispersedly arranged over the entire area of ​​the wiring 63 and the wiring 73, connecting the wiring 63 to the wiring 73. The entire area of ​​the wiring 63 and the wiring 73 refers to the entire area of ​​the wiring 63 and the wiring 73 mainly in the extension direction, and more specifically, refers to the area of ​​the wiring 63 and the wiring 73 corresponding to 95% or more of the length in the extension direction. In other words, the plurality of vias 112 integrate the wiring 63 and the wiring 73 into a single wiring.

[0112] Figure 2 1 is a perspective view showing the three-dimensional structure of the inductor 14. Figure 2 As shown, the wiring 55, the via 103, the wiring 63 and the wiring 73, the via 122 and the wiring 83 are connected in sequence, thereby forming the inductor 14 formed by the spiral wiring. Specifically, the wiring 55, the wiring 63, the wiring 73 and the wiring 83 are each in a ring shape with a gap in a part. And the wiring 55, the wiring 63, the wiring 73 and the wiring 83 are arranged in such a way that the center of the ring is located on a common axis perpendicular to the main surface 21. The gap 631 of the wiring 63 and the gap 731 of the wiring 73 are arranged in a direction perpendicular to the main surface 21. The via 103 connects the end 552 of the wiring 55 with the end 632 of the wiring 63. The via 122 connects the end 733 (second end) of the wiring 73 with the end 832 of the wiring 83, wherein the end 733 of the wiring 73 is located on the side opposite to the end 732 (first end) of the wiring 73 located on the end 632 of the wiring 63.

[0113] Figure 3 1 is a circuit diagram showing the configuration of an amplifier 1 having a wiring structure 10A. The amplifier 1 includes a transistor 11, an input terminal 191, an output terminal 192, capacitors 131 to 136, inductors 141 to 144, bias power supplies 151 and 152, and a reference potential line 16. The configuration of the transistor 11 is as described above. The configuration of at least one of the capacitors 131 to 136 is the same as the MIM capacitor 13 described above. The configuration of at least one of the inductors 141 to 144 is the same as the inductor 14 described above.

[0114] The first electrode of the capacitor 132 is connected to the input terminal 191. The second electrode of the capacitor 132 is connected to the gate electrode 43 of the transistor 11. Thus, the gate electrode 43 of the transistor 11 inputs the pre-amplified signal via the capacitor 132. The capacitor 132 functions as a coupling capacitor for the pre-amplified signal.

[0115] A first electrode of the capacitor 135 is connected to the drain electrode 42 of the transistor 11. A second electrode of the capacitor 135 is connected to the output terminal 192. Thus, the amplified signal is output from the drain electrode 42 of the transistor 11 via the capacitor 135. The capacitor 135 functions as a coupling capacitor for the amplified signal.

[0116] The capacitor 131 and the inductor 141 are connected in parallel to each other between the input terminal 191 and the reference potential line 16. The capacitor 131 and the inductor 141 act as a filter for the signal before amplification. The capacitor 136 and the inductor 144 are connected in parallel to each other between the output terminal 192 and the reference potential line 16. The capacitor 136 and the inductor 144 act as a filter for the signal after amplification.

[0117] The capacitor 133 is connected between the positive electrode of the bias power supply 151 and the reference potential line 16. The inductor 142 is connected between the positive electrode of the bias power supply 151 and the gate electrode 43 of the transistor 11. The capacitor 133 and the inductor 142 act as a filter for the input bias voltage supplied from the bias power supply 151 to the gate electrode 43. The capacitor 134 is connected between the positive electrode of the bias power supply 152 and the reference potential line 16. The inductor 143 is connected between the positive electrode of the bias power supply 152 and the drain electrode 42 of the transistor 11. The capacitor 134 and the inductor 143 act as a filter for the output bias voltage supplied from the bias power supply 152 to the drain electrode 42.

[0118] Effects obtained by the wiring structure 10A and the amplifier 1 according to the present embodiment having the above-described configuration will be described together with comparative examples. Figure 8 : is a diagram showing a cross-sectional structure of a wiring structure of a comparative example. In this comparative example, the lower electrode 62 of the MIM capacitor 13 is included in the first wiring layer 50. And, the upper electrode 72 of the MIM capacitor 13 is included in the second wiring layer 60. In this case, the flatness of the lower electrode 62 is sometimes impaired. When the flatness of the lower electrode 62 is impaired, the unevenness of the thickness of the insulating layer 32 formed between the lower electrode 62 and the upper electrode 72 becomes larger, and the electric field is locally increased in the portion where the thickness of the insulating layer 32 is small. This will lead to uneven characteristics of the semiconductor device and a decrease in the reliability of the semiconductor device.

[0119] In contrast, in the present embodiment, in the wiring structure 10A, the lower electrode 62 of the MIM capacitor 13 is not included in the first wiring layer 50 as the lowermost layer among the plurality of wiring layers on the substrate 20, but is included in the second wiring layer 60 provided on the first wiring layer 50. Generally, the insulating layer 31 is sandwiched between the first wiring layer 50 and the second wiring layer 60. The unevenness of the surface of the first wiring layer 50 is gradually eliminated on the surface of the insulating layer 31 when the insulating layer 31 is stacked. Therefore, by including the lower electrode 62 in the second wiring layer 60, the surface of the lower electrode 62 can be made flatter than when the lower electrode 62 is included in the first wiring layer 50. As a result, the unevenness of the thickness of the insulating layer 32 formed between the lower electrode 62 and the upper electrode 72 is reduced, and the local increase of the electric field in the MIM capacitor 13 can be suppressed.

[0120] Furthermore, in the present embodiment, the inductor 14 is configured to include: the wiring 55 of the first wiring layer 50 which is the lowest layer among the plurality of wiring layers; and the wiring 63 and the wiring 73 respectively included in the second wiring layer 60 and the third wiring layer 70 which are also used for the MIM capacitor 13. Therefore, in the wiring structure 10A having both the MIM capacitor 13 and the inductor 14, the number of overall wiring layers can be reduced.

[0121] As in the present embodiment, the wiring structure 10A may include: a wiring 54 provided between the MIM capacitor 13 and the substrate 20 and included in the first wiring layer 50; and one or more vias 102 connecting the lower electrode 62 to the wiring 54. In this case, the lower electrode 62 can be electrically connected to the wiring 54 included in the first wiring layer 50 with low inductance.

[0122] As in the present embodiment, the wiring structure 10A may include: a metal film 91 provided on the back surface 22; and a via 92 provided to penetrate between the main surface 21 and the back surface 22 of the substrate 20, connecting the metal film 91 to the wiring 54. Furthermore, when viewed from a direction perpendicular to the main surface 21, the via 92 may overlap with the MIM capacitor 13 and the wiring 54. In this case, the lower electrode 62 of the MIM capacitor 13 can be electrically connected to the metal film 91 (for example, a reference potential line) provided on the back surface 22. Moreover, this is similar to the case where the via 92 is provided at a position that does not overlap with the MIM capacitor 13 when viewed from a direction perpendicular to the main surface 21 (see Figure 8 ) compared to the embodiment of the present invention, the area on the main surface 21 required for the wiring structure 10A can be reduced, and the wiring structure 10A can be miniaturized.

[0123] As in the present embodiment, the inductor 14 may include a plurality of vias 112, which are dispersedly arranged in the entire area of ​​the wiring 63 and the wiring 73, connecting the wiring 63 and the wiring 73. In this case, the potential of the wiring 63 and the potential of the wiring 73 are uniformly close to each other in the entire area. Therefore, the inter-wiring capacitance generated by the potential difference between the wiring 63 and the wiring 73 can be reduced, so the capacitance component (parasitic capacitance) of the inductor 14 can be reduced. In addition, the deviation of the flow of current can be reduced between the wiring 63 and the wiring 73. Moreover, by integrating the wiring 63 and the wiring 73, even if the thickness TA2 of the wiring 63 and the thickness TA3 of the wiring 73 are reduced, the decrease in the allowable current density and the increase in the wiring resistance can be suppressed.

[0124] As in the present embodiment, the thickness TA2 of the wiring 63 and the thickness TA3 of the wiring 73 may be smaller than the thickness TA1 of the wiring 55. In this case, by connecting the wiring 63 and the wiring 73 through the plurality of vias 112 as described above, it is possible to suppress a partial increase in the current density of the inductor 14. In addition, by reducing the thickness TA2 of the wiring 63 and the thickness TA3 of the wiring 73, it is possible to shorten the wiring formation time.

[0125] As in the present embodiment, the thickness TA2 of the wiring in the second wiring layer 60 may be smaller than the thickness TA3 of the wiring in the third wiring layer 70. In this case, the possibility of disconnection of the wiring in the third wiring layer 70 extending from the upper electrode 72 of the MIM capacitor 13 can be reduced, and the wiring in the second wiring layer 60 can be thinned to shorten the formation time of the second wiring layer 60.

[0126] As in the present embodiment, the sum of the thicknesses of the wiring 63 and the wiring 73 (TA2+TA3) may be equal to the thickness TA1 of the wiring 55. In this case, the current density of the inductor 14 can be made uniform.

[0127] As in the present embodiment, the plurality of wiring layers of the wiring structure 10A may include a fourth wiring layer 80 stacked on the third wiring layer 70. Furthermore, the inductor 14 may be configured to include a wiring 83 included in the fourth wiring layer 80. In this case, it is possible to easily design the inductor 14 having a larger inductance.

[0128] Here, Figure 4 This is a graph showing the relationship between the number of wiring layers and the area in an inductor and the relationship between the number of wiring layers and the film forming time of the insulating layer in an inductor. Figure 4In the figure, straight line G1 represents the relationship between the number of wiring layers and the area, and straight line G2 represents the relationship between the number of wiring layers and the film forming time. As shown in the figure, the more the number of wiring layers increases, the smaller the area of ​​the inductor. On the other hand, the more the number of wiring layers increases, the longer the film forming time of the insulating layer increases. Moreover, when the number of wiring layers is 3 (point A in the figure), the balance between the area and the film forming time is optimal. That is, since the inductor 14 is composed of three wiring layers, namely, (1) wiring 55, (2) integrated wiring formed by wiring 63 and wiring 73, and (3) wiring 83, the balance between the area and the film forming time is optimal, and the manufacturing cost of the wiring structure 10A can be reduced.

[0129] As in the present embodiment, the thickness TA4 of the wiring 83 may be equal to or greater than the thickness TA1 of the wiring 55. The wiring 83 is included in the fourth wiring layer 80, which is the uppermost layer. Therefore, even if the wiring 83 is formed thick, the time required to form the insulating layer does not increase. By forming the wiring 83 thick, the current density of the wiring 83 can be sufficiently reduced.

[0130] As in the present embodiment, the wiring 55, the wiring 63, the wiring 73, and the wiring 83 may each be in a ring shape having a gap in a part. Furthermore, the wiring 55, the wiring 63, the wiring 73, and the wiring 83 may be arranged so that the center of the ring is located on a common axis perpendicular to the main surface 21. The gap 631 of the wiring 63 and the gap 731 of the wiring 73 may be arranged in a direction perpendicular to the main surface 21. The via 103 may connect the end 552 of the wiring 55 with the end 632 of the wiring 63. The via 122 may connect the end 733 (second end) of the wiring 73 with the end 832 of the wiring 83, wherein the end 733 of the wiring 73 is located on the side opposite to the end 732 (first end) of the wiring 73 located on the end 632 of the wiring 63. For example, with such a structure, the inductor 14 can be formed.

[0131] As in the present embodiment, the fourth wiring layer 80 may include wiring 82 provided on the MIM capacitor 13. For example, by providing the wiring in the fourth wiring layer 80 also on the MIM capacitor 13, the area on the main surface 21 required for the wiring structure 10A can be reduced, and the wiring structure 10A can be miniaturized.

[0132] As in the present embodiment, the wiring structure 10A may include: an insulating layer 31 interposed between the first wiring layer 50 and the second wiring layer 60; and an insulating layer 33 interposed between the second wiring layer 60 and the third wiring layer 70. The thickness TB2 of the insulating layer 32 may be smaller than the thickness TB1 of the insulating layer 31 and the thickness TB3 of the insulating layer 33. The dielectric constant of the insulating layer 32 may be larger than the dielectric constant of the insulating layer 31 and the dielectric constant of the insulating layer 33. In this case, the capacitance of the MIM capacitor 13 per unit area can be increased. As a result, the area on the main surface 21 required for the wiring structure 10A can be reduced, and the wiring structure 10A can be miniaturized.

[0133] The amplifier 1 of this embodiment includes capacitors 131 to 136 having the same structure as the MIM capacitor 13 of the wiring structure 10A, inductors 141 to 144 having the same structure as the inductor 14 of the wiring structure 10A, and a transistor 11 provided on a substrate 20 common to the wiring structure 10A. According to the amplifier 1, local increase of the electric field in the capacitors 131 to 136 can be suppressed, and the number of overall wiring layers can be reduced.

[0134] [Second embodiment]

[0135] Figure 5 1 is a circuit diagram of a passive element 2 according to a second embodiment. The passive element 2 is used, for example, as a matching circuit element connected to an amplifier. The passive element 2 includes an inductor 14 and two MIM capacitors 13A and 13B. One end of the inductor 14 is connected to an input terminal 201, and the other end of the inductor 14 is connected to a node 202. A first electrode of the MIM capacitor 13A is connected to the node 202. A second electrode of the MIM capacitor 13A is connected to a metal film 91 as a reference potential line. A first electrode of the MIM capacitor 13B is connected to the node 202. A second electrode of the MIM capacitor 13B is connected to an output terminal 203.

[0136] Figure 6 It is a plan view of a wiring structure 10B included in the passive element 2 . Figure 7 1 is a diagram showing a cross-sectional structure of the wiring structure 10B. Figure 6 and Figure 7 As shown in FIG. 1 , the inductor 14 and the two MIM capacitors 13A and 13B are arranged in sequence along a predetermined direction and disposed on the substrate 20. The inductor 14 has the same structure as the inductor 14 of the first embodiment except for the following points. The inductor 14 of the present embodiment includes a wiring 84 instead of the wiring 83. The wiring 84 is included in the fourth wiring layer 80. The thickness of the wiring 84 is equal to or greater than the thickness of the wiring 55.

[0137] The MIM capacitors 13A and 13B each have the same structure as the MIM capacitor 13 of the first embodiment. A wiring 84 extending from the inductor 14 is provided on the MIM capacitor 13A instead of the wiring 82 of the first embodiment. The upper electrode 72 of the MIM capacitors 13A and 13B is connected to the wiring 84 via the wiring 71 and the via 121. The lower electrode 62 of the MIM capacitors 13A and 13B is connected to the wiring 54 via the via 102 as in the first embodiment. It should be noted that the wiring 54 connected to the MIM capacitor 13A is connected to the metal film 91 via the via 92 as in the first embodiment. On the other hand, unlike the first embodiment, the via 92 is not connected to the wiring 54 connected to the MIM capacitor 13B.

[0138] Wiring 55 is connected to Figure 5 The wiring 54 connected to the MIM capacitor 13B is connected to the input terminal 201 shown. Figure 5 The output terminal 203 is shown. Figure 5 Node 202 is shown included in wire 84 .

[0139] According to the wiring structure 10B of this embodiment, similarly to the wiring structure 10A of the first embodiment, in the wiring structure including the MIM capacitors 13A, 13B and the inductor 14, local increase of the electric field in the MIM capacitors 13A, 13B can be suppressed and the number of overall wiring layers can be reduced.

[0140] The wiring structure and amplifier disclosed in the present invention are not limited to the above-mentioned embodiments, and other various modifications are possible. For example, in the above-mentioned embodiments, the relationship between the thicknesses of the first wiring layer 50, the second wiring layer 60, the third wiring layer 70, and the fourth wiring layer 80 is mentioned, but the relationship between their thicknesses is not limited to the above-mentioned relationship. In addition, in the above-mentioned embodiments, the relationship between the thicknesses of the insulating layer 31, the insulating layer 32, the insulating layer 33, and the insulating layer 34 is mentioned, but the relationship between their thicknesses is not limited to the above-mentioned relationship.

Claims

1. A wiring structure comprising a MIM capacitor and a spiral wiring, wherein: The wiring structure comprises: a substrate having a main surface and a back surface; as well as A plurality of wiring layers are sequentially stacked on the main surface, The plurality of wiring layers include: a first wiring layer, which is a wiring layer closest to the substrate; a second wiring layer, which is provided on the first wiring layer; and a third wiring layer, which is provided on the second wiring layer. The MIM capacitor is configured to include: a first electrode included in the second wiring layer; a second electrode included in the third wiring layer; and a first insulating layer provided between the first electrode and the second electrode. The spiral wiring is configured to include: a first wiring included in the first wiring layer; a second wiring included in the second wiring layer; and a third wiring included in the third wiring layer.

2. The wiring structure according to claim 1, further comprising: a fourth wiring, provided between the MIM capacitor and the substrate, included in the first wiring layer; and One or more first vias connect the first electrode to the fourth wiring.

3. The wiring structure according to claim 2, further comprising: a metal film disposed on the back surface; and The second via hole is provided to penetrate between the main surface and the back surface of the substrate to connect the metal film to the fourth wiring. The second via hole overlaps with the MIM capacitor and the fourth wiring when viewed from a direction perpendicular to the main surface.

4. The wiring structure according to any one of claims 1 to 3, wherein: The spiral wiring further includes a plurality of third vias, and the plurality of third vias are dispersedly arranged throughout the second wiring and the third wiring to connect the second wiring and the third wiring.

5. The wiring structure according to claim 4, wherein: A thickness of the second wiring and a thickness of the third wiring are smaller than a thickness of the first wiring.

6. The wiring structure according to claim 5, wherein: The thickness of the wiring in the second wiring layer is smaller than the thickness of the wiring in the third wiring layer.

7. The wiring structure according to claim 5, wherein: A sum of a thickness of the second wiring and a thickness of the third wiring is equal to a thickness of the first wiring.

8. The wiring structure according to claim 4, wherein: The plurality of wiring layers further include a fourth wiring layer stacked on the third wiring layer, The spiral wiring is configured to further include a fifth wiring, and the fifth wiring is included in the fourth wiring layer.

9. The wiring structure according to claim 8, wherein: The thickness of the fifth wiring is greater than or equal to the thickness of the first wiring.

10. The wiring structure according to claim 8, wherein: The first wiring, the second wiring, the third wiring, and the fifth wiring are each in a ring shape having a gap in a portion, and the first wiring, the second wiring, the third wiring, and the fifth wiring are arranged in a manner such that the center of the ring shape is located on a common axis perpendicular to the main surface. The gaps of the second wiring and the gaps of the third wiring are arranged in a direction perpendicular to the main surface, The wiring structure further comprises: a fourth via hole connecting an end of the first wiring with an end of the second wiring; as well as A fifth via connects a second end of the third wiring to an end of the fifth wiring, wherein the second end of the third wiring is located on a side opposite to a first end of the third wiring located on the end of the second wiring.

11. The wiring structure according to any one of claims 1 to 7, wherein: The plurality of wiring layers further include a fourth wiring layer stacked on the third wiring layer, The fourth wiring layer includes a sixth wiring provided on the MIM capacitor.

12. The wiring structure according to any one of claims 1 to 11, further comprising: a second insulating layer interposed between the first wiring layer and the second wiring layer; and a third insulating layer, sandwiched between the second wiring layer and the third wiring layer, The thickness of the first insulating layer is smaller than the thickness of the second insulating layer and the thickness of the third insulating layer. The dielectric constant of the first insulating layer is greater than the dielectric constant of the second insulating layer and the dielectric constant of the third insulating layer.

13. An amplifier comprising: The wiring structure according to any one of claims 1 to 12; and A transistor is provided on the substrate common with the wiring structure.

Images