Semiconductor structure and forming method

Abstract

The invention provides a semiconductor structure and a forming method, and the semiconductor structure comprises a substrate, a plurality of metal layers, a plurality of conductive plugs, a plurality of metal interlayer dielectric layers, and a plurality of insulating structures. Wherein the plurality of metal layers are stacked on the substrate layer by layer; the plurality of conductive plugs and the plurality of insulation structures are arranged in the corresponding metal interlayer dielectric layers; in the stacking direction, every two adjacent metal layers are separated through the corresponding metal interlayer dielectric layer and are connected through the corresponding conductive plug; for the conductive plugs located in the same metal interlayer dielectric layer, the insulation structure is arranged between every two adjacent conductive plugs. Therefore, energy loss in the signal transmission process can be reduced, and the signal transmission speed and efficiency can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the development of miniaturization of microelectronic devices in semiconductor integrated circuit chip manufacturing, the number of metal wiring layers is becoming denser and the distance between wires is shrinking. When electronic signals are transmitted between metal wires with a large number of layers, the capacitance-resistance interconnection delay (RC Delay) caused by crosstalk between wires will seriously reduce the transmission performance of semiconductor components.

[0003] Typically, semiconductor structures will set up an inter-metal dielectric (IMD) layer between metal wiring to reduce the interference caused by crosstalk. However, the dielectric constant of the inter-metal dielectric layer is usually between 2.5 and 3.5, which cannot meet the low dielectric constant requirements of chip products such as 5G communications. Therefore, it is necessary to further reduce the interference caused by crosstalk on signal transmission to improve transmission performance. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a formation method to improve the transmission performance of the semiconductor structure.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] An embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate, multiple metal layers, multiple conductive plugs, multiple metal interlayer dielectric layers and multiple insulating structures; wherein the multiple metal layers are stacked layer by layer on the substrate; the multiple conductive plugs and the multiple insulating structures are all arranged in the corresponding metal interlayer dielectric layers; in the stacking direction of the multiple metal layers, every two adjacent metal layers are separated by the corresponding metal interlayer dielectric layers and connected by the corresponding conductive plugs; for the conductive plugs located in the same metal interlayer dielectric layer, the insulating structure is arranged between every two adjacent conductive plugs.

[0007] In the above solution, in the stacking direction, the insulating structure is disposed between every two adjacent conductive plugs, and / or the insulating structure is disposed between each conductive plug and the adjacent metal layer.

[0008] In the above solution, each of the metal layers includes: a first conductive line and a second conductive line adjacent to the first conductive line; wherein the insulating structure is disposed between the first conductive line and the second conductive line.

[0009] In the above solution, a gap is provided in each of the insulating structures.

[0010] In the above solution, each of the insulating structures comprises: polyimide and hollow molecular structures uniformly distributed in the polyimide; wherein the content of the hollow molecular structures accounts for 0 to 5% of the total mass of the insulating structure.

[0011] In the above solution, the insulating structures in every two adjacent metal interlayer dielectric layers are arranged alternately along a first direction; wherein the first direction is parallel to the top surface of the metal interlayer dielectric layer and perpendicular to the stacking direction.

[0012] In the above solution, the dielectric constant of the insulating structure is less than 2.

[0013] The embodiment of the present disclosure also provides a method for forming a semiconductor structure, the method comprising: providing a substrate; alternately stacking metal layers and metal interlayer dielectric layers on the substrate; wherein, in the stacking direction of the plurality of metal layers, every two adjacent metal layers are separated by the corresponding metal interlayer dielectric layer; after stacking to form each metal interlayer dielectric layer, forming a plurality of insulating structures and a plurality of conductive plugs in each metal interlayer dielectric layer; wherein, in the stacking direction, every two adjacent metal layers are connected by a plurality of conductive plugs; for the conductive plugs located in the same metal interlayer dielectric layer, an insulating structure is arranged between every two adjacent conductive plugs; wherein the dielectric constant of the insulating structure is smaller than that of the metal interlayer dielectric layer.

[0014] In the above scheme, a plurality of the insulating structures are formed in each of the metal interlayer dielectric layers, including: depositing a barrier layer, a first insulating dielectric material layer and an etch stop layer in sequence on the metal layer; forming a patterned first hard mask on the top surface of the etch stop layer; etching along the first hard mask until the barrier layer to form a plurality of first grooves; wherein, one or more process cycles are performed in the first grooves to form the insulating structure; wherein each process cycle forms a thin film of molecular thickness; chemical mechanical polishing is performed on the insulating structure and the etch stop layer until the top surface of the first insulating dielectric material layer is exposed; and a second insulating dielectric material layer is deposited on the top surface of the first insulating dielectric material layer; wherein the materials forming the first insulating dielectric material layer and the second insulating dielectric material layer are the same.

[0015] In the above scheme, each process cycle includes: depositing a first organic precursor by molecular layer deposition and purging with the inert gas; wherein the first organic precursor is a dianhydride compound; depositing a second organic precursor by molecular layer deposition and purging with the inert gas; the second organic precursor is a diamine compound; depositing a hollow molecular structure by molecular layer deposition and purging with the inert gas; and polymerizing the first organic precursor and the second organic precursor under ultraviolet light.

[0016] In the above scheme, forming the conductive plug in each of the metal interlayer dielectric layers includes: forming a patterned second hard mask on the top surface of the second insulating dielectric material layer; etching along the second hard mask to form a through hole; wherein the through hole passes through the first insulating dielectric material layer and the second insulating dielectric material layer; and filling the through hole to form the conductive plug.

[0017] The embodiment of the present disclosure provides a semiconductor structure, including: a substrate, multiple metal layers, multiple conductive plugs, multiple metal interlayer dielectric layers and multiple insulating structures; wherein the multiple metal layers are stacked layer by layer on the substrate; the multiple conductive plugs and the multiple insulating structures are all arranged in the corresponding metal interlayer dielectric layers; in the stacking direction, every two adjacent metal layers are separated by the corresponding metal interlayer dielectric layers and connected by the corresponding conductive plugs; for the conductive plugs located in the same metal interlayer dielectric layer, the insulating structure is arranged between every two adjacent conductive plugs. In this way, the present disclosure arranges an insulating structure between adjacent conductive plugs in the same metal interlayer dielectric layer, which can reduce the parasitic capacitance between adjacent conductive plugs. Therefore, the present disclosure can not only reduce the energy loss in the signal transmission process, but also improve the signal transmission speed and efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0019] Figure 2 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0020] Figure 3 A schematic diagram of the structure of a metal layer provided in an embodiment of the present disclosure;

[0021] Figure 4 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 3 ;

[0022] Figure 5 A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 1 ;

[0023] Figure 6 A schematic diagram of a semiconductor structure formed during the process of forming the semiconductor structure according to an embodiment of the present disclosure Figure 1 ;

[0024] Figure 7 A schematic diagram of a semiconductor structure formed during the process of forming the semiconductor structure according to an embodiment of the present disclosure Figure 2 ;

[0025] Figure 8 A schematic diagram of a semiconductor structure formed during the process of forming the semiconductor structure according to an embodiment of the present disclosure Figure 3 ;

[0026] Fig. 9 A schematic diagram of a semiconductor structure formed during the process of forming the semiconductor structure according to an embodiment of the present disclosure Figure 4 ;

[0027] Fig.10 A schematic diagram of a semiconductor structure formed during the process of forming the semiconductor structure according to an embodiment of the present disclosure Figure 5 ;

[0028] Fig.11 A schematic diagram of a semiconductor structure formed during the process of forming the semiconductor structure according to an embodiment of the present disclosure Figure 6 ;

[0029] Fig.12 A schematic diagram of a semiconductor structure formed during the process of forming the semiconductor structure according to an embodiment of the present disclosure Figure 7 ;

[0030] Fig.13 A schematic diagram of a semiconductor structure formed during the process of forming the semiconductor structure according to an embodiment of the present disclosure Figure 8 ;

[0031] Fig.14 A schematic diagram of a semiconductor structure formed during the process of forming the semiconductor structure according to an embodiment of the present disclosure Figure 9 ;

[0032] Fig.15 A schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure Figure 2 ;

[0033] Fig.16 A schematic diagram of a semiconductor structure formed during the process of forming the semiconductor structure according to an embodiment of the present disclosure Figure 10 ;

[0034] Fig.17 A schematic diagram of a semiconductor structure formed during the process of forming the semiconductor structure according to an embodiment of the present disclosure Figure 10 one. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0036] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0037] If similar descriptions of “first / second” appear in the application documents, the following description is added. In the following description, the terms “first / second / third” involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that “first / second / third” can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0039] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, semiconductor structure, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, semiconductor structure, article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, semiconductor structure, article or device including the element.

[0040] Figure 1 It is a schematic structural diagram of an optional semiconductor structure 100 provided in an embodiment of the present disclosure. It should be noted that the first direction X is parallel to the top surface of the metal interlayer dielectric layer 20 and perpendicular to the stacking direction Z, and the second direction Y is perpendicular to the first direction X and the stacking direction Z respectively. Figure 1 Only two metal layers M0 and M1 are illustrated, and the number of metal layers may be other numbers, which is not limited here. The barrier layer 50 is used to prevent the etching step in the process of forming the insulating structures 40a and 40b from damaging the metal layers M0 and M1.

[0041] It should also be noted that Figure 1The cross-section of the insulating structure 40a is shown to be an inverted trapezoid, and the cross-section of the insulating structure 40b is shown to be a rectangle, which is only for example. The cross-sections of the insulating structures 40a and 40b can also be other shapes, which are not limited here. The thickness of the insulating structures 40a and 40b in the stacking direction Z is associated with the thickness of the corresponding metal interlayer dielectric layer 20. For example, the thickness of the insulating structures 40a and 40b in the stacking direction Z is respectively less than or equal to the thickness of the corresponding metal interlayer dielectric layer 20.

[0042] In the embodiments of the present disclosure, reference Figure 1 , the semiconductor structure 100 includes a substrate 10, a plurality of metal layers and a plurality of metal interlayer dielectric layers 20. The plurality of metal layers are used to form wiring. For example, the metal layers M0 and M1 can each be provided with a specific wiring pattern for connecting different devices or circuit parts in the same plane. The plurality of metal layers are stacked layer by layer on the substrate 10. For example, the metal layers M0 and M1 are stacked on the substrate 10 in sequence along the stacking direction Z. In the stacking direction Z, every two adjacent metal layers are separated by a corresponding metal interlayer dielectric layer 20. The plurality of metal interlayer dielectric layers 20 can each be made of insulating material to prevent short circuits between adjacent metal layers. For example, a metal interlayer dielectric layer 20 is provided between the metal layers M0 and M1 to prevent short circuits between the metal layers M0 and M1.

[0043] In the embodiments of the present disclosure, reference Figure 1 The semiconductor structure 100 further includes a plurality of conductive plugs. For example, the semiconductor structure 100 includes conductive plugs 30a and 30b. The conductive plug 30a may be a through-hole filling (TSV filling). The conductive plug 30b may be a plug.

[0044] In the embodiments of the present disclosure, reference Figure 1 , multiple conductive plugs can be used to connect different metal layers, or metal layers and device active areas (such as the source and drain of a transistor). For example, the conductive plug 30b can connect the wiring on the metal layers M0 and M1 by penetrating the metal interlayer dielectric layer 20 to form a complete circuit network, namely: a metal interconnect structure. The contact structure 30c can electrically connect the source, drain or gate of the transistor of the semiconductor structure 100 to the metal interconnect structure. The conductive plug 30a can be electrically connected to the metal interconnect structure to achieve 3D packaging.

[0045] It should be noted that the reference Figure 1Parasitic capacitance is the unexpected capacitance caused by the interaction of electric fields between conductors (such as metal layers or conductive plugs). In high-frequency circuits, this parasitic capacitance will cause delays in signal transmission, namely capacitor-resistor interconnection delay. This capacitor-resistor interconnection delay will increase with the increase of circuit frequency, seriously affecting the overall transmission performance of the chip.

[0046] In the embodiments of the present disclosure, reference Figure 1 , the semiconductor structure 100 further includes a plurality of insulating structures. The plurality of insulating structures are all disposed in the corresponding intermetallic dielectric layer 20. For the conductive plugs disposed in the same intermetallic dielectric layer 20, an insulating structure is disposed between every two adjacent conductive plugs. The dielectric constant of the insulating structure is smaller than that of the intermetallic dielectric layer 20. For example, a conductive plug 30b and a conductive plug 30a are disposed in the intermetallic dielectric layer 20 disposed above the metal layer M1. An insulating structure 40b is disposed between two adjacent conductive plugs 30b. An insulating structure 40b is also disposed between the conductive plug 30b and the conductive plug 30a. The dielectric constant of the insulating structure 40b is smaller than that of the intermetallic dielectric layer 20.

[0047] It can be understood that the embodiment of the present disclosure sets an insulating structure between adjacent conductive plugs in the same metal interlayer dielectric layer. In this way, the insulating structure in the embodiment of the present disclosure can reduce the parasitic capacitance between adjacent conductive plugs. Therefore, the embodiment of the present disclosure can not only reduce the energy loss during signal transmission, but also improve the transmission speed and efficiency of the signal. Moreover, the embodiment of the present disclosure can reduce the energy consumption caused by parasitic capacitance by reducing parasitic capacitance, thereby significantly reducing the power consumption of the semiconductor structure and improving the energy efficiency ratio. In addition, the insulating structure can prevent unnecessary abnormal conditions such as leakage and short circuit between adjacent conductive plugs, thereby improving the stability and reliability of the entire semiconductor structure 100.

[0048] In some embodiments of the present disclosure, reference Figure 1 , in the stacking direction Z, an insulating structure 40a is provided between every two adjacent conductive plugs. For example, an insulating structure 40a is provided between the conductive plug 30b and the contact structure 30c. Every two adjacent conductive plugs can be understood with reference to the conductive plug 30b and the contact structure 30c. In this way, the embodiment of the present disclosure can reduce the parasitic capacitance between every two adjacent conductive plugs along the stacking direction Z. Thus, the embodiment of the present disclosure can not only reduce the energy loss during signal transmission, but also improve the transmission speed and efficiency of the signal. Moreover, in high-frequency circuits, the embodiment of the present disclosure can reduce the energy consumption caused by the parasitic capacitance by reducing the parasitic capacitance, thereby significantly reducing the power consumption of the chip and improving the energy efficiency ratio.

[0049] In some embodiments of the present disclosure, reference Figure 1The insulating structures in every two adjacent metal interlayer dielectric layers 20 are arranged alternately along the first direction X. For example, Figure 1 The three insulating structures 40b located in the same metal interlayer dielectric layer 20 are arranged alternately with the three insulating structures 40a located in the same metal interlayer dielectric layer 20 along the first direction X. In this way, the staggered distribution of the insulating structures can disperse the stress to a wider area, reduce the degree of local stress concentration, and thus reduce the risk of damage to the semiconductor structure 100 due to excessive stress. At the same time, the staggered distribution of the insulating structures can make the heat distribution uniform, reduce the generation and concentration of thermal stress, and help maintain the stability and reliability of the semiconductor structure.

[0050] Figure 2 is a schematic structural diagram of another optional semiconductor structure 100 provided in an embodiment of the present disclosure. It should be noted that: Figure 2 The cross-sectional shape of the middle insulating structure 40 c is only used for illustration and is not limited herein.

[0051] In some embodiments of the present disclosure, reference Figure 2 , an insulating structure 40c is provided between each conductive plug and the adjacent metal layer. For example, Figure 2 The conductive plug 30b located between the metal layers M0 and M1 is provided with an insulating structure 40c between the metal layer M2. An insulating structure 40c is provided between the contact structure 30c and the metal layer M1. In this way, the embodiment of the present disclosure can reduce the parasitic capacitance between the conductive plug and the adjacent metal layer. Thus, the transmission speed and efficiency of the signal can be further improved.

[0052] Figure 3 is an optional structural diagram of the metal layer M0 provided in the embodiment of the present disclosure. It should be noted that: Figure 3 The first wire 61 and the second wire 62 are shown to extend along the second direction Y. The extension direction of the first wire 61 and the second wire 62 may also be other directions, which are not limited here.

[0053] In some embodiments of the present disclosure, reference Figure 3 Each metal layer includes a first wire 61 and a second wire 62 adjacent to the first wire 61. An insulating structure 40d is provided between the first wire 61 and the second wire 62. In this way, the embodiment of the present disclosure can reduce the parasitic capacitance between adjacent wires in the metal layer. Thus, the transmission speed and efficiency of the signal can be further improved.

[0054] Figure 4 is a schematic structural diagram of another optional semiconductor structure 100 provided in an embodiment of the present disclosure, Figure 4 All structures except seam void 41 can be referenced Figure 1The corresponding embodiments can be understood and will not be described in detail here.

[0055] In some embodiments of the present disclosure, reference Figure 4 , a gap (seam void) 41 is provided in each insulating structure. For example, the gap 41 is provided in both the insulating structures 40a and 40b. In this way, the embodiment of the present disclosure can reduce the dielectric constant of the insulating structure. Thus, the embodiment of the present disclosure can further reduce the parasitic capacitance between adjacent conductive plugs in the semiconductor structure 100, further reduce the energy loss in the signal transmission process, and improve the transmission speed and efficiency of the signal.

[0056] In some embodiments of the present disclosure, each insulating structure includes polyimide and a hollow molecular structure uniformly distributed in the polyimide. For example, the hollow molecular structure can be a polyhedral oligomeric silsesquioxane (POSS). In this way, the embodiments of the present disclosure dope oligomeric silsesquioxane in polyimide to introduce a large number of nanopores, thereby effectively improving the porosity of the insulating structure and suppressing the dipole-dipole interaction of polarized molecules in the polyimide, thereby reducing the dielectric constant. Thus, the parasitic capacitance can be further reduced, and the transmission speed and efficiency of the signal can be improved.

[0057]

[0058] Table 1

[0059] It should be noted that Table 1 shows that the frequency of the signal is 10 2 -10 6 Performance parameters of the insulating structure doped with different proportions of oligomeric silsesquioxane in the Hz test range.

[0060] In the disclosed embodiment, referring to Table 1, when the content of the hollow molecular structure accounts for 0 to 5% of the total mass of each insulating structure, the insulating structure has a lower dielectric constant, thereby further improving the transmission speed and efficiency of the signal.

[0061] In some embodiments of the present disclosure, the dielectric constant of the insulating structure is less than 2. For example, Figure 1 The insulating structures 40a and 40b, Figure 2 The insulating structure 40c and Figure 3 The dielectric constant of the insulating structure 40d in the embodiment is less than 2. In this way, in high-frequency circuits, the embodiment of the present disclosure can not only reduce the energy loss in the signal transmission process, but also improve the signal transmission speed and efficiency. Thus, the requirements of chip products such as 5G communication for low dielectric constant are met.

[0062] Figure 5 It is a flow chart of an optional method for forming a semiconductor structure provided in an embodiment of the present disclosure, which will be described in combination with each step.

[0063] S101. Provide a substrate.

[0064] Figure 6 , Figure 7 and Figure 8 is a schematic diagram of a structure in the process of forming a semiconductor structure provided by an embodiment of the present disclosure. It should be noted that: Figure 6 , Figure 7 and Figure 8 All are cross-sectional views. Figure 6 The metal layer M0, the metal interlayer dielectric layer 20 and the contact structure 30c are shown. Figure 7 An insulating structure 40 is shown, Figure 8 A conductive plug 30b is shown.

[0065] In the embodiments of the present disclosure, reference Figure 6 The substrate 10 may be a semiconductor substrate; specifically, it may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art, and may also include other substrates containing semiconductor materials, such as a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, a polycrystalline semiconductor layer on an insulating layer, a silicon-germanium substrate, a SiC substrate, etc.

[0066] S102, alternately stacking metal layers and intermetallic dielectric layers on a substrate; wherein, in a stacking direction, every two adjacent metal layers are separated by a corresponding intermetallic dielectric layer.

[0067] S103. After stacking to form each intermetallic dielectric layer, a plurality of insulating structures and a plurality of conductive plugs are formed in each intermetallic dielectric layer; wherein, in the stacking direction, every two adjacent metal layers are connected by a plurality of conductive plugs; and for the conductive plugs located in the same intermetallic dielectric layer, an insulating structure is arranged between every two adjacent conductive plugs.

[0068] In the present disclosure, Figure 6 and Figure 7 , along the stacking direction Z, a metal layer M0, a barrier layer 50 and an intermetallic dielectric layer 20 are sequentially stacked on the substrate 10, and then a plurality of spaced insulating structures 40 are formed in the intermetallic dielectric layer 20. Finally, a metal layer M1 is deposited on the intermetallic dielectric layer 20. Adjacent metal layers M0 and M1 are separated by the intermetallic dielectric layer 20 therebetween.

[0069] In the embodiments of the present disclosure, reference Figure 7and Figure 8 , the metal layer M1 and the metal interlayer dielectric layer 20 between the metal layers M1 and M0 are etched to form trenches and / or vias, and the metal layer M0 at the positions of the trenches and vias is exposed. Then, the trenches and / or vias are filled with metal materials to form a Figure 8 The conductive plug 30b shown. The adjacent metal layers M0 and M1 are connected by a plurality of conductive plugs 30b. An insulating structure 40 is provided between each two adjacent conductive plugs 30b. In this way, the embodiment of the present disclosure provides an insulating structure between adjacent conductive plugs in the same metal interlayer dielectric layer. Therefore, the embodiment of the present disclosure can not only reduce the energy loss in the signal transmission process, but also improve the transmission speed and efficiency of the signal.

[0070] In some embodiments of the present disclosure, S201 to S206 can be used to implement Figure 1 S103 will be described in combination with each step.

[0071] S201, depositing a barrier layer, a first insulating dielectric material layer and an etching stop layer in sequence on the metal layer.

[0072] S202 , forming a patterned first hard mask on a top surface of the etching stop layer.

[0073] Fig. 9 , Fig.10 and Fig.11 is a schematic diagram of a structure in the process of forming a semiconductor structure provided by an embodiment of the present disclosure. It should be noted that: Fig. 9 , Fig.10 and Fig.11 All are cross-sectional views. Fig. 9 An etch stop layer 60 and a first hard mask 70 are shown. Fig.10 Shown is the method for forming Figure 7 The first trench 90 of the insulating structure 40, Fig.11 A first filling structure 410 is shown.

[0074] In the embodiments of the present disclosure, reference Fig. 9, a barrier layer 50, a first insulating dielectric material layer 210 and an etching stop layer 60 are sequentially deposited on the metal layer M0. The material forming the first insulating dielectric material layer 210 may be fluorosilicate glass (FSG), silicon oxide (SiO2) and titanium oxide (TiO2) and other materials. The material forming the barrier layer 50 may be any one of tungsten (W), tungsten nitride (WN), tungsten silicon nitride (WSiN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN) and tantalum silicon nitride (TaSiN) and other materials. The barrier layer 50 is used to prevent the diffusion of the metal layer in subsequent processes. The material forming the etching stop layer 60 may be silicon nitride (Si3N4) and the like, which is used to provide a stop surface in the subsequent etching process. The blocking layer 50 , the first insulating dielectric material layer 210 and the etching stop layer 60 may be deposited by any one of chemical vapor deposition (CVD) and physical vapor deposition (PVD).

[0075] In the embodiments of the present disclosure, reference Fig. 9 A patterned first hard mask 70 is formed on the top surface of the etch stop layer 60. The material of the first hard mask 70 may be silicon dioxide (SiO2) or other materials. The pattern of the first hard mask 70 may be formed by photolithography and etching. The pattern of the first hard mask 70 is used to determine Fig.12 The shape and position of the insulating structure 40.

[0076] S203 , etching along the first hard mask until reaching the barrier layer to form a plurality of first trenches.

[0077] In the present disclosure, Fig. 9 and Fig.10 , etching is performed along the first hard mask 70 until the barrier layer 50, forming a plurality of first trenches 90. The etching process may adopt a process method such as dry etching, and the desired first trenches 90 may be obtained by precisely controlling the etching depth and shape. The cross section of the first trench 90 may be any one of an inverted trapezoidal and rectangular structure.

[0078] S204, performing one or more process cycles in the first trench to form an insulating structure; wherein each process cycle forms a film with a molecular thickness.

[0079] S205 , performing chemical mechanical polishing on the insulating structure and the etching stop layer until the top surface of the first insulating dielectric material layer is exposed.

[0080] Fig.12 and Fig.13is a schematic diagram of a structure in the process of forming a semiconductor structure provided by an embodiment of the present disclosure. It should be noted that: Fig.12 and Fig.13 All are cross-sectional views. Fig.12 Shows Figure 7 The insulating structure 40, Fig.13 Shows Figure 7 The metal interlayer dielectric layer 20, Figure 7 The metal interlayer dielectric layer 20 includes Fig.13 The first insulating dielectric material layer 210 and the second insulating dielectric material layer 220 are provided.

[0081] In the present disclosure, Fig.10 and Fig.11 , one or more process cycles are performed in the first trench 90 to form a first filling structure 410 .

[0082] It should be noted that, in the process of forming the first filling structure 410, under the specific conditions that the first trench 90 is a rectangular and inverted trapezoidal structure, the following is formed: Fig.14 The insulating structures 40 shown, that is, each insulating structure 40 has a gap 41 formed therein.

[0083] In the present disclosure, Fig.11 and Fig.12 , chemical mechanical polishing (CMP) is performed on the first filling structure 410 and the etch stop layer 60 until the top surface of the first insulating dielectric material layer 210 is exposed. The chemical mechanical polishing process can accurately remove the redundant structures of the etch stop layer 60 and the first filling structure 410 to form the insulating structure 40.

[0084] In the present disclosure, Fig.10 and Fig.11 , each process cycle can form a film of molecular thickness, and the thickness of the first filling structure 410 can be accurately controlled through multiple cycles. In each process cycle, the first organic precursor (dianhydride compound), the second organic precursor (diamine compound) and the hollow molecular structure are deposited in sequence. The hollow molecular structure can be any one of polyhedral oligomeric silsesquioxanes (POSS) such as trisilanol phenyl-POSS, trisilanol isooctyl-POSS and trisilanol isobutyl-POSS. The hollow molecular structure can also be replaced by nanoglass (Nanoglass). After the deposition is completed, ultraviolet light (UV) of an appropriate wavelength is used to irradiate and polymerize the first precursor and the second precursor. In this way, the ultraviolet light (UV) irradiation method can deionize and dissociate molecular bonds, significantly accelerate the polymerization reaction; at the same time, reduce the reaction temperature of the polymerization reaction. In addition, the hollow molecular structure can overcome the double reaction problem that may occur in molecular layer deposition (MLD) to ensure the formation of pure organic polymers.

[0085] S206 , depositing a second insulating dielectric material layer on the top surface of the first insulating dielectric material layer; wherein the first insulating dielectric material layer and the second insulating dielectric material layer are formed of the same material.

[0086] In the present disclosure, Fig.12 and Fig.13 , a second insulating dielectric material layer 220 is deposited on the top surface of the first insulating dielectric material layer 210. The material of the second insulating dielectric material layer 220 can be the same as that of the first insulating dielectric material layer 210 to form a continuous and flat interface. The deposition process of the second insulating dielectric material layer 220 can adopt a process method such as chemical vapor deposition to ensure the uniformity and consistency of the second insulating dielectric material layer 220.

[0087] In some embodiments of the present disclosure, Fig.15 S301 to S304 shown implement S204, which will be described in conjunction with each step.

[0088] S301, depositing a first organic precursor by molecular layer deposition, and purging with an inert gas; wherein the first organic precursor is a dianhydride compound.

[0089] S302, depositing a second organic precursor by molecular layer deposition and purging with an inert gas; the second organic precursor is a diamine compound.

[0090] S303, depositing a hollow molecular structure by molecular layer deposition, and purging with an inert gas.

[0091] In the present disclosure, in combination Fig.10 and Fig.11 In each cycle of forming the first filling structure 410, a molecular layer deposition (MLD) process is used to sequentially deposit the first organic precursor, the second organic precursor, and the hollow molecular structure. After each deposition, an inert gas is used for purging to ensure the purity and uniformity of the deposited layer, which helps to form a high-quality thin film structure.

[0092] S304, polymerizing the first organic precursor and the second organic precursor under ultraviolet light.

[0093] In the present disclosure, Fig.10 and Fig.11In each cycle of forming the first filling structure 410, the process is repeated under ultraviolet light irradiation to successfully prepare an insulating structure of molecular thickness. In this way, compared with the traditional stirring-spin coating-thermal curing method, the molecular layer deposition process used in the embodiment of the present disclosure can significantly optimize the distribution uniformity of the hollow molecular structure in the insulating structure, greatly increase the number of nanopores, and effectively reduce the dielectric constant. At the same time, the embodiment of the present disclosure can also effectively suppress the agglomeration phenomenon of the hollow molecular structure, thereby greatly improving the overall performance of the material.

[0094] In some embodiments of the present disclosure, S204 may be implemented through S401 to S403 shown in the figure, which will be described in conjunction with each step.

[0095] Fig.16 and Fig.17 is a schematic diagram of a structure in the process of forming a semiconductor structure provided by an embodiment of the present disclosure. It should be noted that: Fig.16 and Fig.17 All are cross-sectional views. Fig.16 The second hard mask 110 is shown. Fig.17 Shown is the method for forming Figure 8 The through hole 120 of the conductive plug 30b is formed in the middle.

[0096] S401 , forming a patterned second hard mask on the top surface of the blocking layer.

[0097] In the present disclosure, Figure 7 and Fig.16 ,exist Figure 7 On the metal layer M1 shown, a Fig.16 The barrier layer 51 is shown. Then, a patterned second hard mask 110 is formed on the top surface of the barrier layer 51. The pattern of the second hard mask 110 is used to determine Figure 8 The shape and position of the conductive plug 30b.

[0098] S402 , etching along the second hard mask to form a through hole; wherein the through hole penetrates the first insulating dielectric material layer and the second insulating dielectric material layer.

[0099] In the present disclosure, Fig.16 and Fig.17 , etching is performed along the patterned second hard mask 110, through Fig.17 The metal interlayer dielectric layer 20 in the embodiment of the present invention is: Fig.13 The first insulating dielectric material layer 210 and the second insulating dielectric material layer 220 are formed to form a through hole 120.

[0100] S403, filling the through hole to form a conductive plug.

[0101] In the present disclosure, Fig.17 and Figure 8 , fill the through hole 120 with a metal material to form a conductive plug 30b. The conductive plug 30b is usually made of a metal material such as copper (Cu) or tungsten (W), and the conductive plug 30b can be filled into the through hole 120 by electroplating, chemical vapor deposition, or other processes. The formation of the conductive plug 30b establishes electrical connections between multiple metal layers to achieve signal transmission.

[0102] The above description of the formation method is similar to the description of the above semiconductor structure embodiment, and has similar beneficial effects as the semiconductor structure embodiment. For technical details not disclosed in the formation method embodiment of the present disclosure, please refer to the description of the semiconductor structure embodiment of the present disclosure for understanding.

[0103] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, semiconductor structure, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, semiconductor structure, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, semiconductor structure, article or device including the element.

[0104] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments. The semiconductor structures disclosed in the several semiconductor structure embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new semiconductor structure embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several semiconductor structure or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new semiconductor structure embodiments or device embodiments.

[0105] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: substrate, multiple metal layers, multiple conductive plugs, multiple intermetallic dielectric layers and multiple insulating structures; wherein, The plurality of metal layers are stacked layer by layer on the substrate; the plurality of conductive plugs and the plurality of insulating structures are arranged in the corresponding intermetallic dielectric layers; In the stacking direction of the plurality of metal layers, every two adjacent metal layers are separated by the corresponding intermetallic dielectric layer and connected by the corresponding conductive plugs; For the conductive plugs located in the same intermetallic dielectric layer, the insulating structure is arranged between every two adjacent conductive plugs; wherein the dielectric constant of the insulating structure is smaller than that of the intermetallic dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that: In the stacking direction, the insulating structure is arranged between every two adjacent conductive plugs, and / or, The insulating structure is arranged between each of the conductive plugs and the adjacent metal layer.

3. The semiconductor structure according to claim 1 or 2, characterized in that: Each of the metal layers comprises: a first conductive line and a second conductive line adjacent to the first conductive line; wherein, The insulating structure is disposed between the first conductive wire and the second conductive wire.

4. The semiconductor structure according to claim 1, characterized in that: Each of the insulating structures is provided with a gap.

5. The semiconductor structure according to claim 1, characterized in that: Each of the insulating structures comprises: polyimide and hollow molecular structures uniformly distributed in the polyimide; wherein, The content of the hollow molecular structure accounts for 0 to 5% of the total mass of the insulating structure.

6. The semiconductor structure according to claim 1, characterized in that The insulating structures in every two adjacent metal interlayer dielectric layers are arranged alternately along a first direction; wherein the first direction is parallel to the top surface of the metal interlayer dielectric layer and perpendicular to the stacking direction.

7. The semiconductor structure according to claim 1, characterized in that: The dielectric constant of the insulating structure is less than 2.

8. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; Alternately stacking metal layers and intermetallic dielectric layers on the substrate; wherein, in the stacking direction of the plurality of metal layers, every two adjacent metal layers are separated by corresponding intermetallic dielectric layers; After stacking to form each of the metal interlayer dielectric layers, a plurality of insulating structures and a plurality of conductive plugs are formed in each of the metal interlayer dielectric layers; wherein, in the stacking direction, every two adjacent metal layers are connected by a plurality of the conductive plugs; and for the conductive plugs located in the same metal interlayer dielectric layer, the insulating structure is arranged between every two adjacent conductive plugs.

9. The forming method according to claim 8, characterized in that: A plurality of the insulating structures are formed in each of the metal interlayer dielectric layers, including: Depositing a barrier layer, a first insulating dielectric material layer and an etching stop layer in sequence on the metal layer; forming a patterned first hard mask on a top surface of the etch stop layer; Etching along the first hard mask until the barrier layer is formed to form a plurality of first trenches; wherein, Performing one or more process cycles in the first trench to form the insulating structure; wherein each process cycle forms a film with a molecular thickness; Performing chemical mechanical polishing on the insulating structure and the etching stop layer until the top surface of the first insulating dielectric material layer is exposed; A second insulating dielectric material layer is deposited on the top surface of the first insulating dielectric material layer; wherein the first insulating dielectric material layer and the second insulating dielectric material layer are formed of the same material.

10. The forming method according to claim 9, characterized in that: Each of the process cycles includes: Depositing a first organic precursor by molecular layer deposition and purging with an inert gas; wherein the first organic precursor is a dianhydride compound; Depositing a second organic precursor by molecular layer deposition and purging with the inert gas; the second organic precursor is a diamine compound; Depositing the hollow molecular structure by molecular layer deposition and purging with the inert gas; Under ultraviolet light, the first organic precursor and the second organic precursor are polymerized.

11. The forming method according to claim 9, characterized in that: Forming the conductive plug in each of the metal interlayer dielectric layers, comprising: forming a patterned second hard mask on a top surface of the second insulating dielectric material layer; Etching along the second hard mask to form a through hole; wherein the through hole penetrates the first insulating dielectric material layer and the second insulating dielectric material layer; The through hole is filled to form the conductive plug.

Images