Semiconductor device structure and preparation method thereof

Abstract

The invention provides a semiconductor device structure and a preparation method thereof, and belongs to the technical field of semiconductor device production. The semiconductor device structure comprises a substrate, a drift region and a plurality of protective layers which are sequentially arranged along a first direction, and scribing channels for chip cutting are arranged between adjacent cellular regions corresponding to a semiconductor device in the protective layers. In the first direction, the section of the scribing channel is step-shaped, and the width of the section of the scribing channel is gradually increased; the first direction is a direction from the back surface to the front surface of the semiconductor device. According to the structure, the scribing channel with the step-shaped cross section is formed in the protective layer, so that the protective layer can greatly reduce the probability that chips sputtered at a high speed damage cells in the scribing process, and edge breakage generated in the scribing process is reduced; and the step-shaped scribing channel can limit the area of the scribing cutter wheel, so that the probability that the cutter wheel slides the cutter is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of SIC device production, and in particular to a semiconductor device structure and a preparation method thereof. Background Art

[0002] In the field of power electronics, silicon-based IGBTs (insulated gate bipolar transistors) have long dominated high-voltage and high-current application scenarios. However, with the advancement of science and technology and the rapid development of emerging industries such as new energy vehicles and photovoltaic power generation, the limitations of silicon-based IGBTs have gradually emerged, especially under high-frequency conditions. They cannot withstand the pressure brought by high-frequency switching and have high power consumption, which limits their application in certain high-efficiency and high-frequency demanding situations. Silicon carbide (SiC), as a new type of semiconductor material, has excellent properties of high-voltage and high-temperature resistance. This allows SiC devices, especially SiC-based MOSFETs (metal oxide semiconductor field effect transistors), to cover the voltage resistance level of silicon-based IGBTs with only a simpler device design and avoid their high energy consumption disadvantages. Experimental data show that under the same environment, SiC-based MOSFETs reduce energy losses by 66% compared to silicon-based IGBTs of the same specifications. This significant reduction is mainly due to the significant reduction in switching losses.

[0003] Therefore, SiC materials are widely used in key components such as inverters, on-board chargers, and fast charging piles that drive and control motors to improve system efficiency and reliability. However, in the production process of SiC devices, scribing is a crucial step. The quality of scribing directly affects the performance and yield of the device. Due to the super hardness of SiC materials, the difficulty of scribing with a knife wheel is much greater than that of silicon-based devices during the scribing process. On the one hand, the debris generated during scribing is easily sputtered to the cell area during high-speed movement, resulting in damage to the cell graphics; on the other hand, since there is no effective protective layer at the boundary between the cell and the scribing path, it is easy to produce large edge collapse, further damaging the cell area. In order to prevent the edge collapse from damaging the cell graphics area, a larger scribing path distance needs to be set, but this will reduce the effective utilization of the wafer and increase production costs. In addition, the knife slip phenomenon is prone to occur during the scribing process, further affecting the quality and yield of the device.

[0004] Therefore, it is necessary to improve the existing SIC device scribing process to overcome the defects of the prior art. Summary of the invention

[0005] In order to overcome the problems existing in the related art, one of the objects of the present invention is to provide a semiconductor device structure, which forms a scribing path with a step-shaped cross-section on the protective layer, so that the protective layer can greatly reduce the probability of damage to cells by debris sputtered at high speed during the scribing process, and reduce the edge chipping caused during the scribing process; and the step-shaped scribing path can limit the area of ​​the scribing wheel, reducing the probability of the wheel slipping.

[0006] A semiconductor device structure comprises a substrate, a drift region and a plurality of protective layers arranged in sequence along a first direction, wherein a dicing path for chip cutting is provided between adjacent cell regions corresponding to the semiconductor device in the protective layer;

[0007] Along the first direction, the cross section of the scribe line is step-shaped, and the width of the cross section of the scribe line gradually increases; the first direction is the direction from the back side to the front side of the semiconductor device.

[0008] These protective layers are located between the two cell areas. Due to the presence of the protective layer, the high-speed sputtering debris generated during the scribing process is effectively blocked, reducing the chance of the debris directly contacting the cell area, thereby greatly reducing the probability of debris damaging the cell. The protective layer provides a physical barrier for the cell area. It can reduce the direct impact on the cell area boundary during the scribing process, thereby reducing the edge collapse caused by scribing, protecting the integrity of the cell, and reducing the wafer area sacrificed to prevent edge collapse, thereby improving the effective utilization of the wafer, thereby improving production efficiency and material utilization. In addition, the scribing road limits the scribing area of ​​the cutter wheel, and the cutter wheel is guided to operate within a specific scribing road area, reducing the possibility of the cutter wheel deviating from the predetermined path, thereby reducing the risk of slipping.

[0009] In a preferred technical solution of the present invention, the protective layer includes a first protective layer, a second protective layer, a third protective layer and a fourth protective layer sequentially arranged along the first direction; the scribing road is divided into a first scribing area, a second scribing area, a third scribing area and a fourth scribing area corresponding to the above protective layers, and the width of each scribing area is d1, d2, d3 and d4 respectively;

[0010] Among them, d1 / d2=0.42-0.85; d3 / d2=1.1-2.8; d4 / d2=1.2-3.5.

[0011] In a preferred technical solution of the present invention, the first protection layer includes a field oxide layer, and the field oxide layer includes multiple layers of SiO2 arranged in sequence along the first direction. 2 layer.

[0012] In a preferred technical solution of the present invention, the field oxide layer includes a first SiO 2 Layer, second SiO 2Layer and third SiO 2 layer; wherein the first SiO 2 The second SiO layer is generated by thermal oxidation process. 2 The third SiO layer is formed by low pressure chemical vapor deposition LPCVD process. 2 The first SiO layer is formed by plasma enhanced chemical vapor deposition (PECVD) process; 2 layer, the second SiO 2 layer and the third SiO 2 The ratio of the layer thickness is 1:8:65-1:10:80.

[0013] In a preferred technical solution of the present invention, the second protective layer includes a gate oxide layer and a polysilicon layer sequentially arranged along the first direction, wherein the gate oxide layer is grown on top of the field oxide layer, and the polysilicon layer is grown on top of the gate oxide layer;

[0014] The ratio of the total thickness of the second protective layer to the thickness of the first protective layer is 15:4-15:6.

[0015] The gate oxide layer and the polysilicon layer are grown on top of the field oxide layer to form a composite protective layer. The gate oxide layer provides good electrical insulation performance, while the polysilicon layer is used as the gate material. This structure enhances the stability and reliability of the device under high voltage. The design of the second scribing area allows for more precise control of the path of the cutter wheel during the scribing process, reduces damage to other parts of the device, and improves the accuracy of scribing and the yield of the device. The design of the ratio of the total thickness of the gate oxide layer and the polysilicon layer to the thickness of the field oxide layer helps to provide sufficient mechanical support during the scribing process and reduce device deformation or damage caused by scribing.

[0016] In a preferred technical solution of the present invention, the third protective layer includes a deposited interlayer dielectric layer; the deposited interlayer dielectric layer includes an LPTEOS layer and a PETEOS layer arranged in sequence along a first direction, wherein the LPTEOS layer is grown on top of the polysilicon layer, and the PETEOS layer is grown on top of the LPTEOS layer.

[0017] The deposited interlayer dielectric layer includes an LPTEOS layer and a PETEOS layer, which are grown on top of the polysilicon layer and the LPTEOS layer, respectively. The double-layer dielectric layer structure provides stronger electrical insulation performance, reduces the leakage current of the device under high voltage, and improves the reliability of the device. The thickness design of the LPTEOS layer and the PETEOS layer, as well as the design of the ratio to the total thickness of the gate oxide layer and the polysilicon layer, can reduce the physical damage to the device during the dicing process and improve the durability of the device.

[0018] In a preferred technical solution of the present invention, the fourth protective layer includes a passivation layer; the passivation layer includes a fourth SiO 2 Layer and Si 3 N 4 Layer, fourth SiO 2 layer is grown on top of the deposited interlayer dielectric layer, Si 3 N 4 Layer grown on the fourth SiO 2 The top of the fourth layer 2 Layer and Si 3 N 4 The ratio of the thickness of the layers is 6:1-1:1.

[0019] This double-layer passivation structure further improves the device's chemical corrosion resistance and moisture resistance, extending the device's service life. 3 N 4 The layer is known for its high hardness and wear resistance and is grown on SiO 2 This structure improves the mechanical stability and wear resistance of the device during subsequent processing and use, and reduces the risk of physical damage. In addition, by precisely controlling the ratio of d4 to d2, it is possible to reduce debris and edge collapse during the dicing process, protect sensitive areas of the device, and improve the reliability and life of the device.

[0020] In a preferred technical solution of the present invention, the ratio of the total thickness of the gate oxide layer and the polysilicon layer to the thickness of the deposited interlayer dielectric layer is 1:1.5-1:3.

[0021] A second object of the present invention is to provide a method for preparing a semiconductor device structure, the method being used to prepare the semiconductor device structure as described above;

[0022] The method comprises:

[0023] sequentially generating a plurality of protective layers on a drift region of a semiconductor device;

[0024] After each protective layer is formed, a scribe area is formed by etching between adjacent cell areas of the corresponding semiconductor device; and along a first direction, the cross-sectional width of the scribe area gradually increases, thereby forming a scribe path with a step-shaped cross-section; the first direction is the direction from the back to the front of the semiconductor device.

[0025] In a preferred technical solution of the present invention, the protective layer includes a first protective layer, a second protective layer, a third protective layer and a fourth protective layer sequentially arranged along a first direction; the first protective layer includes a field oxide layer, the second protective layer includes a gate oxide layer and a polysilicon layer sequentially arranged along the first direction, the third protective layer includes a deposited interlayer dielectric layer, and the fourth protective layer includes a passivation layer; wherein,

[0026] The method for preparing the first protective layer comprises: the field oxide layer comprises a plurality of SiO layers sequentially arranged along a first direction. 2 Layer, each SiO 2 The layer is formed using a thermal oxygen process, a low pressure chemical vapor deposition LPCVD process and / or a plasma enhanced chemical vapor deposition PECVD process;

[0027] The preparation method of the second protective layer comprises: growing the gate oxide layer on the field oxide layer by using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process, and growing the polysilicon layer on the gate oxide layer by using a low pressure chemical vapor deposition (LPCVD) process;

[0028] The preparation method of the third protective layer comprises: the deposited interlayer dielectric layer comprises an LPTEOS layer and a PETEOS layer sequentially arranged along a first direction, the LPTEOS layer is grown on the polysilicon layer using a low pressure chemical vapor deposition (LPTECVD) process, and the PETEOS layer is grown on the LPTEOS layer using a plasma enhanced chemical vapor deposition (PECVD) process;

[0029] The method for manufacturing the fourth protective layer includes: the passivation layer includes fourth SiO2 layers sequentially arranged along a first direction. 2 Layer and Si 3 N 4 A fourth SiO layer is grown on the PETEOS layer using a chemical vapor deposition CVD process or an atomic layer deposition ALD process. 2 layer, in the fourth SiO 2 The Si layer is grown by chemical vapor deposition (CVD) process. 3 N 4 layer.

[0030] Specifically, the detailed preparation process of each protective layer of the present application is as follows:

[0031] The method for manufacturing the field oxide layer comprises:

[0032] Perform RCA cleaning on the substrate and drift region;

[0033] Using hot oxygen process, N 2 and O 2 , and grow 100A-500A first SiO on the top of the drift region at 1000℃-1200℃ 2 layer;

[0034] Cleaning growth has the first SiO 2 Layer devices;

[0035] Using LPCVD process, tetraethyl orthosilicate and O 2 As raw material, continue to grow 1000A-5000A second SiO at a temperature of 600℃-900℃ 2 layer;

[0036] Using PECVD process, tetraethyl orthosilicate and O 2 The raw material is grown at 600℃-900℃ for 10000A-20000A third SiO 2 layer;

[0037] Densification treatment is carried out at 1000°C-1200°C;

[0038] Using an exposure and development process, removing a middle portion of the field oxide layer, so that the first scribing area is formed in the middle portion of the field oxide layer;

[0039] The method for manufacturing the second protective layer comprises:

[0040] Growing a gate oxide layer of 200A-1000A on the field oxide layer;

[0041] Depositing a polysilicon layer of 2000A-6000A on the gate oxide layer;

[0042] Etching and removing the middle parts of the gate oxide layer and the polysilicon layer, so that the second scribing area is formed in the middle part of the second protection layer;

[0043] The method for manufacturing the third protective layer comprises:

[0044] Depositing a 1000A-4000A LPTEOS layer on top of the polysilicon layer;

[0045] Depositing a 5000A-8000A PETEOS layer on top of the LPTEOS layer;

[0046] Etching and removing the middle parts of the LPTEOS layer and the PETEOS layer, so that the third scribing area is formed in the middle of the third protection layer;

[0047] The method for manufacturing the fourth protective layer comprises:

[0048] A fourth SiO2 layer of 4000A-10000A is grown on top of the deposited interlayer dielectric layer. 2 layer;

[0049] In the fourth SiO 2 The top of the layer grows 4000A-10000A Si 3 N 4 layer;

[0050] Etching to remove the fourth SiO 2 layer, the Si 3 N 4 The middle part of the fourth protective layer forms the fourth scribing area.

[0051] The beneficial effects of the present invention are:

[0052] The present invention provides a semiconductor device structure, which includes a substrate, a drift region and a plurality of protective layers arranged in sequence along a first direction, wherein a scribing path for chip cutting is provided between adjacent cell regions corresponding to the semiconductor device in the protective layer. Along the first direction, the scribing path has a step-shaped cross section, and the width of the scribing path cross section gradually increases; the first direction is the direction from the back to the front of the semiconductor device. The semiconductor device structure forms a scribing path with a step-shaped cross section on the protective layer, for example, the cross section of the scribing path can be similar to a "V" shape or a "U" shape. This design not only enhances the structural strength of the protective layer, but also effectively guides the scribing wheel to cut along a predetermined path, limits the scribing area of ​​the wheel, and the wheel is guided to operate in a specific scribing path area, reducing the possibility of the wheel deviating from the predetermined path, thereby reducing the risk of slipping. Moreover, the protective layer provides a physical barrier for the cell region. It can reduce the direct impact on the boundary of the cell area during the dicing process, thereby reducing the edge collapse phenomenon caused by dicing, protecting the integrity of the cell, reducing the wafer area sacrificed to prevent edge collapse, and improving the effective utilization rate of the wafer, thereby improving production efficiency and material utilization.

[0053] The present application also provides a method for preparing the semiconductor device structure, which can produce a dicing path with a step-like structure on the semiconductor device, thereby reducing damage to the semiconductor device during the dicing process and improving the yield rate of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 is a schematic diagram of a semiconductor device structure provided in an embodiment of the present invention;

[0055] Figure 2 is a schematic diagram of various protective layers provided in an embodiment of the present invention;

[0056] Figure 3 It is a flow chart of a method for preparing a semiconductor device structure provided in an embodiment of the present invention.

[0057] Reference numerals:

[0058] 1. Cell region; 2. Substrate; 3. First protective layer; 4. Drift region; 5. Second protective layer; 51. Gate oxide layer; 52. Polysilicon layer; 6. Third protective layer; 61. LPTEOS layer; 62. PETEOS layer; 7. Fourth protective layer; 71. Si 3 N 4 Layer; 72, fourth SiO 2 layer. DETAILED DESCRIPTION

[0059] The preferred embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.

[0060] In the manufacturing process of existing SiC devices, scribing is a crucial step. The quality of scribing directly affects the performance and yield of the device. Due to the super hardness of SiC materials, the difficulty of scribing with a knife wheel is much greater than that of silicon-based devices. On the one hand, the debris generated during scribing is easily sputtered to the cell area during high-speed movement, causing damage to the cell graphics; on the other hand, since there is no effective protective layer at the boundary between the cell and the scribing path, large edge collapse is likely to occur, further damaging the cell area. In order to prevent the edge collapse from damaging the cell graphics area, a larger scribing path distance needs to be set, but this will reduce the effective utilization rate of the wafer and increase production costs. In addition, the knife slip phenomenon is prone to occur during the scribing process, further affecting the quality and yield of the device.

[0061] Based on this, the present application provides a semiconductor device structure.

[0062] Example 1

[0063] like Figure 1-Figure 2 As shown, a semiconductor device structure provided in this embodiment includes a substrate 2, a drift region 4 and a plurality of protective layers arranged in sequence along a first direction, wherein dicing lanes for chip cutting are provided between adjacent cell regions 1 corresponding to the semiconductor device in the protective layers; the substrate of the present application is SiC material.

[0064] Along the first direction, the cross section of the scribe line is step-shaped, and the width of the cross section of the scribe line gradually increases; the first direction is the direction from the back side to the front side of the semiconductor device.

[0065] The semiconductor device structure forms a scribing path with a stepped cross-section on the protective layer. For example, the cross-section of the scribing path can be similar to a "V" shape or a "U" shape. This design not only enhances the structural strength of the protective layer, but also effectively guides the scribing wheel to cut along a predetermined path, limits the scribing area of ​​the wheel, and guides the wheel to operate within a specific scribing path area, thereby reducing the possibility of the wheel deviating from the predetermined path, thereby reducing the risk of slipping. Moreover, the protective layer provides a physical barrier for the cell area 1. It can reduce the direct impact on the boundary of the cell area 1 during the scribing process, thereby reducing the edge collapse phenomenon caused by scribing, protecting the integrity of the cell, and can reduce the wafer area sacrificed to prevent edge collapse, thereby improving the effective utilization of the wafer, thereby improving production efficiency and material utilization.

[0066] Specifically, the protective layer includes a first protective layer 3, a second protective layer 5, a third protective layer 6 and a fourth protective layer 7 arranged in sequence along the first direction; the scribing road is divided into a first scribing area, a second scribing area, a third scribing area and a fourth scribing area corresponding to the above protective layers, and the width of each scribing area is d1, d2, d3 and d4 respectively;

[0067] Among them, d1 / d2=0.42-0.85; d3 / d2=1.1-2.8; d4 / d2=1.2-3.5.

[0068] In a specific implementation, the width of the first scribing area is d1, wherein d1 is 30um-50um, and d1 is 5um-10um larger than the scribing width of the cutter wheel. In practical applications, the width of d1 can be determined according to the thickness of the cutter wheel.

[0069] Furthermore, the first protective layer 3 comprises a field oxide layer, and the field oxide layer comprises a plurality of SiO layers sequentially arranged along a first direction. 2 layer.

[0070] Through multi-layer SiO 2 The field oxide layer formed by the layer can play a good role in electrical isolation, ensuring that different parts inside the device are electrically separated and preventing current from flowing in undesired paths. In addition, the presence of the field oxide layer also enhances the overall stability of the device. It helps to maintain the stability and reliability of the device during operation and ensures that the device can operate stably for a long time.

[0071] The second protection layer 5 includes a gate oxide layer 51 and a polysilicon layer 52, wherein the gate oxide layer 51 is grown on the top of the field oxide layer, and the polysilicon layer 52 is grown on the top of the gate oxide layer 51;

[0072] The ratio of the total thickness of the second protective layer 5 to the thickness of the first protective layer 3 is 15:4-15:6.

[0073] The present application controls the total thickness of the second protective layer 5 and the thickness of the first protective layer 3 to ensure that the protective layer has sufficient strength and thickness to effectively resist the mechanical stress and debris impact generated during the dicing process. In addition, by setting the total thickness of the second protective layer 5 and the total thickness of the first protective layer 3, the cost can be reduced as much as possible while ensuring the performance, thereby improving the economic efficiency of the device.

[0074] Further, the third protection layer 6 includes a deposited interlayer dielectric layer; the deposited interlayer dielectric layer includes an LPTEOS layer 61 and a PETEOS layer 62 , the LPTEOS layer 61 is grown on top of the polysilicon layer 52 , and the PETEOS layer 62 is grown on top of the LPTEOS layer 61 .

[0075] Specifically, the thickness of LPTEOS layer 61: the thickness of PETEOS layer 62 = 1:2-1:5. The structural strength of the deposited interlayer dielectric layer I LD (Interlayer Dielectric) can be optimized by controlling the deposition thickness ratio of the LPTEOS layer 61 and the PETEOS layer 62. An appropriate thickness ratio helps to improve the I LD layer's ability to withstand the mechanical stress generated during the dicing process and reduce the risk of edge collapse.

[0076] Further, the fourth protective layer 7 includes a passivation layer; the passivation layer includes a fourth SiO 2 Layer 72 and Si 3 N 4 Layer 71, fourth SiO 2 Layer 72 is grown on top of the deposited interlayer dielectric layer, Si 3 N 4 Layer 71 is grown on top of the fourth SiO2 layer 72. 2 The thickness of layer 72 is related to Si 3 N 4 The thickness of layer 71 is in a ratio of 6:1 to 1:1.

[0077] This application adjusts SiO 2 with Si 3 N 4 The film thickness ratio can optimize the performance of the passivation layer, making it more resistant to corrosion, oxidation and mechanical stress. 2 The thickness of layer 72 is related to Si 3 N 4 The design of a thickness ratio of 6:1-1:1 for the layer 71 helps to form a more stable structure and improve the overall reliability of the device.

[0078] Furthermore, the thickness of the second protective layer 5:the thickness of the fourth protective layer 7=3:12-5:12.

[0079] The thickness ratio of the second protective layer 5 to the fourth protective layer 7 can ensure that the fourth protective layer 7 has sufficient thickness and strength to more effectively protect the cell region 1. In addition, a proper thickness ratio helps to form a more precise dicing street structure, reduce the risk of knife slippage, and improve dicing efficiency.

[0080] This is critical to improving device yield and reliability.

[0081] Example 2

[0082] like Figure 1-Figure 3 As shown, this embodiment provides a method for preparing a semiconductor device structure, comprising:

[0083] S100, sequentially generating a plurality of protective layers on the drift region 4 of the semiconductor device;

[0084] S200, after each protective layer is formed, a scribe area is formed by etching between adjacent cell areas 1 of the corresponding semiconductor device; and along a first direction, the cross-sectional width of the scribe area gradually increases, thereby forming a scribe path with a step-shaped cross-section; the first direction is the direction from the back side to the front side of the semiconductor device.

[0085] Specifically, the protective layer includes a first protective layer 3, a second protective layer 5, a third protective layer 6 and a fourth protective layer 7 arranged in sequence along a first direction; the scribing road is divided into a first scribing area, a second scribing area, a third scribing area and a fourth scribing area corresponding to the above protective layers, and the width of each scribing area is d1, d2, d3 and d4 respectively;

[0086] Among them, d1 / d2=0.42-0.85; d3 / d2=1.1-2.8; d4 / d2=1.2-3.5.

[0087] More specifically, the first protection layer 3 includes a field oxide layer, and the field oxide layer includes a first SiO2 layer sequentially arranged along a first direction. 2 Layer, second SiO 2 Layer, third SiO 2 Layer: First SiO 2 Layer: Second SiO 2 Layer: Third SiO 2 The thickness ratio of the layers is 1:8:65-1:10:80;

[0088] The second protection layer 5 includes a gate oxide layer 51 and a polysilicon layer 52, wherein the gate oxide layer 51 is grown on the top of the field oxide layer, and the polysilicon layer 52 is grown on the top of the gate oxide layer 51;

[0089] The thickness of the gate oxide layer 51: the thickness of the polysilicon layer 52 = 1:6-1:12; the thickness of the second protective layer 5: the thickness of the first protective layer 3 = 15:4-15:6;

[0090] The third protective layer 6 includes a deposited interlayer dielectric layer, wherein the deposited interlayer dielectric layer includes an LPTEOS layer 61 and a PETEOS layer 62; the LPTEOS layer 61 is grown on top of the polysilicon layer 52, and the PETEOS layer 62 is grown on top of the LPTEOS layer 61; the thickness of the LPTEOS layer 61: the thickness of the PETEOS layer 62 = 1:2-1:5; the thickness of the second protective layer 5: the thickness of the third protective layer 6 = 1:1.5-1:3;

[0091] The fourth protective layer 7 includes a passivation layer, the passivation layer includes a fourth SiO 2 Layer 72 and Si 3 N 4 Layer 71, fourth SiO 2 Layer 72 is grown on top of the deposited interlayer dielectric layer, and Si3N4 layer 71 is grown on the fourth SiO 2 The top of the fourth SiO 2 Layer 72 thickness: Si 3 N 4 Layer 71 thickness = 6:1-1:1; second protective layer 5 thickness: fourth protective layer 7 thickness = 3:12-5:12.

[0092] The present application also provides methods for preparing each protective layer, which are as follows:

[0093] The growth process of the field oxide layer of the first protection layer 3 is specifically as follows:

[0094] First, RCA (Radio Corporation of America) cleaning is performed on the substrate 2 and the drift region 4, which is a standard semiconductor cleaning process for removing organic pollutants and metal ions on the surface. This step helps protect the device from chemical corrosion and prolongs the service life of the device.

[0095] On the cleaned substrate 2, N is introduced at a temperature of 1000°C-1200°C by thermal oxidation process. 2 (nitrogen) and O 2 (oxygen), grow a first SiO layer of 100-500 angstroms on the top of the drift region 4 2 This step is carried out at high temperature and helps to form high-quality SiO 2 layer.

[0096] Growing the First SiO 2After the layers are formed, the device is cleaned to remove any residue or impurities that may have been produced during the growth process.

[0097] Then, a low-pressure chemical vapor deposition (LPCVD) process was used to deposit tetraethyl orthosilicate (TES) and O at a temperature of 600°C-900°C. 2( Oxygen) as raw material, continue to grow 1000A-5000A of the second SiO 2 The LPCVD process helps to grow uniform SiO layers at lower pressures. 2 layer.

[0098] The plasma enhanced chemical vapor deposition (PECVD) process was used to deposit tetraethyl orthosilicate and O at a temperature of 600°C-900°C. 2 As raw material, grow 10000A-20000A of the third SiO 2 The PECVD process can grow SiO2 layers at lower temperatures by using plasma to promote chemical reactions.

[0099] After growing all SiO 2 After the layer, a densification treatment (high temperature annealing) is performed at 1000℃-1200℃ to increase the SiO 2 Increases the density and quality of the layers, reducing porosity and defects.

[0100] In this embodiment, the field oxide layer is grown by thermal oxidation process, LPCVD and PECVD process, and the growth temperature and SiO2 are precisely controlled. 2 The thickness of the layer ensures the uniformity and quality of the field oxide layer, reduces defects and impurities, and improves the overall performance and reliability of the device. 2 Layer, second SiO 2 Layer and third SiO 2 The ratio of the layers is controlled between 1:8:65 and 1:10:80. This gradient thickness design enhances the insulation performance of the field oxide layer, reduces leakage current, and improves the withstand voltage capability of the device. 2 Layer growth and densification, which enhances the mechanical strength of the device and reduces mechanical damage during dicing and subsequent processing.

[0101] The second protection layer 5 includes a gate oxide layer 51 and a polysilicon layer 52, wherein the gate oxide layer 51 is grown on the top of the field oxide layer, and the polysilicon layer 52 is grown on the top of the gate oxide layer 51;

[0102] The ratio of the total thickness of the gate oxide layer 51 and the polysilicon layer 52 to the thickness of the field oxide layer is 15:4-15:6;

[0103] A second scribe area is disposed in the middle of the gate oxide layer 51 and the polysilicon layer 52 .

[0104] In this embodiment, on one side of the scribe line, the distance between the edge of the second scribe area and the edge of the first scribe area is d2, wherein the width of d2 is 2um-10um. In practical applications, if d2 is too large, the physical size of the field oxide layer protecting the cell area 1 is reduced, and the thinning splashes are easily sputtered to the cell area 1 to damage the cell area 1 pattern and affect the size of the subsequent film layer. If d2 is too small, the thinning debris deposition channel is reduced by being close to the boundary of the field oxide layer. In addition, the sputtering hits the boundary, resulting in large stress, so that the gate oxide layer 51 and the polysilicon layer 52 are easily damaged, affecting the overall effect.

[0105] A gate oxide layer 51 and a polysilicon layer 52 are grown on top of the field oxide layer in sequence to form a composite protective layer. The gate oxide layer 51 provides good electrical insulation properties, while the polysilicon layer 52 serves as a gate material. This structure enhances the stability and reliability of the device under high voltage. The design of the second scribing area allows for more accurate control of the path of the cutter wheel during the scribing process, reduces damage to other parts of the device, and improves scribing accuracy and device yield. The design of the ratio of the total thickness of the gate oxide layer 51 and the polysilicon layer 52 to the thickness of the field oxide layer helps provide sufficient mechanical support during the scribing process and reduces device deformation or damage caused by scribing.

[0106] The growth process of the gate oxide layer 51 and the polysilicon layer 52 is specifically as follows:

[0107] The top of the field oxide layer is thoroughly cleaned to ensure good contact and adhesion between the gate oxide layer 51 and the field oxide layer.

[0108] The gate oxide layer 51 is grown using chemical vapor deposition (CVD) or atomic layer deposition (ALD) technology. The gate oxide layer 51 may be made of silicon dioxide (SiO 2 ) material, and the thickness is precisely controlled according to the device design requirements. When growing the gate oxide layer 51, parameters such as temperature, pressure, and gas flow rate need to be precisely controlled to ensure the uniformity and quality of the gate oxide layer 51.

[0109] After the gate oxide layer 51 is grown, a surface treatment is performed, such as a final HF (hydrofluoric acid) treatment, to remove the natural oxide layer on the surface and ensure good contact between the polysilicon layer 52 and the gate oxide layer 51 .

[0110] The polysilicon layer 52 is usually grown using a low pressure chemical vapor deposition (LPCVD) technique, which can grow a uniform polysilicon layer 52 at a relatively low pressure. After the polysilicon layer 52 is grown, it is doped to adjust its electrical properties, such as by doping elements such as boron and phosphorus to form p-type or n-type polysilicon. After doping, an annealing process is performed to activate the dopant and reduce defects, thereby improving the conductivity and stability of the polysilicon layer 52.

[0111] The third protection layer 6 includes a deposited interlayer dielectric layer, and the deposited interlayer dielectric layer is grown on the top of the polysilicon layer 52;

[0112] The deposited interlayer dielectric layer includes an LPTEOS layer 61 and a PETEOS layer 62;

[0113] The LPTEOS layer 61 is grown on the top of the polysilicon layer 52, and the PETEOS layer 62 is grown on the top of the LPTEOS layer 61;

[0114] The thickness of the LPTEOS layer 61 is 1000A-4000A, and the thickness of the PETEOS layer 62 is 5000A-8000A;

[0115] The ratio of the total thickness of the gate oxide layer 51 (GOX) and the polysilicon layer 52 to the thickness of the deposited interlayer dielectric layer is 1:1.5-1:3.

[0116] In this embodiment, a third scribing area is provided in the middle of the deposited interlayer dielectric layer, and a distance between an edge of the third scribing area and an edge of the first scribing area on one side of the scribing road is d3;

[0117] Among them, d3 / d2=0.8:1.2.

[0118] It should be noted that the LPTEOS layer 61 of the present application refers to a process of growing SiO2 by LPTECVD low-pressure chemical vapor deposition using TEOS tetraethyl orthosilicate as a raw material; the PETEOS layer 62 refers to a process of growing SiO2 by PECVD plasma enhanced chemical vapor deposition using TEOS tetraethyl orthosilicate as a raw material.

[0119] In practical applications, if d3 is too large, the physical size of the deposited interlayer dielectric layer protecting the cell region 1 is reduced, and the thinning splashes are easily sputtered to the cell region 1 to damage the cell region 1 pattern. If d3 is too small, the deposited interlayer dielectric layer is close to the boundary between the gate oxide layer 51 (GOX) and the polysilicon layer 52, thereby reducing the thinning debris deposition channel. In addition, the sputtering hits the boundary and causes large stress, so that the deposited interlayer dielectric layer is easily damaged, affecting the overall effect.

[0120] The deposited interlayer dielectric layer includes an LPTEOS layer 61 and a PETEOS layer 62, which are grown on the top of the polysilicon layer 52 and the top of the LPTEOS layer 61, respectively. The double-layer dielectric layer structure provides stronger electrical insulation performance, reduces the leakage current of the device under high voltage, and improves the reliability of the device. The thickness design of the LPTEOS layer 61 and the PETEOS layer 62, as well as the design of the ratio to the total thickness of the gate oxide layer 51 and the polysilicon layer 52, can reduce the physical damage to the device during the dicing process and improve the durability of the device.

[0121] The third scribing area cooperates with the structure of the first and second scribing areas to more accurately control the path of the cutter wheel during the scribing process, reduce damage to other parts of the device, and improve the scribing accuracy and device yield.

[0122] This embodiment provides a preparation step of depositing an interlayer dielectric layer:

[0123] After the growth of the polysilicon layer 52 is completed, the surface is thoroughly cleaned to ensure good contact and adhesion between the deposited interlayer dielectric layer and the polysilicon layer 52 .

[0124] Using low pressure chemical vapor deposition (LPCVD) technology, SiO2 is grown at a temperature of 600°C-900°C using TEOS tetraethyl orthosilicate as a raw material.

[0125] A third scribing area is set in the middle of the deposited interlayer dielectric layer, and the scribing area pattern is transferred to the device surface using photolithography technology. The LPTEOS layer 61 and the PETEOS layer 62 are etched according to the photolithography pattern using wet or dry etching technology to form the third scribing area.

[0126] The fourth protective layer 7 also includes a passivation layer, and the passivation layer includes a fourth SiO 2 Layer 72 and Si 3 N 4 Layer 71, fourth SiO 2 Layer 72 is grown on top of the deposited interlayer dielectric layer, Si 3 N 4 Layer 71 is grown on the fourth SiO 2 the top of layer 72;

[0127] Among them, the fourth 2 The thickness of layer 72 is 4000A-10000A, Si 3 N 4 The thickness of layer 71 is 4000A-10000A; SiO 2 Layer thickness and Si 3 N 4 The thickness of layer 71 is in a ratio of 6:1 to 1:1.

[0128] More preferably, a fourth scribing area is provided in the middle of the passivation layer, and a distance between an edge of the fourth scribing area and an edge of the third scribing area on one side of the scribing street is d4;

[0129] Among them, d4 / d2=0.8:1.2; if d4 is too large, the physical size of the passivation layer protecting the cell area 1 will be reduced, and the thinning spatter will easily sputter to the cell area 1 and damage the cell area 1 pattern. If d4 is too small, the boundary of the dielectric layer between the passivation layer and the lower deposition layer will be close to reduce the thinning debris deposition channel. In addition, the sputtering will hit the boundary and cause large stress, so that the PAS layer will be easily damaged and affect the overall effect.

[0130] The ratio of the total thickness of the gate oxide layer 51 and the polysilicon layer 52 to the thickness of the passivation layer is 3:12-5:12. The passivation layer includes the fourth SiO 2 Layer 72 and Si 3 N 4 Layer 71 provides more protective layers for the device. This double-layer passivation structure further improves the chemical corrosion resistance and moisture resistance of the device and prolongs the service life of the device. 3 N 4 Layer 71 is known for its high hardness and wear resistance and is grown on SiO 2 This structure improves the mechanical stability and wear resistance of the device during subsequent processing and use, and reduces the risk of physical damage. In addition, by precisely controlling the ratio of d4 to d2, it is possible to reduce debris and edge collapse during the dicing process, protect sensitive areas of the device, and improve the reliability and life of the device.

[0131] The detailed preparation steps of the passivation layer are as follows:

[0132] The top of the deposited interlayer dielectric layer is thoroughly cleaned to ensure good contact and adhesion between the passivation layer and the deposited interlayer dielectric layer.

[0133] Using chemical vapor deposition (CVD) or atomic layer deposition (ALD) technology, a fourth SiO 2 Layer 72. Fourth SiO 2 The thickness of layer 72 is controlled between 4000A and 10000A.

[0134] In the fourth 2 The Si layer 72 is grown by chemical vapor deposition (CVD) technology. 3 N 4 Layer 71. Si 3 N 4 The thickness of layer 71 is controlled between 4000A and 10000A.

[0135] A fourth scribing area is set in the middle of the passivation layer, and the scribing area pattern is transferred to the device surface using photolithography technology. The fourth SiO is removed by etching according to the photolithography pattern using wet or dry etching technology. 2 Layer 72 and Si 3N 4 The middle portion of layer 71 is cut to form a fourth scribe region.

[0136] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant field may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so that once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings. In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0137] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" may include both "above" and "below". The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0138] In addition, it should be noted that the use of words such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above words have no special meaning and therefore cannot be understood as limiting the scope of protection of this application. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A semiconductor device structure, comprising a substrate, a drift region and a plurality of protective layers arranged in sequence along a first direction, wherein a dicing path for chip cutting is provided between adjacent cell regions corresponding to the semiconductor device in the protective layer; characterized in that: Along the first direction, the cross section of the scribe line is step-shaped, and the width of the cross section of the scribe line gradually increases; the first direction is the direction from the back side to the front side of the semiconductor device.

2. The semiconductor device structure according to claim 1, characterized in that: The protective layer comprises a first protective layer, a second protective layer, a third protective layer and a fourth protective layer arranged in sequence along the first direction; the scribing road is divided into a first scribing area, a second scribing area, a third scribing area and a fourth scribing area corresponding to the above protective layers, and the width of each scribing area is d1, d2, d3 and d4 respectively; Among them, d1 / d2=0.42-0.85; d3 / d2=1.1-2.8; d4 / d2=1.2-3.

5.

3. The semiconductor device structure according to claim 2, characterized in that: The first protection layer includes a field oxide layer, and the field oxide layer includes a plurality of SiO2 layers sequentially arranged along a first direction.

4. The semiconductor device structure according to claim 3, characterized in that: The field oxide layer includes a first SiO2 layer, a second SiO2 layer and a third SiO2 layer arranged in sequence along a first direction; wherein the first SiO2 layer is generated by a thermal oxidation process, the second SiO2 layer is generated by a low-pressure chemical vapor deposition LPCVD process, and the third SiO2 layer is generated by a plasma enhanced chemical vapor deposition PECVD process; the thickness ratio of the first SiO2 layer, the second SiO2 layer and the third SiO2 layer is 1:8:65-1:10:

80.

5. The semiconductor device structure according to claim 3, characterized in that: The second protection layer comprises a gate oxide layer and a polysilicon layer sequentially arranged along a first direction, wherein the gate oxide layer is grown on top of the field oxide layer, and the polysilicon layer is grown on top of the gate oxide layer; The ratio of the total thickness of the second protective layer to the thickness of the first protective layer is 15:4-15:

6.

6. The semiconductor device structure according to claim 5, characterized in that: The third protective layer includes a deposited interlayer dielectric layer; the deposited interlayer dielectric layer includes an LPTEOS layer and a PETEOS layer arranged in sequence along a first direction, wherein the LPTEOS layer is grown on top of the polysilicon layer, and the PETEOS layer is grown on top of the LPTEOS layer; the thickness ratio of the LPTEOS layer to the PETEOS layer is 1:2-1:

5.

7. The semiconductor device structure according to claim 6, characterized in that: The fourth protective layer includes a passivation layer; the passivation layer includes a fourth SiO2 layer and a Si3N4 layer arranged in sequence along the first direction, wherein the fourth SiO2 layer is grown on top of the deposited interlayer dielectric layer, and the Si3N4 layer is grown on top of the fourth SiO2 layer, and the thickness ratio of the fourth SiO2 layer to the Si3N4 layer is 6:1-1:

1.

8. The semiconductor device structure according to claim 7, characterized in that: The ratio of the total thickness of the gate oxide layer and the polysilicon layer to the thickness of the deposited interlayer dielectric layer is 1:1.5-1:

3.

9. A method for preparing a semiconductor device structure, used for preparing the semiconductor device structure as claimed in any one of claims 1 to 8, characterized in that: The method comprises: sequentially generating a plurality of protective layers on a drift region of a semiconductor device; After each protective layer is formed, a scribe area is formed by etching between adjacent cell areas corresponding to the semiconductor device; and along a first direction, the cross-sectional width of the scribe area gradually increases, thereby forming a scribe path with a step-shaped cross-section; the first direction is the direction from the back to the front of the semiconductor device.

10. The method for preparing a semiconductor device structure according to claim 9, characterized in that: The protective layer comprises a first protective layer, a second protective layer, a third protective layer and a fourth protective layer arranged in sequence along a first direction; the first protective layer comprises a field oxide layer, the second protective layer comprises a gate oxide layer and a polysilicon layer arranged in sequence along the first direction, the third protective layer comprises a deposited interlayer dielectric layer, and the fourth protective layer comprises a passivation layer; wherein, The method for preparing the first protective layer comprises: the field oxide layer comprises a plurality of SiO2 layers sequentially arranged along a first direction, and each SiO2 layer is formed by a thermal oxidation process, a low pressure chemical vapor deposition LPCVD process and / or a plasma enhanced chemical vapor deposition PECVD process; The preparation method of the second protective layer comprises: growing the gate oxide layer on the field oxide layer by using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process, and growing the polysilicon layer on the gate oxide layer by using a low pressure chemical vapor deposition (LPCVD) process; The preparation method of the third protective layer comprises: the deposited interlayer dielectric layer comprises an LPTEOS layer and a PETEOS layer sequentially arranged along a first direction, the LPTEOS layer is grown on the polysilicon layer using a low pressure chemical vapor deposition (LPTECVD) process, and the PETEOS layer is grown on the LPTEOS layer using a plasma enhanced chemical vapor deposition (PECVD) process; The manufacturing method of the fourth protective layer includes: the passivation layer includes a fourth SiO2 layer and a Si3N4 layer arranged in sequence along the first direction, the fourth SiO2 layer is grown on the PETEOS layer using a chemical vapor deposition CVD process or an atomic layer deposition ALD process, and the Si3N4 layer is grown on the fourth SiO2 layer using a chemical vapor deposition CVD process.

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