Microstrip combiner

By adopting the upper and lower wide-side coupling structure and Z-axis laminated design in the microstrip combiner, the problems of large size and low power of the traditional combiner are solved, and a miniaturized, high-power and low insertion loss microstrip combiner is realized, which is suitable for high-power scenarios.

CN119944264APending Publication Date: 2025-05-06NAWEI SEMICONDUCTOR TECHNOLOGY (HEFEI) CO LTD
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Patent Information

Application Number
CN202510301443.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-03-14
Publication Date
2025-05-06

AI Technical Summary

Technical Problem

The physical size of traditional short-band combiners is too large and difficult to integrate. The existing technology has problems such as easy components to fall off and low power capacity in high-power scenarios above 500W, and it is difficult to achieve strong coupling and wide bandwidth in the same plane edge coupling method.

Method used

The microstrip combiner design with upper and lower wide edge coupling is adopted to achieve energy transmission by optimizing the coupling structure and parameters, and combining the Z-axis laminate design and standard PCB process to reduce manufacturing cost and process difficulty.

Benefits of technology

It realizes miniaturization, low insertion loss and high power synthesis capabilities, solves the technical bottleneck of traditional low-frequency circuit combinations, reduces the volume to less than 1/5, and has a power capacity of ≥1kW, and is suitable for industrial RF heating and communication base station systems.

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Abstract

The invention discloses a microstrip combiner which comprises a first microstrip line, a second microstrip line and a dielectric substrate, the first microstrip line and the second microstrip line are arranged in parallel up and down in the Z-axis direction, the first microstrip line is located on the upper layer of the dielectric substrate, and the second microstrip line is located on the lower layer of the dielectric substrate. The first microstrip line and the second microstrip line realize energy transmission in the Z-axis direction through broadside coupling, the phase difference between an input port (port 2) of the first microstrip line and an input port (port 3) of the second microstrip line is 90 degrees, and an output port (port 4) of the first microstrip line is connected to a load. According to the microstrip combiner, the upper and lower broadside coupling structures replace traditional coplanar edge coupling, the processing problem caused by too small coupling gaps is avoided, and meanwhile, the device size is effectively reduced. Compared with a traditional Wilkinson combiner, the size of the Wilkinson combiner is reduced to below 1 / 5. A Z-axis direction lamination design is adopted, and a standard PCB process is combined, so that complex three-dimensional structure processing is not needed, and the manufacturing cost and the process difficulty are reduced.
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Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency power synthesis, and in particular to a microstrip combiner. Background Art

[0002] Traditional short-wave combiners (such as the Wilkinson structure) are limited by the quarter-wavelength principle in the low-frequency band, resulting in excessive physical size (such as the branch length of several meters at 13.56MHz), which makes them difficult to integrate. In the prior art, the solution of using lumped components to simulate the distribution effect of microstrip lines has problems such as easy falling off of components and low power capacity, which limits its application in high-power scenarios above 500W. In addition, the traditional co-planar edge coupling method is difficult to achieve strong coupling and wide bandwidth due to processing accuracy limitations. In response to the above problems, the present invention proposes a microstrip combiner based on upper and lower wide-edge coupling, which achieves miniaturization, low insertion loss and high power synthesis capability by optimizing the coupling structure and parameters. Summary of the invention

[0003] In order to solve the technical problems existing in the background technology, the present invention provides a microstrip combiner.

[0004] A microstrip combiner proposed in the present invention comprises a first microstrip line, a second microstrip line and a dielectric substrate, the first microstrip line and the second microstrip line are arranged in parallel up and down in a Z-axis direction, the first microstrip line is located in an upper layer of the dielectric substrate, the second microstrip line is located in a lower layer of the dielectric substrate, the first microstrip line and the second microstrip line realize energy transmission in the Z-axis direction through broadside coupling, the phase difference between an input port port2 of the first microstrip line and an input port port3 of the second microstrip line is 90°, and an output port port4 of the first microstrip line is connected to a load.

[0005] Preferably, the reflection coefficients of the input / output ports of the first microstrip line and the second microstrip line are both ≤-20 dB, and the insertion losses of the input ports of the first microstrip line and the second microstrip line are both ≤-3.2 dB.

[0006] Preferably, the coupling coefficient C between the first microstrip line and the second microstrip line satisfies:

[0007]

[0008] Among them, Z Ce is the even-mode impedance; Z Co is odd mode impedance.

[0009] Preferably, the line width W of the first microstrip line and the second microstrip line is in the range of 1-5 mm, and the line length difference ΔL between the first microstrip line and the second microstrip line is calculated according to the following formula:

[0010]

[0011] Where c is the speed of light, f = 13.56MHz, ΔL is the difference in length between the first microstrip line and the second microstrip line, and its value is 10-15mm; ε r is the relative dielectric constant of the dielectric substrate.

[0012] Preferably, an island copper ground is arranged around the first microstrip line and the second microstrip line, and the width of the island copper ground is 2-3 times the width of the first microstrip line or the second microstrip line. The island copper ground is connected to the bottom reference plane of the microstrip combiner through a through-hole array with a diameter of 0.2-0.5 mm; coupling capacitors and filter capacitors are welded on the island copper ground.

[0013] Preferably, the coupling capacitance is calculated by the following formula:

[0014] C M =C·C O ;

[0015]

[0016] Wherein, W is the line width of the first microstrip line and the second microstrip line; H is the thickness of the dielectric substrate; C is the coupling coefficient between the first microstrip line and the second microstrip line; ε r is the relative dielectric constant of the dielectric substrate; T is the copper foil thickness of the microstrip line; C O C is the distributed capacitance per unit length of the microstrip line, with a value of 0.5-1.5pF / in; M is the coupling capacitor.

[0017] Preferably, a metal shielding cover is provided outside the microstrip combiner, and the metal shielding cover is welded to the isolated copper ground or connected to the isolated copper ground through a conductive adhesive.

[0018] Preferably, the material of the dielectric substrate is FR4 or Rogers 4350B, and the relative dielectric constant ε of the dielectric substrate is r The value range of is 3.5-5, and the value range of the thickness H of the dielectric substrate is 1-2 mm.

[0019] Preferably, the distance D between the first microstrip line and the second microstrip line in the broadside coupling corresponding area is in the range of 0.1-0.3 mm, and the length of the coupling area is Wherein, λ is the wavelength corresponding to 13.56 MHz.

[0020] Preferably, the ends of the first microstrip line and the second microstrip line adopt a gradient line structure with a gradient angle of 30°-60° for impedance matching and reflection suppression.

[0021] In the present invention, the proposed microstrip combiner replaces the traditional coplanar edge coupling with the upper and lower wide-edge coupling structures, avoiding the processing difficulties caused by too small coupling gaps, and effectively reducing the size of the device. Compared with the traditional Wilkinson combiner, the volume is reduced to less than 1 / 5. The Z-axis stacking design is adopted, combined with the standard PCB process, and no complex three-dimensional structure processing is required, which reduces the manufacturing cost and process difficulty. Miniaturization, low loss, high power capacity and wide bandwidth characteristics are achieved, solving the technical bottleneck of traditional low-frequency combiners. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A 2D structural schematic diagram of a microstrip combiner proposed by the present invention;

[0023] Figure 2 A 2D structural schematic diagram of one of the microstrip coils of a microstrip combiner proposed by the present invention;

[0024] Figure 3 A 2D structural schematic diagram of another microstrip coil of a microstrip combiner proposed by the present invention;

[0025] Figure 4 A schematic diagram of simulation data of reflection coefficients of each port of a microstrip combiner of the microstrip combiner proposed by the present invention;

[0026] Figure 5 This is a schematic diagram of the insertion loss simulation data of ports 2 and 3 of the microstrip combiner of the present invention;

[0027] Figure 6 This is a schematic diagram of the isolation simulation data of ports 2 and 3 of the microstrip combiner of the present invention;

[0028] Figure 7 This is a schematic diagram of the simulation data of the phase difference between ports 2 and 3 of the microstrip combiner of the present invention;

[0029] Figure 8 This is the circuit diagram of the equivalent lumped LC element of the microstrip combiner of the present invention.

[0030] Description of reference numerals:

[0031] 1. Input port port2; 2. Input port port3; 3. Island copper ground area one; 4. Microstrip coil; 5. Island copper ground area two; 6. Filter capacitor solder point one; 7. Coupling capacitor solder point one; 8. Filter capacitor solder point two; 9. Coupling capacitor solder point two; 10. Load solder point one; 11. Filter capacitor solder point three; 12. Load solder point two; 13. Output port port1; 14. Coupling capacitor solder point three; 15. Microstrip line layer change connection line one; 16. Microstrip line layer change via one; 17. Microstrip line layer change connection line two; 18. Microstrip line layer change via two. DETAILED DESCRIPTION

[0032] Reference Figure 1-8 A microstrip combiner proposed in the present invention comprises a first microstrip line, a second microstrip line and a dielectric substrate, the first microstrip line and the second microstrip line are arranged in parallel in the Z-axis direction, the first microstrip line is located in the upper layer of the dielectric substrate, the second microstrip line is located in the lower layer of the dielectric substrate, the first microstrip line and the second microstrip line realize energy transmission in the Z-axis direction through broadside coupling, the phase difference between the input port port2 of the first microstrip line and the input port port3 of the second microstrip line is 90°, and the output port port4 of the first microstrip line is connected to the load.

[0033] In this embodiment, the bandwidth of the microstrip combiner at the center frequency is ±5% of the center frequency 13.56MHz (i.e., 12.89-14.23MHz), which meets the current working bandwidth adaptation requirements of RF power synthesis. The output port port4 of the first microstrip line is connected to a 50Ω load resistor. The return loss RL of the microstrip combiner is ≥20dB; the dielectric substrate adopts a water-cooled plate structure, and the water-cooled channel is embedded in the substrate, and the heat dissipation efficiency is ≥50W / cm 2 .

[0034] In this embodiment, the microstrip line switching layers are connected through vias, the via diameter is 0.3-0.6 mm, the copper thickness of the hole wall is ≥25 μm, and the via spacing is 1.5-2 times the line width.

[0035] In this embodiment, the reflection coefficients of the input / output ports of the first microstrip line and the second microstrip line are both ≤-20 dB, and the insertion losses of the input ports of the first microstrip line and the second microstrip line are both ≤-3.2 dB.

[0036] In this embodiment, the coupling coefficient C between the first microstrip line and the second microstrip line satisfies:

[0037]

[0038] Among them, Z Ce is the even-mode impedance; Z Co is odd mode impedance.

[0039] Specifically, the impedance of the microstrip line is 50-60Ω.

[0040] In this embodiment, the line width W of the first microstrip line and the second microstrip line ranges from 1 to 5 mm, and the line length difference ΔL between the first microstrip line and the second microstrip line is calculated according to the following formula:

[0041]

[0042] Where c is the speed of light, f = 13.56MHz, ΔL is the difference in length between the first microstrip line and the second microstrip line, and its value is 10-15mm; εr is the relative dielectric constant of the dielectric substrate.

[0043] In this embodiment, an island copper ground is arranged around the first microstrip line and the second microstrip line. The width of the island copper ground is 2-3 times the width of the first microstrip line or the second microstrip line. The island copper ground is connected to the bottom reference plane of the microstrip combiner through a through-hole array with a diameter of 0.2-0.5 mm; coupling capacitors and filter capacitors are welded on the island copper ground.

[0044] Specifically, the coupling capacitor is mainly used to compensate and adjust the coupling degree between the two coupled microstrip lines, and the filter capacitor is used to adjust the reflection coefficient of the input and output ports.

[0045] In this embodiment, the coupling capacitance is calculated by the following formula:

[0046] C M =C·C O ;

[0047]

[0048] Wherein, W is the line width of the first microstrip line and the second microstrip line; H is the thickness of the dielectric substrate; C is the coupling coefficient between the first microstrip line and the second microstrip line; ε r is the relative dielectric constant of the dielectric substrate; T is the copper foil thickness of the microstrip line; C O C is the distributed capacitance per unit length of the microstrip line, with a value of 0.5-1.5pF / in; M is the coupling capacitor.

[0049] Specifically, the value range of the coupling capacitor is 0.5-2 pF, and the value range of the filter capacitor is 10-100 pF.

[0050] In this embodiment, a metal shielding cover is disposed outside the microstrip combiner, and the metal shielding cover is welded to the isolated copper ground or connected to the isolated copper ground through a conductive adhesive.

[0051] Specifically, the shielding cover is filled with thermal conductive silicone grease, and the thermal conductivity is ≥3W / (m·K).

[0052] In this embodiment, the material of the dielectric substrate is FR4 or Rogers 4350B, and the relative dielectric constant ε of the dielectric substrate is r The value range of is 3.5-5, and the value range of the thickness H of the dielectric substrate is 1-2 mm.

[0053] In this embodiment, the distance D between the first microstrip line and the second microstrip line in the broadside coupling corresponding area ranges from 0.1 to 0.3 mm, and the length of the coupling area Wherein, λ is the wavelength corresponding to 13.56 MHz.

[0054] In this embodiment, the ends of the first microstrip line and the second microstrip line adopt a gradient line structure with a gradient angle of 30°-60° for impedance matching and reflection suppression.

[0055] In this embodiment, the phase difference ΔΦ between the two microstrip lines is controlled by the following formula:

[0056]

[0057] Where K is the phase slope, and K is calculated by the odd-mode and even-mode impedance parameters to satisfy the following formula:

[0058]

[0059] Where ε is the ripple factor, α is related to the return loss RL, and θ is related to the electrical length at the cutoff frequency. c The relationship is as follows:

[0060] And the formula We can get the normalized (z a , z b ) and then obtain the odd and even analog impedance value of the circuit structure (z Ce , z Co ), ε and α can be measured based on actual data, and K is obtained by the formula Calculated.

[0061] In this embodiment, the power capacity of the microstrip combiner is ≥1kW, and the operating temperature range is -40°C to +125°C, which is suitable for industrial RF heating and communication base station systems.

[0062] In this embodiment, the coupling inductance between the first microstrip line and the second microstrip line is C*L; the inductance L of the microstrip line is calculated by the following empirical formula:

[0063]

[0064] Where N is the number of turns of the coil, h is the coil height (0.5-2cm), L ar =a+b (a and b are the length and width of the rectangular coil, ranging from 1-5 cm), d is the thickness of the coil (d≈N·W).

[0065] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A microstrip combiner, characterized in that: The invention comprises a first microstrip line, a second microstrip line and a dielectric substrate, wherein the first microstrip line and the second microstrip line are arranged in parallel in the Z-axis direction, the first microstrip line is located in the upper layer of the dielectric substrate, and the second microstrip line is located in the lower layer of the dielectric substrate, the first microstrip line and the second microstrip line realize energy transmission in the Z-axis direction through broadside coupling, the phase difference between the input port port2 of the first microstrip line and the input port port3 of the second microstrip line is 90°, and the output port port4 of the first microstrip line is connected to the load.

2. The microstrip combiner according to claim 1, characterized in that: The reflection coefficients of the input / output ports of the first microstrip line and the second microstrip line are both ≤-20 dB, and the insertion losses of the input ports of the first microstrip line and the second microstrip line are both ≤-3.2 dB.

3. The microstrip combiner according to claim 1, characterized in that: The coupling coefficient C between the first microstrip line and the second microstrip line satisfies: Among them, Z Ce is the even-mode impedance; Z Co is odd mode impedance.

4. The microstrip combiner according to claim 3, characterized in that: The line width W of the first microstrip line and the second microstrip line ranges from 1 to 5 mm, and the line length difference ΔL between the first microstrip line and the second microstrip line is calculated according to the following formula: Where c is the speed of light, f = 13.56MHz, ΔL is the difference in length between the first microstrip line and the second microstrip line, and its value is 10-15mm; ε r is the relative dielectric constant of the dielectric substrate.

5. The microstrip combiner according to claim 3, characterized in that: An island copper ground is arranged around the first microstrip line and the second microstrip line. The width of the island copper ground is 2-3 times the width of the first microstrip line or the second microstrip line. The island copper ground is connected to the bottom reference plane of the microstrip combiner through a through-hole array with a diameter of 0.2-0.5 mm; coupling capacitors and filter capacitors are welded on the island copper ground.

6. The microstrip combiner according to claim 5, characterized in that: The coupling capacitance is calculated by the following formula: C M =C·C O ; Wherein, W is the line width of the first microstrip line and the second microstrip line; H is the thickness of the dielectric substrate; C is the coupling coefficient between the first microstrip line and the second microstrip line; ε r is the relative dielectric constant of the dielectric substrate; T is the copper foil thickness of the microstrip line; C O C is the distributed capacitance per unit length of the microstrip line, with a value of 0.5-1.5pF / in; M is the coupling capacitor.

7. The microstrip combiner according to claim 5, characterized in that: A metal shielding cover is arranged outside the microstrip combiner, and the metal shielding cover is welded to the isolated copper ground or connected to the isolated copper ground through a conductive adhesive.

8. The microstrip combiner according to claim 6, characterized in that: The material of the dielectric substrate is FR4 or Rogers 4350B, and the relative dielectric constant ε of the dielectric substrate is r The value range of is 3.5-5, and the value range of the thickness H of the dielectric substrate is 1-2 mm.

9. The microstrip combiner according to claim 1, characterized in that: The distance D between the first microstrip line and the second microstrip line in the broadside coupling corresponding area is in the range of 0.1-0.3 mm. Wherein, λ is the wavelength corresponding to 13.56 MHz.

10. The microstrip combiner according to claim 1, characterized in that: The ends of the first microstrip line and the second microstrip line adopt a gradient line structure with a gradient angle of 30°-60° for impedance matching and reflection suppression.

Citation Information

Patent Citations

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