Pulse power suppression circuit suitable for wide pulse load frequency range
By integrating multiple pulse power suppression topology within a wide pulse load frequency range and switching topology according to the frequency band, the problems of low system power density, low efficiency or system instability in the prior art are solved, and stable power supply of load voltage and optimization of system efficiency and power density are achieved.
Patent Information
- Application Number
- CN202510107182.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2025-05-06
AI Technical Summary
Existing pulse power suppression topology has problems with low system power density, low efficiency, or system instability over a wide pulse load frequency range, and using different topology in different frequency bands will increase the complexity of the power supply architecture.
A new pulse power suppression circuit integrating multiple pulse power suppression topology was designed. By dividing low, medium and high frequency bands and switching topologies according to the frequency band, a fixed number of power converters are shared to achieve high integration of topology and optimization of efficiency and power density.
Ensure the stability of the load voltage within a wide pulse load frequency range, provide stable power supply, and keep the load voltage basically unchanged when switching between different frequency bands, with a maximum fluctuation of only 0.7V, achieving optimization of system efficiency and power density.
Smart Images
Figure CN119945097A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of electronic circuits, and in particular relates to a pulse power suppression circuit suitable for a wide pulse load frequency range. Background Art
[0002] Pulse load operating characteristics such as Figure 1 As shown, where f p is the pulse load frequency, the power required by the pulse load will be D p is the duty cycle, at P max With P min The power supply system architecture with pulse loads is as follows: Figure 2 As shown in the figure, the high peak-to-average ratio pulse power characteristics of the pulse load will cause the input voltage, current and bus voltage to fluctuate greatly, which will have a negative impact on the normal operation of the power supply system and other loads, and endanger their stable and safe operation.
[0003] Pulse power can be decomposed into two parts: constant average power and pulsating power. The pulsating component of pulse power can be transferred through pulse power suppression technology to balance the input constant power and pulse power. Existing pulse power suppression technologies mainly include passive suppression technology and active suppression technology.
[0004] Passive suppression is achieved by connecting passive capacitors in parallel across the pulse load. The topology is as follows: Figure 3 As shown, the converter I transmits a constant average power and the capacitor C s Passively bear the pulsating power. Capacitor C in the passive capacitor pulse power suppression topology s The allowed voltage fluctuation range is smaller, but the pulse power only undergoes one level of power conversion.
[0005] Active suppression technology adds a power converter to the passive energy storage element, and actively transfers the pulsating power through the power converter, including parallel type and cascade type. The parallel type pulse power suppression topology and its power flow path are as follows: Figure 4 As shown, the converter I transmits a constant average power and the capacitor C s The pulsating power is compensated by converter II. The cascade type pulse power suppression topology and its power flow path are as follows: Figure 5 As shown, C s It absorbs the constant average power transmitted by converter I and releases the pulse power backward through converter II. The power change in one pulse cycle is equal to the pulsating power component. Parallel and cascade pulse power suppression topology capacitor C s The voltage can be allowed to fluctuate within a larger range. The pulsating component of the pulse power needs to undergo three-stage power conversion in the parallel topology, while the entire pulse power only needs to undergo two-stage power conversion in the cascade topology.
[0006] In the pulse power suppression topology, the lower the pulse load frequency, the lower the decoupling capacitor voltage C s The larger the voltage fluctuation range, the more energy the power converter needs to process. At the same time, the fewer power conversion levels the pulse power passes through, the higher the efficiency of the system; the decoupling capacitor C s The larger the allowed voltage fluctuation range, the lower the demand for capacitor capacity and the higher the system power density. Therefore, the passive capacitor pulse power suppression topology has a large demand for capacitor capacity, resulting in low system power density, but the system efficiency is very high. The parallel pulse power suppression topology has low efficiency, but low demand for capacitor capacity and high system power density. In the cascade pulse power suppression topology, since the widely fluctuating decoupling capacitor voltage is the output of converter I, it brings challenges to the topology and control design of converter I, which may affect the stable operation of the input side and cause input voltage and current fluctuations. Therefore, it is necessary to limit the decoupling capacitor C. s Due to the voltage fluctuation range, the capacitor capacity requirement increases, resulting in a decrease in the power density of the system; but it only requires two stages of power conversion, and the system efficiency is relatively high.
[0007] In summary, the existing pulse power suppression topologies have advantages and disadvantages within the wide pulse load frequency range, as shown in Table 1, and therefore are limited to work within a certain fixed pulse load frequency range. If the existing pulse power suppression topologies are directly applied to the wide pulse load frequency range, it may cause a series of problems such as low system power density, low efficiency, or system instability; if different pulse power suppression topologies are directly used in different frequency bands, it may result in a large number of power supply architectures, and the system power density will also be affected. Therefore, it is necessary to design a new type of pulse power suppression topology that can integrate multiple pulse power suppression topologies, share a fixed number of power converters, and use a frequency band switching topology to achieve stable operation of the system within the wide pulse load frequency range, while optimizing system efficiency and power density.
[0008] Table 1 Comparison of pulse power suppression topology efficiency and power density
[0009] Pulse Power Suppression Topology Power density efficiency Passive capacitors Low high Parallel type high Low Cascade Type middle middle Summary of the invention
[0010] The present invention aims to provide stable power supply to pulse loads within a wide pulse load frequency range and optimize efficiency and power density, and proposes a new type of pulse power suppression circuit suitable for a wide pulse load frequency range. The present invention integrates multiple pulse power suppression topologies, divides the wide pulse load frequency range into low, medium and high frequency bands, selects the optimal topology according to the frequency band by switching switches, and each topology shares a power converter, ensuring load voltage stability within a wide pulse load frequency range while optimizing efficiency and power density, thereby achieving high integration of pulse power suppression topologies.
[0011] The technical solution of the present invention is:
[0012] A pulse power suppression circuit suitable for a wide pulse load frequency range includes a dual-output phase-shifted full-bridge converter, a bidirectional Buck / Boost converter, a switching switch, a decoupling capacitor and an output capacitor;
[0013] The dual-output phase-shifted full-bridge converter includes a full-bridge circuit and a first output circuit and a second output circuit. The input of the full-bridge circuit is connected to an external input voltage. The output of the full-bridge circuit is coupled to two output circuits through upper and lower windings of a transformer, respectively. The first output circuit is composed of a first diode, a second diode, a third diode, a fourth diode, and a first inductor. The anode of the first diode and the cathode of the second diode are connected to the same-name end of the secondary side of the transformer. The anode of the third diode and the cathode of the fourth diode are connected to the opposite-name end of the secondary side of the transformer. The cathode of the first diode and the cathode of the third diode are connected to one end of the first inductor. The other end of the first inductor is connected to the The second output circuit is composed of a fifth diode, a sixth diode, a seventh diode, an eighth diode, and a second inductor. The anode of the fifth diode and the cathode of the sixth diode are connected to the same-name end of the secondary side of the transformer. The anode of the seventh diode and the cathode of the eighth diode are connected to the opposite-name end of the secondary side of the transformer. The cathode of the fifth diode and the cathode of the seventh diode are connected to one end of the second inductor. The other end of the second inductor is connected to one end of the output capacitor and the positive end of the pulse load. The anode of the second diode, the anode of the fourth diode, the anode of the sixth diode, and the anode of the eighth diode are connected to the other end of the output capacitor and the negative end of the pulse load.
[0014] The bidirectional Buck / Boost converter is composed of a first switch, a second switch, and a third inductor. One end of the first switch is connected to the other end of the switching switch and one end of the decoupling capacitor, the other end of the first switch is connected to one end of the second switch and one end of the third inductor, and the other end of the third inductor is connected to one end of the output capacitor; the other end of the decoupling capacitor and the other end of the second switch are connected to the other end of the output capacitor.
[0015] According to the set standard, the pulse load is divided into three frequency bands: low, medium and high. The corresponding control methods are:
[0016] Low frequency band: disconnect the switching switch, the bidirectional Buck / Boost converter works normally, and the dual-output phase-shifted full-bridge converter outputs only through the second output circuit;
[0017] Mid-frequency band: Close the switch, the bidirectional Buck / Boost converter works normally, and the dual-output phase-shifted full-bridge converter outputs through the first output circuit and the second output circuit at the same time;
[0018] High frequency band: the switching switch is turned off, the bidirectional Buck / Boost converter is turned off, and the dual-output phase-shifted full-bridge converter outputs only through the second output circuit.
[0019] The beneficial effects of the present invention are: it can ensure the stability of the load voltage within a wide pulse load frequency range and provide stable power supply to the pulse load; at the same time, when the pulse load frequency is switched between different frequency bands, topology switching can be achieved and the load voltage can still be kept basically unchanged. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is a schematic diagram of pulse load working characteristics.
[0021] Figure 2 It is a schematic diagram of the power supply system architecture containing pulse loads.
[0022] Figure 3 It is the topology diagram of passive capacitor pulse power suppression.
[0023] Figure 4 It is a parallel pulse power suppression topology diagram.
[0024] Figure 5 It is a cascade type pulse power suppression topology diagram.
[0025] Figure 6 It is a new type of pulse power suppression circuit suitable for a wide pulse load frequency range.
[0026] Figure 7 The following are the circuit diagrams of each frequency band, where (a) is the low frequency band circuit, (b) is the medium frequency band circuit, and (c) is the high frequency band circuit.
[0027] Figure 8 : The pulse power suppression topology diagrams of each frequency band, where (a) is the low frequency band topology, (b) is the middle frequency band topology, and (c) is the high frequency band topology.
[0028] Fig. 9 This is the converter control block diagram.
[0029] Fig.10 It is switch S a The control flow diagram of .
[0030] Fig.11 It is a schematic diagram of simulation results, where (a) is 5-500Hz switching, (b) is 500-5Hz switching, (c) is 500-1500Hz switching, (d) is 1500-500Hz switching, (e) is 5-1500Hz switching, and (f) is 1500-5Hz switching. DETAILED DESCRIPTION
[0031] The technical solution of the present invention is described in detail below with reference to the accompanying drawings.
[0032] The pulse power suppression circuit proposed by the present invention is as follows: Figure 6 As shown. It contains two power converters, converter I is a dual-output phase-shifted full-bridge converter, and converter II is a bidirectional Buck / Boost converter; the decoupling capacitor C s and output capacitor C o ; Switch S a Implement topology switching.
[0033] Each frequency band circuit is as follows Figure 7 As shown in the figure, the pulse power suppression topology and power flow path of each frequency band are as follows Figure 8 As shown. In the low frequency band, switch S a Disconnect and switch to the parallel pulse power suppression topology, the circuit is as follows Figure 7 As shown, the simplified topology and power flow path are as follows Figure 8 As shown in the figure. Since the lower the pulse load frequency, the higher the decoupling capacitor capacity requirement, the required decoupling capacitor capacity needs to be calculated at the lowest frequency. At the same time, the parallel topology requires the smallest capacitor capacity compared to other topologies, which can ensure the optimal capacitor capacity and optimize the system power density.
[0034] Mid-band switch S a Close and switch to the cascade type pulse power suppression topology. The circuit is as follows Figure 7 As shown, the simplified topology and power flow path are as follows Figure 8 As shown. At this time, both converter I and converter II only need unidirectional power conversion, and the difference from the traditional cascade pulse power suppression topology is that the average power of the pulse load is further decomposed, and the steady-state power component of the pulse power output by the lower winding is directly given to the load, and the upper winding outputs the remaining power, which can further improve the system efficiency. Since the cascade pulse power suppression topology requires a larger capacitor capacity but a higher efficiency, when the pulse load frequency is in the mid-frequency band, the designed capacitor capacity can already meet the needs of the cascade topology, which can make the switch S a The conduction forms a cascaded pulse power suppression topology to optimize system efficiency.
[0035] High frequency switch S a Disconnect, and converter II does not work, switch to the passive capacitor pulse power suppression topology, the circuit is as follows Figure 7 As shown, the simplified topology and power flow path are as follows Figure 8 As shown. The passive capacitor pulse power suppression topology has the highest efficiency but requires the largest capacitance. Therefore, when the pulse load frequency is in the high frequency band, the output capacitor C o The capacity can meet the requirements of passive capacitor pulse power suppression topology, and can be switched to passive capacitor pulse power suppression topology to further improve system efficiency.
[0036] The control involved in this circuit mainly includes three aspects: the control of the dual-output phase-shifted full-bridge converter, the control of the bidirectional Buck / Boost converter, and the control of the switch S a In the original pulse power suppression topology, the output voltage v is controlled by converter I in the parallel topology. o , Converter II controls the decoupling capacitor voltage v Cs ; The cascade topology is controlled by converter I to control the decoupling capacitor voltage v Cs , converter II controls the output voltage v o In order to simplify the control and unify the control variables, the output voltage v is used for the dual output phase-shifted full-bridge converter. o Single closed-loop control, bidirectional Buck / Boost converter using decoupling capacitor voltage v Cs Inductor current i Lb Double closed-loop control, its control block diagram is as follows Fig. 9 As shown. Switch S a The control is only related to the pulse load frequency, and the frequency band is identified. The shutdown or conduction is determined according to the frequency band. The control flow chart is as follows Fig.10 shown.
[0037] Based on the proposed pulse power suppression circuit and its control suitable for a wide pulse load frequency range, verification is carried out in the Matlab / Simulink simulation platform, and the simulation parameters are shown in Table 1. Based on this simulation parameter, the frequency bands are divided: low frequency band 1-15Hz, medium frequency band 15-1000Hz, and high frequency band 1000-5000Hz.
[0038] Table 1 Simulation parameters
[0039]
[0040] The simulation verification was carried out in the pulse load frequency range of 1-5000Hz, and 5, 500, and 1500Hz were taken for testing, and the three frequencies were switched among each other. The simulation results are as follows Fig.11 As shown, the load voltage V is respectively the same under 6 frequency band switching conditions. o 、Load current I o , inductor current I Lb , decoupling capacitor voltage V Cs Waveform.
[0041] From the simulation results, it can be seen that the circuit and control suitable for a wide pulse load frequency range proposed in the present invention can ensure the stability of the load voltage within the wide pulse load frequency range and provide a stable power supply for the pulse load; at the same time, when the pulse load frequency is switched between different frequency bands, the topology switching can be realized, and the load voltage can still be kept basically unchanged, and the maximum fluctuation of the load voltage is only 0.7V. Lb The value of can determine the type of pulse power suppression topology. The pulse power suppression topology in the low frequency band is parallel type, in the medium frequency band it is cascade type, and in the high frequency band it is passive capacitor. Therefore, the proposed circuit can realize the sharing of converters within a wide pulse load frequency range, integrate multiple pulse power suppression topologies, realize topology switching, optimize efficiency and power density within a wide pulse load frequency range, and realize high integration of pulse power suppression topologies.
Claims
1. A pulse power suppression circuit suitable for a wide pulse load frequency range, characterized in that: It includes a dual-output phase-shifted full-bridge converter, a bidirectional Buck / Boost converter, a switching switch, a decoupling capacitor and an output capacitor; The dual-output phase-shifted full-bridge converter includes a full-bridge circuit and a first output circuit and a second output circuit. The input of the full-bridge circuit is connected to an external input voltage. The output of the full-bridge circuit is coupled to two output circuits through upper and lower windings of a transformer, respectively. The first output circuit is composed of a first diode, a second diode, a third diode, a fourth diode, and a first inductor. The anode of the first diode and the cathode of the second diode are connected to the same-name end of the secondary side of the transformer. The anode of the third diode and the cathode of the fourth diode are connected to the opposite-name end of the secondary side of the transformer. The cathode of the first diode and the cathode of the third diode are connected to one end of the first inductor. The other end of the first inductor is connected to the The second output circuit is composed of a fifth diode, a sixth diode, a seventh diode, an eighth diode, and a second inductor. The anode of the fifth diode and the cathode of the sixth diode are connected to the same-name end of the secondary side of the transformer. The anode of the seventh diode and the cathode of the eighth diode are connected to the opposite-name end of the secondary side of the transformer. The cathode of the fifth diode and the cathode of the seventh diode are connected to one end of the second inductor. The other end of the second inductor is connected to one end of the output capacitor and the positive end of the pulse load. The anode of the second diode, the anode of the fourth diode, the anode of the sixth diode, and the anode of the eighth diode are connected to the other end of the output capacitor and the negative end of the pulse load. The bidirectional Buck / Boost converter is composed of a first switch, a second switch, and a third inductor. One end of the first switch is connected to the other end of the switching switch and one end of the decoupling capacitor, the other end of the first switch is connected to one end of the second switch and one end of the third inductor, and the other end of the third inductor is connected to one end of the output capacitor; the other end of the decoupling capacitor and the other end of the second switch are connected to the other end of the output capacitor.
2. A pulse power suppression circuit suitable for a wide pulse load frequency range according to claim 1, characterized in that: According to the set standard, the pulse load is divided into three frequency bands: low, medium and high. The corresponding control methods are: Low frequency band: disconnect the switching switch, the bidirectional Buck / Boost converter works normally, and the dual-output phase-shifted full-bridge converter outputs only through the second output circuit; Mid-frequency band: Close the switch, the bidirectional Buck / Boost converter works normally, and the dual-output phase-shifted full-bridge converter outputs through the first output circuit and the second output circuit at the same time; High frequency band: the switching switch is turned off, the bidirectional Buck / Boost converter is turned off, and the dual-output phase-shifted full-bridge converter outputs only through the second output circuit.