A three-phase analog pulse load with high precision and high dynamic response

Abstract

The present invention relates to a three-phase analog pulse load with high precision and high dynamic response. The three-phase power supply is rectified into direct current by a three-phase uncontrolled rectifier bridge. A spike voltage absorption circuit, a total of n + 1 load branches from 0 to n, are connected in parallel between the positive and negative buses of the DC circuit. Each load branch includes a high-speed power switch device in series with a resistor, and each resistor is in parallel with a freewheeling diode. Among them, the capacity of each load branch is defined as the ratio of the square of the DC bus voltage to the resistance value of the load resistor. The capacity of load branch 0 is designed as the minimum adjustment capacity P0 of the system. The rated power capacity of each of the load branches from 0 to n - 1 is designed according to a geometric progression with a common ratio of 2, and the designed capacity Pn of the nth load is taken as (1 + r%)Q N -2 n P0, where the rated capacity requirement of the system is Q N , and the margin is r%. The present invention is used to meet the test requirements of pulse loads for three-phase AC power supplies or power generation sets.

Description

Technical Field

[0001] The present invention relates to the field of electrical testing, and particularly to a three-phase analog pulse load electrical structure with high precision and high dynamic response and an implementation method thereof. Background Art

[0002] In new military equipment, such as phased array radars, high-energy microwave weapons, etc., their load characteristics are in the form of continuous pulses. We call such electrical loads pulse loads, and pulse loads pose relatively high requirements on the power supply. During the R & D and production test process of the power supply, an analog pulse load is required to replace the pulse load electrical equipment in actual applications to conduct various working condition tests to check whether the power supply can operate normally under the condition of carrying a pulse load and whether it affects the required pulse power output.

[0003] The paper "An Analog Device for Nonlinear Pulse Characteristics of Modern Radars" published in the journal Modern Radar in March 2016 introduced the implementation principle of a continuous pulse simulation device. It simplifies the complex radar system into a rectifier module, a DC switch module, and a load module. It uses insulated gate bipolar transistors (IGBTs) to control the switching of multiple groups of resistive loads to simulate the power mutation of the pulse load. Different switching cycles and duty ratios are achieved by setting the trigger pulses of the DC switches, and different peak powers of the pulse load are also achieved by changing the number of resistor groups connected to the circuit. It uses a three-phase rectifier bridge based on thyristor devices to rectify three-phase alternating current into direct current, and then obtains a DC voltage with less ripple through LC filtering to provide a constant DC voltage for each resistor branch controlled by a relay. Although the proposed circuit structure and control method can simulate the pulse load to a certain extent, due to the slow voltage regulation response speed of the thyristor rectifier and the adoption of LC filtering devices, it is impossible to simulate and implement a pulse load with a pulse step response time requirement as small as 0.1 ms level. Moreover, it is difficult to accurately control and ensure the amplitude of the input current on the AC side. That is to say, the technical solution described in the paper is difficult to meet the requirements of high precision and high dynamic response.

[0004] Figure 1It is the basic shape of the input AC current peak curve during pulse load application. The load is powered by a three-phase AC power supply with a rated line voltage Un (such as 200V) and a rated frequency f (such as 400Hz). Among them, t1, t2, t3, t4, t5, t6, t7, t8 are the pulse time widths (which can be arbitrarily set from a few millimeters to dozens of millimeters), and i1, i2, i3, i4, i5, i6 are the corresponding pulse amplitudes, that is, the three-phase AC current peaks. These parameters can be arbitrarily set from 0 to the maximum value (such as 600A). The pulse load adjustment step size requirement can be as small as 0.1kVA, and the pulse step response time is as short as 0.1ms. In order to simulate and implement such a pulse load current peak curve, this paper proposes a main circuit architecture and implementation method for a three-phase simulated pulse load with high precision and high dynamic response. Summary of the Invention

[0005] The object of the present invention is to propose a main circuit scheme and control implementation principle for a simulated pulse load with high dynamic response, high control accuracy, and an arbitrarily programmable amplitude curve to meet the test requirements of pulse loads for three-phase AC power supplies or power generation generators.

[0006] To achieve the above object, a three-phase simulated pulse load with high precision and high dynamic response is provided, including a three-phase power supply, a three-phase uncontrolled rectifier bridge, a spike voltage absorption circuit, and a total of n + 1 load branches from 0 to n;

[0007] The three-phase power supply is rectified into DC by the three-phase uncontrolled rectifier bridge, and the spike voltage absorption circuit is connected in parallel between the positive and negative busbars of the DC circuit to absorb current. The spike voltage absorption circuit has a series resistor Rd and capacitor C;

[0008] Each of the load branches is connected in parallel between the positive and negative busbars of the DC circuit. Each load branch includes a high-speed power switch device in series with a resistor, and each resistor is connected in parallel with a freewheeling diode. Among them, the capacity of each load branch is defined as the square of the DC bus voltage divided by the resistance value of the load resistor. The capacity of load branch 0 is designed as the minimum adjustment capacity P0 of the system. The rated power capacities of load branches 0 to n - 1 are designed according to a geometric progression with a common ratio of 2, and the designed capacity Pn of the nth load is taken as (1 + r%)Q N -2 n P0, where the system rated capacity requirement is Q N , and the margin is r%.

[0009] Furthermore, the heat dissipation design of the high-speed power switch device only needs to consider the conduction loss and does not need to consider the switching loss.

[0010] Further, when the system current exceeds 50 A, the high-speed power switching device uses an IGBT to control the on / off of the resistance current of this branch, and / or when the system current is lower than 50 A, the high-speed power switching device uses a MOSFET.

[0011] Further, the parameter configuration of the spike voltage absorption circuit is such that when all load branches conduct simultaneously to the moment of simultaneous turn-off, the energy stored in the line inductance in the front section of the three-phase rectifier and the DC side bus inductance is released to the capacitor C, and the steady-state and transient voltages across the RC cannot exceed the safe operating voltage of each power switching device.

[0012] Further, a real-time input value i_peak_ref of the given AC current peak pulse curve is input, and the difference between it and the peak value of the capacitor current of the spike voltage absorption circuit is multiplied by the peak value of the line voltage on the three-phase AC side to obtain the real-time load power control command P * ;

[0013] Calculate the effective value of the three-phase input AC voltage U abrms and the square of the ratio of the rated voltage U n to obtain the adaptive adjustment coefficient m (i.e., m = (U abrms / U n ) 2 );

[0014] Multiply the adaptive adjustment coefficient m by the designed minimum adjustment capacity P0 parameter to obtain the actual minimum adjustment capacity at the current input AC voltage Similarly, the actual capacity of the nth load branch is obtained by multiplying the designed Pn by the coefficient m and adjusting it according to the three-phase AC input voltage

[0015] According to P * , and to calculate the control bits of the high-speed power switching devices of each load branch.

[0016] Further, the calculation of the control bits of the high-speed power switching devices of each load branch according to P * , and further includes:

[0017] If P * < P n t , b n is set to 0, and let W = P *

[0018] If P * ≥ P n t , bn Set 1 and let W = P * -P n t ;

[0019] Take the ratio of W to After rounding, convert it into a binary number to obtain the binary number b n-1 b n-2 …b2b1b0;

[0020] The 0th bit b0 corresponds to the control of the load branch 0. If it is 1, turn on the high-speed power switch device T0 of this load branch; if it is 0, turn off the switch device T0. For the other bits from the 1st bit b1 to the (n - 1)th bit b n-1 And b n Correspond to the switch devices T1 to Tn in turn and adopt the same switching control strategy.

[0021] Furthermore, it also includes an auxiliary branch. The auxiliary branch is connected in parallel between the positive and negative buses of the DC circuit. The auxiliary branch is configured to connect an inductor in series with a resistor under the framework of the load branch to smooth the resistive current of the high-speed power switch device Th in the auxiliary branch under PWM control. The freewheeling diode in the auxiliary branch is connected in parallel with the branch of the resistor in series with the inductor.

[0022] Furthermore, detect and sample the three-phase input currents ia and ib to calculate the three-phase current peak values. Subtract the difference between the detected value of the resistive current in the auxiliary branch from the difference between the given three-phase AC current peak pulse curve value and the actually detected and calculated three-phase current peak values as the input of the control regulator. Its output passes through a limiter to obtain a modulation wave, and the PWM pulse obtained by comparing it with a triangular carrier wave is used to control the on-off of the high-speed power switch device Th in the auxiliary branch.

[0023] Adopting the patent solution of the present invention, the main circuit structure is simple, the control of the system is relatively simple to implement, the dynamic response of the pulsed load current is very fast. Using conventional high-speed power switch devices, even if the on-off time of the switch device is less than 50 μs, the dynamic response time can still be achieved below 0.1 ms. Because an adaptive adjustment coefficient related to the AC voltage amplitude fluctuation is introduced, and an auxiliary branch is introduced for steady-state error compensation, the system can achieve high-precision target tracking control while meeting high dynamic response. Brief Description of the Drawings

[0024] Figure 1 Shows the waveform of the AC current peak value output by the power supply under pulsed load.

[0025] Figure 2 Shows the main circuit structure of the analog pulsed load of the present invention.

[0026] Figure 3Shows the control strategy of the high-speed switching transistors T0 to Tn of the present invention.

[0027] Figure 4 Shows the input current peak error compensation control of the present invention.

[0028] Figure 5 Shows the simulation waveform of the analog pulse load of the present invention.

[0029] Figure 6 Shows the partial enlarged view of the simulation waveform of the analog pulse load of the present invention. Detailed implementation manners

[0030] The technical solution of the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0031] 1) Main circuit architecture

[0032] Figure 2 Is the schematic diagram of the main circuit of the proposed analog pulse load. Among them, the three-phase power supply is rectified into direct current by a three-phase uncontrolled rectifier bridge. A spike voltage absorption circuit is connected in parallel between the positive and negative busbars of the DC circuit to absorb current. There are a total of n + 1 load branches from 0 to n and an auxiliary branch. Each load branch is connected in parallel between the positive and negative busbars of the DC circuit. Each load branch consists of a high-speed power switching device in series with a resistor, and each resistor is connected in parallel with a freewheeling diode. T0 to Tn and Th are high-speed power switching devices (such as IGBTs, etc., whose turn-on and turn-off times are both less than 10 us), and D0 to Dn and Dh are freewheeling diodes.

[0033] There is also a small-capacity auxiliary branch, which is connected in parallel between the positive and negative busbars of the DC circuit and is used for the current pulse steady-state error tracking compensation control in some possible special cases. It is a small inductor connected in series with a resistor under the architecture of the load branch to smooth the resistor current of Th under PWM control. The current of this resistor is detected and sampled for the need of current closed-loop control. The freewheeling diode in the auxiliary branch is connected in parallel with the branch of the resistor in series with the inductor, as Figure 2 shown.

[0034] In order to meet the high dynamic response requirements of the pulse load and reduce the system cost, the small current load branch can use MOSFET transistors to control the on and off of the resistor current of this branch, and the large current switching device exceeding 50A can use IGBT to control the on and off of the resistor current of this branch. These high-speed power switching transistors T0 to Tn are controlled by the drive pulses issued by the control system, and using the control strategy mentioned later, it is basically possible to turn on only at the pulse rising edge and turn off only at the falling edge in the load current curve. Since the pulse frequency of the load current peak curve is generally from a few hertz to dozens of hertz, therefore, the heat dissipation design of these power switching transistors only needs to consider the conduction loss and does not need to consider the switching loss.

[0035] The peak voltage absorption circuit consists of a series-connected resistor Rd and a capacitor C. The parameter design principle is that when all load branches are turned on and off simultaneously, the steady-state and transient voltages across RC caused by the energy storage release of the line inductance in the front section of the three-phase rectifier and the DC-side bus inductance to the capacitor C should not exceed the safe operating voltage of each power switch tube. Since there is a ripple voltage in the three-phase rectifier output to the DC side, the introduction of Rd can reduce the current flowing through the capacitor branch, thereby reducing the impact of the capacitor branch current on the precision control of the AC input-side pulse current.

[0036] The three-phase input voltage and the current flowing through the capacitor C are sampled and detected in real time at high speed, and are used for the adaptive control link of the precision of the AC input-side pulse current.

[0037] Due to the need for current tracking control, the three-phase input voltages u ab 、u bc and the currents i a and i b are continuously detected and sampled in real time and sent to the control section.

[0038] 2) Design method for the capacity of each load branch

[0039] The on and off of each resistor load is realized by controlling the on and off of the high-speed power switch device. The rated power capacity design of the 0 to n-1 paths of each load branch is designed according to a geometric progression with a common ratio of 2. The capacity of each load branch is defined as the square of the DC bus voltage divided by the resistance value of the load. For example, the resistance value of the load branch 0 is R0, and the DC-side bus voltage connected is U d , which is taken as the peak value of the three-phase rated voltage Un. Then the load capacity of this load branch is U d 2 / R0. The capacity of the load branch 0 is designed as the minimum adjustment capacity of the system, denoted as P0. Then for the other load branches from the 1st to the n-1th, the designed capacity of the Kth load branch is 2 K ×P0. As for the designed capacity of the nth load, it depends on the rated capacity and design margin of the system device. Assuming that the system rated capacity requirement is Q N , and the margin is r%, then Pn can be taken as (1 + r%)Q N -2 n P0.

[0040] 3) Control strategy

[0041] 3.1 Control of switches T0 to T1

[0042] Based on the design method of the main circuit architecture and the capacity of each load branch mentioned above, in order to achieve high-precision control of the input current of the analog pulse load device for a given pulse waveform, the following control strategy is proposed for the high-speed power switching tubes of each load branch. This control is completed by a digital processing chip such as a DSP for the control logic. Figure 3 As shown in the figure, i_peak_ref is the real-time input value of the peak pulse curve of the AC current shown in the figure. The difference between it and the peak value of the capacitor current of the spike voltage absorption circuit is multiplied by the peak value of the line voltage on the three-phase AC side to obtain the real-time load power control instruction P

[0043] As Figure 3 shown Figure 1 As shown, i_peak_ref is the real-time input value of the peak pulse curve of the AC current shown in the figure. The difference between it and the peak value of the capacitor current of the spike voltage absorption circuit is multiplied by the peak value of the line voltage on the three-phase AC side to obtain the real-time load power control instruction P * .

[0044] Since the capacity of each load branch is calculated and selected based on the rated value of the three-phase AC voltage, when the effective value of the AC input voltage deviates from the rated value, the actual capacity of each load branch will change with the change of the effective value of the input voltage. Therefore, calculate the square of the ratio of the effective value of the three-phase input AC voltage U abrms to the rated voltage U n to obtain the adaptive adjustment coefficient m (i.e., m = (U abrms / U n ) 2 ). Multiply this adjustment coefficient by the designed minimum adjustment capacity P0 parameter to obtain the actual minimum adjustment capacity at the current input AC voltage Similarly, the actual capacity of the nth load branch is obtained by multiplying the designed Pn by the coefficient m and adjusting it with the three-phase AC input voltage

[0045] According to P * , and to calculate the control bits of the high-speed power switches of each load branch. Specifically as follows:

[0046] If P * < P n t , set b n to 0, and let W = P *

[0047] If P * ≥ P n t , set b n to 1, and let W = P * - P n t

[0048] Take the integer part of the ratio of W to and convert it into a binary number to obtain the binary number b n-1b n-2 …b2b1b0。

[0049] The 0th bit b0 corresponds to the control of the load branch 0. If it is 1, the switch tube T0 is turned on; if it is 0, the switch tube T0 is turned off. The other bits from the 1st bit b1 to the (n - 1)th bit b n-1 and b n correspond to the switch controls of the switch tubes T1 to Tn in sequence. Similarly, when it is 1, the corresponding switch tube is controlled to conduct immediately; when it is 0, the corresponding switch tube is immediately controlled to turn off.

[0050] 3.2 Control of the auxiliary branch switch tube Th

[0051] The switch tubes from T0 to Tn above actually adopt real-time open-loop control to strictly ensure a sufficiently small dynamic response time of the analog load current (for example, less than 0.1 ms) to meet the requirement that the rising edge of the pulse current of the analog load is steep enough. If there is a slight steady-state current deviation between the actual current and the target value during the pulse width of the pulse, the current closed-loop control of the auxiliary branch can be used. For example, Figure 4 the three-phase input currents ia and ib are detected and sampled to calculate the peak values of the three-phase currents. The difference between the given numerical value of the three-phase AC current peak pulse curve and the actually detected and calculated peak values of the three-phase currents minus the detected value of the auxiliary DC resistance current is used as the input of the control regulator (which can be a proportional-integral regulator, etc.). Its output passes through a limiter to obtain a modulation wave, and the PWM pulse obtained by comparing with the triangular carrier wave is used to control the on-off of the high-speed power switch Th of the auxiliary branch.

[0052] 3.3 Simulation verification

[0053] For a simulated pulse load with a rated power of 150 KW, the input is a three-phase AC voltage with an effective value of 200 V at 400 HZ. The minimum resolution of each load branch is required to be 0.1 kVA, and in the three-phase AC current peak pulse curve, the pulse dynamic response time is required to be less than 0.1 ms. The capacities of the 10 load branches designed under the condition of the rated AC input voltage increase in a geometric progression with a common ratio of 2 in sequence, namely 0.1 kVA, 0.2 kVA, 0.4 kVA,... 51.2 kVA. In addition, there is also a load branch with a capacity of 60 kVA and an auxiliary branch with a capacity of 12.8 kVA. Attached Figure 5 is the simulation waveform, Figure 6 and Figure 5 is the partial simulation waveform of . Among them, the Curve curve is the target value of the three-phase AC current peak curve, and i(L1a), i(L1b), and i(L1c) are the waveforms of the three-phase input currents actually achieved by control. The simulation shows that by using the circuit architecture and control method proposed in this paper, the accuracy of current tracking control is very high, and the error can basically be within 1%, and the current dynamic response can also be less than 0.1 ms.

[0054] Compared with the traditional technology, the present invention has the following advantages:

[0055] 1) By adopting the patent solution of the present invention, the main circuit architecture is simple, the control of the system is relatively easy to implement, the dynamic response of the pulse load current is very fast. Using conventional high-speed power switching devices, even if the turn-on and turn-off time of the switching device is less than 50 μs, the dynamic response time can still be achieved below 0.1 ms. Because an adaptive adjustment coefficient related to the AC voltage amplitude fluctuation is introduced, and an auxiliary branch is introduced for steady-state error compensation, the system can achieve high-precision target tracking control while meeting high dynamic response.

[0056] 2) The power switching device mainly operates in a switching state with an extremely low frequency, and the switching loss can basically be ignored.

[0057] The above specific embodiments are only several preferred embodiments of the present invention. Based on the technical solution of the present invention and the relevant inspirations of the above embodiments, those skilled in the art can make various alternative improvements and combinations to the above specific embodiments.

Claims

1. A three-phase analog pulse load with high precision and high dynamic response, characterized in that: It includes a three-phase power supply, a three-phase uncontrolled rectifier bridge, a spike voltage absorption circuit, and a total of n + 1 load branches from 0 to n; The three-phase power supply is rectified into direct current by the three-phase uncontrolled rectifier bridge, and the spike voltage absorption circuit is connected in parallel between the positive and negative busbars of the DC circuit to absorb current. The spike voltage absorption circuit has a series resistor Rd and capacitor C; Each of the load branches is connected in parallel between the positive and negative DC busbars. Each load branch includes a high-speed power switch device in series with a resistor, and each resistor is connected in parallel with a freewheeling diode. Among them, the capacity of each load branch is defined as the square of the DC bus voltage divided by the resistance value of the load resistor. The capacity of load branch 0 is designed as the minimum regulation capacity P0 of the system. The rated power capacities of load branches 0 to n-1 are designed according to a geometric progression with a common ratio of 2, and the designed capacity Pn of the nth load is taken as (1 + r%)Q N -2 n P0, where the rated capacity requirement of the system is Q N , and the margin is r%; The parameter configuration of the spike voltage absorption circuit is such that at the moment when all load branches are turned on and off simultaneously, the energy stored in the line inductance in the front section of the three-phase rectifier and the DC side busbar inductance is released to the capacitor C, and the steady-state and transient voltages across the RC do not exceed the safe operating voltage of each power switch tube.

2. The three-phase analog pulse load according to claim 1, characterized in that: The heat dissipation design of the high-speed power switch device only needs to consider the conduction loss and does not need to consider the switching loss.

3. The three-phase analog pulse load according to claim 2, characterized in that: When the system current exceeds 50A, the high-speed power switch device uses an IGBT to control the on and off of the resistance current of this branch, and / or when the system current is lower than 50A, the high-speed power switch device uses a MOSFET tube.

4. The three-phase analog pulse load according to claim 1, characterized in that: Given the real-time input value \(i_{peak\_ref}\) of the AC current peak pulse curve, multiply the difference between it and the peak value of the capacitor current of the spike voltage absorption circuit by the peak value of the line voltage on the three-phase AC side to obtain the real-time control command \(P\) for the load power * ; Calculate the square of the ratio of the effective value of the three-phase input AC voltage U abrms to the rated voltage U n to obtain the adaptive adjustment coefficient m, m = (U abrms / U n ) 2 ; Multiply the adaptive adjustment coefficient m by the designed minimum adjustment capacity P0 parameter to obtain the actual minimum adjustment capacity at the current input AC voltage. Similarly, the actual capacity of the nth load branch is obtained by multiplying the designed Pn by the coefficient m and is adjusted with the three-phase AC input voltage. According to P * , and to calculate the control bits of the high-speed power switch devices of each load branch.

5. The three-phase analog pulse load according to claim 4, wherein Said according to P * , and to calculate the control bits of the high-speed power switch devices of each load branch, further comprising: If P * <P n t , b n is set to 0, and let W = P * If P * ≥P n t , b n is set to 1, and let W = P * -P n t ; Take the integer ratio of W to and convert it to a binary number, obtaining the binary number b n-1 b n-2 …b2b1b0; The 0th bit b0 corresponds to the control of load branch 0. If it is 1, the high-speed power switch device T0 of this load branch is turned on. If it is 0, the switch device T0 is turned off. For the other bits from the 1st bit b1 to the (n - 1)th bit b n-1 and b n successively correspond to the switch devices T1 to Tn, and the same switching control strategy is adopted.

6. The three-phase analog pulse load according to claim 1 or 4, characterized in that: It further includes an auxiliary branch, which is connected in parallel between the positive and negative busbars of the DC circuit. The auxiliary branch is configured to connect an inductor in series with a resistor under the framework of the load branch to smooth the resistance current of the high-speed power switch device Th in the auxiliary branch under PWM control. The freewheeling diode in the auxiliary branch is connected in parallel with the branch of the resistor in series with the inductor.

7. The three-phase analog pulse load according to claim 6, characterized in that: The three-phase input currents ia and ib are detected and sampled to calculate the peak values of the three-phase currents. The difference between the given three-phase AC current peak pulse curve value and the actually detected and calculated peak values of the three-phase currents minus the difference of the detected value of the resistance current in the auxiliary branch is used as the input of the control regulator. Its output is passed through a limiter to obtain a modulation wave, and the PWM pulse obtained by comparing with the triangular carrier wave is used to control the on and off of the high-speed power switch device Th in the auxiliary branch.

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