Automatic reverse current regulation in active clamped flyback converter

Abstract

The invention relates to automatic reverse current regulation in an active clamped flyback converter. According to one embodiment, a method is presented that includes sensing a reverse current through a main switch of an active clamped flyback (ACF) converter. The ACF converter includes a flyback transformer and an auxiliary switch. The method further includes determining whether a sensed voltage corresponding to the reverse current exceeds a threshold; reducing a duration of the reverse current by an incremental time interval, the duration of the reverse current including a first incremental time interval, the duration of the reverse current corresponding to a duration in which the auxiliary switch is activated; increasing the duration by a second incremental time interval greater than the first incremental time interval, the increasing in response to the reverse current not exceeding the threshold; and activating the auxiliary switch for the duration to achieve zero voltage switching (ZVS).

Description

Technical Field

[0001] The present disclosure relates generally to power converters and, in particular embodiments, to automatic reverse current regulation in an active clamp flyback converter. Background Art

[0002] Zero voltage switching (ZVS) in converters refers to a switching technique in which a power semiconductor switch (i.e., transistor) is turned on when there is zero voltage (or very close to zero) between its terminals (e.g., drain terminal and source terminal). This is in contrast to hard switching, in which the switch is turned on or off when voltage and current are present, resulting in higher switching losses due to the simultaneous presence of voltage and current during transitions.

[0003] The main advantage of achieving ZVS is the reduction of switching losses in the converter, especially at higher frequencies. By ensuring that the switching transitions occur at or near zero voltage, the energy dissipated during each switching event is minimized. This improves efficiency, reduces thermal stress on components, and can allow higher operating frequencies.

[0004] In an active clamp flyback (ACF) converter designed to achieve optimal efficiency, the low-side switch is operated under ZVS. To achieve this, the high-side switch remains activated for a set duration. This allows a certain amount of primary current associated with the set duration to flow reversely in the opposite direction after the set duration. Determining the set duration and therefore the precise reverse current value becomes critical to achieving this goal. If the set duration is too low, ZVS is not achieved, resulting in losses in the switch. Conversely, if the set duration is too high, while ZVS is achieved, the increased conduction losses offset its advantages.

[0005] Component variations and operating conditions affect existing techniques to regulate reverse current. As a result, these techniques lack precision in consistently ensuring the desired ZVS state. Therefore, improvements to conventional solutions are needed. Summary of the invention

[0006] Technical advantages are generally achieved by embodiments of the present disclosure, which describe automatic reverse current regulation in an active clamp flyback converter.

[0007] A first aspect relates to a method. The method includes detecting a reverse current through a main switch of an active clamp flyback (ACF) converter. The ACF converter includes a flyback transformer and an auxiliary switch. The method also includes determining whether a sense voltage corresponding to the reverse current exceeds a threshold; reducing a duration of the reverse current by an incremental time interval, the duration of the reverse current including a first incremental time interval, the duration of the reverse current corresponding to a duration during which the auxiliary switch is activated; increasing the duration by a second incremental time interval greater than the first incremental time interval, the increase being in response to the reverse current not exceeding the threshold; and activating the auxiliary switch for the duration to achieve zero voltage switching (ZVS).

[0008] A second aspect relates to an active clamped flyback (ACF) converter. The ACF converter includes a flyback transformer, the flyback transformer including a primary winding and a secondary winding; a main switch coupled in series with the primary winding between a DC voltage node and a reference voltage node; a clamping circuit coupled across the primary winding, the clamping circuit including a capacitor and an auxiliary switch; and a controller configured to control activation and deactivation of the main switch and the auxiliary switch, and sense a reverse current through the main switch. The controller is configured to sense the reverse current through the main switch through a current sensing node, determine whether a sensed voltage corresponding to the reverse current exceeds a threshold, reduce a duration of the reverse current by an incremental time interval, the duration of the reverse current including a first incremental time interval, the duration of the reverse current corresponding to a duration during which the auxiliary switch is activated, increase the duration by a second incremental time interval greater than the first incremental time interval, the increase in response to the reverse current not exceeding the threshold, and activate the auxiliary switch within the duration to achieve zero voltage switching (ZVS).

[0009] A third aspect relates to a system. A system includes: a load; a switch circuit system coupled to the load, the switch circuit system including an auxiliary switch and a main switch coupled in series between a power supply voltage node and a reference voltage node; and a controller configured to control activation and deactivation of the main switch and the auxiliary switch, and sense a reverse current through the main switch. The controller is configured to sense the reverse current through the main switch through a current sensing node, determine whether a sensing voltage corresponding to the reverse current exceeds a threshold, reduce a duration of the reverse current by an incremental time interval, the duration of the reverse current including a first incremental time interval, the duration of the reverse current corresponding to a duration during which the auxiliary switch is activated, increase the duration by a second incremental time interval greater than the first incremental time interval, the increase in response to the reverse current not exceeding the threshold, and activate the auxiliary switch within the duration to achieve zero voltage switching (ZVS).

[0010] Embodiments may be implemented in hardware, software or any combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a schematic diagram of a standard flyback converter;

[0013] Figure 2 is a schematic diagram of an active clamp flyback converter;

[0014] Figure 3 and Figure 4 They are the comparative waveforms of the gate control signals of the complementary control method and the non-complementary control method respectively;

[0015] Figure 5 is a graphical representation of the operation of an active clamp flyback converter operating under a complementary control method;

[0016] Figure 6 is a graphical representation of the operation of an active clamp flyback converter operating under a non-complementary control method; Figure 7 According to an embodiment Figure 2 Schematic diagram of the equivalent circuit of the active clamp flyback converter;

[0017] Figure 8A-8D Schematic diagrams showing embodiments of a timing circuit, an adjustment circuit, a filtering circuit and a reverse timer circuit respectively;

[0018] Fig. 9is a flow chart of an embodiment method of self-adjusting reverse current (IREV) using a timing circuit during an off-state of a low-side switch;

[0019] Fig.10 is based on Fig. 9 Embodiments of the method of timing circuit operation waveform;

[0020] Fig.11 Is used based on Fig. 9 Embodiments of a method of timing the operation of a circuit for amplifying a waveform;

[0021] Fig.12 is based on Fig. 9 Embodiments of a method of timing the operation of a circuit for amplifying a waveform;

[0022] Fig.13 is a block diagram of an embodiment power converter having a totem pole power factor correction (PFC) topology; and

[0023] Fig.14 is a block diagram of an embodiment system. DETAILED DESCRIPTION

[0024] The present disclosure provides many applicable inventive concepts that can be implemented in a variety of specific contexts. The specific embodiments are merely illustrations of specific configurations and do not limit the scope of the claimed embodiments. Unless otherwise stated, features from different embodiments may be combined to form additional embodiments. Various embodiments are shown in the accompanying drawings, in which the same parts and elements are represented by the same reference numerals, and repeated descriptions are omitted for brevity.

[0025] The changes or modifications described in one embodiment may also be applied to other embodiments. In addition, various changes, substitutions and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0026] Although aspects of the present invention are described primarily in the context of an active clamp flyback converter, it should also be understood that aspects of the invention may also be applied to other types of power converters. Specifically, aspects of the present invention may be similarly applied to power converters featuring a half-bridge structure that allows current reversal and power converters having switches synchronized with zeroing of reverse current. For example, embodiments of the present invention may be similarly applied to power converters having a totem-pole power factor correction (PFC) topology with delta current mode (TCM) operation.

[0027] Typically, in an active clamp flyback converter, when the main switch of the active clamp flyback converter is in the off state, the reverse current (I REV) flows on the primary side of the transformer. The reverse current helps to deplete the drain capacitance of the active clamp circuit before the main switch is turned on to achieve soft switching (ie, ZVS). In an embodiment, a method for automatically determining the reverse current (I REV ) duration to achieve ZVS in the main switch.

[0028] Figure 1 1 shows a schematic diagram of a standard flyback converter 100. The standard flyback converter 100 includes a controller 102, a low-side switch (Q1) 104, a drain capacitor (C DRAIN )106, transformer 108, output capacitor (C OUT )110, output diode (D OUT ) 112 and RCD clamp circuit 114, which may (or may not) be arranged as shown. RCD clamp circuit 114 includes resistor (R) 116, capacitor (C) 118 and diode (D) 120. Standard flyback converter 100 may include additional components not shown, such as a load at the output.

[0029] Controller 102 directs the operation of standard flyback converter 100. Controller 102 generates the necessary control signals, typically in the form of pulse width modulation (PWM), to regulate the output voltage (V OUT ) or current. The controller 102 monitors the output and adjusts the switching frequency or duty cycle to maintain a stable output under varying load and input conditions.

[0030] The low-side switch (Q1) 104, typically a metal oxide semiconductor field effect transistor (MOSFET), is the main switching element of the standard flyback converter 100. The controller 102 drives the low-side switch (Q1) 104, turning it on and off at a specific frequency and duty cycle. When the low-side switch (Q1) 104 is turned on, energy is stored in the primary winding of the transformer 108. When the low-side switch (Q1) 104 is turned off, the stored energy is transferred to the secondary winding of the transformer 108 and then to the output.

[0031] In an embodiment, the drain capacitor (C DRAIN ) 106 is not an external discrete component, although an external capacitor can be added in some cases. The drain capacitor (C DRAIN ) 106 is a representation of the lump sum of the capacitance of the parasitic contributors, such as the output capacitance (C OSS ), the end-to-end capacitance of the primary winding of the transformer 108, the junction capacitance of the secondary rectifier reflected to the primary side (or C in the case of synchronous rectification) OSS) plus other spurious contributors. From a circuit analysis point of view, these parasitic contributors are all dynamically in parallel with each other and can be represented by the drain capacitor (C DRAIN )106 to indicate.

[0032] Transformer 108 provides input (V IN ) and output (V OUT It also stores energy during the on-state of the low-side switch (Q1) 104 (in its primary winding) and releases it to the load of the standard flyback converter 100 during the off-state of the low-side switch (Q1) 104 (i.e., through its secondary winding).

[0033] Output capacitor (C OUT ) 110 is located after the second winding of transformer 108. It filters out high frequency switching ripples and ensures a stable and smooth DC output voltage (V OUT ). By storing energy, it also provides instantaneous power to the load during transition conditions.

[0034] Output diode (D OUT ) 112 allows current to flow from the secondary winding of the transformer 108 to the output terminal during the off phase of the low-side switch (Q1) 104, and blocks the current during the on phase, ensuring unidirectional current flow at the output terminal.

[0035] The RCD clamp circuit 114 or resistor-capacitor-diode clamp circuit is a protection circuit that is added to manage voltage spikes that may occur due to the leakage inductance of the transformer 108. The resistor (R) 116 helps dissipate energy, the capacitor (C) 118 absorbs the voltage spike, and the diode (D) 120 provides a path for the leakage energy to return, thereby ensuring that the voltage spike does not exceed a safe level and thus protecting the low side switch (Q1) 104.

[0036] In operation, the standard flyback converter 100 switches the low side switch (Q1) 104 on and off in a controlled manner. When the low side switch (Q1) 104 is in the on state, energy is stored in the primary winding of the transformer 108. When the low side switch (Q1) 104 is in the off state, the stored energy is transferred to the secondary winding of the transformer 108, which is rectified, filtered and provided to the load at the output of the standard flyback converter 100.

[0037] The controller 102 continuously adjusts the operation of the standard flyback converter 100 based on feedback from the output to ensure that the desired output voltage (V OUT ) or current. The RCD clamp circuit 114 ensures that any potential voltage spikes are managed and do not damage the converter's components.

[0038] Although the standard flyback converter 100 offers the advantages of simplicity and cost-effectiveness, it has significant disadvantages. Notably, it converts energy from the leakage inductance into heat, adversely affecting efficiency. In addition, it limits the use of high switching frequencies and produces sharp and sawtooth waveforms, resulting in significant electromagnetic interference (EMI).

[0039] Figure 2 1 shows a schematic diagram of an active clamp flyback converter 200. The active clamp flyback converter 200 includes a controller 202, a low-side switch (Q1) 104, a drain capacitor (C DRAIN )106, transformer 108, output capacitor (C OUT )110, output diode (D OUT ) 112, and an active clamp 204, which may (or may not) be arranged as shown. The active clamp circuit 204 includes a clamp capacitor (CC) 206 and a high-side switch (Q2) 208 (i.e., an auxiliary switch). The active clamp flyback converter 200 may include additional components not shown, such as a load at the output or an optional clamp resistor arranged in parallel with the clamp capacitor (CC) 206.

[0040] The controller 202 dictates the precise timing and duration of the low-side switch (Q1) 104 and the high-side switch (Q2) 208. The controller 202 is responsible for ensuring that the operation of the two switches regulates the output voltage (V OUT ) or current.

[0041] Low-side switch (Q1) 104, drain capacitor (C DRAIN )106, transformer 108, output capacitor (C OUT )110 and output diode (D OUT The operation of )112 is similar to that described with respect to the standard flyback converter 100 and will not be repeated for the sake of brevity.

[0042] The active clamp 204, which is a distinguishing feature of the active clamp flyback converter 200, includes a high-side switch (Q2) 208 and a clamp capacitor (C C ) 206. Together, they recover energy stored in the leakage inductance of transformer 108, reducing voltage spikes and improving efficiency. The high-side switch (Q2) 208 provides a controlled path for this energy, while the clamping capacitor (C C )206 Temporarily store and release energy.

[0043] In operation, when the low side switch (Q1) 104 is activated, current flows into the primary winding of the transformer 108, storing energy. When the low side switch (Q1) 104 is deactivated, the energy moves to the secondary winding due to the collapsing magnetic field, and then through the output diode (D OUT ) 112 to the output. At the same time, in a complementary control arrangement, the high-side switch (Q2) 208 in the active clamp 204 is turned on, providing any excess energy (from the leakage inductance of the transformer) to the clamp capacitor (C C ) 206, thereby preventing harmful voltage spikes. This active clamping operation improves efficiency and extends component life. The controller 202 synchronizes the operation of the low-side switch (Q1) 104 and the high-side switch (Q2) 208 to maintain a regulated output. In an embodiment, in a non-complementary control setting, the clamping capacitor (C C )206 are both charged via the body diode (not shown) of the high-side switch (Q2)208.

[0044] Despite the increased complexity of the active clamped flyback converter 200, primarily due to the drive requirements of the high side switch (Q2) 208, it has the benefit of utilizing the energy from the leakage inductance to achieve soft switching (i.e., ZVS) of the low side switch (Q1) 104 and the high side switch (Q2) 208. The active clamped flyback converter 200 can achieve efficiencies in excess of 93% even at high switching frequencies in excess of 200 kHz. In addition, the active clamped flyback converter 200 produces a smooth waveform with very limited electromagnetic interference.

[0045] Figure 3 and Figure 4 Comparative waveforms 300, 400 of the gating signals for the complementary control method and the non-complementary control method for operating the active clamp flyback converter 200 are shown, respectively. Figure 3 and Figure 4 In each of FIG. 1 , a first gating signal 302 , 402 at the gate terminal of the low-side switch ( Q1 ) 104 and a second gating signal 304 , 404 at the gate terminal of the high-side switch ( Q2 ) 208 originating from the controller 202 are shown.

[0046] Under the complementary control method, the first gating signal 302 and the second gating signal 304 operate in a mutually exclusive manner, so that when one switch is turned on (i.e., activated), the other switch is turned off (i.e., deactivated), and vice versa. Under this method, the low-side switch (Q1) 104 and the high-side switch (Q2) 208 never operate at the same time.

[0047] Obviously, even in the case of complementary control, there is a short dead time between the turn-off of one switch and the turn-on of the other switch, where both switches are in the off state. This is critical not only to prevent simultaneous turn-on, which could be catastrophic, but also to achieve ZVS, as it allows the voltage at the drain terminal of the low-side switch (Q1) 104 time to transition from a high-to-low or low-to-high logic level state.

[0048] Under the non-complementary control method, an intentional pause or "dead time" is introduced between the deactivation of one switch and the activation of the other switch. This intentional delay ensures a brief moment when both switches are turned off. In addition, the same (or usually similar in duration) dead time is inserted after both switches are turned off. Typically, a dead time in the strictest sense is inserted between the turn-off of the high-side switch (Q2) 208 and the turn-on of the low-side switch (Q1) 10, while after the turn-off of the low-side switch (Q1) 10, there is a controlled delay (typically depending on the operating conditions of the converter) instead of a dead time. Typically, the duration of the dead time is shorter, while the controlled delay is longer.

[0049] The complementary control method ensures a continuous path for the current, either through the primary winding of the transformer 108 or through the clamping capacitor (C C )206, depending on which switch is turned on. However, this continuous switching may result in a higher root mean square (RMS) current on the primary side, potentially leading to increased power losses. One of the main challenges of the complementary control method is its limited flexibility in handling a wide range of input and output voltages, especially when trying to meet modern power requirements, such as those of Universal Serial Bus (USB) Power Delivery (PD).

[0050] Although ZVS can be achieved under both complementary and non-complementary control, the key advantage of non-complementary control is that ZVS is achieved with a lower RMS primary current. With ZVS, the next switch can be turned on when the voltage across it is at a minimum, thereby reducing switching losses and improving the overall efficiency of the active clamp flyback converter 200. The non-complementary control method, with its inherent advantages, tends to produce lower RMS currents in the primary circuit, resulting in reduced power losses. In addition, the strategy provides a more adaptive method of managing varying input and output voltage ranges, making it particularly suitable for modern power delivery standards.

[0051] Figure 5The operation of the active clamp flyback converter 200 operating under the complementary control method is shown. Specifically, the primary side current 502 in the primary winding of the transformer 108 is described with reference to the first gating signal 302 of the complementary control method. During time t0 to time t1, the low side switch (Q1) 104 is in the off state. At time t1, the low side switch (Q1) 104 is activated and is in the on state.

[0052] In addition to the primary current 502 during the on-time of the low-side switch (Q1) 104 from time t1 to time t2, a large amount of current flows through the primary current 502 during the off-time of the low-side switch (Q1) 104 from time t0 to time t1. The current flowing through the primary current 502 during the off-time of the low-side switch (Q1) 104 from time t0 to time t1 generates conduction losses on the resistance of the primary winding of the transformer 108. Therefore, in addition to the power loss caused by the conduction of the low-side switch (Q1) 104 during the on-time from time t1 to time t2, there is also conduction loss during the off-time of the low-side switch (Q1) 104 from time t0 to time t1. This results in a higher root mean square (RMS) current on the primary side, resulting in increased power loss.

[0053] Figure 6 The operation of the active clamp flyback converter 200 operating under the non-complementary control method is shown. Specifically, the primary side current 602 in the primary winding of the transformer 108 and the secondary side current 604 through the secondary winding of the transformer 108 are shown with reference to the first gating signal 402 and the second gating signal 404 of the non-complementary control method. The high side switch (Q2) 208 is turned on in response to the secondary side current 604 becoming zero.

[0054] During time t0 and time t1, the low side switch (Q1) 104 is in the on state. At time t1, the low side switch (Q1) 104 is deactivated. During time t0 to time t3, the high side switch (Q2) 208 is in the off state. At time t3, the high side switch (Q2) 208 is activated. At time t4, the high side switch (Q2) 208 is deactivated. Between time t1 and time t3, the low side switch (Q1) 104 and the high side switch (Q2) 208 are deactivated.

[0055] During the on-time of the low-side switch (Q1) 104, from time t0 to time t1, the primary current 602 ramps up from a zero value at time t0 to a maximum peak current value at time t1. At time t1, the first gating signal 402 transitions and the low-side switch (Q1) 104 is deactivated, causing the primary current 602 to become zero at time t2. Between time t1 and time t2, the clamp capacitor (C C) 206 is recharged, and the secondary current 604 ramps up from a zero value at time t1 to a maximum peak current value at time t2. At time t2, once the clamp capacitor (C C ) 206 is recharged (eg, the clamp capacitor (C C ) The voltage across 206 rises slightly above the reflected voltage (V R )(That is, the output voltage (V OUT ) multiplied by the primary to secondary turns ratio), the secondary side current 604 gradually ramps down from the maximum peak current value at time t2 to zero at time t3.

[0056] At time t3, the high-side switch (Q2) 208 is activated in response to the secondary current 604 having a zero value. The primary current 602 operates in the reverse direction (i.e., a negative current value) from time t3 to time t4. When the primary current 602 operates in the reverse direction from time t3 to time t4, the secondary current 604 ramps up from the zero value at time t3 to the second maximum peak current value at time t4. The direction of the current flowing on the primary current 602 during the off state is opposite to the direction of the current flowing on the primary current 602 during the on state.

[0057] In order to properly operate the active clamp flyback converter 200 under the non-complementary control method and achieve ZVS of the low-side switch (Q1) 104, it is necessary to actively manage the operation of the primary current 602 when flowing in the reverse direction from time t3 to time t4. When operating in the reverse direction, the management of the primary current 602 provides enough energy to completely switch the half-bridge midpoint from a high level to a low level within the dead time.

[0058] If the duration of the primary current 602 when flowing in the reverse direction is too short, the voltage at the midpoint of the half-bridge will not transition to zero, resulting in increased switching losses. Conversely, if the duration of the primary current 602 when flowing in the reverse direction is too long, the voltage at the midpoint of the half-bridge will transition to zero appropriately, but when the primary current 602 generates conduction losses, the additional losses will overcome any benefits provided by the soft switching provided by the active clamp flyback converter 200.

[0059] Figure 7 A schematic diagram of an equivalent circuit 700 of the active clamped flyback converter 200 is shown during the off state of the low side switch (Q1) 104 between time t3 and time t4. When the high side switch (Q2) 208 is activated, in response to the primary side current 602 flowing in the reverse direction, current flows on the secondary winding of the transformer 108, and the active clamped flyback converter 200 operates similar to an actual transformer.

[0060] To illustrate the leakage inductance of transformer 108, the magnetizing inductance (LM )702 (i.e., storing energy that can be transferred to the secondary side) and leakage inductance (L σ )704 (i.e., storing energy that cannot be transferred to the secondary side).

[0061] The primary side current 602 (ie, the current flowing in the reverse direction) at a particular time (t) is shown as i P (t), the magnetizing current at a specific time (t) is shown as i M (t), and the secondary side current 604 at a specific time (t) is shown as i S (t).

[0062] i P (t) and i M The relationship between (t) can be expressed by the following formula: Where Z c is including leakage inductance (L σ )704 and clamping capacitor (C C ) The characteristic impedance of the resonant circuit of 206 can be expressed as The resonant frequency ω associated with the resonant circuit C It can be expressed as V CL (0) is the clamp capacitor (C C ) 206 at time t3 (equal to the value at time t2, i.e., the value at the end of the charging phase), and the reflected voltage is the voltage across the primary winding of the transformer 108 when the high-side switch (Q2) 208 is activated. This is due to the clamping capacitor (C C ) 206 is isolated and maintains its voltage during the time interval between time t2 and time t3 corresponding to the high-side switch (Q2) 208 being in the off state.

[0063] The magnetizing current i with a linear ramp M (t) can be expressed by the following equation: Magnetizing current i M (t) is used to determine whether ZVS is achieved by the active clamped flyback converter 200.

[0064] i P (t),i M (t) and i S The relationship between (t) can be expressed by the following formula: S (t) = -n×[i p (t)-i M (t)] where is the number of turns on the primary winding (N P ) and the number of turns on the second winding (N S ) ratio.

[0065] In order to achieve soft switching, the reverse current (I REV ) is approximately equal to Where V R =n×V OUT In modern power delivery applications, such as USB-PD applications, where the input voltage (V IN ) and output voltage (V OUT ) changes in value to obtain accurate reverse current (I REV ) can be challenging to calculate mathematically during manufacturing or to look up from a table of given variances in component values.

[0066] A conventional solution to achieve ZVS of the low-side switch (Q1) 104 is to set a duration from time t3 to time t4 where the primary current 602 flows in the reverse direction. Assuming the input voltage (V IN ) is much larger than the reflected voltage V on the primary side of the transformer 108. R The square value (V IN / V R >>1), the duration from time t3 to time t4 can be programmed to be proportional to the input voltage (V IN ) is proportional to the output voltage (V OUT ) is inversely proportional. Unfortunately, in this solution, the reverse current (I REV ) to the magnetizing inductance (L M )702, leakage inductance (L σ )704 and drain capacitor (C DRAIN ) is sensitive to the parameter tolerance of 106. In addition, the approximate relationship cannot guarantee a sufficient duration from time t3 to time t4 to achieve ZVS under all operating conditions.

[0067] Another conventional solution to achieve ZVS is to use a sensor to monitor the drain voltage of the low-side switch (Q1) 104. In this solution, the duration from time t3 to time t4 is automatically adjusted to make the drain voltage of the low-side switch (Q1) 104 lower than the set voltage. Disadvantageously, this solution does not ensure that ZVS is achieved. In addition, this solution lacks fine-tuning options and requires additional capacitors and external depletion MOSFETs, which are limited in terms of availability and implementation cost. In addition, this solution requires two pins of the control IC dedicated to this purpose.

[0068] Figure 8A-8D Schematic diagrams of embodiments of a timing circuit 800 , an adjustment circuit 806 , a filtering circuit 808 , and a reverse timer circuit 824 are shown respectively. Fig. 91 is a diagram for self-regulating the reverse current (I) of the active clamp flyback converter 200 using the timing circuit 800 during the off state of the low side switch (Q1) 104 between time t3 and time t4. REV ) 1018 is a flowchart of an embodiment method 900. Note that all steps outlined in the flowchart of method 900 are not necessarily required and may be optional. In addition, changes in the arrangement of steps, removal of one or more steps and path connections, and addition of steps and path connections are similarly contemplated.

[0069] Fig.10 An example waveform 1000 illustrating the operation of timing circuit 800 based on method 900 is shown. Fig.11 It shows that when Q1 is turned on, the current sense voltage (VCS) 1110 is lower than the (negative) threshold (V CS_TH ) is more negative, an embodiment of an amplified waveform 1100 for operation of the timing circuit 800 based on the method 900. Fig.12 shows the current sense voltage (V CS )1110 is not greater than the threshold value (V CS_TH ) is less negative, an embodiment of an amplified waveform 1200 for operation of the timing circuit 800 based on the method 900.

[0070] In an embodiment, method 900 utilizes a fine-tuning element (R FT )804 to check the necessary conditions for ZVS. The trimming element (R FT ) 804 combined with the current output from the regulating circuit 806 produces a positive offset voltage that allows the reset of the circuit to effectively see a voltage higher than that across the sense resistor (RS) 802. In practice, this is equivalent to setting the threshold (V CS_TH ) to a more negative value.

[0071] The timing circuit 800 and method 900 provide a solution for automatically adjusting the duration between time t3 and time t4 to achieve ZVS, or to be programmed to approach ZVS if required for efficiency reasons. FT ) The value of 804 can be fine-tuned to achieve near ZVS or to achieve ZVS. Advantageously, unlike conventional solutions, the timing circuit 800 does not require a dedicated pin.

[0072] Independent of the power converter solution, the necessary condition for the switch to turn on with ZVS is that at the instant the switch turns on, there must be a current flowing from the source terminal to the drain terminal (i.e., the drain-source voltage (VDS) is negative). This current is called "reverse" because normally the current flows from the drain to the source in a MOSFET switch.

[0073] In order for this condition to be sufficient, the reverse current (I REV ) must be greater than the drain capacitor (C DRAIN )106 minimum required. If with reverse current (I REV ) is proportional to the amount of current stored in the leakage inductance (L σ )704 exceeds the minimum amount, the drain capacitor (C DRAIN )106 can be completely exhausted.

[0074] In the case of a MOSFET switch, this reverse current flows from the source terminal to the drain terminal through the body diode of the switch. In the case of a gallium nitride (GaN) high electron mobility transistor (HEMT) switch, the current flows from the source terminal to the drain terminal in a reverse conduction mode. In an embodiment, the present invention checks that this condition (i.e., the current flowing from the source terminal to the drain terminal of the switch exceeds a minimum value) is met. If this condition is not met, embodiments of the present disclosure provide a solution to increase the duration of reverse conduction until the condition is met.

[0075] Typically, a sense resistor is placed between the source terminal of the main switch and ground to sense the primary current during the on-time. Sensing is typically performed by controlling a dedicated pin in an integrated circuit to perform peak current mode control. Embodiments of the present disclosure use the same dedicated pin and sense resistor to sense the reverse current (if any) flowing through the primary winding of the transformer 108 immediately before the main switch is activated. Thus, embodiments of the present disclosure achieve ZVS or near ZVS using existing components within a typical power converter without any additional dedicated pins.

[0076] The timing circuit 800 includes a trimming element (R FT ) 804, an optional adjustment circuit 806, a filter circuit 808, an adder circuit 810, a first comparator (COMP1) 812, a first inverter 814, a second inverter 816, a first AND gate 818, a first flip-flop (FF1) 820, a second AND gate 822, a reverse timer circuit 824, and a second flip-flop (FF2) 826, which may (or may not) be arranged as shown. The output (Q) of the second flip-flop (FF2) 826 is coupled to the high-side switch (Q2) 208 via, for example, a gate driver (not shown). The timing circuit 800 may include additional components not shown. In an embodiment, the first flip-flop (FF1) 820 and the second flip-flop (FF2) 826 are edge-sensitive SR (set-reset) type flip-flops.

[0077] The optional regulation circuit 806 includes a third flip-flop (FF3) 828 and a first current generator 830, which may or may not be arranged as shown. In an embodiment, the first current generator 830 is activated for a set period of time.

[0078] The filter circuit 808 includes a first capacitor (C1) 832 and a resistor (R1) 834, which may (or may not) be arranged as shown. In an embodiment, the filter circuit 808 is a low pass filter. The filter circuit 808 is configured to filter out noise, interference, and voltage spikes, thereby producing a cleaner signal at the inverting input of the first comparator (COMP1) 812.

[0079] The reverse timer circuit 824 includes a first one-shot (MF1) 836, a second one-shot (MF2) 838, a second current generator 840, a second capacitor (C2) 842, a third current generator 844, a fixed current generator 846, a switch (SW) 848, a third capacitor (C3) 850, and a second comparator (COMP2) 852, which may (or may not) be arranged as shown. The output of the second AND gate 822 is coupled to the input of the first one-shot (MF1) 836. The output of the second comparator (COMP2) 852 is coupled to the "reset" (R) input of the second flip-flop (FF2) 826.

[0080] In an embodiment, the first one-shot (MF1) 836, the second one-shot (MF2) 838, the second current generator 840, the second capacitor (C2) 842, and the third current generator 844 form a reverse current timer programming circuit 823 of the reverse timer circuit 824. Alternatively, in an embodiment, the reverse current timer programming circuit 823 is digitally implemented as an up-down counter.

[0081] In an embodiment, the fixed current generator 846, the switch (SW) 848 and the third capacitor (C3) 850 form the reverse current timer circuit 825 of the reverse timer circuit 824. Alternatively, in an embodiment, the reverse current timer circuit 825 is digitally implemented as an up-counter.

[0082] In an embodiment, when the reverse current timer programming circuit 823 and the reverse current timer circuit 825 are digitally implemented, the second comparator (COMP2) 852 is implemented as a digital comparator.

[0083] As shown, the sensing resistor (RS) 802 is arranged between the source terminal of the low-side switch (Q1) 104 and ground. P (t)) flows through the sensing resistor. The trimming element (R FT) 804 has a first terminal coupled to a common node between the sense resistor (RS) 802 and the source terminal of the low side switch (Q1) 104. The trimming element (R FT ) 804 is coupled to a current sense (CS) node 805 (eg, a pin of a control IC) of the timing circuit 800. The drain voltage (VD) 1006, 1106, 1206 of the low-side switch (Q1) 104 is Fig.10 , Fig.11 and Fig.12 Shown in.

[0084] The timing circuit 800 is used to compare the threshold value (V CS_TH ) to check the filter current sense (V CSF ) The filtered current sense voltage (V CSF ) 1008, 1108, 1208. In an embodiment, the filtered current sense (V CSF ) The filtered current sense voltage (V CSF ) 1008, 1108, 1208 is approximately equal to the current sense voltage (VCS) 1010, 1110, 1210 at the current sense (CS) node 805, which itself is equal to the current sense voltage (VCS) 1010, 1110, 1210 across the sense resistor (R S )802's voltage, despite being filtered by filter circuit 808.

[0085] The first comparator (COMP1) 812 is configured to have hysteresis - its past state affects its output due to the feedback connection via the adder circuit 810. The adder circuit 810 has a circuit configured to receive a threshold value (V CS_TH ) and a second input configured to receive the comparator output. The first comparator (COMP1) 812 has a first input configured to receive the filtered current sensing voltage (V CSF ) 1008, 1108, 1208 inverting input (-). The first comparator (COMP1) 812 is configured to receive the sum of the thresholds (V CS_TH ) and the comparator output. The first comparator (COMP1) 812 is configured to generate an output signal that is fed to a first input of a first AND gate 818. It should be noted that in embodiments, other techniques besides adder circuits may be used to implement hysteresis.

[0086] The first inverter 814 is configured to receive a gate signal (GD) for driving the high-side switch (Q2) 208. H )1002, 1102, 1202, and generate an inverted signal (GD HNIn an embodiment, when the high-side switch (Q2) 208 is in the on state, the gate signal (GD H )1002, 1102, 1202 are at a logic level high, and when the high-side switch (Q2) 208 is in the off state, the gate signal (GD H )1002, 1102, 1202 are at logic level low. The inverting signal (GD HN ) is fed to the “set” (S) input of the first flip-flop (FF1) 820.

[0087] The first AND gate 818 is configured to receive the output signal from the first comparator (COMP1) 812 at a first input and receive a gate signal (GD) for driving the low-side switch (Q1) 104 at a second input. L ) 1004, 1104, 1204. In an embodiment, when the low-side switch (Q1) 104 is in the on state, the gate signal (GD L ) 1004, 1104, 1204 are at a logic level high, and when the low-side switch (Q1) 104 is in the off state, the gating signal is at a logic level low. The first AND gate 818 implements a logical connection based on the input signals at its first and second inputs, which is fed to the "reset" (R) input of the first flip-flop (FF1) 820. This effectively allows the output of the first comparator (COMP1) 812 to be gated at the moment when the low-side switch (Q1) 104 is turned on.

[0088] The first flip-flop (FF1) 820 is based on the inverted signal (GD) at the “set” (S) input terminal. HN ) and the logic connection of the first comparator (COMP1) 812 and the gate signal (GD L ) 1004, 1104, 1204 generate an output signal at its output terminal (Q). Therefore, the first flip-flop (FF1) 820 can be reset when the low-side switch (Q1) 104 is turned on. When the high-side switch (Q2) 208 is turned off, the first flip-flop (FF1) 820 is set.

[0089] The second inverter 816 is configured to receive the gating signal (GD L ) 1004, 1104 and generate an inverted signal (GD LN The second AND gate 822 has a first input coupled to the output (Q) of the first flip-flop (FF1) 820. The second input of the second AND gate 822 is configured to receive the inverted signal (GD) from the second inverter 816. LN ). The second AND gate 822 implements a logical connection based on input signals at its first and second inputs, which are fed to the reverse timer circuit 824.

[0090] In operation, at step 902, the method 900 begins immediately before activating the low-side switch (Q1) 104. At step 904, the filtered current sense voltage (V CSF )1008, 1108, 1208 and threshold (V CS_TH ) is compared. In an embodiment, the threshold value (V CS_TH ) is slightly negative (e.g., -20 or -30 mV). In an embodiment, the filtered current sensing voltage (V CSF ) 1008, 1108, 1208 are sensing resistors (R S ) The current sensing voltage across 802 (V CS )1010 is a filtered signal.

[0091] In an embodiment, the first comparator (COMP1) 812 is based on the filtered current sensing voltage (V CSF )1008, 1108, 1208 and threshold (V CS_TH ) provides an output signal to the first AND gate 818. In response to the sum value being greater than the filtered current sensing voltage (V CSF ) 1008, 1108, the first comparator (COMP1) 812 will output a logic level high (eg, '1'). In response to the threshold (V CS_TH ) and the comparator output is less than the filtered current sense voltage (V CSF ) 1008, 1208, the first comparator (COMP1) 812 will output a logic level low (eg, '0').

[0092] In response to the filtered current sense voltage (V CSF )1008, 1108, the negative value is not greater than the threshold value (V CS_TH ) is less negative, at step 906, the flag (Z flag) 1012, 1112 is set to a logic level high (eg, '1'). Setting the flag (Z flag) 1012, 1112 to a logic level high indicates that the negative current is insufficient. In response to the filtered current sense voltage (V CSF )1008,1208 than the threshold value (V CS_TH ) is more negative, at step 908, the flag (Z flag) 1012, 1212 is set to a logic level low (e.g., '0'). Setting the flag (Z flag) 1012, 1212 to a logic level low indicates a sufficiently negative current. In an embodiment, the output of the first flip-flop (FF1) 820 corresponds to the value of the flag (Z flag) 1012, 1112, 1212.

[0093] During the period when the low-side switch (Q1) 104 is in the on state, the gate signal (GD L ) 1004, 1104 are at a logic level high, and if the output of the first comparator (COMP1) 812 is at a logic level high, indicating a sufficient negative current, the input of the first AND gate 818 is at a logic level high. Therefore, the output of the first AND gate 818 is at a logic level high, resulting in the assertion of a reset signal at the "reset" input of the first flip-flop (FF1) 820. When the first flip-flop (FF1) 820 is reset, the flag (Z flag) 1012, 1112 is set to a logic level low.

[0094] In an embodiment, when the high-side switch (Q2) 208 is off, the flag (Z flag) defaults to a logic level high. When the internal signal commanding the low-side switch (Q1) 104 indicates that the low-side switch (Q1) 104 is turned on (Q1 is turned on after some delay introduced by the internal circuit), if the output of the first comparator (COMP1) 812 is high, the first flip-flop (FF1) 820 is reset and the flag (Z flag) is set to a logic level low; otherwise, it remains at a logic level high. Since the first flip-flop (FF1) 820 is edge sensitive, the gate signal (GD L ) transitions from a logic low level to a logic high level, only the state of the first comparator (COMP1) 812 is significant.

[0095] Therefore, in an embodiment, the default state of the flag (Z flag) 1012, 1112, 1212 is set to a logic level high, and in response to the comparison operation at step 904, when the reset signal is asserted at the first flip-flop (FF1) 820, the flag (Z flag) 1012 can be set to a logic level low.

[0096] In general, the amount of energy required to achieve ZVS depends on various factors, such as parasitic capacitance of the low side switch (Q1) 104 and the transformer 108, or stray contributions such as metal objects (e.g., heat sinks) near the low side switch (Q1) 104. To account for these various contributors, a regulation circuit 806 may optionally be added to the timing circuit 800 to regulate the amount of negative current. In addition, the regulation circuit 806 may optionally be added to the timing circuit 800 to account for variations in component tolerances.

[0097] In an embodiment, in step 910, immediately before the low-side switch (Q1) 104 is activated, the first current generator 830 is turned on for a short program time. At the end of the short duration, the first current generator 830 is turned off. In response to the high-side switch (Q2) 208 being in the off state, corresponding to the gate signal (GD H)1002, 1102, 1202 are at logic level low and the inverting signal (GD HN ) is at a logic level high, the third flip-flop (FF3) 828 is set. In an embodiment, the third flip-flop (FF3) 828 is a SR (set-reset) flip-flop.

[0098] Thus, when the high-side switch (Q2) 208 is deactivated, the first current generator 830 is turned on. In response to a leading edge blanking (LEB) signal asserted at the “reset” (R) input of the third flip-flop (FF3) 828, the first current generator 830 is turned off. The LEB signal is typically used in a peak current mode controller arrangement to blank out spikes on the current sense signal when the power switch transitions between the OFF and ON states to avoid premature shutdown and false triggering of the protection mechanism. When the gate signal (GD L ) 1004 is set high and is asserted high a short time after the low side switch (Q1) 104 is activated at step 910, the LEB signal is asserted low at the regulating circuit 806. In an embodiment, the short time window is equal to 100 to 200 ns after the low side switch (Q1) 104 is activated.

[0099] The amount of current generated by the first current generator 830 may be fixed or variable with respect to the input voltage (V IN ) is proportional (i.e., k×V IN , where k is a scaling factor). By injecting the current generated by the first current generator 830 at the current sensing (CS) node 805, the current sensing voltage (V CS ) 1010, 1110, 1210 are offset by a voltage equal to the current generated by the first current generator 830 multiplied by the fine-tuning element (R FT )804 resistance value.

[0100] If the current generated by the first current generator 830 is equal to zero (eg, excluding the regulation circuit 806 from the timing circuit 800), the filtered current sense (V CSF ) The filtered current sense voltage (V CSF ) 1008, 1108, 1208 are approximately equal to the current sensing voltage (V CS )1010,1110,1210.

[0101] However, if the regulation circuit 806 is included, the filtered current sense (V CSF ) The filtered current sense voltage (VCSF )1008, 1108, 1208 than the current sensing voltage (V CS ) 1010, 1110, 1210 are slightly more positive. Then, for the non-inverting input of the first comparator (COMP1) 812 to be below the threshold (V CS_TH ), the offset will require a filtered current sense voltage (V CSF ) 1008, 1108, 1208 are more negative, which results in a longer duration of the time interval between time t3 and time t4. This can be achieved by changing the fine-tuning element (R FT )The resistance value of 804 can be used to adjust this effect.

[0102] Thus, advantageously, the regulation circuit 806 allows the timing circuit 800 to regulate the reverse current (I REV )1018, 1118, 1218 to achieve ZVS or close to ZVS. In an embodiment, the fine-tuning element (R FT )804 is set to 100 ohms to have a low impedance that does not produce significant additional noise to the system.

[0103] Immediately following steps 906 and 908, at step 910, the low-side switch (Q1) 104 is activated. At step 912, after the low-side switch (Q1) 104 is in the on state, the count end (EoC) counter value is reduced by one step. Note that if the value of the count end (EoC) counter is zero, the value of the count end (EoC) counter is not reduced. The primary current begins to ramp up from the moment the low-side switch (Q1) 104 is activated. The reason for reducing the count end (EoC) counter value by one step at step 912 in each cycle is that operating conditions can change, and step 912 allows dynamic adjustment regardless of the filtered current sense voltage (V CSF )1008, 1108, 1208 are greater than or less than the threshold value (V CS_TH ).

[0104] In step 914, the output voltage (V OUT ) control loop determines that the low side switch (Q1) 104 will be deactivated when the primary current reaches a peak. Immediately after the low side switch (Q1) 104 is deactivated, at step 916, the status of the flag (Z flag) 1012, 1112, 1212 is analyzed.

[0105] The flag (Z flag) 1012, 1112, 1212 is provided as the output of the first flip-flop (FF1) 820 to the first input of the second AND gate 822. The second input of the second AND gate 822 is at a logic level high because the low-side switch (Q1) 104 is deactivated, which corresponds to the gate signal (GD L) 1004, 1104, 1204 are at logic level low and the inverting signal (GD LN ) is at logic level high.

[0106] The end of count (EoC) counter is implemented in the timing circuit 800 by the reverse current timer programming circuit 823. The first one-shot (MF1) 836 is configured to switch from a stable state to an unstable state within a predetermined period in response to being triggered, and then automatically return to the stable state. In an embodiment, the first one-shot (MF1) 836 is arranged as a positive edge triggered one-shot.

[0107] Therefore, if the flag (Z flag) 1012, 1112 is at a logic level high, the second AND gate 822 provides a positive edge signal to the input of the first one-shot (MF1) 836. The positive edge signal (signal transition from a logic level low to a logic level high) triggers the first one-shot (MF1) 836, causing the state of the first one-shot (MF1) 836 to change and generate a charging pulse (CHP) 1016, 1116, 1216 of duration (Δt) at its output (Q), thereby activating the second current generator 840.

[0108] Activation of the second current generator 840 causes a charge flow into the second capacitor (C2) 842. The charge (ΔQ) added to the second capacitor (C2) 842 can be represented by the following equation: ΔQ=I×Δt. Where I is the constant current generated by the second current generator 840 and Δt is the duration. In an embodiment, the charge (ΔQ) added to the second capacitor (C2) 842 is 250 pico-Coulombs (μC). In an embodiment, the second capacitor (C2) 842 is integrated within the timing circuit 800. In an embodiment, the second capacitor (C2) 842 is several pico-farads (pF).

[0109] At step 918, in response to the flag (Z flag) 1012 being at a logic level high, the end of count (EoC) counter value is increased by k steps due to the negative current shortage, where k is an integer greater than 1. In an embodiment, k is equal to 2. If necessary, step 918 is based on the filtered current sense voltage (V CSF )1008, 1108, 1208 and the threshold value of the current cycle (V CS_TH ) to offset the impact of step 912.

[0110] At step 920 , in response to flag (Z flag) 1012 being at a logic level low, or after step 918 , a first dead time is introduced wherein both low side switch ( Q1 ) 104 and high side switch ( Q2 ) 208 are deactivated for a set duration.

[0111] At step 922, at the end of the first dead time, the high side switch (Q2) 208 is activated. When the active clamped flyback converter 200 operates in the complementary control method 300 in response to the end of the first dead time, the high side switch (Q2) 208 is activated. When the active clamped flyback converter 200 operates in the non-complementary control method 400 in response to detecting demagnetization, the high side switch (Q2) 208 is activated. Demagnetization refers to the zeroing of the energy stored in the transformer 108, which corresponds to the zeroing of the current flowing through the primary and secondary windings of the transformer 108.

[0112] In an embodiment, the second flip-flop (FF2) 826 is set by asserting a set signal to a “set” (S) input of the second flip-flop (FF2) 826 in response to the end of the first dead time or detecting demagnetization based on the type of control method.

[0113] At step 924, once the end of count (EoC) counter value has been set, the reverse current timer programming circuit 823 sets the duration (I REV ).

[0114] Similar to the first one-shot (MF1) 836, the second one-shot (MF2) 838 switches from a stable state to an unstable state within a predetermined period in response to being triggered, and then automatically returns to a stable state. In an embodiment, the second one-shot (MF2) 838 is arranged as a positive edge triggered one-shot.

[0115] When the high-side switch (Q2) 208 is deactivated, the gate signal (GD H )1002, 1102, 1202 are at logic level low and inverted signal (GD HN ) is at a logic level high, and a positive edge signal is provided to the input of the second one-shot (MF2) 838. The positive edge signal triggers the second one-shot (MF2) 838, causing the state of the second one-shot (MF2) 838 to change and generate a discharge pulse (DISCHP) 1014, 1114, 1214 of duration (Δt) at its output (Q), which activates the third current generator 844. The third current generator 844 is a negative current generator. The activation of the third current generator 844 causes the discharge of the second capacitor (C2) 842.

[0116] In an embodiment, when the flag (Z flag) 1012 is high and caused by the second current generator 840, the increase in voltage generated on the second capacitor (C2) 842 by the reverse current timer programming circuit 823 is K times the decrease caused by the activation of the third current generator 844 in each cycle. Therefore, the duration of the pulses generated by the first one-shot (MF1) 836 and the second one-shot (MF2) 838 are the same, and the current provided by the second current generator 840 is K times the current of the third current generator 844. Alternatively, the second current generator 840 and the third current generator 844 are equal, and the pulse duration of the first one-shot (MF1) 836 is K times longer than the pulse duration of the second one-shot (MF2) 838. Regardless, the result is the same.

[0117] Since charging of the second capacitor (C2) 842 occurs only during the period when the flag (Z flag) 1012 is at a logic level high in step 916, and discharging of the second capacitor (C2) 842 occurs during each period in step 926, the timing circuit 800 determines a balance in which the flag (Z flag) 1012 is at a logic level high for a specific number of periods and the flag (Z flag) 1012 is at a logic level low for a specific number of periods.

[0118] Therefore, over multiple cycles, a DC voltage with small ripples is generated on the second capacitor (C2) 842. The size of the second capacitor (C2) 842 is such that the ripples are negligible compared to the DC voltage. The DC voltage is provided to the inverting input terminal of the second comparator (COMP2) 852 as a reference voltage.

[0119] The fixed current generator 846 and the third capacitor (C3) 850 provide a ramp voltage to the non-inverting input of the second comparator (COMP2) 852. When the ramp voltage provided to the non-inverting input of the second comparator (COMP2) 852 reaches a DC voltage level, a reset signal is asserted at the "reset" (R) input of the second flip-flop (FF2) 826. Since the output (Q) of the second flip-flop (FF2) 826 provides a gate signal (GD) for driving the high-side switch (Q2) 208, H ) 1002 , 1102 , 1202 , resetting the second flip-flop ( FF2 ) 826 results in deactivation of the high-side switch ( Q2 ) 208 .

[0120] The control signal of the switch (SW) 848 is output by the inverted output of the second flip-flop (FF2) 826. Provided. When the gate signal (GD H )1002, 1102, 1202 are at logic level low, the inverted output of the second flip-flop (FF2) 826 At a logic level high, it closes switch (SW) 848 and resets timing circuit 800.

[0121] Therefore, at step 926, after the counter of the timing circuit 800 reaches the end of count (EoC) counter value, the high side switch (Q2) 208 is deactivated. At step 928, a second dead time is introduced. At the end of the second dead time, the method 900 returns to step 904, where the low side switch (Q1) 104 will turn on, and the steps are repeated for the next cycle.

[0122] Thus, for consecutive cycles, in response to insufficient negative current, the end of count (EoC) counter value increases, and in response to sufficient negative current, the end of count (EoC) counter value decreases, but at a slower rate than it increases. Effectively, this provides a "reset spring" type of operation, enabling the reverse current to be reduced if operating conditions change such that less reverse current is required to achieve ZVS. Advantageously, this process allows the reverse current (I REV ) durations of 1018, 1118, 1218 to achieve ZVS or close to ZVS.

[0123] In the active clamp flyback converter 200, if the input voltage (V IN ) is less than the reflected voltage (V R )(i.e. V IN ≤V R ), ZVS is naturally achieved without the need for reverse current (I REV )1018,1118,1218.

[0124] Therefore, optionally, if the reverse current (I REV ) 1018, 1118, 1218 of the programming duration (i.e., the DC voltage provided as the reference voltage to the inverting input of the second comparator (COMP2) 852) is below the minimum value, the high side switch (Q2) 208 is not activated during the switching cycle. Alternatively, if the flag (Z flag) 1012 is at a logic level low for n consecutive switching cycles (i.e., the second capacitor (C2) 842 is not charged at step 916), the high side switch (Q2) 208 is deactivated and is only re-enabled when the flag (Z flag) 1012 is detected to be at a logic level high (i.e., the second capacitor (C2) 842 is charged at step 916) during the cycle.

[0125] Fig.13 1 is a block diagram of an embodiment power converter 1300 having a totem pole power factor correction (PFC) topology. The power converter 1300 includes a first semiconductor switch (S1) 1302, a second semiconductor switch (S2) 1304, a first capacitor (CP1 )1306, the second capacitor (C P2 ) 1308, output capacitor (C0) 1310, inductor (L) 1312 and voltage source 1314, which may (or may not) be arranged as shown. Power converter 1300 may include additional components not shown, such as a load at the output of power converter 1300 arranged in parallel with output capacitor (C0) 1310.

[0126] In an embodiment, each of the first semiconductor switch (S1) 1302 and the second semiconductor switch (S2) 1304 is a MOSFET or a GaN-type FET. The first semiconductor switch (S1) 1302 and the second semiconductor switch (S2) 1304 are arranged in a totem-pole topology (ie, vertically stacked).

[0127] In triangular current mode (TCM), also known as boundary conduction mode (BCM) or critical conduction mode (CrCM), the power switch is operated exactly at the boundary between continuous conduction mode (CCM) and discontinuous conduction mode (DCM). In TCM, the current of the inductor (L) 1312 rises from zero and returns to zero in each switching cycle. TCM control ensures that the power converter 1300 always switches when the inductor (L) 1312 current reaches zero, thereby reducing switching losses.

[0128] The timing circuit 800 and the method 900 may be similarly applied to the operation of the first semiconductor switch (S1) 1302 and the second semiconductor switch (S2) 1304, wherein the first semiconductor switch (S1) 1302 and the second semiconductor switch (S2) 1304 operate similarly to the low-side switch (Q1) 104 and the high-side switch (Q2) 208, respectively.

[0129] The timing circuit 800 and the method 900 are implemented in the operation of the power converter 1300 so that the current (I L ) is sufficiently negative to achieve soft switching of the first semiconductor switch (S1) 1302 and the second semiconductor switch (S2) 1304. The timing circuit 800 and the method 900 may be used to automatically regulate the negative current of the inductor (L) 1312.

[0130] Fig.14A block diagram of an embodiment system 1400 is shown. In an embodiment, the system 1400 includes a filter and rectifier circuit 1402, an optional power factor correction (PFC) stage circuit 1404, an active clamp flyback DC-DC converter 1406, and a USBPD control stage circuit 1408, which may (or may not) be arranged as shown. The system 1400 may include additional components not shown. In an embodiment, the system 1400 is a high-density USB-C charger for charging, for example, mobile devices, etc.

[0131] The filter and rectifier circuit 1402 is configured to receive an alternating current (AC) input from a power source. The filter and rectifier circuit 1402 filters noise and unwanted frequencies from the AC input and converts it to direct current (DC).

[0132] The PFC stage 1404 ensures that both the voltage and current waveforms are sinusoidal and in phase to maximize power transfer efficiency. The PFC stage 1404 typically requires an input power level greater than 75 Watts (W).

[0133] The active clamped flyback DC-DC converter 1406 converts the DC output from the PFC stage circuit 1404 to another DC level suitable for the USB PD control stage circuit 1408. In an embodiment, the active clamped flyback DC-DC converter 1406 is implemented as an active clamped flyback converter 200 with a timing circuit 800 and operates according to the method 900 to achieve ZVS or near ZVS.

[0134] The USB PD control stage circuit 1408 transmits an output voltage (V OUT ) to regulate and control power.

[0135] A first aspect relates to a method. The method includes detecting a reverse current through a main switch of an active clamp flyback (ACF) converter. The ACF converter includes a flyback transformer and an auxiliary switch. The method also includes determining whether a sense voltage corresponding to the reverse current exceeds a threshold; reducing a duration of the reverse current by an incremental time interval, the duration of the reverse current including a first incremental time interval, the duration of the reverse current corresponding to a duration during which the auxiliary switch is activated; increasing the duration by a second incremental time interval greater than the first incremental time interval, the increase being in response to the reverse current not exceeding the threshold; and activating the auxiliary switch for the duration to achieve zero voltage switching (ZVS).

[0136] In a first implementation form of the method according to the first aspect, the determination whether the detection voltage exceeds the threshold value is completed before the main switch is activated within the same period as the duration for which the auxiliary switch is set.

[0137] In a second implementation form of the method according to the first aspect itself or any preceding implementation form of the first aspect, the method further comprises delaying a first dead time after deactivating the main switch, wherein activating the auxiliary switch occurs after delaying the first dead time.

[0138] In a third implementation form of the method according to the first aspect itself or any of the preceding implementation forms of the first aspect, the method further comprises delaying a second dead time after deactivating the auxiliary switch. Activation of the main switch of the next cycle occurs after delaying the second dead time.

[0139] In a fourth implementation form of the method according to the first aspect itself or any of the preceding implementation forms of the first aspect, activating the auxiliary switch within the duration for achieving ZVS includes starting a reverse current timer after activating the auxiliary switch; and deactivating the auxiliary switch when the reverse current timer reaches the end of the count.

[0140] In a fifth implementation form of the method according to the first aspect as such or any preceding implementation form of the first aspect, the sensing of the reverse current through the main switch comprises sensing a voltage across a sensing resistor coupled in series with the main switch.

[0141] In a sixth implementation form of the method according to the first aspect as such or any preceding implementation form of the first aspect, the threshold is a negative voltage threshold.

[0142] A second aspect relates to an active clamped flyback (ACF) converter. The ACF converter includes a flyback transformer, the flyback transformer including a primary winding and a secondary winding; a main switch coupled in series with the primary winding between a DC voltage node and a reference voltage node; a clamping circuit coupled across the primary winding, the clamping circuit including a capacitor and an auxiliary switch; and a controller configured to control activation and deactivation of the main switch and the auxiliary switch, and sense a reverse current through the main switch. The controller is configured to sense the reverse current through the main switch through a current sensing node, determine whether a sensed voltage corresponding to the reverse current exceeds a threshold, reduce a duration of the reverse current by an incremental time interval, the duration of the reverse current including a first incremental time interval, the duration of the reverse current corresponding to a duration during which the auxiliary switch is activated, increase the duration by a second incremental time interval greater than the first incremental time interval, the increase in response to the reverse current not exceeding the threshold, and activate the auxiliary switch within the duration to achieve zero voltage switching (ZVS).

[0143] In a first implementation form of the ACF converter according to the second aspect, the ACF further comprises a sensing resistor coupled between the reference voltage node and a current sensing node coupled to a source of a field effect transistor (FET) forming the main switch.

[0144] In a second implementation of the ACF converter according to the second aspect or any preceding implementation of the second aspect, the controller includes a comparison circuit having a first input coupled to a current sensing node and a second input coupled to receive a threshold value. The comparison circuit is configured to generate a reverse current sensing signal indicating whether the reverse current through the main switch exceeds the threshold value.

[0145] In a third implementation form of the ACF converter according to the second aspect or any of the foregoing implementation forms of the second aspect, the controller further comprises a reverse current timer programming circuit. The reverse current timer programming circuit comprises a discharge current source, the discharge current source being coupled to discharge the voltage node to reduce the voltage of the reverse current time signal generated on the voltage node, the discharge current source being configured to discharge the voltage node in each switching cycle of the ACF converter in response to a gate drive signal applied to control the deactivation of the auxiliary switch; and a charge current source being coupled to charge the voltage node and increase the voltage of the reverse current time signal on the voltage node in each switching cycle of the ACF converter in response to a reverse current sensing signal indicating that the reverse current through the main switch does not exceed a threshold.

[0146] In a fourth implementation form of the ACF converter according to the second aspect or any of the preceding implementation forms of the second aspect, the controller further comprises a reverse current timer circuit coupled to a voltage node of the reverse current timer programming circuit. The reverse current timer circuit is configured to generate a gate drive signal to deactivate the auxiliary switch in response to a ramp voltage signal on the ramp voltage node reaching a voltage of the reverse current time signal.

[0147] In a fifth implementation form of the ACF converter according to the second aspect or any preceding implementation form of the second aspect, the ACF further includes a regulation circuit, which includes a resistor element coupled between the current sensing node and the first input of the comparison circuit; and a current source coupled to the first input of the comparison circuit, the current source being configured to supply charge to the first input of the comparison circuit to regulate the voltage value on the first input in response to a gate drive signal applied to deactivate the auxiliary switch, and further configured to stop supplying charge to the first input in response to a leading edge blanking signal.

[0148] In a sixth implementation form of the ACF converter according to the second aspect as such or any preceding implementation form of the second aspect, the threshold is a negative voltage threshold.

[0149] A third aspect relates to a system. A system comprising a load; a switch circuit system coupled to the load, the switch circuit system comprising an auxiliary switch and a main switch coupled in series between a power supply voltage node and a reference voltage node; and a controller configured to control activation and deactivation of the main switch and the auxiliary switch, and sense a reverse current through the main switch. The controller is configured to sense a reverse current through the main switch through a current sensing node, determine whether a sense voltage corresponding to the reverse current exceeds a threshold, reduce a duration of the reverse current by an incremental time interval, the duration of the reverse current comprising a first incremental time interval, the duration of the reverse current corresponding to a duration during which the auxiliary switch is activated, increase the duration by a second incremental time interval greater than the first incremental time interval, the increase being in response to the reverse current not exceeding the threshold, and activate the auxiliary switch within the duration to achieve zero voltage switching (ZVS).

[0150] In a first implementation form of the system according to the third aspect, the switching circuit system comprises a delta current mode (TCM) power factor correction (PCF) circuit.

[0151] In a second implementation of the system according to the third aspect or any preceding implementation of the third aspect, the switching circuitry comprises an actively clamped flyback converter switching circuitry, and the auxiliary switch corresponds to a clamp switch of an active clamp circuit of the actively clamped flyback converter switching circuitry.

[0152] In a third implementation form of the system according to the third aspect or any preceding implementation form of the third aspect, the controller includes a comparison circuit having a first input coupled to the current sensing node and a second input coupled to receive a threshold value. The comparison circuit is configured to generate a reverse current sensing signal indicating whether the reverse current through the main switch exceeds the threshold value.

[0153] In a fourth implementation form of the system according to the third aspect or any of the foregoing implementation forms of the third aspect, the controller further comprises a reverse current timer programming circuit. The reverse current timer programming circuit comprises a discharge current source, the discharge current source being coupled to discharge the voltage node to reduce the voltage of the reverse current time signal generated on the voltage node, the discharge current source being configured to discharge the voltage node in each switching cycle of the switching circuit system in response to a gate drive signal applied to control the deactivation of the auxiliary switch; and a charge current source being coupled to charge the voltage node and increase the voltage of the reverse current time signal on the voltage node in each switching cycle of the switching circuit system in response to a reverse current sensing signal indicating that the reverse current through the main switch does not exceed a threshold.

[0154] In a fifth implementation form of the system according to the third aspect or any of the preceding implementation forms of the third aspect, the controller further comprises a reverse current timer circuit coupled to a voltage node of the reverse current timer programming circuit. The reverse current timer circuit is configured to generate a gate drive signal to deactivate the auxiliary switch in response to a ramp voltage signal on the ramp voltage node reaching a voltage of the reverse current time signal.

[0155] Although the present specification has been described in detail, it should be understood that various changes, substitutions and modifications may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims. In the various drawings, the same elements are represented by the same reference numerals. In addition, the scope of the present disclosure is not intended to be limited to the specific embodiments described herein, because it will be readily understood by those of ordinary skill in the art from this disclosure that processes, machines, manufactures, material compositions, means, methods or steps currently existing or to be developed later may perform substantially the same functions as the corresponding embodiments described herein or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, means, methods or steps within their scope.

[0156] Accordingly, the specification and drawings are to be considered merely illustrative of the present disclosure, which is defined by the appended claims, and are to cover any and all modifications, variations, combinations or equivalents falling within the scope of the present disclosure.

Claims

1. A method comprising: sensing a reverse current through a main switch of an active clamp flyback ACF converter, the ACF converter comprising a flyback transformer and an auxiliary switch; determining whether a sense voltage corresponding to the reverse current exceeds a threshold; reducing a duration of the reverse current by an incremental time interval, the duration of the reverse current comprising a first incremental time interval, the duration of the reverse current corresponding to a duration that the auxiliary switch is activated; increasing the duration by a second incremental time interval, the second incremental time interval being greater than the first incremental time interval, the increasing being in response to the reverse current not exceeding the threshold; as well as The auxiliary switch is activated for the duration to achieve zero voltage switching ZVS. 2 . The method of claim 1 , wherein determining whether the sense voltage exceeds the threshold is done before activating the main switch for the same period as the duration for setting the auxiliary switch. 3 . The method of claim 1 , further comprising delaying a first dead time after deactivating the main switch, wherein activating the auxiliary switch occurs after delaying the first dead time. 4 . The method of claim 1 , further comprising delaying a second dead time after deactivating the auxiliary switch, wherein activating the main switch in a next cycle occurs after delaying the second dead time.

5. The method of claim 1 , wherein activating the auxiliary switch for the duration to achieve ZVS comprises: After activating the auxiliary switch, starting a reverse current timer; as well as The auxiliary switch is deactivated when the reverse current timer reaches the end of count. 6 . The method of claim 1 , wherein sensing the reverse current through the primary switch comprises sensing a voltage across a sense resistor coupled in series with the primary switch. The method of claim 1 , wherein the threshold is a negative sensing voltage threshold.

8. An active clamp flyback ACF converter, comprising: A flyback transformer, including a primary winding and a secondary winding; a main switch coupled in series with the primary winding between a DC voltage node and a reference voltage node; a clamping circuit coupled across the primary winding, the clamping circuit comprising a capacitor and an auxiliary switch; as well as a controller configured to control activation and deactivation of the main switch and the auxiliary switch and configured to sense a reverse current through the main switch, the controller being configured to: sensing a reverse current through the main switch via a current sensing node, determining whether a sense voltage corresponding to the reverse current exceeds a threshold, reducing a duration of the reverse current by an incremental time interval, the duration of the reverse current comprising a first incremental time interval, the duration of the reverse current corresponding to a duration that the auxiliary switch is activated, increasing the duration by a second incremental time interval, the second incremental time interval being greater than the first incremental time interval, the increasing being in response to the reverse current not exceeding the threshold, and The auxiliary switch is activated for the duration to achieve zero voltage switching ZVS.

9. The ACF converter of claim 8, further comprising a sense resistor coupled between the reference voltage node and a current sensing node, the sense current node being coupled to a source of a field effect transistor FET forming the main switch.

10. The ACF converter of claim 8, wherein the controller comprises a comparison circuit having a first input coupled to the current sensing node and a second input coupled to receive the threshold value, the comparison circuit being configured to generate a reverse current sensing signal indicating whether the reverse current through the main switch exceeds the threshold value.

11. The ACF converter of claim 10, wherein the controller further comprises a reverse current timer programming circuit, the reverse current timer programming circuit comprising: a discharge current source coupled to discharge a voltage node to reduce a voltage of a reverse current time signal generated at the voltage node, the discharge current source being configured to discharge the voltage node at each switching cycle of the ACF converter in response to a gate drive signal applied to control deactivation of the auxiliary switch; as well as A charging current source is coupled to charge the voltage node and increase the voltage of the reverse current time signal on the voltage node in each switching cycle of the ACF converter in response to the reverse current sensing signal indicating that the reverse current through the main switch does not exceed the threshold.

12. The ACF converter of claim 11 , wherein the controller further comprises a reverse current timer circuit coupled to the voltage node of the reverse current timer programming circuit, the reverse current timer circuit being configured to generate a gate drive signal to deactivate the auxiliary switch in response to a ramp voltage signal on a ramp voltage node reaching a voltage of the reverse current time signal.

13. The ACF converter according to claim 10, further comprising a regulating circuit, the regulating circuit comprising: a resistive element coupled between the current sensing node and the first input of the comparison circuit; as well as a current source coupled to the first input of the comparison circuit, the current source being configured to supply charge to the first input of the comparison circuit to adjust a voltage value on the first input in response to a gate drive signal applied to deactivate the auxiliary switch, and further configured to stop supplying charge to the first input in response to a leading edge blanking signal.

14. The ACF converter of claim 8, wherein the threshold is a negative sensing voltage threshold.

15. A system comprising: load; a switching circuit system coupled to the load, the switching circuit system comprising an auxiliary switch and a main switch coupled in series between a supply voltage node and a reference voltage node; as well as a controller configured to control activation and deactivation of the main switch and the auxiliary switch and configured to sense a reverse current through the main switch, the controller being configured to: sensing a reverse current through the main switch via a current sensing node, determining whether a sense voltage corresponding to the reverse current exceeds a threshold, reducing a duration of the reverse current by an incremental time interval, the duration of the reverse current comprising a first incremental time interval, the duration of the reverse current corresponding to a duration that the auxiliary switch is activated, increasing the duration by a second incremental time interval, the second incremental time interval being greater than the first incremental time interval, the increasing being in response to the reverse current not exceeding the threshold, and The auxiliary switch is activated for the duration to achieve zero voltage switching ZVS.

16. The system of claim 15, wherein the switching circuitry comprises a delta current mode (TCM) power factor correction (PCF) circuit.

17. The system of claim 15, wherein the switching circuitry comprises an actively clamped flyback converter switching circuitry, wherein the auxiliary switch corresponds to a clamp switch of an active clamp circuit of the actively clamped flyback converter switching circuitry.

18. The system of claim 15, wherein the controller includes a comparison circuit having a first input coupled to the current sensing node and a second input coupled to receive the threshold, the comparison circuit being configured to generate a reverse current sensing signal indicating whether the reverse current through the main switch exceeds the threshold.

19. The system of claim 15, wherein the controller further comprises a reverse current timer programming circuit, the reverse current timer programming circuit comprising: a discharge current source coupled to discharge a voltage node to reduce a voltage of a reverse current time signal generated at the voltage node, the discharge current source being configured to discharge the voltage node at each switching cycle of the switching circuit system in response to a gate drive signal applied to control deactivation of the auxiliary switch; as well as A charging current source is coupled to charge the voltage node and increase the voltage of the reverse current time signal on the voltage node in each switching cycle of the switching circuit system in response to the reverse current sensing signal indicating that the reverse current through the main switch does not exceed the threshold.

20. The system of claim 19, wherein the controller further comprises a reverse current timer circuit coupled to the voltage node of the reverse current timer programming circuit, the reverse current timer circuit being configured to generate a gate drive signal to deactivate the auxiliary switch in response to a ramp voltage signal on a ramp voltage node reaching a voltage of the reverse current time signal.

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