Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can reduce the overall surface area of ​​multiple diode elements in a clamp circuit while satisfying the required element breakdown voltage for each individual diode element. [Solution] The semiconductor device includes a chip 2 having a first main surface 3, a p-type first well region 64 formed on the surface of the first main surface 3, and an active clamp circuit interposed between the drain terminal 15 and the gate control circuit. The active clamp circuit includes a plurality of diode elements DS formed on the surface of the first well region 64 in a diode formation region 8 set on the first main surface 3 and connected in series with each other. The plurality of diode elements DS include two first diode elements DS1 and ten second diode elements DS2 whose distance in the first element direction X1 on the outer circumference is shorter than that of the first diode elements DS1. The two first diodes DS1 are connected to the drain terminal 15 side of the ten second diodes DS2.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 includes a semiconductor chip having a main surface, a main transistor formed on the main surface so as to be individually controlled, and an active clamp circuit. The active clamp circuit protects the main transistor from the back electromotive force by limiting the output voltage when the back electromotive force is input to the main transistor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary]

[0005] One embodiment of this disclosure provides a semiconductor device including a chip having a first main surface and a second main surface opposite to the first main surface, and a plurality of diode elements connected in series to each other included in a clamp circuit interposed between a power supply terminal and a control terminal. Each of the plurality of diode elements may include a first impurity region of a first conductivity type formed in a surface layer portion of the first main surface in a diode formation region set on the first main surface, a plurality of second impurity regions of a second conductivity type formed at intervals in a direction along the first main surface in a surface layer portion of the first impurity region, and a plurality of anode regions and a plurality of cathode regions formed in a surface layer portion of the second impurity region. The plurality of diode elements may include at least one first diode element and a second diode element having a shorter outer peripheral distance than the first diode element, and at least one second diode element. The first diode element may be connected to the power supply terminal side with respect to the second diode element.

Brief Description of Drawings

[0006] [Figure 1] Figure 1 is a schematic plan view of a semiconductor device according to one embodiment of the present disclosure. [Figure 2] Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. [Figure 3] Figure 3 is a schematic circuit diagram showing the electrical configuration of the semiconductor device shown in Figure 1. [Figure 4] Figure 4 is a schematic circuit diagram showing the configuration of the output transistor. [Figure 5A] Figure 5A is a schematic circuit diagram showing the configuration of the active clamp circuit shown in Figure 1. [Figure 5B] Figure 5B is a schematic circuit diagram showing the configuration of the main components of the voltage clamp circuit shown in Figure 1. [Figure 6] Figure 6 is a layout diagram of the first main surface in the diode formation region shown in Figure 1. [Figure 7] Figure 7 is a plan view of the diode formation region. [Figure 8] Figure 8 is an enlarged view of the region enclosed by the dashed line VIII in Figure 6. [Figure 9] Figure 9 is an enlarged view of the region enclosed by the dashed line IX in Figure 7. [Figure 10] Figure 10 is a layout diagram of the first main surface of the first diode element shown in Figure 6. [Figure 11] Figure 11 is a cross-sectional view along the line XI-XI shown in Figure 9. [Figure 12] Figure 12 is a cross-sectional view along the line XII-XII shown in Figure 9. [Figure 13] Figure 13 is a layout diagram of the first main surface of the second diode element shown in Figure 6. [Figure 14] Figure 14 is a cross-sectional view along the line XIV-XIV shown in Figure 9. [Figure 15] Figure 15 is a cross-sectional view along the line XV-XV shown in Figure 13. [Figure 16A] Figure 16A is a cross-sectional view along the line XVIA-XVIA shown in Figure 8. [Figure 16B] FIG. 16B is a schematic diagram showing the electrical configuration of the semiconductor device. [Figure 16C] FIG. 16C is a diagram showing a first modification in which the layout of the second diode element is changed, and is a diagram corresponding to FIG. 13. [Figure 16D] FIG. 16D is a diagram showing a second modification in which a third diode element is further formed in the diode formation region, and is a diagram corresponding to FIG. 7. [Figure 16E] FIG. 16E is a layout diagram of the first main surface of the third diode element shown in FIG. 16D. [Figure 17] FIG. 17 is a plan view showing a second form of the arrangement of the first diode element and the second diode element. [Figure 18] FIG. 18 is a plan view showing a third form of the arrangement of the first diode element and the second diode element. [Figure 19] FIG. 19 is an enlarged cross-sectional view taken along line XIX-XIX shown in FIG. 18. [Figure 20] FIG. 20 is a plan view showing a fourth form of the arrangement of the first diode element and the second diode element. [Figure 21] FIG. 21 is a plan view showing a fifth form of the arrangement of the first diode element and the second diode element. [Figure 22] FIG. 22 is a plan view showing a sixth form of the arrangement of the first diode element and the second diode element. [Figure 23] FIG. 23 is an enlarged cross-sectional view taken along line XXIII-XXIII shown in FIG. 22.

[0007] [Detailed Description] The embodiments will now be described in detail with reference to the attached drawings. The attached drawings are schematic diagrams and not strictly accurate; the scale and other aspects may not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the description given before the omission or simplification applies.

[0008] When the phrase "substantially equal" is used in a description where a comparison target exists, this phrase includes not only numerical values ​​(forms) that are equal to the numerical value (form) of the comparison target, but also numerical errors (form errors) within a range of ±10% based on the numerical value (form) of the comparison target. In the embodiments, phrases such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of explanation and are not intended to limit the names of each structure.

[0009] Figure 1 is a plan view showing a semiconductor device 1 according to one embodiment of the present disclosure. Figure 2 is a cross-sectional view along the line II-II shown in Figure 1. Referring to Figures 1 and 2, the semiconductor device 1 includes a chip 2 formed in the shape of a rectangular parallelepiped. In this embodiment, the chip 2 is a Si chip containing a Si single crystal.

[0010] Chip 2 may consist of a wide-bandgap semiconductor chip including a single crystal of a wide-bandgap semiconductor. A wide-bandgap semiconductor is a semiconductor having a bandgap larger than that of Si. Examples of wide-bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). For example, Chip 2 may be a SiC chip including a SiC single crystal.

[0011] Referring to Figure 2, the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape in a plan view (hereinafter simply referred to as "plan view") as seen from their normal direction Z. The normal direction Z is also the thickness direction of the chip 2.

[0012] The first main surface 3 is a circuit surface on which various circuit structures constituting an electronic circuit are formed. The second main surface 4 is a non-circuit surface that does not have any circuit structures.

[0013] Referring to Figure 1, the first side surface 5A and the second side surface 5B extend in the first direction X along the first main surface 3 and face the second direction Y which intersects (specifically orthogonal to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0014] The semiconductor device 1 includes an output region 6 provided on the first main surface 3. The output region 6 is a region having an electronic circuit (circuit device) configured to generate an output signal to be output to the outside. In this embodiment, the output region 6 is demarcated on the first main surface 3 in the region on the first side surface 5A side. In a plan view, the output region 6 is demarcated in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.

[0015] The semiconductor device 1 includes a control region 7 located in a region different from the output region 6 on the first main surface 3. The control region 7 is a region having multiple types of electronic circuits (circuit devices) configured to generate control signals for controlling the output region 6. In this embodiment, the control region 7 is partitioned in the region on the second side surface 5B side relative to the output region 6 and faces the output region 6 in the second direction Y. In this embodiment, the control region 7 is partitioned in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.

[0016] The semiconductor device 1 includes at least one diode formation region 8 on the first main surface 3. The semiconductor device 1 may include a plurality of diode formation regions 8. In this embodiment, the semiconductor device 1 includes a diode formation region 8 corresponding to an active clamp circuit (clamp circuit) 30. The semiconductor device 1 further includes a diode formation region 8 corresponding to a voltage clamp circuit (clamp circuit) 35. The diode formation region 8 corresponding to the active clamp circuit 30 and the diode formation region 8 corresponding to the voltage clamp circuit 35 are formed with a gap between them. Only one of these diode formation regions 8 may be provided, and the other may be omitted.

[0017] Each diode formation region 8, in this configuration, has a planar area less than the planar area of ​​the control region 7 and is partitioned inward within the control region 7. A group of diodes 9, consisting of multiple diode elements connected in series in opposite directions, is formed in each diode formation region 8.

[0018] Referring to Figure 2, the semiconductor device 1 includes an n-type (first conductivity type) drain region 10 formed on the surface layer of the second main surface 4. The n-type impurity concentration in the drain region 10 is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following is also possible: The drain region 10 is formed in a layered manner extending along the second main surface 4 over the entire surface layer of the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. The drain region 10 may have a thickness of 50 μm or more and 400 μm or less. Preferably, the thickness of the drain region 10 is 50 μm or more and 200 μm or less. More preferably, the thickness of the drain region 10 is 150 μm or less. In this embodiment, the drain region 10 is formed of an n-type semiconductor substrate (Si substrate).

[0019] The semiconductor device 1 includes an n-type drift region 11 formed on the surface layer of the first main surface 3. The drift region 11 has a lower n-type impurity concentration than the drain region 10. The n-type impurity concentration of the drift region 11 is 1 × 10⁻⁶. 15cm -3 The above 1 x 10 18 cm -3 The following is also possible: The drift region 11 is formed in layers extending along the first main surface 3 in the output region 6 and the control region 7. Specifically, the drift region 11 is formed in layers extending along the first main surface 3 over the entire surface layer of the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0020] The drift region 11 is electrically connected to the drain region 10 within the chip 2. The drift region 11 has a thickness less than the thickness of the drain region 10. The thickness of the drift region 11 may be 1 μm or more and 20 μm or less. Preferably, the thickness of the drift region 11 is 5 μm or more and 15 μm or less. Particularly preferable is a thickness of 10 μm or less. In this embodiment, the drift region 11 is formed by an n-type epitaxial layer (Si epitaxial layer).

[0021] The semiconductor device 1 includes an interlayer insulating layer 12 that covers the first main surface 3. The interlayer insulating layer 12 covers the output region 6 and the control region 7 together. The interlayer insulating layer 12 may cover the entire area of ​​the first main surface 3 so as to be continuous with the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D). Of course, the interlayer insulating layer 12 may be formed with a gap inward from the periphery of the first main surface 3 so as to expose the periphery of the first main surface 3. The interlayer insulating layer 12 may contain at least one of a silicon oxide film and a silicon nitride film.

[0022] The semiconductor device 1 includes a plurality of terminals 13-15 arranged on either one or both (both in this embodiment) of the first main surface 3 and the second main surface 4. The plurality of terminals 13-15 include a source terminal 13, a plurality of control terminals 14, and a drain terminal 15.

[0023] In this embodiment, the source terminal 13 is provided as an output terminal electrically connected to a load and is positioned on the portion of the interlayer insulating layer 12 that covers the output region 6. The source terminal 13 may cover the entire output region 6 in a plan view. The source terminal 13 may include at least one of the following: a pure Al layer, a Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0024] Referring to Figures 1 and 2, the multiple control terminals 14 are terminals that are electrically connected to various electronic circuits within the control region 7, and are arranged on the portion of the interlayer insulating layer 12 that covers the control region 7. The multiple control terminals 14 are arranged at intervals from each other along the periphery of the control region 7 (the periphery of the first main surface 3).

[0025] The planar area of ​​each control terminal 14 is set to a range to which a bonding wire can be connected. The planar area of ​​each control terminal 14 may be 1 / 10 or less of the planar area of ​​the source terminal 13. Multiple control terminals 14 may include at least one of the following: a pure Al layer, a Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0026] The multiple control terminals 14 include at least one ground terminal 14a fixed to ground potential, and at least one input terminal 14b for supplying an electrical signal to the control region 7. The location of the ground terminal 14a is arbitrary. In a plan view, the ground terminal 14a may be located in the inner part of the control region 7, along one side of the first main surface 3, or at a corner of the first main surface 3. The ground terminal 14a is connected to a bonding wire, and ground potential is supplied from the outside via the bonding wire.

[0027] The location of the input terminal 14b is arbitrary. In a plan view, the input terminal 14b may be located in the inner part of the control area 7, along one side of the first main surface 3, or at a corner of the first main surface 3.

[0028] In this configuration, an example is shown in which the input terminal 14b consists of a test terminal to which a test signal is input for testing the electrical characteristics of the control circuit 23 during the manufacturing process. The test terminal is provided as a contact point for the probe of the electrical characteristics test device and is configured to receive a test signal from the probe.

[0029] Input terminal 14b is a structure that is not connected to bonding wires in the semiconductor device 1 after manufacturing. In other words, input terminal 14b is formed as an open terminal (dummy terminal). An open terminal is a terminal that does not accept signals (potential) from the outside and is formed in an electrically floating state.

[0030] For example, when the semiconductor device 1 is mounted in a semiconductor package, the entire area of ​​the input terminal 14b is covered with an insulator (e.g., a sealing resin containing multiple filler and matrix resins) to electrically isolate it from other structures. Of course, the input terminal 14b may also be electrically connected to the lead terminals of the semiconductor package via bonding wires, and configured so that a test signal can be input even after the semiconductor device 1 has been mounted in the semiconductor package.

[0031] Referring to Figure 2, the drain terminal 15, as an example of a power terminal, directly covers the second main surface 4 of the chip 2 in this configuration. In other words, the semiconductor device 1 in this configuration is a high-side switching device electrically interposed between the power supply and the load. The drain terminal 15 is electrically connected to the drain region 10 on the second main surface 4. The drain terminal 15 covers the entire area of ​​the second main surface 4 so as to extend along its periphery (first to fourth side surfaces 5A to 5D).

[0032] Figure 3 is a schematic circuit diagram showing the electrical configuration of the semiconductor device 1 shown in Figure 1. Figure 4 is a schematic circuit diagram showing the configuration of the output transistor 20. Figure 5A is a schematic circuit diagram schematically showing the configuration of the active clamp circuit 30 shown in Figure 3. Figure 5B is a schematic circuit diagram showing the configuration of the main parts of the voltage clamp circuit 35 shown in Figure 3.

[0033] Figure 3 shows an example of the operation of the semiconductor device 1, in which an inductive load L is electrically connected to the source terminal 13 as an example of a load. The inductive load L is not a component of the semiconductor device 1. Therefore, the configuration including the semiconductor device 1 and the inductive load L may be called an "inductive load drive device" or an "inductive load control device". Relays, solenoids, lamps, motors, etc. are examples of inductive load L. The inductive load L may also be an inductive load for automotive use. That is, the semiconductor device 1 may be an automotive semiconductor device.

[0034] Referring to Figures 3 and 4, the semiconductor device 1 includes an output transistor 20 formed in the output region 6. In this embodiment, the output transistor 20 consists of a gate-divided transistor including one main drain, one main source, and multiple main gates. The main drain is electrically connected to the drain terminal 15. The main source is electrically connected to the source terminal 13.

[0035] Multiple main gates are configured to receive multiple electrically independent gate signals (gate potentials) individually. The output transistor 20 generates a single output current Io (output signal) in response to the multiple gate signals. In other words, the output transistor 20 consists of a multi-input single-output switching device. The output current Io is the drain-source current flowing between the main drain and the main source. The output current Io is output to the outside of the chip 2 (inductive load L) via the source terminal 13.

[0036] The output transistor 20 includes a plurality (two or more) of electrically independently controlled system transistors 21. In this embodiment, the plurality of system transistors 21 include a first system transistor 21A and a second system transistor 21B. The plurality of system transistors 21 are aggregated and formed in the output region 6. The plurality of system transistors 21 are connected in parallel so that a plurality of gate signals are individually input to them, and are configured to have both ON and OFF state system transistors 21.

[0037] Each of the multiple system transistors 21 includes a system drain, a system source, and a system gate. The multiple system drains are electrically connected to the main drain (drain terminal 15). The multiple system sources are electrically connected to the main source (source terminal 13). Each system gate is electrically connected to each main gate. In other words, each system gate constitutes each main gate.

[0038] Multiple system transistors 21 each generate a system current Is in response to a corresponding gate signal. Each system current Is is a drain-source current flowing between the system drain and system source of each system transistor 21. Multiple system currents Is may have different values ​​or may have approximately equal values. Multiple system currents Is are added together between the main drain and main source. This generates a single output current Io consisting of the sum of the multiple system currents Is.

[0039] Referring to Figure 4, each of the multiple system transistors 21 includes one or more unit transistors 22 that are systematized (grouped) as individually controlled objects. Specifically, each of the multiple system transistors 21 is composed of a parallel circuit containing one or more unit transistors 22. In this configuration, each of the multiple unit transistors 22 is a trench gate vertical type. Each of the multiple system transistors 21 may be composed of the same number of unit transistors 22, or it may be composed of different numbers of unit transistors 22.

[0040] Each unit transistor 22 includes a unit drain, a unit source, and a unit gate. The unit drain of each unit transistor 22 is electrically connected to the system drain of the corresponding system transistor 21. The unit source of each unit transistor 22 is electrically connected to the system source of the corresponding system transistor 21. The unit gate of each unit transistor 22 is electrically connected to the system gate of the corresponding system transistor 21.

[0041] Multiple unit transistors 22 each generate a unit current Iu in response to a corresponding gate signal. Each unit current Iu is the drain-source current flowing between the unit drain and unit source of each unit transistor 22. Multiple unit currents Iu may have different values ​​or may have approximately equal values. Multiple unit currents Iu are added together between the corresponding system drain and system source. This generates a system current Is, which consists of the sum of the multiple unit currents Iu.

[0042] Thus, the output transistor 20 is configured such that the first system transistor 21A and the second system transistor 21B are electrically independent of each other and can be switched on and off independently. That is, the output transistor 20 is configured such that both the first system transistor 21A and the second system transistor 21B are turned on simultaneously. Alternatively, the output transistor 20 may be configured such that either the first system transistor 21A or the second system transistor 21B is turned on and the other is turned off.

[0043] When both the first-system transistor 21A and the second-system transistor 21B are turned on simultaneously, the channel utilization of the output transistor 20 increases and its on-resistance decreases. When either the first-system transistor 21A or the second-system transistor 21B is turned on while the other is turned off, the channel utilization of the output transistor 20 decreases and its on-resistance increases. In other words, the output transistor 20 consists of a switching device with variable on-resistance.

[0044] Referring to Figures 1 and 3, the semiconductor device 1 includes a control circuit 23 formed in the control region 7 to be electrically connected to the output transistor 20. The control circuit 23 may also be referred to as a "control IC". The control circuit 23 comprises various functional circuits and, together with the output transistor 20, constitutes an IPD (Intelligent Power Device). The IPD may also be referred to as an "IPM (Intelligent Power Module)", "IPS (Intelligent Power Switch)", "smart power driver", "smart MISFET (smart MOSFET)", or "protected MISFET (protected MOSFET)".

[0045] In this configuration, the control circuit 23 includes a gate control circuit 24, a current monitor circuit 25, an overcurrent protection circuit 26, an overtemperature protection circuit 27, an undervoltage malfunction prevention circuit 28, a load open detection circuit 29, an active clamp circuit 30, a power supply reverse connection protection circuit 31, a logic circuit 32, a test circuit 33, an amplification circuit 34, and a voltage clamp circuit 35. The control circuit 23 does not necessarily need to include all of these functional circuits simultaneously; it may include at least one of them.

[0046] The current monitoring circuit 25 may also be called the CS circuit (Current Sense circuit). The overcurrent protection circuit 26 may also be called the OCP circuit (Over Current Protection circuit). The overheating protection circuit 27 may also be called the TSD circuit (Thermal shut down circuit). The undervoltage malfunction prevention circuit 28 may also be called the UVLO circuit (Under Voltage Lock Out circuit). The load open detection circuit 29 may also be called the OLD circuit (Open Load Detection circuit). The power supply reverse connection protection circuit 31 may also be called the RBP circuit (Reverse Battery Protection circuit). The amplification circuit 34 may also be called the AMP circuit (Amplifier circuit).

[0047] The gate control circuit 24 is configured to generate gate signals that control the on / off state of the output transistor 20. Specifically, the gate control circuit 24 generates multiple gate signals that individually control the on / off state of multiple system transistors 21. In other words, in this configuration, the gate control circuit 24 generates a first gate signal that individually controls the on / off state of the first system transistor 21A, and a second gate signal that individually controls the on / off state of the second system transistor 21B, electrically independent of the first system transistor 21A.

[0048] The current monitoring circuit 25 generates a monitor current to monitor the output current Io of the output transistor 20 and outputs it to other circuits. For example, the monitoring circuit may include a transistor having a similar configuration to the output transistor 20 and be configured to generate a monitor current linked to the output current Io by being controlled on and off simultaneously with the output transistor 20. Of course, the current monitoring circuit 25 may also be configured to generate a monitor current linked to one or more system currents Is.

[0049] The overcurrent protection circuit 26 generates an electrical signal to control the gate control circuit 24 based on the monitored current from the current monitor circuit 25, and works in cooperation with the gate control circuit 24 to control the on / off state of the output transistor 20. For example, the overcurrent protection circuit 26 may be configured to determine that the output transistor 20 is in an overcurrent state when the monitored current exceeds a predetermined threshold, and to work in cooperation with the gate control circuit 24 to control some or all of the output transistor 20 (multiple system transistors 21) to an off state. Alternatively, the overcurrent protection circuit 26 may be configured to work in cooperation with the gate control circuit 24 to transition the output transistor 20 to normal operation when the monitored current falls below a predetermined threshold.

[0050] The overheat protection circuit 27 includes a first temperature-sensing device (e.g., a temperature-sensing diode) for detecting the temperature of the output region 6, and a second temperature-sensing device (e.g., a temperature-sensing diode) for detecting the temperature of the control region 7. The overheat protection circuit 27 generates an electrical signal to control the gate control circuit 24 based on a first temperature detection signal from the first temperature-sensing device and a second temperature detection signal from the second temperature-sensing device, and works in cooperation with the gate control circuit 24 to control the on / off state of the output transistor 20.

[0051] For example, the overheat protection circuit 27 may be configured to determine that the output region 6 is in an overheated state when the difference value between the first temperature detection signal and the second temperature detection signal exceeds a predetermined threshold, and to cooperate with the gate control circuit 24 to control some or all of the output transistors 20 (multiple system transistors 21) to an off state. Alternatively, the overheat protection circuit 27 may be configured to cooperate with the gate control circuit 24 to switch the output transistors 20 to normal operation when the difference value falls below a predetermined threshold.

[0052] The low-voltage malfunction prevention circuit 28 is configured to prevent various functional circuits within the control circuit 23 from malfunctioning when the starting voltage for starting the control circuit 23 is below a predetermined value. For example, the low-voltage malfunction prevention circuit 28 may be configured to start the control circuit 23 when the starting voltage is above a predetermined threshold voltage, and to stop the control circuit 23 when the starting voltage falls below the threshold voltage. The threshold voltage may have hysteresis characteristics.

[0053] The load open detection circuit 29 determines the electrical connection state of the inductive load L. For example, the load open detection circuit 29 may be configured to monitor the terminal voltage of the output transistor 20 and determine that the inductive load L is open when the terminal voltage exceeds a predetermined threshold. For example, the load open detection circuit 29 may be configured to determine that the inductive load L is open when the monitored current falls below a predetermined threshold.

[0054] Referring to Figure 5A, the active clamp circuit 30 is electrically connected to the main drain and at least one main gate of the output transistor 20 (for example, the system gate of the first transistor 21A). In the example in Figure 5A, the active clamp circuit 30 is electrically connected to the drain terminal 15 and the gate control circuit 24. The gate control circuit 24 has a control terminal 14 electrically connected to it.

[0055] The active clamp circuit 30 includes a group of diodes 9 formed by connecting multiple diodes D, each consisting of a Zener diode, in series. The active clamp circuit 30 also includes a pn junction diode 36 connected in reverse bias series to the diode group 9. The pn junction diode is a reverse current blocking diode that prevents reverse current from the output transistor 20.

[0056] The cathode of diode group 9 may be electrically connected to the drain terminal 15. In other words, the cathode of diode group 9 is connected to the drain terminal 15. The anode of diode group 9 may be connected to the gate control circuit 24 (control terminal 14). In other words, the anode of diode group 9 is connected to the gate control circuit 24 (control terminal 14).

[0057] Referring to Figures 1 and 3, the active clamp circuit 30 works in cooperation with the gate control circuit 24 to turn on part or all of the output transistor 20 when a back electromotive force due to an inductive load L is applied to the output transistor 20. Specifically, the output transistor 20 is controlled in several operating modes, including normal operation, first off operation, active clamp operation, and second off operation.

[0058] In normal operation, both the first-system transistor 21A and the second-system transistor 21B are controlled to be ON simultaneously. This increases the channel utilization rate of the output transistor 20 and reduces its on-resistance. In the first OFF operation, both the first-system transistor 21A and the second-system transistor 21B are controlled to be OFF simultaneously. This applies the back electromotive force caused by the inductive load L to both the first-system transistor 21A and the second-system transistor 21B.

[0059] Active clamp operation is an operation in which the output transistor 20 absorbs (consumes) the energy stored in the inductive load L, and is performed when the back electromotive force caused by the inductive load L exceeds a predetermined threshold voltage. In active clamp operation, the first transistor 21A is controlled from the off state to the on state, and at the same time, the second transistor 21B is controlled (maintained) in the off state.

[0060] The channel utilization rate of the output transistor 20 during active clamp operation is less than that of the output transistor 20 during normal operation. The on-resistance of the output transistor 20 during active clamp operation is greater than that of the output transistor 20 during normal operation. This suppresses a rapid temperature rise of the output transistor 20 during active clamp operation, improving its active clamp withstand capability.

[0061] The second off operation is performed when the back electromotive force falls below a predetermined threshold voltage. In the second off operation, the first transistor 21A is controlled from the ON state to the OFF state, and at the same time, the second transistor 21B is controlled (maintained) in the OFF state. In this way, the back electromotive force (energy) of the inductive load L is absorbed by a portion of the output transistor 20 (in this case, the first transistor 21A). Of course, during active clamp operation, the first transistor 21A may be controlled (maintained) in the OFF state, while the second transistor 21B may be controlled to the ON state.

[0062] The power supply reverse connection protection circuit 31 is configured to detect the reverse voltage when the power supply is connected in reverse and to protect the control circuit 23 and output transistor 20 from the reverse voltage (reverse current). The logic circuit 32 is configured to generate electrical signals that are supplied to various circuits within the control circuit 23.

[0063] The test circuit 33 is formed on the first main surface 3 so as to be electrically interposed between the input terminal 14b and the drain terminal 15, and is electrically connected to the input terminal 14b and the drain terminal 15. The test circuit 33 is formed to indirectly evaluate the electrical characteristics of the control circuit 23 during the manufacturing process. Preferably, the test circuit 33 is located in a region adjacent to the input terminal 14b in a plan view.

[0064] The amplification circuit 34 is configured to amplify detection signals input to the semiconductor device 1 from various sensors mounted on the vehicle (e.g., pressure sensors, inertial sensors, MR sensors, etc.) when the semiconductor device 1 is mounted on a vehicle.

[0065] Referring to Figure 5B, the voltage clamp circuit 35 may also be called an overvoltage protection circuit. The voltage clamp circuit 35 includes a diode group 9 which comprises multiple diodes D, each consisting of a Zener diode. Figure 5B shows only the portion of the voltage clamp circuit 35 related to the diode group 9.

[0066] The cathode of diode group 9 is connected to the drain terminal 15. The anode of diode group 9 is connected to the ground side (ground terminal 14a (control terminal 14) side).

[0067] The voltage clamp circuit 35 limits the voltage input to the control circuit 23 to a range from ground (0V) to a predetermined clamp voltage, even when an overvoltage is applied to the drain terminal 15. This prevents overvoltage from being input to the control circuit 23.

[0068] Referring to Figure 1, as described above, the semiconductor device 1 includes a diode formation region 8 partitioned in the inner part of the control region 7. The diode formation region 8 is located on the first main surface 3, spaced apart from the periphery of the control region 7. Diode groups 9 included in the voltage clamp circuit 35 and diode groups 9 included in the active clamp circuit 30 are formed in the diode formation region 8.

[0069] The diode group 9 will now be described. The diode group 9 may be at least one of the diode group 9 included in the voltage clamp circuit 35 and the diode group 9 included in the active clamp circuit 30. The diode group 9 is formed in the diode formation region 8 (Figure 1) set on the first main surface 3 of the control region 7 (Figure 1).

[0070] Figure 6 is a layout diagram of the first main surface 3 in the diode formation region 8. Figure 7 is a plan view of the diode formation region 8. Figure 8 is an enlarged view of the region enclosed by the dashed line VIII in Figure 6. Figure 9 is an enlarged view of the region enclosed by the dashed line IX in Figure 7. Figure 10 is a layout diagram of the first main surface 3 of the first diode element DS1 shown in Figure 6. Figure 11 is a cross-sectional view along the line XI-XI shown in Figure 9. Figure 12 is a cross-sectional view along the line XII-XII shown in Figure 9. Figure 13 is a layout diagram of the first main surface 3 of the second diode element DS2 shown in Figure 6. Figure 14 is a cross-sectional view along the line XIV-XIV shown in Figure 9. Figure 15 is a cross-sectional view along the line XV-XV shown in Figure 13. Figure 16A is a cross-sectional view along the line XVIA-XVIA shown in Figure 9. In Figures 7 and 9, hatching is applied to the connection wiring 80 for clarity (the same applies in Figure 16D, which will be described later).

[0071] Referring to Figures 6 and 7, one diode group 9 includes multiple diodes D connected in series in the reverse direction. The reverse voltages of the multiple diodes D in one diode group 9 are equivalent to each other. In this configuration, one diode group 9 includes 12 diodes D. The number of diodes D in one diode group 9 is just an example, and other numbers may be used. The diodes D in one diode group 9 may be called "clamp diodes".

[0072] As mentioned above, the cathode of diode group 9 is connected to the drain terminal 15. The anode of diode group 9 is connected to the gate control circuit 24 (Figure 5A) or the ground terminal 14a (Figure 5B). Of the multiple diodes D connected in series, the diode D closest to the cathode is sometimes called the drain diode DD. Of the multiple diodes D connected in series, the diode D closest to the anode is sometimes called the ground diode element (control terminal diode element) DG.

[0073] The number of diodes D in a single diode group 9 may differ between the diode group 9 in the active clamp circuit 30 (Figure 5A) and the diode group 9 in the voltage clamp circuit 35 (Figure 5B). The reverse voltages of the diodes D may differ between the diode group 9 in the active clamp circuit 30 and the diode group 9 in the voltage clamp circuit 35.

[0074] Multiple diodes D are formed in a diode formation region 8 set on the first main surface 3 of the control region 7. In this configuration, the diode formation region 8 is strip-shaped along the first direction X. In this configuration, there is one diode formation region 8. The diode formation region 8 may also be strip-shaped along the second direction Y. The diode formation region 8 is partitioned by a trench separation structure 60. There is one trench separation structure 60.

[0075] The trench isolation structure 60 surrounds the multiple diodes D. The trench isolation structure 60 electrically isolates the multiple diodes D from other areas of the control region 7. The trench isolation structure 60 may also be referred to as a "region isolation structure," a "DTI (deep trench isolation) structure," or an "internal isolation structure."

[0076] Referring to Figures 11, 12, and 14, the trench isolation structure 60 includes an isolation trench 61, an isolation insulating layer 62, and an isolation electrode 63. That is, the trench isolation structure 60 has a single electrode structure including a single electrode embedded in the isolation trench 61 with an insulator in between.

[0077] The separation trench 61 is excavated from the first main surface 3 toward the second main surface 4. The separation trench 61 is formed with a gap from the bottom of the drift region 11 toward the first main surface 3. The separation insulating layer 62 covers the wall surface of the separation trench 61. The separation insulating layer 62 may contain a silicon oxide film. The separation insulating layer 62 may contain a silicon oxide film made of the oxide of the chip 2, or a silicon oxide film formed by the CVD method. The separation electrode 63 is embedded in the separation trench 61 with the separation insulating layer 62 in between. The separation electrode 63 may contain conductive polysilicon.

[0078] The trench separation structure 60 has a trench width WT and a trench depth DT. The trench width WT is the width in the direction perpendicular to the direction in which the trench separation structure 60 extends in a plan view. The aspect ratio DT / WT of the trench separation structure 60 may be greater than 1 and less than or equal to 5. The aspect ratio DT / WT is the ratio of the trench depth DT to the trench width WT. It is preferable that the aspect ratio DT / WT is 2 or greater. It is preferable that the bottom wall of the trench separation structure 60 is spaced 1 μm to 5 μm from the bottom of the drift region 11.

[0079] Referring to Figures 8 and 9, the trench separation structure 60 has corners that connect the portions extending in the first direction X and the second direction Y in an arc shape (curved shape). In this embodiment, the four corners of the trench separation structure 60 are formed in an arc shape. Preferably, the corners of the trench separation structure 60 have a constant trench width WT along the arc direction.

[0080] Referring to Figure 11, etc., the separation trench 61 includes side walls and a bottom wall. The angle between the side walls of the separation trench 61 and the first main surface 3 within the chip 2 may be 90° or more and 92° or less. The separation trench 61 may be formed in a tapered shape, with the opening width narrowing from the opening towards the bottom wall. The corners of the bottom wall of the separation trench 61 are preferably formed in a curved shape. The entire bottom wall of the separation trench 61 may be formed in a curved shape toward the second main surface 4.

[0081] The isolation insulating layer 62 is formed on the wall surface of the isolation trench 61. Specifically, the isolation insulating layer 62 is formed in a film-like manner over the entire wall surface of the isolation trench 61, and partitions the recess space within the isolation trench 61. The isolation insulating layer 62 preferably contains a silicon oxide film. It is particularly preferable that the isolation insulating layer 62 contains a silicon oxide film made of the oxide of the chip 2.

[0082] The separation electrode 63 is embedded as an integrated member in the separation trench 61, with the separation insulating layer 62 in between. In this embodiment, the separation electrode 63 contains conductive polysilicon. A source potential is applied to the separation electrode 63. The separation electrode 63 has an electrode surface (separation electrode surface) that is exposed from the separation trench 61. The electrode surface of the separation electrode 63 may be curved and recessed toward the bottom wall of the separation trench 61. It is preferable that the electrode surface of the separation electrode 63 is spaced apart from the first main surface 3 to the bottom wall of the separation trench 61 with respect to the depth direction of the separation trench 61.

[0083] Referring to Figures 11, 12, and 14-16A, in the diode formation region 8, a first well region (first impurity region) 64 is formed on the surface layer of the first main surface 3. The first well region 64 is a p-type (first conductivity type) impurity region formed on the surface layer of the drift region 11 in the diode formation region 8. The first well region 64 extends in layers along the first main surface 3.

[0084] The first well region 64 is formed to be shallower than the trench separation structure 60 and has a bottom that is located on the first main surface 3 side of the bottom wall of the trench separation structure 60. Preferably, the bottom of the first well region 64 is located on the second main surface 4 side of the intermediate part of the depth range of the trench separation structure 60.

[0085] The first well region 64 is in contact with the trench isolation structure 60 at the outer periphery of the diode formation region 8. In this embodiment, the first well region 64 is not formed in a region outside the trench isolation structure 60.

[0086] Referring to Figures 14 to 16A, in this configuration, multiple diodes D are formed on the surface of the first well region 64. In this configuration, all of the multiple diodes D are Zener diodes. More specifically, all of the multiple diodes D are drift-less Zener diodes. In this configuration, the multiple diodes D are arranged in a strip along the first direction X. One diode D will be described below.

[0087] Referring to Figures 11, 12, and 14-16A, each diode D includes an n-type well region (second impurity region) 66 formed on the surface of a first well region 64, and a cathode region 67 and an anode region 68 formed on the surface of the n-type well region 66. Multiple n-type well regions 66 are formed at intervals in the first direction X.

[0088] One diode D includes an n-type well region 66 formed on the surface of the first well region 64, and an n-type cathode region 67 and a p-type anode region 68 formed on the surface of each n-type well region 66.

[0089] As described below, in this configuration, the anode region 68 has a rectangular shape with a longitudinal side in a plan view. Hereinafter, the longitudinal direction of the anode region 68 will be referred to as the first element direction X1, and the direction perpendicular to the first element direction X1 will be referred to as the second element direction Y1. In this configuration, the first element direction X1 and the second element direction Y1 coincide with the first direction X and the second direction Y, respectively.

[0090] The n-type well region 66 includes a second well region (first concentration region) 69 and a third well region (second concentration region) 70. The second well region 69 is an n-type (second conductivity type) impurity region formed on the surface of the first well region 64. The second well region 69 extends in layers along the first main surface 3.

[0091] The second well region 69 is formed inward from the trench separation structure 60. The outer edge of the second well region 69 is constant in the depth direction. The bottom of the second well region 69 may be formed in the region on the first main surface 3 side relative to the intermediate part of the trench separation structure 60.

[0092] Referring to Figures 10 and 13, the second well region 69 is a rectangular shape in plan view, with periphery aligned along the first element direction X1 and the second element direction Y1. The distances L2 (Figure 10) and L22 (Figure 13) of the second well region 69 in the first element direction X1 are longer than the distances L12 (Figure 10) and L32 (Figure 13) of the second well region 69 in the second element direction Y1, respectively.

[0093] Referring to Figures 11, 12, and 14-16A, the third well region 70 is an n-type impurity region formed on the surface of the second well region 69. The third well region 70 has a higher concentration of n-type impurities than the second well region 69.

[0094] The third well region 70 extends in layers along the first main surface 3. The third well region 70 is formed inward from the trench separation structure 60. The third well region 70 is formed inward from the first well region 64. The outer edge of the third well region 70 is constant in the depth direction.

[0095] The bottom of the third well region 70 may be formed in the region on the first main surface 3 side relative to the intermediate portion of the trench separation structure 60.

[0096] Referring to Figures 10 and 13, the third well region 70 is a rectangular shape in plan view, with periphery aligned along the first element direction X1 and the second element direction Y1. The distances L3 (first distance, Figure 10) and L23 (second distance, Figure 13) of the third well region 70 in the first element direction X1 are longer than the distances L13 (Figure 10) and L33 (Figure 13) of the third well region 70 in the second element direction Y1, respectively.

[0097] Referring to Figures 11, 12, and 14-16A, the third well region 70 is formed inward and toward the first main surface 3 from the first well region 64. In other words, the second well region 69 not only covers the bottom of the third well region 70 from below, but also surrounds the third well region 70. In other words, the second well region 69 has a surrounding portion 69a that encloses the sides of the third well region 70.

[0098] Referring to Figures 10 and 13, the surrounding portion 69a encloses the entire outer perimeter of the third well region 70. The surrounding portion 69a is exposed to the first main surface 3. The surrounding portion 69a has widths W1 and W21 in the first element direction X1. The surrounding portion 69a has widths W11 and W31 in the second element direction Y1. Widths W1, W11, W21 and W31 are constant in the depth direction.

[0099] In this configuration, each diode D contains one cathode region 67 and one anode region 68. In this configuration, the cathode region 67 surrounds the anode region 68 in a ring shape. The number of at least one of the cathode region 67 and anode region 68 may be multiple.

[0100] Referring to Figures 11, 12, and 14-16A, the cathode region 67 and anode region 68 are formed on the surface of the third well region 70. The cathode region 67 and anode region 68 are not formed on the surface of the second well region 69. The cathode region 67 and anode region 68 are in contact with the surface of the third well region 70. The cathode region 67 and anode region 68 form a pn junction with a portion of the third well region 70 in between.

[0101] In this configuration, the cathode region 67 and the anode region 68 are formed on the surface of the third well region 70 with a gap in both the first element direction X1 and the second element direction Y1.

[0102] The anode region 68 is exposed to the first main surface 3. The anode region 68 has a p-type impurity concentration that exceeds the p-type impurity concentration of the first well region 64. As described above, the anode region 68 has a rectangular shape with its longitudinal side in the first element direction X1 when viewed from above. The periphery of the anode region 68 is aligned with the first element direction X1 and the second element direction Y1.

[0103] The cathode region 67 is exposed to the first main surface 3. The cathode region 67 has an n-type impurity concentration that exceeds the n-type impurity concentration of the third well region 70. The cathode region 67 is formed in a quadrilateral ring shape along the first element direction X1 and the second element direction Y1. The cathode region 67 surrounds the anode region 68. In this configuration, the cathode region 67 surrounds the entire outer periphery of the anode region 68.

[0104] Referring to Figures 10 and 13, the anode region 68 has widths W3 (Figure 10) and W23 (Figure 13) in the first element direction X1. The anode region 68 has widths W13 (Figure 10) and W33 (Figure 13) in the second element direction Y1. Widths W3 and W23 are wider than widths W13 and W33, respectively. Widths W3 and W23 may be equal to or narrower than widths W13 and W33, respectively.

[0105] The cathode region 67 has widths W4 (Figure 10) and W24 (Figure 13) in the first element direction X1. The cathode region 67 has widths W14 and W34 in the second element direction Y1. In this embodiment, widths W4 and W24 are narrower than widths W14 and W34, respectively. Widths W4 and W24 may be equivalent to widths W14 and W34, or they may be wider than widths W14 and W34, respectively.

[0106] In other words, the cathode region 67 faces the anode region 68 in both the first element direction X1 and the second element direction Y1, with a portion of the third well region 70 in between.

[0107] The opposing spacing between the cathode region 67 and the anode region 68 in the first element direction X1 is spacing W5 (Figure 10) and spacing W25 (Figure 13). The opposing spacing between the cathode region 67 and the anode region 68 in the second element direction Y1 is spacing W15 (Figure 10) and spacing W35 (Figure 13).

[0108] In this configuration, spacings W5 and W25 are equivalent to spacings W15 and W35, respectively. Spacings W5 and W25 may be wider than spacings W15 and W35, or narrower than spacings W15 and W35, respectively.

[0109] In each diode D, the cathode potential is applied to the cathode region 67, and the anode potential is applied to the anode region 68. The third well region 70 is at the same potential as the cathode region 67. Therefore, in each diode D, the third well region 70 is at the cathode potential.

[0110] Referring to Figure 8, the semiconductor device 1 further includes a plurality of p-shaped guard ring regions 71 exposed on the first main surface 3. The plurality of guard ring regions 71 are strip-shaped and extend along the first direction X (first element direction X1) and the second direction Y (second element direction Y1).

[0111] In this configuration, the multiple guard ring regions 71 include a first guard ring region 72 and multiple second guard ring regions 73. The first guard ring region 72 and the multiple second guard ring regions are connected to each other. Therefore, the multiple second guard ring regions 73 are at the same potential as the first guard ring region 72.

[0112] Referring to Figures 11 and 14, the first guard ring region 72 is formed on the surface of the outer periphery of the first well region 64. The first guard ring region 72 is exposed to the first main surface 3. The first guard ring region 72 has a p-type impurity concentration that exceeds the p-type impurity concentration of the first well region 64. The first guard ring region 72 may have a p-type impurity concentration equivalent to the n-type impurity concentration of the cathode region 67.

[0113] Referring to Figures 8, 10, and 13, the first guard ring region 72 is formed in an annular shape along the trench separation structure 60 in a plan view. The first guard ring region 72 is formed with a gap inward from the trench separation structure 60. The first guard ring region 72 is band-shaped and extends along the first direction X (first element direction X1) and the second direction Y (second element direction Y1).

[0114] The first guard ring region 72 has two linear portions extending in the first direction X (first element direction X1). The two linear portions of the first guard ring region 72 sandwich a plurality of diodes D in the second element direction Y1.

[0115] In other words, one diode D faces each of the two linear portions of the first guard ring region 72 in the second element direction Y1. The distance between one diode D and the first guard ring region 72 is the distance W12 (first distance, Figure 10) and the distance W32 (second distance, Figure 13).

[0116] Referring to Figures 12, 15, and 16A, the multiple second guard ring regions 73 are formed on the surface of the first well region 64. The multiple second guard ring regions 73 are exposed to the first main surface 3.

[0117] The multiple second guard ring regions 73 have a p-type impurity concentration that exceeds the p-type impurity concentration of the first well region 64. Preferably, the multiple second guard ring regions 73 have a p-type impurity concentration equivalent to that of the first guard ring region 72. The multiple second guard ring regions 73 may also have a p-type impurity concentration equivalent to that of the n-type impurity concentration of the cathode region 67.

[0118] Each of the multiple second guard ring regions 73 is sandwiched between two diodes D that are facing each other. The multiple second guard ring regions 73 are strip-shaped and extend in directions that intersect (are perpendicular to) the opposing directions of the two diodes D.

[0119] In this configuration, the second guard ring region 73 is sandwiched in the first element direction X1 by two diodes D adjacent to each other in the first direction X. In this configuration, the number of second guard ring regions 73 sandwiched by the two diodes D is one. However, the number of second guard ring regions 73 sandwiched by the two diodes D may be two or more.

[0120] In this configuration, multiple second guard ring regions 73 are formed in a strip shape extending in the second element direction Y1 between two diodes D facing each other in the first element direction X1. Both ends of each second guard ring region 73 in the second element direction Y1 are connected to the first guard ring region 72.

[0121] In other words, in this configuration, one diode D is surrounded by two linear portions of the first guard ring region 72 and two second guard ring regions 73.

[0122] In other words, one diode D faces each of the two linear portions of the first guard ring region 72 in the direction Y1 of the second element. The distance between one diode D and the first guard ring region 72 is the distance W12 (Figure 10) and the distance W32 (Figure 13).

[0123] In other words, one diode D faces the second guard ring region 73 in the first element direction X1. The distance between one diode D and the second guard ring region 73 is the distance W2 (Figure 10) and the distance W22 (Figure 13).

[0124] Referring to Figures 11, 12, and 14-16A, the semiconductor device 1 includes a plurality of inner isolation structures 74 and a plurality of outer isolation structures 75 that selectively cover the first main surface 3 in the diode formation region 8.

[0125] Multiple inner isolation structures 74 and multiple outer isolation structures 75 are provided in a one-to-one relationship with each of the multiple diodes D. Each outer isolation structure 75 surrounds the outside of the corresponding inner isolation structure 74.

[0126] Let's describe one inner separation structure 74. The inner separation structure 74 is formed in an annular shape. Inside the inner separation structure 74, there is a region where the anode region 68 is exposed. In other words, the inner circumference of the inner separation structure 74 demarcates the outer circumference of the anode region 68.

[0127] An area is formed outside the inner separation structure 74 where the cathode region 67 is exposed. In other words, the outer circumference of the inner separation structure 74 demarcates the inner circumference of the cathode region 67.

[0128] Let's describe one outer separation structure 75. The outer separation structure 75 is formed in an annular shape that surrounds the inner separation structure 74. Inside the outer separation structure 75, there is a region where the cathode region 67 is exposed. In other words, the inner circumference of the outer separation structure 75 demarcates the outer circumference of the cathode region 67.

[0129] Referring to Figure 16A, two adjacent outer separation structures 75 form an area that exposes the second guard ring region 73. In this configuration, two adjacent outer separation structures 75 in the first element direction X1 (first direction X) form an area that exposes the second guard ring region 73. In other words, two adjacent outer separation structures 75 in the first element direction X1 (first direction X) demarcate the side edge of the second guard ring region 73 in the first element direction X1 (first direction X).

[0130] Referring to Figure 12, the semiconductor device 1 includes a main surface insulating layer 76 that selectively covers the first main surface 3 within the control region 7. The main surface insulating layer 76 may include a silicon oxide film. Preferably, the main surface insulating layer 76 includes a silicon oxide film made of the oxide of the chip 2. The main surface insulating layer 76 is not formed in the diode formation region 8.

[0131] Referring to Figures 11, 12, and 14, the semiconductor device 1 includes a field insulating layer 77 that selectively covers the first main surface 3 within the control region 7. The field insulating layer 77 is thicker than the main surface insulating layer 76. The field insulating layer 77 may have a thickness approximately equal to that of the isolation insulating layer 62. The field insulating layer 77 may contain a silicon oxide film. The field insulating layer 77 may contain a silicon oxide film made of the oxide of the chip 2, or a silicon oxide film formed by the CVD method.

[0132] The field insulating layer 77 covers the first main surface 3 along the inner wall of the trench separation structure 60 within the control area 7 and is connected to the main surface insulating layer 76. Outside the control area 7, the field insulating layer 77 covers the first main surface 3 along the outer wall of the trench separation structure 60 and is integrally connected to the separation insulating layer 62. The field insulating layer 77 is drawn out horizontally from the separation trench 61 along the first main surface 3.

[0133] Inside the field insulating layer 77, an area is formed in which the first guard ring region 72 is exposed. In other words, the field insulating layer 77 and the outer separation structure 75 form an area in which the first guard ring region 72 is exposed.

[0134] Referring to Figures 11, 12, and 14-16A, the aforementioned interlayer insulating layer 12 covers the trench isolation structure 60, cathode region 67, anode region 68, first guard ring region 72, second guard ring region 73, inner isolation structure 74, and outer isolation structure 75 in the control region 7.

[0135] The interlayer insulating layer 12 is formed of an insulator such as silicon oxide or silicon nitride. The interlayer insulating layer 12 may also be a USG (HDP-USG: High Density Plasma CVD-Undoped Silica Glass) film formed by a high-density plasma CVD method. The interlayer insulating layer 12 may include a plurality of insulating layers. The plurality of insulating layers may be separated based on the hierarchy of wiring layers formed on their respective main surfaces. For example, the insulating layer on which the first wiring layer of a multilayer wiring structure formed inside the interlayer insulating layer 12 is formed may be the first insulating layer, and the insulating layer on which the second wiring layer is formed may be the second insulating layer.

[0136] In this embodiment, the semiconductor device 1 includes a first wiring layer 78 disposed within the interlayer insulating layer 12. The first wiring layer 78 is formed on the first insulating layer 79. The first wiring layer 78 includes the following connecting wiring 80.

[0137] Referring to Figure 9, the semiconductor device 1 includes a plurality of connection lines 80 that connect two adjacent diodes D in series. In this configuration, one connection line 80 includes two cathode lines 81 and one anode line 82. The two cathode lines 81 and the one anode line 82 are connected to each other.

[0138] Referring to Figures 8 and 9, the semiconductor device 1 includes a plurality of first plug electrodes 83, a plurality of second plug electrodes 84, a plurality of third plug electrodes 85 (Figure 8), and a plurality of fourth plug electrodes 86 (Figures 11 and 14). The first plug electrodes 83, second plug electrodes 84, third plug electrodes 85, and fourth plug electrodes 86 are all embedded in the interlayer insulating layer 12.

[0139] Multiple first plug electrodes 83 and multiple second plug electrodes 84 correspond to one diode D.

[0140] Referring to Figures 11 and 14, the first plug electrode 83 is a plug electrode that transmits the cathode potential to the cathode region 67 of the corresponding diode D. The cathode wire 81 of the connecting wire 80 is connected to the upper end of the first plug electrode 83. The cathode wire 81 of the connecting wire 80 is electrically connected to the cathode region 67 of the corresponding diode D via the first plug electrode 83.

[0141] The first plug electrode 83 may be formed in a triangular, square, rectangular, polygonal, circular, or elliptical shape in a plan view. Of course, the first plug electrode 83 may also be formed in a strip shape (for example, rectangular) extending in the direction of the first element X1 or the direction of the second element Y1.

[0142] The second plug electrode 84 is a plug electrode that transmits the anode potential to the anode region 68 of the corresponding diode D. The anode wire 82 of the connecting wire 80 is connected to the upper end of the second plug electrode 84. The anode wire 82 of the connecting wire 80 is electrically connected to the anode region 68 of the corresponding diode D via the second plug electrode 84.

[0143] The second plug electrode 84 may be formed in a triangular, square, rectangular, polygonal, circular, or elliptical shape in a plan view. Of course, the second plug electrode 84 may also be formed in a strip shape (for example, rectangular) extending in the direction of the first element X1 or the direction of the second element Y1.

[0144] Multiple third plug electrodes 85 are plug electrodes that transmit ground potential to the first guard ring region 72. Multiple fourth plug electrodes 86 are plug electrodes that transmit ground potential to the trench separation structure 60.

[0145] The third plug electrode 85 and the fourth plug electrode 86 may be formed in a triangular, square, rectangular, polygonal, circular, or elliptical shape in a plan view. Of course, the third plug electrode 85 and the fourth plug electrode 86 may also be formed in a strip shape (for example, rectangular) extending in the direction of the first element X1 or the direction of the second element Y1.

[0146] Referring to Figures 11 and 14, the isolation electrode 63 of the trench isolation structure 60 is supplied with ground potential from the ground wiring 87 via the fourth plug electrode 86. The ground wiring 87 is electrically connected to the first guard ring region 72 via the third plug electrode 85. This supplies ground potential to the guard ring region 71.

[0147] Furthermore, as mentioned above, the first guard ring region 72 and the multiple second guard ring regions are connected to each other, and the multiple second guard ring regions 73 are at the same potential as the first guard ring region 72. Therefore, a ground potential is also applied to the multiple second guard ring regions 73. By applying a ground potential to the first guard ring region 72 and the multiple second guard ring regions 73, the first well region 64 is fixed at the ground potential.

[0148] Referring to Figure 12, the drain-side connection wiring 80A connected to the first diode D1 (drain-side diode DD) closest to the drain terminal 15 includes one cathode wiring 81 and a plurality of end plug electrodes 90 that electrically connect the cathode wiring 81 to the drift region 11.

[0149] The control region 7 includes an end plug placement region 91 adjacent to the diode formation region 8 on one side in the first direction X via a trench isolation structure 60. The end plug placement region 91 is an area insulated from the diode formation region 8. In the end plug placement region 91, the first main surface 3 is selectively covered by a main surface insulating layer 76. The end plug placement region 91 may also be an area insulated from the control region 7 on the first main surface 3. That is, the end plug placement region 91 may be an area insulated from both the diode formation region 8 and the control region 7.

[0150] In the end plug arrangement region 91, a high-concentration n-type region 92 is formed on the surface layer of the first main surface 3. The high-concentration region 92 is exposed to the first main surface 3. The concentration of n-type impurities in the high-concentration region 92 is higher than the concentration of n-type impurities in the first well region 64.

[0151] The upper ends of the multiple end plug electrodes 90 are in contact with the lower surface of the drain-side connection wiring 80A. The lower ends of the multiple end plug electrodes 90 penetrate the main surface insulating layer 76 and are connected to the high-concentration region 92 exposed on the first main surface 3. In other words, the multiple end plug electrodes 90 are connected to both the cathode wiring 81 and the drift region 11. As a result, the anode wiring 82 is electrically connected to the drift region 11 via the multiple end plug electrodes 90.

[0152] The drift region 11 is electrically connected to both the drain region 10 and the drain terminal 15. Therefore, the drain-side connection wiring 80A is electrically connected to the drain terminal 15 via the drift region 11 and the drain region 10. This applies the power supply potential to the drain-side connection wiring 80A.

[0153] Referring to Figures 6 and 7, the plurality of diodes D include at least one first diode D1 and at least one second diode D2. The second diode D2 has a shorter peripheral distance than the first diode D1. The first diode D1 and the second diode D2 have equivalent configurations to each other, except for the peripheral distance.

[0154] The first diode D1 and the second diode D2 have equivalent reverse voltages. An example of the reverse voltages of both the first diode D1 and the second diode D2 is, for example, approximately 5.4V. Of course, the reverse voltages of the first diode D1 and the second diode D2 are not limited to this example.

[0155] The second diode D2 has a lower element breakdown voltage than the first diode D1. The element breakdown voltages of the first diode D1 and the second diode D2 may be referred to as "guaranteed breakdown voltages". The element breakdown voltages of the first diode D1 and the second diode D2 are the well breakdown voltages between the third well region 70 (n-type well region 66) and the first well region 64, respectively, contained within the first diode D1 and the second diode D2.

[0156] The ratio of the element breakdown voltage of the second diode D2 to the element breakdown voltage of the first diode D1 may be 0.3 or more and less than 1.0. Preferably, this element breakdown voltage ratio is 0.7 or more and 0.9 or less. Examples of element breakdown voltages for the first diode D1 and the second diode D2 are approximately 70V and approximately 55V, respectively. Of course, the element breakdown voltages for the first diode D1 and the second diode D2 are not limited to this example.

[0157] There may be multiple second diodes D2. There may be multiple first diodes D1. The first diodes D1 may be connected to the drain terminal 15 side for all second diodes D2. The number of first diodes D1 may be less than the number of second diodes D2.

[0158] In this configuration, of the 12 diodes D connected in series, the two diodes D closer to the drain terminal 15 are the first diodes D1. The drain-side diode DD is the first diode D1.

[0159] Of the 12 diodes D connected in series, the 10 diodes D located on the opposite side of the drain terminal 15 are the second diode D2. The ground-side diode DG is the second diode D2.

[0160] The differences in dimensions between the first diode D1 and the second diode D2 will be explained in detail below.

[0161] Referring to FIGS. 10 and 13, the distance L21 (second distance, FIG. 13) in the first element direction X1 on the outer periphery of the second diode D2 is shorter than the distance L1 (first distance, FIG. 10) in the first element direction X1 on the outer periphery of the first diode D1 (L21 < L1). The distance ratio (L21 / L1) of the distance L21 to the distance L1 may be 0.1 or more and 1.0 or less. The distance ratio (L21 / L1) is preferably 0.3 or more and 1.0 or less.

[0162] The distance L31 (FIG. 13) in the second element direction Y1 on the outer periphery of the second diode D2 is shorter than the distance L11 (FIG. 10) in the second element direction Y1 on the outer periphery of the first diode D1 (L31 < L11). The distance ratio (L31 / L11) of the distance L31 to the distance L11 may be 0.1 or more and 1.0 or less. The distance ratio (L31 / L11) is preferably 0.3 or more and 1.0 or less.

[0163] The distance L22 (FIG. 13) in the first element direction X1 on the outer periphery of the second well region 69 in the second diode D2 is shorter than the distance L2 (FIG. 10) in the first element direction X1 on the outer periphery of the second well region 69 in the first diode D1 (L22 < L2). The distance ratio (L22 / L2) of the distance L22 to the distance L2 may be 0.1 or more and 1.0 or less. The distance ratio (L22 / L2) is preferably 0.3 or more and 1.0 or less.

[0164] The distance L32 (FIG. 13) in the second element direction Y1 on the outer periphery of the second well region 69 in the second diode D2 is shorter than the distance L12 (FIG. 10) in the second element direction Y1 on the outer periphery of the second well region 69 in the first diode D1 (L32 / L12). The distance ratio (L32 / L12) of the distance L32 to the distance L12 may be 0.1 or more and 1.0 or less. The distance ratio (L32 / L12) is preferably 0.3 or more and 1.0 or less.

[0165] The distance W22 (the fourth distance, FIG. 13) in the first element direction X1 between the outer periphery of the second well region 69 and the guard ring region 71 in the second diode D2 is narrower than the distance W2 (the third distance, FIG. 10) in the first element direction X1 between the outer periphery of the second well region 69 and the second guard ring region 73 in the first diode D1 (W22 < W2). The distance ratio (W22 / W2) of the distance W22 to the distance W2 may be 0.1 or more and 2.0 or less. The distance ratio (W22 / W2) is preferably 0.3 or more and 1.0 or less.

[0166] The distance W32 (FIG. 13) in the second element direction Y1 between the outer periphery of the second well region 69 and the guard ring region 71 in the second diode D2 is narrower than the distance W12 (FIG. 10) in the second element direction Y1 between the outer periphery of the second well region 69 and the second guard ring region 73 in the first diode D1 (W32 < W12). The distance ratio (W32 / W12) of the distance W32 to the distance W12 may be 0.1 or more and 2.0 or less. The distance ratio (W32 / W12) is preferably 0.3 or more and 1.0 or less.

[0167] The distance L23 (the fourth distance, FIG. 13) in the first element direction X1 of the outer periphery of the third well region 70 in the second diode D2 is shorter than the distance L3 (the third distance, FIG. 10) in the first element direction X1 of the outer periphery of the third well region 70 in the first diode D1 (L23 < L3). The distance ratio (L23 / L3) of the distance L23 to the distance L3 may be 0.1 or more and 1.0 or less. The distance ratio (L23 / L3) is preferably 0.3 or more and 1.0 or less.

[0168] The distance L33 (FIG. 13) in the second element direction Y1 of the outer periphery of the third well region 70 in the second diode D2 is shorter than the distance L13 (FIG. 10) in the second element direction Y1 of the outer periphery of the third well region 70 in the first diode D1 (L33 < L13). The distance ratio (L33 / L13) of the distance L33 to the distance L13 may be 0.1 or more and 1.0 or less. The distance ratio (L33 / L13) is preferably 0.3 or more and 1.0 or less.

[0169] The width W21 (second width, FIG. 13) of the surrounding portion 69a in the first element direction X1 of the second diode D2 is narrower than the width W1 (first width, FIG. 10) of the surrounding portion 69a in the first element direction X1 of the first diode D1 (W21 < W1). The width ratio (W21 / W1) of the width W21 to the width W1 may be 0.1 or more and 0.8 or less. Preferably, the width ratio (W21 / W1) is 0.2 or more and 0.6 or less.

[0170] The width W31 (FIG. 13) of the surrounding portion 69a in the second element direction Y1 of the second diode D2 is narrower than the width W11 (FIG. 10) of the surrounding portion 69a in the second element direction Y1 of the first diode D1 (W31 < W11). The width ratio (W31 / W11) of the width W31 to the width W11 may be 0.1 or more and 0.8 or less. Preferably, the width ratio (W31 / W11) is 0.2 or more and 0.6 or less.

[0171] The width W23 (FIG. 13) of the anode region 68 in the first element direction X1 of the second diode D2 is narrower than the width W3 (FIG. 10) of the anode region 68 in the first element direction X1 of the first diode D1 (W23 < W3). The interval W23 may be the same as the interval W3. The width ratio (W23 / W3) of the width W23 to the width W3 may be 0.1 or more and 1.0 or less. Preferably, the width ratio (W23 / W3) is 0.3 or more and 1.0 or less.

[0172] The width W33 (FIG. 13) of the anode region 68 in the second element direction Y1 of the second diode D2 is narrower than the width W13 (FIG. 10) of the anode region 68 in the second element direction Y1 of the first diode D1 (W33 < W13). The interval W33 may be the same as the interval W13. The width ratio (W33 / W13) of the width W33 to the width W13 may be 0.1 or more and 1.0 or less. Preferably, the width ratio (W33 / W13) is 0.3 or more and 1.0 or less.

[0173] The width W24 (FIG. 13) of the cathode region 67 of the second diode D2 in the first device direction X1 is narrower than the width W4 (FIG. 10) of the cathode region 67 of the first diode D1 in the first device direction X1 (W24 < W4). The interval W24 may be the same as the interval W4. The width ratio (W24 / W4) of the width W24 to the width W4 may be 0.1 or more and 1.0 or less. The width ratio (W24 / W4) is preferably 0.3 or more and 1.0 or less.

[0174] The width W34 (FIG. 13) of the cathode region 67 of the second diode D2 in the second device direction Y1 is narrower than the width W14 (FIG. 10) of the cathode region 67 of the first diode D1 in the second device direction Y1 (W34 < W14). The interval W34 may be the same as the interval W14. The width ratio (W34 / W14) of the width W34 to the width W14 may be 0.1 or more and 1.0 or less. The width ratio (W34 / W14) is preferably 0.3 or more and 1.0 or less.

[0175] The interval W25 (FIG. 13) between the cathode region 67 and the anode region 68 of the second diode D2 in the first device direction X1 is narrower than the interval W5 (FIG. 10) between the cathode region 67 and the anode region 68 of the first diode D1 in the first device direction X1 (W25 < W5). The interval W25 may be the same as the interval W5. The width ratio (W25 / W5) of the width W25 to the width W5 may be 0.1 or more and 1.0 or less. The width ratio (W25 / W5) is preferably 0.3 or more and 1.0 or less.

[0176] The interval W35 (FIG. 13) between the cathode region 67 and the anode region 68 of the second diode D2 in the second device direction Y1 is narrower than the interval W15 (FIG. 10) between the cathode region 67 and the anode region 68 of the first diode D1 in the second device direction Y1 (W35 < W15). The interval W35 may be the same as the interval W15. The width ratio (W35 / W15) of the width W35 to the width W15 may be 0.1 or more and 1.0 or less. The width ratio (W35 / W15) is preferably 0.3 or more and 1.0 or less.

[0177] Referring to FIG. 8, two adjacent first diodes D1 face each other in the first direction X (first element direction X1) with an interval W6 therebetween. Two adjacent second diodes D2 face each other in the first direction X (first element direction X1) with an interval W26 therebetween. The interval W26 is narrower than the interval W6 (W26 < W6). The width ratio (W26 / W6) of the width W26 to the width W6 may be 0.1 or more and 2.0 or less. Preferably, the width ratio (W26 / W6) is 0.3 or more and 1.0 or less.

[0178] As described above, in this embodiment, one diode D is surrounded by two straight portions of the first guard ring region 72 and two second guard ring regions 73. In this specification, one diode D, the guard ring region 71 (two straight portions of the first guard ring region 72 and two second guard ring regions 73) surrounding the periphery of the diode D, and the region between the outer periphery of one diode D and the outer periphery of the guard ring region 71 in the surface layer portion of the first main surface 3 are collectively referred to as one diode element DS.

[0179] The guard ring region 71 (two straight portions of the first guard ring region 72 and two second guard ring regions 73) forms the element boundary B (FIG. 8) of the first main surface 3 in a plan view and partitions the diode element DS.

[0180] The diode element DS will be described below.

[0181] Referring to FIGS. 6 and 7, the semiconductor device 1 includes a plurality (for example, 12) of diode elements DS arranged in the first direction X. Two diode elements DS adjacent to each other in the first direction X are in contact with each other. That is, two adjacent diode elements DS share the element boundary B (FIG. 8).

[0182] The plurality of diode elements DS includes at least one first diode element DS1 and at least one second diode element DS2. The outer peripheral distance of one second diode element DS2 is shorter than that of one first diode element DS1.

[0183] Referring to Figures 8 and 10, one first diode element DS1 includes one first diode D1, a guard ring region 71 surrounding the first diode D1, and a region on the surface of the first main surface 3 between the outer circumference of the first diode D1 and the guard ring region 71.

[0184] The first diode element DS1 has a rectangular shape in plan view. The two linear portions of the first guard ring region 72 surrounding the first diode D1 and the two second guard ring regions 73 constitute the four sides (element boundary B) of the first diode element DS1 in plan view. The four sides of the first diode element DS1 are aligned along both the first element direction X1 and the second element direction Y1.

[0185] The first diode element DS1 has a distance L5 in the first element direction X1. The first diode element DS1 has a distance L15 in the second element direction Y1. In this embodiment, distance L5 is longer than distance L15 (L5 > L15).

[0186] The first diode element DS1 is formed with a gap inward from the trench isolation structure 60.

[0187] Two adjacent first diode elements DS1 in the first direction X (first element direction X1) are in contact with each other. That is, two adjacent first diode elements DS1 share the element boundary B.

[0188] Referring to Figures 8 and 13, one second diode element DS2 includes one second diode D2, a guard ring region 71 surrounding the second diode D2, and a region on the surface of the first main surface 3 between the outer circumference of the second diode D2 and the guard ring region 71.

[0189] The second diode element DS2 has a rectangular shape in plan view. The two linear portions of the first guard ring region 72 surrounding the second diode D2 and the two second guard ring regions 73 constitute the four sides (element boundary B) of the second diode element DS2 in plan view. The four sides of the second diode element DS2 are aligned along both the first element direction X1 and the second element direction Y1.

[0190] The second diode element DS2 has a distance L25 in the direction X1 of the first element. The second diode element DS2 has a distance L35 in the direction Y1 of the second element. In this configuration, distance L25 is longer than distance L35 (L25 > L35).

[0191] The distance L25 (Figure 13) of the second diode element DS2 in the first element direction X1 is shorter than the distance L5 (Figure 10) of the first diode element DS1 in the first element direction X1. The distance L35 (Figure 13) of the second diode element DS2 in the second element direction Y1 is shorter than the distance L15 (Figure 10) of the first diode element DS1 in the second element direction Y1.

[0192] The second diode element DS2 is formed with a gap inward from the trench isolation structure 60. The gap between the second diode element DS2 and the trench isolation structure 60 in the second direction Y (second element direction Y1) is wider than the gap between the first diode element DS1 and the trench isolation structure 60 in the second direction Y (second element direction Y1).

[0193] Two adjacent second diode elements DS2 in the first direction X are in contact with each other. That is, two adjacent second diode elements DS2 share the element boundary B.

[0194] Referring to Figure 16A, the first diode element DS1 and the second diode element DS2, which are adjacent in the first direction X, are in contact with each other. That is, the adjacent first diode element DS1 and the second diode element DS2 share the element boundary B.

[0195] The area ratio of the planar area of ​​one first diode element DS1 to one second diode element DS2 may be 0.2 or more and 0.8 or less. This area ratio may also be 0.3 or more and 0.6 or less. More preferably, it may be 0.4 or more and 0.5 or less.

[0196] Referring to Figure 6, etc., the clamp circuit (active clamp circuit 30 and voltage clamp circuit 35) protects the object from back electromotive force by limiting a predetermined clamp voltage when back electromotive force is input to the object to be protected. This clamp voltage is determined by the reverse voltage (BVz) and number of diodes D connected in series in diode group 9.

[0197] For example, consider a case where a clamp voltage of approximately 64.8V is achieved by connecting diodes D with BVz = 5.4V in series. In this case, the number of diodes D connected in series is 12.

[0198] The cathode potential applied to the 12 diodes D included in diode group 9 decreases as you move away from the drain terminal 15 (from the drain-side diode DD (Figure 6, etc.) towards the ground-side diode DG (Figure 6, etc.)).

[0199] Figure 16B is a schematic diagram showing the electrical configuration of semiconductor device 1.

[0200] Referring to Figure 16B, the 12 diodes D included in diode group 9 are designated as "No. 1" to "No. 12" in order from the drain terminal 15 side. In this case, the potentials applied to the 12 diodes D ("No. 1" to "No. 12") are 64.8V, 59.4V, 54V, 48.6V, 43.2V, 37.8V, 32.4V, 27V, 21.6V, 16.2V, 10.8V, and 5.4V, respectively.

[0201] As described above, each of the diodes D includes multiple n-type well regions 66 and multiple cathode regions 67 and anode regions 68 formed on the surface of the first well region 64. In each diode D, the third well region 70 (n-type well region 66) is at the cathode potential.

[0202] Each of the multiple diodes D is required to have an element breakdown voltage that exceeds the cathode potential. This element breakdown voltage is the inter-well breakdown voltage between the third well region 70 (n-type well region 66) and the first well region 64. In this specification, the element breakdown voltage of diode D is referred to as the element breakdown voltage of the diode element DS (diode element DS containing diode D).

[0203] In this configuration, the twelve diode elements DS consist of two first diode elements DS1 and ten second diode elements DS2, which have a shorter peripheral distance than the first diode elements DS1. The element breakdown voltage of the second diode elements DS2 is lower than that of the first diode elements DS1. In the example in Figure 16B, an example of the element breakdown voltages of the first diode elements DS1 and the second diode elements DS2 is approximately 70V and approximately 55V, respectively.

[0204] Of the 12 diode elements DS, the two diode elements DS closer to the drain terminal 15 are the first diode elements DS1. In other words, the diode elements DS corresponding to diodes "No. 1" and "No. 2" (hereinafter sometimes referred to as "diode elements DS of "No. 1" and "No. 2") are the first diode elements DS1.

[0205] The cathode potentials applied to these two diode elements DS are 64.8V and 59.4V, respectively. Since the element breakdown voltage of the first diode element DS1 is approximately 70V, the element breakdown voltage exceeds the cathode potential. In other words, it satisfies the element breakdown voltage requirements for diode elements DS "No. 1" and "No. 2".

[0206] It is not advisable to apply the second diode element DS2 to diode elements DS No. 1 and DS No. 2. This is because the element breakdown voltage of the second diode element DS2 is approximately 55V, and the element breakdown voltage falls below the cathode potential.

[0207] On the other hand, of the 12 diode elements DS, the 10 diode elements DS located on the opposite side of the drain terminal 15 are the second diode elements DS2. In other words, the diode elements DS corresponding to the 10 diodes "No. 3" to "No. 12" are the second diode elements DS2.

[0208] The cathode potential applied to these 10 diode elements DS is in the range of 5.4V to 54V. The element breakdown voltage of the second diode element DS2 is approximately 55V. The element breakdown voltage of the second diode element DS2 exceeds the cathode potential applied to diode elements DS No. 3 to No. 12. In other words, the element breakdown voltage of the second diode element DS2 satisfies the element breakdown voltage required for diode elements DS No. 3 to No. 12.

[0209] Conventionally, for example, in order to improve the element breakdown voltage of multiple diode elements, it is conceivable to use elements with high element breakdown voltage (high-voltage elements) for all of the multiple diode elements.

[0210] However, high-voltage elements have a relatively large surface area. Therefore, if high-voltage elements are used for all of the multiple diode elements DS, there is a problem in that the total surface area of ​​the multiple diode elements increases.

[0211] According to the semiconductor device 1, the plurality of diode elements DS include at least one first diode element DS1 and at least one second diode element DS2 having a shorter peripheral distance than the first diode element DS1. The first diode element DS1 is connected to the drain terminal 15 side relative to the second diode element DS2.

[0212] In other words, the first diode element DS1, which has a relatively large peripheral distance, is positioned closer to the drain terminal 15. The second diode element DS2, which has a relatively small peripheral distance, is positioned closer to the opposite side of the drain terminal 15. The element breakdown voltage of the diode element DS tends to decrease as the peripheral distance decreases. Therefore, the second diode element DS2 may have a lower element breakdown voltage than the first diode element DS1.

[0213] The diode element DS1 with a high element breakdown voltage is only necessary for diode elements DS with a high cathode potential; it is not necessarily required for diode elements DS with a low cathode potential. Furthermore, the cathode potential applied to the 12 diode elements DS decreases as you move away from the drain terminal 15.

[0214] Therefore, by applying the first diode element DS1 to the diode elements DS closer to the drain terminal 15, and the second diode element DS2 to some of the other diode elements DS, the required element breakdown voltage for each individual diode element DS can be met. Furthermore, by applying the second diode element DS2, the overall surface area of ​​the multiple diode elements DS can be reduced.

[0215] As a result, in clamp circuits 30 and 35, the overall flat area of ​​multiple diode elements DS can be reduced while satisfying the voltage withstand voltage requirements for each individual diode element DS.

[0216] In this configuration, the first diode element DS1 and the second diode element DS2 have equivalent reverse voltages. Therefore, a diode group 9 can be obtained by connecting multiple diode elements DS having the same reverse voltage in reverse.

[0217] Furthermore, in this configuration, the second diode element DS2 has a lower element breakdown voltage than the first diode element DS1. In other words, the first diode element DS1, which has a higher element breakdown voltage, is positioned closer to the drain terminal 15. The second diode element DS2, which has a lower element breakdown voltage, is positioned closer to the opposite side of the drain terminal 15.

[0218] Furthermore, in this configuration, the first diode element DS1 is connected to the drain terminal 15 side for all second diode elements DS2. In other words, the first diode element DS1 is not positioned on the side opposite to the drain terminal 15. Therefore, the overall planar area of ​​the multiple diode elements DS can be further reduced.

[0219] Furthermore, in this configuration, the number of first diode elements DS1 is less than the number of second diode elements DS2. Therefore, the total planar area of ​​the multiple diode elements DS can be further reduced.

[0220] Figure 16C shows a first modified example in which the layout of the second diode element DS2 has been changed, and corresponds to Figure 13.

[0221] The second diode element DS2 (second diode D2) shown in Figure 16C differs from the second diode element DS2 (second diode D2) shown in Figure 13 in the dimensions of the cathode region 67 and the anode region 68. The other configurations are the same as the second diode element DS2 shown in Figure 13.

[0222] The anode region 68 has a width W63 (fourth width) in the first element direction X1. The anode region 68 has a width W73 in the second element direction Y1. In this embodiment, width W63 is wider than width W73. Width W63 may be equal to width W73, or it may be narrower than width W73.

[0223] The width W63 is equivalent to the width W3 (third width, Figure 10) of the anode region 68 in the first diode D1 in the first element direction X1 (W63=W3). The width W73 is equivalent to the width W13 (Figure 10) of the anode region 68 in the first diode D1 in the second element direction Y1 (W73=W13).

[0224] The cathode region 67 has a width W64 (sixth width) in the first element direction X1. The cathode region 67 has a width W74 in the second element direction Y1. In this embodiment, width W64 is narrower than width W74. Width W64 may be equal to width W74, or it may be wider than width W74.

[0225] The width W64 is equivalent to the width W4 (5th width, Figure 10) of the cathode region 67 in the first diode D1 in the first element direction X1 (W64=W4). The width W74 is equivalent to the width W14 (Figure 10) of the cathode region 67 in the first diode D1 in the second element direction Y1 (W74=W14).

[0226] The opposing distance (second distance) between the cathode region 67 and the anode region 68 in the first element direction X1 is distance W65. The opposing distance between the cathode region 67 and the anode region 68 in the second element direction Y1 is distance W75. Distance W75 is equivalent to distance W65. Distance W75 may be wider or narrower than distance W65.

[0227] The spacing W65 is equivalent to the spacing W5 (first spacing, Figure 10) in the first element direction X1 between the cathode region 67 and the anode region 68 of the first diode D1 (W65=W5). The spacing W75 is equivalent to the spacing W15 (Figure 10) in the second element direction Y1 between the cathode region 67 and the anode region 68 of the first diode D1 (W75=W15).

[0228] Figure 16D is a diagram showing a second modified example in which multiple diode elements DS include a third diode element DS3, and corresponds to Figure 7. Figure 16E is a layout diagram of the first main surface 3 of the third diode element DS3 shown in Figure 16D.

[0229] In the second modified example shown in Figure 16D, the plurality of diodes D formed in the diode formation region 8 include at least one first diode D1, at least one second diode (first element) D2, and at least one third diode (second element) D3. The third diode D3 has a shorter outer circumference than the second diode D2. The first diode D1, the second diode D2, and the third diode D3 have equivalent configurations to each other, except for the outer circumference distance.

[0230] The first diode D1, the second diode D2, and the third diode D3 have equivalent reverse voltages to each other. An example of the reverse voltage of each of the first diode D1, the second diode D2, and the third diode D3 is, for example, approximately 5.4V.

[0231] The third diode D3 has a lower element breakdown voltage than the second diode D2. The ratio of the element breakdown voltage of the third diode D3 to that of the second diode D2 may be 0.5 or more and less than 1.0. If the element breakdown voltages of the first diode D1 and the second diode D2 are approximately 70V and approximately 55V, respectively, then the element breakdown voltage of the third diode D3 is approximately 30V. Of course, the element breakdown voltages of the first diode D1, the second diode D2, and the third diode D3 are not limited to this example.

[0232] In this configuration, of the 12 diodes D connected in series, the two diodes D closer to the drain terminal 15 are the first diode D1. Of the 12 diodes D, the five diodes D closer to the opposite side of the drain terminal 15 are the third diode D3. The ground-side diode DG is the third diode D3. Of the 12 diodes D, the five diodes D positioned between the first diode D1 and the third diode D3 are the second diode D2.

[0233] The difference between the second modified example shown in FIG. 16D and the embodiment shown in FIG. 6 etc. lies in that, among the ten diodes D from "No. 3" to "No. 12", the diodes from "No. 8" to "No. 12" are changed from the second diode D2 to the third diode D3. The five diodes D from "No. 3" to "No. 7" are the second diode D2, similar to the embodiment shown in FIG. 6 etc.

[0234] Referring to FIG. 16E, the distance L42 in the first element direction X1 of the outer periphery of the second well region 69 in the third diode D3 is shorter than the distance L22 (FIG. 13) in the first element direction X1 of the outer periphery of the second well region 69 in the second diode D2 (L42 < L22). The distance L52 in the second element direction Y1 of the outer periphery of the second well region 69 in the third diode D3 is shorter than the distance L32 (FIG. 13) in the second element direction Y1 of the outer periphery of the second well region 69 in the second diode D2 (L52 < L32).

[0235] The interval W42 in the first element direction X1 between the outer periphery of the second well region 69 and the guard ring region 71 in the third diode D3 is narrower than the interval W22 in the first element direction X of the outer periphery of the second well region 69 and the second guard ring region 73 in the second diode D2 (W42 < W22). The interval W52 in the second element direction Y1 between the outer periphery of the second well region 69 and the guard ring region 71 in the third diode D3 is narrower than the interval W32 (FIG. 13) in the second element direction Y1 between the outer periphery of the second well region 69 and the second guard ring region 73 in the second diode D2 (W52 < W32).

[0236] The distance L43 (FIG. 13) in the first element direction X1 of the outer periphery of the third well region 70 in the third diode D3 is shorter than the distance L23 (FIG. 13) in the first element direction X1 of the outer periphery of the third well region 70 in the second diode D2 (L43 < L23). The distance L53 in the second element direction Y1 of the outer periphery of the third well region 70 in the third diode D3 is shorter than the distance L33 (FIG. 13) in the second element direction Y1 of the outer periphery of the third well region 70 in the second diode D2 (L53 < L33).

[0237] The width W41 of the surrounding portion 69a of the third diode D3 in the first element direction X1 is narrower than the width W21 (FIG. 13) of the surrounding portion 69a of the second diode D2 in the first element direction X1 (W41 < W21). The width W51 of the surrounding portion 69a of the third diode D3 in the second element direction Y1 is narrower than the width W31 (FIG. 13) of the surrounding portion 69a of the first diode D1 in the second element direction Y1 (W51 < W31).

[0238] The width W43 of the anode region 68 of the third diode D3 in the first element direction X1 is narrower than the width W23 (FIG. 13) of the anode region 68 of the second diode D2 in the first element direction X1 (W43 < W23). The width W53 of the anode region 68 of the third diode D3 in the second element direction Y1 is narrower than the width W33 (FIG. 13) of the anode region 68 of the second diode D2 in the second element direction Y1 (W53 < W33).

[0239] The width W44 of the cathode region 67 of the third diode D3 in the first element direction X1 is narrower than the width W24 (FIG. 13) of the cathode region 67 of the second diode D2 in the first element direction X1 (W44 < W24). The interval W44 may be the same as the interval W24. The width Ws4 of the cathode region 67 of the third diode D3 in the second element direction Y1 is narrower than the width W34 (FIG. 13) of the cathode region 67 of the second diode D2 in the second element direction Y1 (W54 < W3s4). The interval W54 may be the same as the interval W34.

[0240] The interval W45 between the cathode region 67 and the anode region 68 of the third diode D3 in the first element direction X1 is narrower than the interval W25 (FIG. 13) between the cathode region 67 and the anode region 68 of the second diode D2 in the first element direction X1 (W45 < W25). The interval W45 may be the same as the interval W25. The interval W55 between the cathode region 67 and the anode region 68 of the third diode D3 in the second element direction Y1 is narrower than the interval W35 (FIG. 13) between the cathode region 67 and the anode region 68 of the second diode D2 in the second element direction Y1 (W55 < W35). The interval W55 may be the same as the interval W35.

[0241] One third diode element DS3 includes one third diode D3, a guard ring region 71 surrounding the periphery of the third diode D3, and a region between the outer periphery of the third diode D3 and the guard ring region 71 in the surface layer portion of the first main surface 3.

[0242] In a plan view, the third diode element DS3 has a rectangular shape. Two straight portions of the first guard ring region 72 surrounding the periphery of the third diode D3 and two second guard ring regions 73 are the four side edges (element boundary B) of the third diode element DS3 in a plan view. The four side edges of the third diode element DS3 are along both the first element direction X1 and the second element direction Y1.

[0243] The distance L45 in the first element direction X1 of the outer periphery of the third diode element DS3 is shorter than the distance L25 (FIG. 13) in the first element direction X1 of the outer periphery of the second diode D2 (L45 < L25). The distance L55 in the second element direction Y1 of the outer periphery of the third diode element DS3 is shorter than the distance L35 (FIG. 13) in the second element direction Y1 of the outer periphery of the second diode element DS2 (L55 < L35).

[0244] That is, in the second modification shown in FIGS. 16D and 16E, the twelve diode elements DS include two first diode elements DS1, five second diode elements DS2, and five third diode elements DS3 having a shorter outer periphery distance than the second diode element DS2.

[0245] There may be a plurality of third diode elements DS3. All the third diode elements DS3 may be arranged closer to the side opposite to the drain terminal 15 with respect to all the second diode elements DS2. The number of the third diode elements DS3 may be the same as the number of the second diode elements DS2. The number of the third diode elements DS3 may be less than the number of the second diode elements DS2, or may be more than the number of the second diode elements DS2.

[0246] Of the 12 diode elements DS, the five diode elements DS located on the opposite side of the drain terminal 15 are the third diode elements DS3. In other words, of the diodes labeled "No. 1" to "No. 12", the five diode elements DS corresponding to diodes "No. 8" to "No. 12" are the third diode elements DS3.

[0247] The cathode potential applied to these five diode elements DS is in the range of 5.4V to 27V. The element breakdown voltage of the third diode element DS3 is approximately 30V. The element breakdown voltage of the third diode element DS3 exceeds the cathode potential applied to diode elements DS No. 8 to No. 12. In other words, the element breakdown voltage of the third diode element DS3 satisfies the element breakdown voltage required for diode elements DS No. 8 to No. 12.

[0248] In the embodiments shown in Figures 1 to 16C, a first form of the array layout of the first diode element DS1 and the second diode element DS2 was described. Hereafter, variations of the array layout examples of the first diode element DS1 and the second diode element DS2 will be described with reference to Figures 17 to 23.

[0249] In the second to sixth embodiments, multiple diode elements DS are arranged in a matrix along the first direction X and the second direction Y within the diode formation region 8. Any two adjacent diode elements DS in the first direction X and the second direction Y are in contact with each other. That is, two adjacent diode elements DS share a common element boundary B.

[0250] Figure 17 shows a second configuration of the array layout of the first diode element DS1 and the second diode element DS2.

[0251] In the second embodiment, specifically, 14 diode elements DS are arranged in a 5x3 grid. Of the five columns extending in the first direction X, the outermost column in the second direction Y (the uppermost column in Figure 17) has two first diode elements DS1 arranged in the first direction X. In the remaining four columns, each has three first diode elements DS1 arranged in the first direction X.

[0252] For convenience, the five columns extending in the first direction X will be referred to as row 1, row 2, row 3, row 4, and row 5, starting from the furthest side (the same will apply in the descriptions of the second to sixth forms below).

[0253] The first diode element DS1 is included only in the first row, and not in rows 2 through 5. The second diode element DS2 is included only in rows 2 through 5, and not in row 1. In other words, the two first diode elements DS1 and the twelve second diode elements DS2 are arranged so that they are included in different columns from each other.

[0254] In the first row, one element boundary B between the two first diode elements DS1 and two element boundaries B between the three second diode elements DS2 in the second row and beyond are offset in the first direction X. That is, the one first diode element DS1 in the first row and the two second diode elements DS2 in the second row and beyond are facing each other in the second direction Y.

[0255] Of the twelve second diode elements DS2, two are not electrically connected to the first diode element DS1 or the other second diode elements DS2. In other words, these two second diode elements DS2 are not included in diode group 9. These second diode elements DS2 are diode elements DSA used in other circuits.

[0256] In other words, in the second embodiment, the multiple diode elements DS connected in series with each other include two first diode elements DS1 and ten diode elements DS2.

[0257] As shown in Figure 17, multiple diode elements DS are connected in series with multiple connecting wires 80. The multiple connecting wires 80 connect the three second diode elements DS2 in each column in a meandering manner in a plan view, from the first row to the fifth row.

[0258] The first diode element DS1 closest to the drain terminal 15 (the first diode element DS1 corresponding to the drain-side diode DD) is positioned towards one side of the first direction X (the right side in Figure 17) in the first row. The drain-side connection wiring 80A is connected to this first diode element DS1 (drain-side diode DD).

[0259] The second diode element DS2 (ground-side diode DG), which is furthest from the drain terminal 15, is located at one end of the first direction X (right side in Figure 17) in the fifth row. One end of the opposite-side connection wiring 80B is connected to this second diode element DS2. The other end of the opposite-side connection wiring 80B is electrically connected to either the gate control circuit 24 side (Figure 5A) or the ground terminal 14a side (Figure 5B).

[0260] The two other diode elements (DSA) are placed in the remaining positions in the fifth row.

[0261] Figure 18 shows a third configuration of the array layout of the first diode element DS1 and the second diode element DS2. Figure 19 is an enlarged cross-sectional view along the line XIX-XIX shown in Figure 18.

[0262] The array layout of the first diode element DS1 and the second diode element DS2 in the third embodiment is the same as the array layout in the second embodiment (Figure 17).

[0263] Multiple diode elements DS are connected in series with each other by multiple connecting wires 80. The multiple connecting wires 80 extend along the periphery of the diode formation region 8 so as to surround the second diode element DS2 (ground-side diode DG) that is furthest away from the drain terminal 15.

[0264] The second diode element DS2 (ground-side diode DG), which is furthest from the drain terminal 15, is positioned in the center of the first direction X, for example, in the fourth row. The opposite-side connection wiring 80C, included in the second wiring layer 100 (see Figure 19), is connected to this second diode element DS2. The other end of the opposite-side connection wiring 80C is connected to either the gate control circuit 24 side (Figure 5A) or the ground terminal 14a side (Figure 5B).

[0265] Multiple connection wires 80 connect multiple second diode elements DS2 in a spiral pattern, with the second diode element DS2 including the ground diode DG as the endpoint. In other words, multiple second diode elements DS2 are arranged in a spiral pattern.

[0266] The two other diode elements, DSAs, are located in the second row.

[0267] Referring to Figure 19, in this embodiment, the interlayer insulating layer 12 includes a second insulating layer 101 formed on the first insulating layer 79. The semiconductor device 1 also includes a second wiring layer 100 disposed within the interlayer insulating layer 12. The second wiring layer 100 is formed on the second insulating layer 101. The opposite-side connection wiring 80C is included in the second wiring layer 100.

[0268] The semiconductor device 1 includes a fifth plug electrode 111. The fifth plug electrode 111 is a plug electrode that transmits the anode potential to the anode region 68 of the ground-side diode DG. The upper end of the fifth plug electrode 111 is connected to the opposite side connection wiring 80C. The lower end of the fifth plug electrode 111 is connected to the second plug electrode 84 via anode wiring 82. The opposite side connection wiring 80C is electrically connected to the anode region 68 of the ground-side diode DG via the fifth plug electrode 111 and the second plug electrode 84.

[0269] Figure 20 shows a fourth example of the array layout of the first diode element DS1 and the second diode element DS2.

[0270] In the fourth exemplary form, twelve diode elements DS are arranged in four rows and four columns. The plurality of diode elements DS connected in series with each other includes two first diode elements DS1 and ten diode elements DS2.

[0271] In the first row of the four columns extending in the first direction X, two first diode elements DS1 are arranged side by side in the first direction X.

[0272] The two first diode elements DS1 are formed across the first row and the second row. The ten second diode elements DS2 are arranged one by one in the first row and the second row, and four by four in the third row and the fourth row.

[0273] One element boundary B between the two first diode elements DS1 and two element boundaries B between the three second diode elements DS2 after the third row are shifted in the first direction X. That is, one first diode element DS1 and two second diode elements DS2 after the third row are opposed to each other in the second direction Y.

[0274] Also, one first diode element DS1 and the second diode elements DS2 in the first row and the second row are opposed to each other in the first direction X. In other words, the first diode element DS1 is surrounded by the plurality of second diode elements DS2 from two directions.

[0275] FIG. 21 is a diagram showing a fifth exemplary form of the arrangement layout of the first diode element DS1 and the second diode element DS2.

[0276] In the fifth exemplary form, twelve diode elements DS are arranged in four rows and four columns. The plurality of diode elements DS connected in series with each other includes two first diode elements DS1 and ten diode elements DS2.

[0277] In the second row of the four columns extending in the first direction X, two first diode elements DS1 are arranged side by side in the first direction X.

[0278] Two first diode elements DS1 are formed spanning the second and third rows. Ten second diode elements DS2 are arranged one each in the second and third rows, and four each in the first and fourth rows.

[0279] One element boundary B between the two first diode elements DS1 and two element boundaries B between the three second diode elements DS2 in the first row are offset in the first direction X. That is, one first diode element DS1 and the two second diode elements DS2 in the first row are facing each other in the second direction Y.

[0280] One element boundary B between the two first diode elements DS1 and two element boundaries B between the three second diode elements DS2 in the fourth row are offset in the first direction X. That is, one first diode element DS1 and the two second diode elements DS2 in the fourth row face each other in the second direction Y. In other words, one first diode element DS1 is surrounded from three directions by multiple second diode elements DS2.

[0281] Furthermore, the four second diode elements DS2 included in the outermost column (right side in Figure 21) in the first direction X among the four columns extending in the second direction Y have a 90° difference in orientation (orientation in the first element direction X1) compared to the other six second diode elements DS2.

[0282] Figure 22 shows an example of a sixth configuration of the array layout of the first diode element DS1 and the second diode element DS2.

[0283] In the sixth embodiment, 16 diode elements DS are arranged in a 4x5 grid. Multiple diode elements DS connected in series together include 2 first diode elements DS1 and 14 diode elements DS2.

[0284] In the second row of the four columns extending in the first direction X, two first diode elements DS1 are arranged side by side in the first direction X.

[0285] The two first diode elements DS1 are formed across the second and third rows. The fourteen second diode elements DS2 are arranged two to each of the second and third rows, and five to each of the first and fourth rows.

[0286] One element boundary B between the two first diode elements DS1 and two element boundaries B between the three second diode elements DS2 in the first row are offset in the first direction X. That is, one first diode element DS1 and the two second diode elements DS2 in the first row are facing each other in the second direction Y.

[0287] One element boundary B between the two first diode elements DS1 and two element boundaries B between the three second diode elements DS2 in the fourth row are offset in the first direction X. That is, one first diode element DS1 and the two second diode elements DS2 in the fourth row are facing each other in the second direction Y.

[0288] Furthermore, one first diode element DS1 and two second diode elements DS2 (second diode elements DS2 in the second and third rows) are facing each other in the first direction X.

[0289] The 14 second diode elements DS2 surround the two diodes all around. In other words, the first diode element DS1 is surrounded from four directions by multiple second diode elements DS2.

[0290] Furthermore, the four second diode elements DS2 located in the leftmost column (in Figure 22) of the four columns extending in the second direction Y have a 90° difference in orientation (direction in the first element direction X1) compared to the other ten second diode elements DS2.

[0291] Furthermore, the four second diode elements DS2 included in the outermost column (right side in Figure 22) in the first direction X among the four columns extending in the second direction Y are other diode elements DSA.

[0292] In this configuration, the first diode element DS1 closest to the drain terminal 15 (the first diode element DS1 corresponding to the drain-side diode DD), including the drain-side diode DD, is positioned in the center of the first direction X in the second and third rows. The drain-side connection wiring 80D included in the second wiring layer 100 (see Figure 23) is connected to this first diode element DS1. The drain-side connection wiring 80D is equivalent to the drain-side connection wiring 80A except that it is part of the second wiring layer 100, and includes a cathode wiring 81 (Figure 12) and a plurality of end plug electrodes 90 (Figure 12).

[0293] Referring to Figure 23, the semiconductor device 1 includes a sixth plug electrode 121. The sixth plug electrode 121 is a plug electrode that transmits the cathode potential to the cathode region 67 of the drain-side diode DD. The drain-side connection wiring 80D is connected to the upper end of the sixth plug electrode 121. The first plug electrode 83 is connected to the lower end of the sixth plug electrode 121 via the cathode wiring 81. The drain-side connection wiring 80D is electrically connected to the cathode region 67 of the drain-side diode DD via the fifth plug electrode 111 and the first plug electrode 83.

[0294] In the second to sixth embodiments, the same effects and benefits as those exhibited in the embodiments shown in Figures 1 to 16B are also achieved.

[0295] While embodiments of this disclosure have been described above, this disclosure can also be implemented in other forms.

[0296] As an example, two types of diode elements DS (second diode element DS2 and third diode element DS3) with different peripheral distances are used as diode elements DS with a smaller peripheral distance than the first diode element DS1. However, three or more types of diode elements DS with different peripheral distances may also be used.

[0297] In addition, in each of the above-described embodiments, an example in which the first conductivity type is p-type and the second conductivity type is n-type has been described. However, the first conductivity type may be n-type and the second conductivity type may be p-type. The specific configuration in this case can be obtained by replacing the n-type region with a p-type region and the p-type region with an n-type region in the above description and the accompanying drawings.

[0298] As described above, the embodiments of the present disclosure are illustrative in all respects and should not be construed in a limited sense, and modifications are intended to be included in all respects.

[0299] The following features can be extracted from the description of this specification and the drawings. Hereinafter, the alphanumerics in parentheses represent the corresponding components and the like in the above-described embodiments, but the scope of each item (Clause) is not intended to be limited to the embodiments.

[0300] [Appendix 1-1] A chip (2) having a first main surface (3) and a second main surface (4) opposite to the first main surface (3); A first impurity region (64) of the first conductivity type formed in the surface layer portion of the first main surface (3); A plurality of diode elements (DS) directly connected to each other included in a clamp circuit (30, 35) connected to a power supply terminal (15), and a plurality of diode elements (DS) formed in the surface layer portion of the first impurity region (64) in a diode formation region (9) set on the first main surface (3); Each of the diode elements (DS) includes a second impurity region (66) of the second conductivity type formed at intervals in a direction along the first main surface (3) in the surface layer portion of the first impurity region (64) in the diode formation region (9), and an anode region (68) and a cathode region (67) formed in the surface layer portion of the second impurity region (66); The plurality of diode elements (DS) includes at least one first diode element (DS) and a second diode element (DS) having a shorter outer peripheral distance than the first diode element (DS), and at least one second diode element (DS); A semiconductor device (1) in which the first diode element (DS) is connected to the power supply terminal (15) side relative to the second diode element.

[0301] [Appendix 1-2] The semiconductor device (1) described in Appendix 1-1, wherein the first diode element (DS1) and the second diode element (DS2) have equivalent reverse voltages to each other.

[0302] [Appendix 1-3] The semiconductor device (1) according to Appendix 1-1 or Appendix 1-2, wherein the second diode element (DS2) has a lower element breakdown voltage than the element breakdown voltage of the first diode element (DS1).

[0303] [Appendix 1-4] The semiconductor device (1) described in Appendices 1-1 to 1-3 has a ground potential applied to the first impurity region (64).

[0304] [Appendix 1-5] A semiconductor device (1) as described in any one of the appendices 1-1 to 1-4, wherein there are multiple second diode elements (DS2).

[0305] [Appendix 1-6] The semiconductor device (1) described in Appendix 1-5, wherein the first diode element (DS1) is connected to the power supply terminal (15) side for all of the second diode elements (DS2).

[0306] [Appendix 1-7] The second impurity region (66) includes a first concentration region (69) formed on the surface of the first main surface (3), and a second concentration region (70) formed on the surface of the first concentration region (69) having a higher concentration of second conductivity type impurities than the first impurity region (64). A semiconductor device (1) according to any one of the appendices 1-1 to 1-6, wherein the anode region (68) and the cathode region (67) are formed on the surface of the second concentration region (70).

[0307] [Appendix 1-8] The semiconductor device (1) as described in Appendix 1-7, wherein in the first concentration region (69) of the second diode element (DS2), the surrounding portion (69a) that surrounds the outer periphery of the second concentration region (70) of the second diode element (DS2) has a second width (W21) in the first element direction (X1) that is narrower than the first width (W1) in the first element direction (X1) of the surrounding portion (69a) that surrounds the outer periphery of the second concentration region (70) of the first diode element (DS1) in the first concentration region (69) of the first diode element (DS1).

[0308] [Appendix 1-9] A semiconductor device (1) as described in Appendix 1-7 or Appendix 1-8, wherein the second distance (L21), which is the distance in the first element direction (X1) on the outer periphery of the second concentration region (70) of the second diode element (DS2), is shorter than the first distance (L1), which is the distance in the first element direction (X1) on the outer periphery of the first concentration region (69) of the first diode element (DS1).

[0309] [Appendix 1-10] A semiconductor device (1) as described in any one of the appendices 1-7 to 1-9, wherein the fourth distance (L23), which is the distance in the first element direction (X1) on the outer periphery of the second concentration region (70) of the second diode element (DS2), is shorter than the third distance (L3), which is the distance in the first element direction (X1) on the outer periphery of the second concentration region (70) of the first diode element (DS1).

[0310] [Appendix 1-11] The anode region (68) and the cathode region (67) are formed with a gap between them in a direction along the first main surface (3). A semiconductor device (1) as described in any one of the appendices 1-1 to 1-10, wherein the first spacing (W5) in the first element direction between the anode region (68) and the cathode region (67) of the first diode element (DS1) is equivalent to the second spacing (W65) in the first element direction between the anode region (68) and the cathode region (67) of the second diode element (DS2).

[0311] [Appendix 1-12] The third width (W3) in the first element direction (X1) of the anode region (68) in the first diode element (DS1) is equivalent to the fourth width (W63) in the first element direction (X1) of the anode region (68) in the second diode element (DS2), The semiconductor device (1) as described in Appendix 1-11, wherein the fifth width (W4) in the first element direction (X1) of the cathode region (67) in the first diode element (DS1) is equivalent to the sixth width (W64) in the first element direction (X1) of the cathode region (67) in the second diode element (DS2).

[0312] [Appendix 1-13] Each of the plurality of diode elements (DS) further includes a plurality of guard ring regions (71) of a second conductivity type, each formed to surround a plurality of the plurality of second impurity regions (66), a plurality of the anode regions (68), and a plurality of the cathode regions (67), A semiconductor device (1) as described in Appendix 1-9 or Appendix 1-10, wherein the fourth distance between the outer circumference of the second impurity region (66) of the second diode element (DS2) and the guard ring region (71) is narrower than the third distance (W2) between the outer circumference of the second impurity region (66) of the first diode element (DS1) and the guard ring region (71).

[0313] [Appendix 1-14] Each of the plurality of diode elements (DS) further includes a plurality of guard ring regions (71) of a second conductivity type, each formed to surround a plurality of the plurality of second impurity regions (66), a plurality of the anode regions (68), and a plurality of the cathode regions (67), A semiconductor device (1) according to any one of the appendices 1-1 to 1-7, wherein the fourth gap (W22) between the outer circumference of the second impurity region (66) of the second diode element (DS2) and the guard ring region (71) is narrower than the third gap (W2) between the outer circumference of the second impurity region (66) of the first diode element (DS1) and the guard ring region (71).

[0314] [Appendix 1-15] The first diode element (DS1) and the second diode element (DS2) are multiple, A semiconductor device (1) as described in any one of the appendices 1-1 to 1-14, wherein the sixth spacing (W26), which is the spacing between the second impurity regions (46) of two opposing second diode elements (DS2), is narrower than the fifth spacing (W6), which is the spacing between the second impurity regions (46) of two opposing first diode elements (DS1).

[0315] [Appendix 1-16] The semiconductor device (1) according to any one of the appendices 1-4 to 1-6, wherein the plurality of diode elements (DS) are arranged in a matrix along a first direction (X) and a second direction (Y) intersecting the first direction (X), such that the first diode element (DS1) and the plurality of second diode elements (DS2) are included in different columns.

[0316] [Appendix 1-17] The plurality of diode elements (DS) are arranged in a matrix along a first direction (X) and a second direction (Y) intersecting the first direction (X). A semiconductor device (1) according to Appendix 1-5 or Appendix 1-6, wherein a plurality of the second diode elements (DS2) are facing one of the diode elements (DS) in the second direction (Y).

[0317] [Appendix 1-18] A semiconductor device (1) according to any one of the appendices 1-5, 1-6, and 1-17, wherein a plurality of the aforementioned second diode elements (DS2) are arranged in a spiral shape.

[0318] [Appendix 1-19] A semiconductor device (1) according to any one of the appendices 1-5, 1-6, 1-17, and 1-18, wherein a plurality of the second diode elements (DS2) are arranged to surround the first diode element (DS1).

[0319] [Appendix 1-20] The plurality of second diode elements (DS2) include a first element (DS2) whose distance in the outer peripheral direction (X1) is shorter than that of the first diode element (DS1), and a second element (DS3) whose distance in the outer peripheral direction (X1) is shorter than that of the first element (DS2), A semiconductor device (1) according to any one of the appendices 1-5, 1-6, and 1-17 to 1-19, wherein the first element (DS2) is connected to the power terminal (15) side of the second element (DS3).

[0320] [Appendix 1-21] The power terminal (15) covers the second main surface (4), In the chip (2), a first semiconductor region (11) is formed on the surface layer of the first main surface (3) so as to be electrically connected to the power terminal (15), The present invention further includes connecting wiring (80A) that connects the cathodes of the plurality of diode elements (D) to the first semiconductor region (11), A semiconductor device (1) according to any one of the appendices 1-1 to 1-20, wherein the first impurity region (64) is formed on the surface of the first semiconductor region (11).

[0321] [Appendix 1-22] A semiconductor device (1) as described in Appendix 1-5 or Appendix 1-6, wherein the number of first diode elements (DS1) is less than the number of second diode elements (DS2). [Explanation of Symbols]

[0322] 1: Semiconductor device 2: Tip 3: First main surface 4: Second main surface 5A: 1st side 5B: 2nd side 5C: 3rd side 5D: 4th side 6: Output area 7: Control Domain 8: Diode formation region 9: Diode group 10: Drain area 11: Drift region 12: Interlayer insulating layer 13: Source terminal 14: Control terminal 14a: Ground terminal 14b: Input terminal 15: Drain terminal (power terminal) 20: Output transistor 21: System transistors 21A: First-system transistor 21B: Second transistor 22: Unit Transistor 23: Control circuit 24: Gate control circuit 25: Current monitoring circuit 26: Overcurrent protection circuit 27: Overheat protection circuit 28: Low-voltage malfunction prevention circuit 29: Load Open Detection Circuit 30: Active clamp circuit (clamp circuit) 31: Power supply reverse connection protection circuit 32: Logic Circuits 33: Test Circuit 34: Amplifier Circuit 35: Voltage clamp circuit (clamp circuit) 36: pn junction diode 37: Resistance 60: Trench separation structure 61: Separation Trench 62: Separation insulating layer 63: Separation electrode 64: First well region (first impurity region) 66: n-type well region (second impurity region) 67: Cathode region 68: Anode region 69: Second well region (first concentration region) 69a: Encircled area 70: Third well region (second concentration region) 71: Guard Ring Area 72: First Guard Ring Area 73: Second Guard Ring Area 74:Inner separation structure 75:Outer separation structure 76: Main surface insulating layer 77: Field insulating layer 78: 1st wiring layer 79: First insulating layer 80: Connection wiring 80A: Drain side connection wiring 80B: Opposite side connection wiring 80C: Opposite side connection wiring 80D: Drain side connection wiring 81: Cathode wiring 82: Anode wiring 83: First plug electrode 84: Second plug electrode 85: Third plug electrode 86: Fourth plug electrode 87: Ground wiring 90: End plug electrode 91: End plug placement area 92: High concentration area 100: 2nd wiring layer 101: Second insulating layer 111: Fifth plug electrode 121: 6th plug electrode B: Element boundary D: Diode D1: First diode D2: Second diode D3: Third diode DD: Drain diode DG: Ground diode DS: Diode element DS1: First diode relates DS2: Second diode element (first element) DS3: Third diode element (second element) DSA: Other diode elements Io: Output current Is: Grid current Iu: Unit current L: Inductive load L1: Distance (1st distance) L2: distance L3: Distance (3rd distance) L5: distance L11 :Distance L12 :Distance L13 :Distance L15 :Distance L21: Distance (second distance) L22 :Distance L23: Distance (4th distance) L25: distance L31 :Distance L32 :Distance L33 :Distance L35 :Distance L42 :Distance L43 :Distance L45 :Distance L52 :Distance L53 :Distance L55 :Distance W1: Width (1st width) W2: Width W3: Width (3rd width) W4: Width (5th width) W5: Interval (1st interval) W11:Width W12:Width W13: Width W14: Width W15: Interval W21: Width (second width) W22: Width W23: Width W24: Width W25: Spacing W31: Width W32:Width W33: Width W34: Width W35: Interval W63: Width (4th width) W64: Width (6th width) W65: Interval (2nd interval) W73: Width W74: Width W75: Interval (1st interval) WT: Trench width X: 1st direction X1: Direction of the first element Y: Second direction Y1: Direction of the second element Z: Normal direction

Claims

1. A chip having a first main surface and a second main surface opposite to the first main surface, A clamp circuit connected to a power terminal includes multiple diode elements connected in series with each other, Each of the plurality of diode elements includes a first impurity region of a first conductivity type formed on the surface layer of the first main surface in a diode formation region set on the first main surface, a plurality of second impurity regions of a second conductivity type formed at intervals in the direction along the first main surface on the surface layer of the first impurity region, and a plurality of anode regions and a plurality of cathode regions formed on the surface layer of the second impurity region. The plurality of diode elements include at least one first diode element and at least one second diode element having a shorter peripheral distance than the first diode element. A semiconductor device in which the first diode element is connected to the power supply terminal side relative to the second diode element.

2. The semiconductor device according to claim 1, wherein the first diode element and the second diode element have equivalent reverse voltages to each other.

3. The semiconductor device according to claim 1, wherein the second diode element has a lower element breakdown voltage than the element breakdown voltage of the first diode element.

4. The semiconductor device according to claim 1, wherein a ground potential is applied to the first impurity region.

5. The semiconductor device according to claim 1, wherein the second diode element is a plurality of elements.

6. The semiconductor device according to claim 5, wherein the first diode element is connected to the power supply terminal side for all of the second diode elements.

7. The second impurity region includes a first concentration region formed on the surface of the first main surface and a second concentration region formed on the surface of the first concentration region, where the concentration of the second conductivity type impurity is higher than that of the first impurity region. The semiconductor device according to any one of claims 1 to 6, wherein the anode region and the cathode region are formed on the surface of the second concentration region.

8. The semiconductor device according to claim 7, wherein the surrounding portion that encloses the outer periphery of the second concentration region of the second diode element in the first concentration region of the second diode element has a second width in the first element direction that is narrower than the first width in the first element direction of the surrounding portion that encloses the outer periphery of the second concentration region of the first diode element in the first concentration region of the first diode element.

9. The semiconductor device according to claim 8, wherein the second distance, which is the distance in the direction of the first element from the outer periphery of the second concentration region of the second diode element, is shorter than the first distance, which is the distance in the direction of the first element from the outer periphery of the first concentration region of the first diode element.

10. The semiconductor device according to claim 8, wherein the fourth distance, which is the distance in the direction of the first element from the outer periphery of the second concentration region of the second diode element, is shorter than the third distance, which is the distance in the direction of the first element from the outer periphery of the second concentration region of the first diode element.

11. The anode region and the cathode region are formed with a gap between them in the direction along the first main surface. The semiconductor device according to claim 9, wherein the first spacing in the first element direction between the anode region and the cathode region of the first diode element is equivalent to the second spacing in the first element direction between the anode region and the cathode region of the second diode element.

12. The third width of the anode region in the first element direction in the first diode element is equivalent to the fourth width of the anode region in the first element direction in the second diode element. The semiconductor device according to claim 11, wherein the fifth width of the cathode region in the first element direction of the first diode element is equivalent to the sixth width of the cathode region in the first element direction of the second diode element.

13. Each of the plurality of diode elements further includes a plurality of guard ring regions of a second conductivity type formed so as to surround a plurality of the second impurity regions, a plurality of the anode regions, and a plurality of the cathode regions, The semiconductor device according to claim 9, wherein the fourth distance between the outer periphery of the second impurity region of the second diode element and the guard ring region is narrower than the third distance between the outer periphery of the second impurity region of the first diode element and the guard ring region.

14. Each of the plurality of diode elements further includes a plurality of guard ring regions of a second conductivity type formed so as to surround a plurality of the second impurity regions, a plurality of the anode regions, and a plurality of the cathode regions, The semiconductor device according to any one of claims 1 to 6, wherein the fourth distance between the outer periphery of the second impurity region of the second diode element and the guard ring region is narrower than the third distance between the outer periphery of the second impurity region of the first diode element and the guard ring region.

15. The first diode element and the second diode element are multiple, The semiconductor device according to claim 5 or 6, wherein the sixth distance, which is the distance between the second impurity regions of two opposing second diode elements, is narrower than the fifth distance, which is the distance between the second impurity regions of two opposing first diode elements.

16. The semiconductor device according to claim 5 or 6, wherein the plurality of diode elements are arranged in a matrix along a first direction and a second direction intersecting the first direction, such that the first diode element and the plurality of second diode elements are included in different columns.

17. The plurality of diode elements are arranged in a matrix along a first direction and a second direction intersecting the first direction. The semiconductor device according to claim 5 or 6, wherein a plurality of the second diode elements are facing one of the diode elements in the second direction.

18. The semiconductor device according to claim 5 or 6, wherein a plurality of the second diode elements are arranged in a spiral shape.

19. The semiconductor device according to claim 5 or 6, wherein a plurality of the second diode elements are arranged to surround the first diode element.

20. The plurality of second diode elements include a first element whose outer circumference in the direction of the first element is shorter than that of the first diode element, and a second element whose outer circumference in the direction of the first element is shorter than that of the first element. The semiconductor device according to claim 5 or 6, wherein the first element is connected to the power supply terminal side relative to the second element.

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