Multi-mode control method and system for active clamp class converter

Abstract

This invention discloses a multi-mode control method and system for an active clamp converter. The control method selects the control mode of the switching transistor based on the real-time load, including four consecutive load threshold ranges from light to heavy: extremely light load, light load, medium load, and heavy load. When the real-time load is in the extremely light load range, a constant on-time mode is used to control the switching transistor; when the real-time load is in the light load range, a voltage-controlled oscillator (VCO) mode is used; when the real-time load is in the medium load range, an intermittent on-time mode is used; and when the real-time load is in the heavy load range, a critical on-time mode is used. This control method can further reduce losses under various load conditions, improve conversion efficiency, and maintain good efficiency across the entire load range.

Description

Technical Field

[0001] This invention belongs to the field of buck-boost converter control technology, and specifically relates to a multi-mode control method and system for an active clamp converter. Background Technology

[0002] With the development of modern electronic systems, especially for communication / server power supply applications, design requirements such as high power density, high efficiency, and low EMI have become the most challenging issues. Dual-clamp ZVS (zero voltage switching) converters and active-clamp flyback converters, due to their simple circuit structure and wide input range, have been widely studied and used in academia and industry.

[0003] The key technologies for active clamp converter control are: (1) achieving zero-voltage conduction across the entire input voltage and load range by effectively controlling the conduction time of the four switching transistors, thereby improving the converter efficiency. (2) Light-load control reduces the switching frequency while ensuring zero-voltage conduction of the four switching transistors, thereby reducing standby power consumption. Therefore, multi-mode control is more suitable for this type of topology. The conversion efficiency of existing multi-mode control methods still has room for improvement, and existing multi-mode control suffers from the problems of insufficient flexibility and lack of real-time monitoring when using analog control, and numerous control variables and high operating frequency when using digital control. Summary of the Invention

[0004] Purpose of the invention: The purpose of this invention is to propose a multi-mode control method for active clamp converters, which further improves the conversion efficiency of the converter under light load, medium load and heavy load and reduces standby power consumption.

[0005] Another objective of this invention is to propose a control circuit that can implement the above-mentioned multi-mode control method. By combining digital and analog signals, it can achieve flexible control and real-time monitoring while reducing the number of control variables.

[0006] Technical Solution: The multi-mode control method for active clamp converters described in this invention selects the control mode of the switching transistor based on the real-time load, including four continuous load threshold ranges from light to heavy: extremely light load, light load, medium load, and heavy load. When the real-time load is in the extremely light load range, a constant on-time mode is used to control the switching transistor; when the real-time load is in the light load range, a voltage-controlled oscillator mode is used to control the switching transistor; when the real-time load is in the medium load range, an intermittent on-time mode is used to control the switching transistor; and when the real-time load is in the heavy load range, a critical on-time mode is used to control the switching transistor.

[0007] Furthermore, when the load is in the light load range, the control coefficient of the voltage-controlled oscillator mode satisfies the following condition: at the boundary between the light load range and the medium load range, the switching frequency of the converter reaches its extreme value.

[0008] Furthermore, the boundary between the extremely light load range and the light load range is 20% of the full load, the boundary between the light load range and the medium load range is 50% of the full load, and the boundary between the medium load range and the heavy load range is 80% of the full load.

[0009] Further steps include: S1: Acquiring the input voltage V of the active clamp converter topology. in Clamping capacitor voltage v clamp And the midpoint voltage v of the two bridge arms A and v B ;

[0010] S2: Select the control mode based on the real-time load status, and combine the selected control mode with the input voltage V. in Clamping capacitor voltage v clamp And the midpoint voltage v of the two bridge arms A and v B The control signals for the first to fourth switching transistors Q1, Q2, Q3 and Q4 are generated.

[0011] Furthermore, step S2 includes the following steps:

[0012] S2.1: Based on the clamping capacitor voltage v clamp The AD value Vclamp_AD_FF and the reference voltage V ref Compare the production error signal Verr;

[0013] Based on the midpoint voltage v of the bridge arm B Compared with the comparator reference voltage V DAC3 For comparison, generate the ZVS signal Q4_zvs and the Q4 on signal Q4_zvs_on;

[0014] Based on the midpoint voltage v of the bridge arm A and v B A simulated signal for generating the excitation inductor current is generated by differential detection. This simulated signal is then amplified to generate v. Lm_sense Signal and comparator reference voltage V DAC1 The comparison generates the Q3 turn-off signal Q3_off;

[0015] S2.2: The regulator output signal PIoutput is generated after the error signal Verr is compensated by the digital loop Hc(z) and clamped.

[0016] S2.3: Based on the input voltage V inThe AD value Vin_AD_FF and the regulator output signal PIoutput, combined with the control mode selected according to the regulator output signal PIoutput, generate two control quantities duty_out1 and duty_out3, where duty_out3 controls the converter frequency and duty_out1 controls the converter conduction time.

[0017] S2.4: Generate the frequency conversion signal Sync_clk based on the ZVS signal Q4_zvs;

[0018] S2.5: Based on the frequency conversion signal Sync_clk, the Q4 turn-on signal Q4_zvs_on, the Q3 turn-off signal Q3_off, and the control quantities duty_out1 and duty_out3, generate the PWM control signals for the first to fourth switching transistors Q1, Q2, Q3, and Q4.

[0019] S2.6: Based on the generated PWM control signal, the current is amplified by the driver to generate the drive signals for the first to fourth switching transistors Q1, Q2, Q3 and Q4.

[0020] Furthermore, in step S2.3, when the selected control mode is critical conduction mode, intermittent conduction mode, or voltage-controlled oscillator mode:

[0021]

[0022] When the selected control mode is constant on-time mode:

[0023]

[0024] When the selected control mode is critical conduction mode or intermittent conduction mode, duty_out3 is a set value;

[0025] When the selected control mode is voltage-controlled oscillator mode and constant on-time mode:

[0026]

[0027] Where K_PG2DC_xishu and K_PG3DC_VCO are both conversion coefficients, and PIoutput_clamp is the set clamp value for PIoutput.

[0028] The multi-mode control system for the active clamp converter of the present invention includes: a sampling module for acquiring the input voltage V of the converter. in Clamping capacitor voltage v clamp And the midpoint voltage v of the two bridge arms A and v BThe voltage is converted into a corresponding digital intermediate signal. A multi-mode control logic module is used to select the control mode of the switching transistor based on the real-time load, controlling the switching frequency and conduction time of the converter. This includes four consecutive load threshold ranges from light to heavy: extremely light load, light load, medium load, and heavy load. When the real-time load is in the extremely light load range, a constant conduction time mode is used to control the switching transistor; when the real-time load is in the light load range, a voltage-controlled oscillator mode is used; when the real-time load is in the medium load range, an intermittent conduction mode is used; and when the real-time load is in the heavy load range, a critical conduction mode is used. A PWM module is used to generate PWM control signals for the first to fourth switching transistors based on the digital intermediate signals output by the multi-mode control logic module and the sampling module.

[0029] Furthermore, the sampling module is built from analog circuits, while the multi-mode control logic module and PWM module are digital modules.

[0030] Beneficial Effects: Compared with existing technologies, this invention has the following advantages: 1. Based on real-time load conditions, it implements constant on-time mode, voltage-controlled oscillator mode, intermittent on-time mode, and critical on-time mode for control under extremely light load, light load, medium load, and heavy load conditions, respectively, further reducing losses and improving conversion efficiency under various load conditions. 2. It adopts a combination of analog and digital methods, using analog circuits for sampling and digital modules for generating control signals. This combines the speed and low latency of analog control with the flexibility and ease of implementing advanced control algorithms of digital control. Attached Figure Description

[0031] Figure 1 This is a topology diagram of a dual-clamp zero-voltage switching converter.

[0032] Figure 2 This is a waveform diagram of the CRM under actual heavy load.

[0033] Figure 3 The waveform diagram of DCM under actual light load is shown.

[0034] Figure 4 This is the equivalent circuit diagram of the converter during the energy storage stage.

[0035] Figure 5 This is the equivalent circuit diagram of the converter during the resonant stage of the magnetizing inductance and junction capacitance.

[0036] Figure 6 This is the equivalent circuit diagram of the converter during the resonant stage of the magnetizing inductor and clamping capacitor.

[0037] Figure 7 This is the equivalent circuit diagram of the converter in energy transfer stage 1.

[0038] Figure 8 This is the equivalent circuit diagram of the converter in energy transfer stage 2.

[0039] Figure 9 This is the equivalent circuit diagram of the converter during the resonant stage of the magnetizing inductor and the junction capacitances of Q3 and Q4.

[0040] Figure 10 This is the equivalent circuit diagram of the converter during the clamping phase.

[0041] Figure 11 For the converter in the magnetizing inductor L m Equivalent circuit diagram of the resonant stage of the junction capacitance of Q1 and Q2.

[0042] Figure 12 This is a graph showing the relationship between the switching frequency and the load under the control method of this invention.

[0043] Figure 13 This is a flowchart of the control method according to an embodiment of the present invention.

[0044] Figure 14 This is a system block diagram of the control system according to an embodiment of the present invention.

[0045] Figure 15 This is a control logic diagram of the multi-mode control logic module in an embodiment of the present invention.

[0046] Figure 16 This is a schematic diagram of the PWM module according to an embodiment of the present invention.

[0047] Figure 17 This is an efficiency curve diagram under the control of the control method in an embodiment of the present invention.

[0048] Figure 18 This is a graph showing the relationship between frequency and load under the control method of this invention. Detailed Implementation

[0049] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0050] The control method and system of this invention are applicable to the control of active clamp converters such as Buck, Boost, Buck-Boost, flyback, forward, active clamp flyback, and active clamp forward. In this embodiment, using... Figure 1 The control method and control system of this invention will be described using the dual-clamp zero-voltage switching converter shown as an example.

[0051] Reference Figure 1The dual-clamp zero-voltage switching converter includes a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, and a fifth switch Q5, as well as corresponding body diodes D1, D2, D3, D4 and junction capacitors C1, C2, C3, C4. The third switch is also called the active clamping transistor, and a power transformer T is also included. Figure 1 As shown within the dashed box, one end of the primary winding of the power transformer is connected between the first switch Q1 and the second switch Q2, and the other end is connected between the active clamping transistor Q3 and the fourth switch Q4. One end of the secondary winding of the transformer is connected to the output voltage v. o One end is connected to the positive terminal of the circuit, and the other end is connected to the fifth switching transistor Q5. The controller controls the circuit by controlling the on / off state of the four primary-side switching transistors, thereby achieving the switching of different input voltages V. in Transformed into a stable output voltage v o The purpose is to provide power to the load. The driving of switching transistors Q1, Q2, Q4, and clamping switching transistor Q3 is selected as the control circuit for study; the magnetizing current i of transformer T... Lm Transformer leakage inductance L r current i Lr Secondary transformer current i sec Clamping capacitor voltage v clamp and current i clamp And the drain-source voltages v of switches Q2 and Q4 A ,v B The operating waveforms are used as part of the power circuit research.

[0052] The timing control logic of Q1, Q2, Q3 and Q4 within one switching cycle is shown in Table 1, which includes seven parts: energy storage stage, ZVS Phase A, B, C, energy transfer stage, and clamping stage.

[0053] Table 1 Timing control logic table for one switching cycle

[0054]

[0055] In practice, combined with Figure 2 The waveform diagram shown is in CRM (Critical On Mode) under heavy load. The dual-clamp zero-voltage switching converter is divided into eight operating modes within one switching cycle, and the specific analysis is as follows: 1. Time period t0~t1 (energy storage stage).

[0056] At time t0, switch Q4 remains on, continuing its previous operating state. At this time, the controller turns on the first switch Q1, and the primary side of the transformer is supplied with the input voltage source V. in The transformer T is energized via switching transistors Q1 and Q4, disconnecting the secondary side of the converter, and the output filter capacitor C... o Give load R oPower supply. The duration of this period depends on the circuit's on-time control. Figure 4 The equivalent circuit for this time period is given. The primary-side resonant cavity current during this time period can be expressed as:

[0057]

[0058] 2. The time period from t1 to t2 (ZVS Phase A---resonance of magnetizing inductance and junction capacitance)

[0059] At time t1, the controller turns off Q1 and Q4 simultaneously, ending the energy storage phase. At this time, since the resonant cavity current is in the positive direction, the energy stored in the magnetizing inductor and leakage inductance charges the junction capacitances C1 and C4 of Q1 and Q4, while discharging the junction capacitances C2 and C3 of Q2 and Q3. This causes v A Point voltage drop v B The voltage rises because the primary voltage of the transformer is less than the output reflected voltage n·v. o The secondary diode D5 is cut off, and the load R o From the output capacitor C o Power supply. The equivalent circuit during this time period is as follows: Figure 5 As shown, the resonant current i at this time Lr The voltage across junction capacitances C2 and C4 can be expressed as follows:

[0060]

[0061]

[0062]

[0063] In the formula, When v A Drop to 0 or v B Rise to v clamp At that time, this period ends.

[0064] 3. The time period from t2 to t3 (ZVS Phase A---resonance of magnetizing inductor and clamping capacitor)

[0065] At time t2, v A The point voltage drops to 0, V B The point voltage rises to the clamping capacitor voltage V clamp At this time, the anti-parallel body diodes D2 and D4 of Q2 and Q4 are turned on. Since the resonant cavity current is still in the positive direction, the energy stored in the magnetizing inductor and leakage inductance charges the clamping capacitor through the body diodes D2 and D4. When the primary voltage of the transformer is greater than the output reflected voltage n·V oWhen the secondary diode D5 turns on, the magnetizing inductor is clamped, and the primary side begins to supply energy to the secondary side. The equivalent circuit during this time period is as follows: Figure 6 As shown. At this time, the resonant current i Lr and clamping capacitor voltage v clamp It can be represented as follows:

[0066]

[0067] v clamp (t)=v clamp +{(n·v o -v clamp )[1-cos(w2(t-t2))]+i Lr (t2)Z2 sin(w2(t-t2))}(6)

[0068] In the formula During this period, Q2 and Q3 can enable ZVS.

[0069] 4. The time period from t3 to t4 (energy transfer phase 1)

[0070] At time t3, the controller turns on Q2 and Q3, transferring energy from the primary side to the secondary side. The resonant inductor L... r Will be related to the clamping capacitor C f It remains in a resonant state, while the magnetizing inductance L m At voltage n·v o Linear discharge under the action of [something]. Excitation inductor current i Lm and resonant inductor current i Lr The difference current i pri The voltage is transmitted to the secondary side through the transformer. The equivalent circuit during this time period is as follows: Figure 7 As shown. At this time, the resonant current i Lr Magnetizing inductor current i Lm and clamping capacitor voltage v clamp It can be represented as follows:

[0071]

[0072]

[0073] When the magnetizing inductor current i Lm When the value is about to drop to 0, Q3 is turned off in advance, and this period ends.

[0074] 5. The time period from t4 to t5 (energy transfer phase 2)

[0075] At time t4, the magnetizing inductor current i Lm When the voltage is about to drop to 0, the controller turns off Q3 prematurely. During this period, the resonant inductor Lr and the clamping capacitor C...f It remains in the resonant state until the resonant current i Lr The current decays to 0 due to the magnetizing inductance current i. Lm Still greater than the resonant current i Lr At this time, the primary current i pri Energy continues to be transferred to the secondary side, and the magnetizing inductor L m current i Lm At voltage n·v o Under the influence of [the current], it continues to decrease linearly to 0, and this process ends. The equivalent circuit for this time period is as follows: Figure 8 As shown. At this time, the resonant current i Lr Magnetizing inductor current i Lm and clamping capacitor voltage v clamp It can be represented as follows:

[0076]

[0077] v clamp (t)=v clamp (t4)+{(n·v o -v clamp (t4))[1-cos(w2(t-t4))]+i Lr (t4)Z2 sin(w2(t-t4))} (11)

[0078]

[0079] 6. The time period from t5 to t6 (ZVS Phase B---resonance of magnetizing inductance and junction capacitance of Q3 and Q4)

[0080] At time t5, the magnetizing inductor current i Lm When the voltage drops to 0, the body diode D3 of Q3 is cut off. Since the voltage across the junction capacitance C4 of Q4 is the clamping capacitor voltage, it can discharge the magnetizing inductor, causing the magnetizing inductor L to... m Current i Lm The voltage continues to drop to negative, while C4 discharges, causing v to... B The voltage drops, and the primary voltage of the transformer is less than the output reflected voltage n·v. o The secondary diode D5 is cut off, and the load R o From the output capacitor C o Power supply. The equivalent circuit during this time period is as follows: Figure 9 As shown. At this time, the resonant current i Lr Magnetizing inductor current i Lm and clamping capacitor voltage v clamp It can be represented as follows:

[0081]

[0082] vclamp (t)=v clamp (t5)cos(w3(t-t5)) (14)

[0083] In the formula, When v B This period ends when the voltage drops to 0.

[0084] 7. The time period from t6 to t7 (clamping phase)

[0085] At time t6, v B When the voltage drops to 0, the body diode D4 of Q4 conducts. The voltage across the magnetizing inductor is 0, and the magnetizing current i... Lm Keeping the negative phase value constant, turning on Q4 in the controller at this time can achieve ZVS. The equivalent circuit during this time period is as follows: Figure 10 As shown.

[0086] 8. Time period t7~t8 (ZVS Phase C---excitation inductance L) m (and the junction capacitance resonance of Q1 and Q2)

[0087] At time t7, the controller turns off Q2. At this time, Q4 remains on. B The voltage is 0. Due to the resonant cavity current i Lr In the negative direction, the energy stored in the magnetizing inductor and leakage inductance discharges the junction capacitance C1 of Q1 and Q2, and charges C2, causing v to... A The voltage rises. If the time is long enough, v A The voltage rises to V in When the body diode D1 of Q1 is turned on, turning on Q1 at this time achieves ZVS. The equivalent circuit during this time period is as follows: Figure 11 As shown. At this time, the resonant current i Lr The voltage across junction capacitance C2 can be expressed as follows:

[0088] i Lr (t)=i Lr (t7)cos(w4(t-t7)) (15)

[0089]

[0090] In the formula, This completes one switching process. At time t8, the digital controller turns on Q1 to begin the next switching cycle.

[0091] Figure 3Under light load, the waveform of the dual-clamp zero-voltage switching converter in DCM (discontinuous conduction mode) is basically the same as that in CRM mode. The only difference is that the clamping phase (t6 to t7) is extended. By adjusting the duration of this period, the output load can be adjusted. For example, under heavy load, this period can be relatively short or even reduced to 0; under light load, this period is extended, thereby reducing the switching frequency and the average input current.

[0092] The above analysis shows that when the dual-clamp converter operates under heavy load in CRM mode, it can achieve ZVS (Zero-Voltage Switching) for the primary-side switch and ZCS (Zero-Cooling Response Switching) for the secondary-side synchronous rectifier. This effectively improves the switching frequency and converter efficiency, while significantly reducing the converter's size and peak current on both the primary and secondary sides. The CRM operating mode is analyzed below:

[0093] (1) The duty cycle D can be obtained by balancing the volt-seconds of the excitation inductor:

[0094]

[0095] (2) The current i of the magnetizing inductor Lm and resonant current i Lr Output current I o The relationship is as follows:

[0096]

[0097] Integrating both sides for one switching cycle yields the following average relationship:

[0098]

[0099] Where P o η represents the output power, f represents the converter efficiency. sw This represents the switching frequency of the converter.

[0100] (3) Peak current i of the magnetizing inductor Lm_peak Valley value i Lm_valley The relationship between the average and the mean can be obtained as follows:

[0101]

[0102]

[0103] Combining equations (17), (19), (20), and (21) above, we can obtain the switching frequency f. sw _ CRM :

[0104]

[0105] It can be seen from formula (22) that when the dual-clamp converter is operating in CRM mode, the switching frequency f sw It will change with the input voltage V in The value increases with the increase of the output load I; o The switching frequency increases as the load decreases. If the converter operates in CRM mode across the entire load range, the switching frequency will be too high under light load, significantly increasing core losses and switching losses, severely impacting the converter's light load efficiency. Therefore, it is necessary to limit the maximum frequency so that when the converter reduces to a medium load (e.g., 80% load), the switching frequency is clamped, and the converter enters DCM operating mode. The switching frequency when operating in DCM mode is as follows:

[0106] f sw_DCM (V in ,v o ,I o )=f sw_max (twenty three)

[0107] As the load decreases further, continuing to operate at the highest switching frequency will also lead to an increase in core losses and the proportion of switching losses, affecting efficiency under light loads. Therefore, under light loads (e.g., below 50% load), it is necessary to reduce the switching frequency. COT (Constant On-Time) control is a good method for frequency reduction. When the converter operates in COT control mode, the analysis is as follows:

[0108] (1) The slope equation of an inductor:

[0109]

[0110] Where T 1min This represents the minimum on-time of Q1.

[0111] (2) Conservation of energy:

[0112]

[0113] By combining equations (24) and (25) above, the switching frequency f can be obtained. sw _ COT :

[0114]

[0115] Equation (26) shows that when the dual-clamp converter operates in COT mode, the switching frequency f sw It will change with the input voltage V in It decreases as the output load I increases; oThe switching frequency decreases as the load decreases. This improves switching and core losses under light loads, increasing efficiency. However, if only COT control is used under light loads, the switching frequency will drop too low under extremely light loads or no-load conditions, reaching frequencies audible to the human ear (below 15kHz). Therefore, to balance no-load conditions and to slow down the rate of frequency increase with load, the slope of frequency change with load needs to be reduced between 20% and 50% load. Thus, VCO (Voltage-Controlled Oscillator) control is introduced. The analysis when the converter operates in VCO control mode is as follows:

[0116] (1) The slope equation of an inductor:

[0117]

[0118] Where T1 represents the on-time of Q1.

[0119] (2) Conservation of energy:

[0120]

[0121] (3) VCO frequency:

[0122] f sw =k·i Lm_peak (29)

[0123] Where k is a proportionality constant, the switching frequency f can be obtained by combining the above equations. sw_VCO :

[0124]

[0125] Equation (30) shows that when the dual-clamp converter operates in VCO mode, the switching frequency will change with the output load I. o The load increases with frequency, and by adjusting the k value, the rate at which the load increases slows down, reaching its maximum frequency at approximately 50% load.

[0126] In summary, the multi-mode control method for the active clamp converter of this invention selects the control mode of the switching transistor according to the real-time load, including four operating modes, corresponding to four consecutive load threshold ranges from light to heavy: very light load, light load, medium load, and heavy load. When the load is in the light load range, the COT mode is used; when the load is in the light load range, the VCO mode is used; when the load is in the medium load range, the DCM control mode is used; and when the load is in the heavy load range, the CRM mode is used. Figure 12As shown. The above control method allows the converter to operate at its optimal state across the entire load range, further improving the converter's conversion efficiency and reducing losses. The boundaries of the four zones are determined based on actual conditions. Generally, the boundary between the extremely light load zone and the light load zone is approximately 20% of the full load, the boundary between the light load zone and the medium load zone is approximately 50%, and the boundary between the medium load zone and the heavy load zone is approximately 80%.

[0127] Reference Figure 14 A multi-mode control system for an active clamp converter according to an embodiment of the present invention includes a sampling module, a multi-mode control logic module, and a PWM module. The sampling module is used to acquire the input voltage V of the converter. in Clamping capacitor voltage v clamp And the midpoint voltage v of the two bridge arms A and v B The voltage is converted into a corresponding digital intermediate signal. The multi-mode control logic module is used to select the control mode according to the real-time load condition according to the above control method, and output the control signal according to the selected control mode. The PWM module is used to generate PWM control signals for the first to fourth switching transistors according to the digital intermediate signals output by the multi-mode control logic module and the sampling module. The generated PWM signals are amplified by the drive circuit to generate drive signals for the first to fourth switching transistors, driving the on / off frequency and duty cycle of the first to fourth switching transistors.

[0128] In this embodiment, to maintain the high speed and low latency of analog control while also possessing the flexibility and ease of design and implementation of digital control, the control system adopts a hybrid analog-digital design. The sampling module responsible for sampling the converter's electrical signals is built using analog circuits, while the multi-mode control logic module and PWM module responsible for multi-mode control are digital modules. The sampling module converts the acquired real-time electrical signals of the converter into digital quantities. The multi-mode control logic module and the PWM module determine the control mode based on the converted digital quantities and generate PWM control signals.

[0129] Reference Figures 13 to 16 As shown, the above control system achieves multi-mode control of the converter through the following specific steps:

[0130] Step 1: Acquire the input voltage V of the active clamp converter topology. in Clamping capacitor voltage v clamp And the midpoint voltage v of the two bridge arms A v B ;

[0131] Step 2: Based on the clamping capacitor voltage v obtained in Step 1 clamp The AD value Vclamp_AD_FF and the reference voltage V refCompare the production error signal Verr;

[0132] Based on the obtained bridge arm midpoint voltage v B Compared with the comparator reference voltage V DAC3 For comparison, generate the ZVS signal Q4_zvs

[0133] And Q4 activates the signal Q4_zvs_on;

[0134] Based on the obtained bridge arm midpoint voltage v A v B A simulated signal for generating the excitation inductor current is generated by differential detection. This simulated signal is then amplified to generate v. Lm_sense Signal and comparator reference voltage V DAC1 The comparison generates the Q3 turn-off signal Q3_off.

[0135] Step 3: Based on the error signal Verr obtained in Step 2, the regulator output signal PIoutput is generated after digital loop compensation Hc(z) and clamping.

[0136] Step 4: Based on the input voltage V obtained in Step 1 in The AD value Vin_AD_FF and the PI output obtained in step 3 are used by the multi-mode control logic module to adaptively select one of the four operating modes based on the load state, and at the same time generate two control quantities, duty_out1 and duty_out3. Duty_out3 controls the converter frequency, and duty_out1 controls the converter on-time.

[0137] Step 5: Based on the ZVS signal Q4_zvs obtained in Step 2, send it to the PWM1 synchronization function module to generate the frequency conversion signal Sync_clk.

[0138] Step 6: Based on the frequency conversion signal Sync_clk obtained in Step 5, the Q4 turn-on signal and Q3 turn-off signal obtained in Step 2, and the two variables duty_out1 and duty_out3 obtained in Step 4, the following steps are performed: Figure 9 The high-resolution DPWM module shown generates PWM control signals for Q1, Q2, Q3, and Q4.

[0139] Step 7: Based on the PWM control signal obtained in step 6, the current is amplified by the driver to generate the drive signal for the power MOSFET.

[0140] Step 8: Drive the converter switching transistors Q1, Q2, Q3, and Q4 to perform reliable ZVS frequency conversion based on the drive signal obtained in step 7.

[0141] Digital loop compensation can be a simple Type I PI system (single zero, single pole), a Type II analog loop system (double zero, double pole), or even a higher-order Type III system (three zeros, three poles). Adjustments are made based on different topologies, input / output voltages, and design parameters. The ultimate goal is to create a zero-error system with phase and gain margins meeting the control system requirements. The regulator's output, PIoutput, reflects the actual load condition to some extent; the larger the load, the larger the PIoutput value; the lighter the load, the smaller the PIoutput value. Therefore, this variable can be used as a basis for multi-mode load assessment.

[0142] Reference Figure 15 When the load is heavy, such as greater than 80% load, the digital controller reads the PI output value to make a judgment. If PI output > 1600, the controller can operate in DCM / CRM mode. Which mode it operates in is determined by the hardware frequency converter. If the hardware frequency converter is 1MHz lower than the maximum frequency, the converter operates in CRM mode; otherwise, it operates in DCM mode. The control equations for the two output variables, duty_out1 and duty_out3, are as follows:

[0143]

[0144] duty_out3 = 4000 is a fixed value, K_PG2DC_xishu = 1.092·10 4 In equation (31), duty_out1 is used for converter turn-on time control. Its calculated value is inversely proportional to the sampled voltage Vin_AD_FF and directly proportional to the voltage regulator output PIoutput. The purpose of introducing input voltage feedforward is to improve the converter's dynamic response to input voltage jump conditions; the value of duty_out1 is directly proportional to the voltage regulator output PIoutput to achieve regulation of the dual-clamp converter's output voltage and output load. When the output voltage v o When a drop causes a deviation from the regulator's reference setting, the PI output increases, which in turn lengthens the on-time of duty_out1, thus increasing the output voltage, and vice versa. duty_out3 is used for converter frequency control, where the digital value 4000 corresponds to a PWM3H on-time of 1µs, because PWM3H is used as a hardware highest frequency clamp, meaning the highest frequency is clamped to around 1MHz.

[0145] When the load decreases, for example, to between 50% and 80% of the load, the PI output is still greater than 1600. The control method is the same as CRM, the only difference being that the reduced on-time causes the Q4_ZVS hardware frequency conversion frequency to exceed 1MHz. The converter is clamped to 1MHz at the highest frequency, operating in fixed-frequency DCM mode. The control equations for the two output variables, duty_out1 and duty_out3, are the same as in CRM.

[0146] When the load continues to decrease, for example, between 20% and 50% of the load, the PI output will be less than 1600, and the converter will enter VCO mode. At this time, the calculation of duty_out1 remains unchanged as shown in equation (31). However, duty_out3 is modified from the previous fixed value of 4000 as follows:

[0147]

[0148] Where K_PG3DC_VCO=7.5·10 6 In equation (32), duty_out3 is used to change the hardware's highest frequency clamp. This value is inversely proportional to PIoutput. The larger the PIoutput value, the smaller the duty_out3, and the higher the frequency; the smaller the PIoutput value, the larger the duty_out3, and the lower the frequency. Therefore, as the load decreases, the PIoutput value decreases, and the duty_out3 increases, leading to a decrease in the switching frequency; and vice versa.

[0149] When the load decreases further, causing PIoutput to be less than 1000, the converter enters COT mode. At this time, the control of duty_out3 remains unchanged as shown in equation (32). However, duty_out1 is modified as follows:

[0150]

[0151] Where PIoutput_clamp is a fixed value equal to 900. In equation (33), duty_out1 is clamped to a fixed value, so that when the input voltage is constant, the conduction time is fixed, and the closed-loop regulation of the converter output voltage and output load is achieved by adjusting the frequency of duty_out3.

[0152] It is understandable that the specific values ​​of the above coefficients, thresholds and fixed values ​​need to be determined according to the actual situation and are affected by the digital-to-analog conversion resolution in the sampling module.

[0153] Reference Figure 16 As shown, in this embodiment, the working principle of the high-resolution DPWM module is as follows:

[0154] (1) DPWM3 is configured as an independent output mode. The DPWM3H function is used for the highest frequency clamp, and the conduction time is assigned by the duty_out3 variable. The frequency determined by Q4 ZVS and the highest frequency clamp determined by duty_out3 are logically ANDed, and the resulting frequency conversion signal is sent to the synchronous frequency conversion module of DPWM1, causing the counter of DPWM1 to be reset. Since the conduction time of DPWM1 is designed to be relatively small at 100ns (PG1DC=350), DPWM1 actually outputs a frequency conversion narrow pulse, which is used as the synchronization signal Sync_clk of other DPWM modules.

[0155] (2) DPWM2 is configured as a complementary output. This module accepts the synchronization signal of DPWM1 and the variable duty_out1 of the multi-mode output to control the conduction time and switching frequency of Q1 and Q2.

[0156] (3) DPWM4 is also configured as a complementary output. Like DPWM2, this module receives the synchronization signal from DPWM1 and the multi-mode output variable duty_out1 to control the on-time and switching frequency of Q4. However, under light load, the on-time of Q4 actually leads the on-time of Q1. Therefore, a Q4 ZVS detection signal is added and sent to the current-limiting function module of DPMW4. The function of this module is to turn on Q4 after detecting Q4 ZVS and turn it off when the counter = 0. The output of this function module is logically ORed with the output of the previous complementary module to generate the final Q4 control pulse width.

[0157] (4) DPWM3 is configured as an independent output mode. DPWM3L is used to generate the Q3 pulse width. The midpoint voltage v of the two bridge arms is detected. A v B This signal is used to simulate the current signal of the magnetizing inductor to determine the volt-second balance of the magnetizing inductor. This signal is compared with the zero-crossing comparator to generate the turn-off signal of Q3, which is sent to the current limiting function module of DPWM3. The initial pulse width of DPWM3L is set relatively large, and this signal is used to turn off Q3 immediately.

[0158] To further illustrate the effectiveness of the control method in this embodiment, a dual-clamp ZVS step-up / step-down converter with an input voltage range of 150V to 450V, an output voltage of 28V / 500W, a transformer magnetizing inductance of 10uH, and a turns ratio n = 6:1 was constructed. The aforementioned control system was then used to implement the control method across the entire load range, achieving the following results: Figure 17 and Figure 18 The efficiency and switching frequency versus load curves shown in the figure demonstrate that the converter controlled by the control method of this embodiment can maintain good efficiency across the entire load range, and the switching frequency versus load curve is basically consistent with the requirements.

Claims

1. A multi-mode control method for an active clamp converter, characterized in that, The control mode of the switching transistor is selected based on the real-time load, including four consecutive load threshold ranges from light to heavy: very light load, light load, medium load, and heavy load. When the real-time load is in the very light load range, the constant on-time mode is used to control the switching transistor; when the real-time load is in the light load range, the voltage-controlled oscillator mode is used to control the switching transistor; when the real-time load is in the medium load range, the intermittent on-time mode is used to control the switching transistor; and when the real-time load is in the heavy load range, the critical on-time mode is used to control the switching transistor. When the selected control mode is critical conduction mode, intermittent conduction mode, or voltage-controlled oscillator mode: ； When the selected control mode is constant on-time mode: ； When the selected control mode is critical conduction mode or intermittent conduction mode, duty_out3 is a set value; When the selected control mode is voltage-controlled oscillator mode and constant on-time mode: ； Where K_PG2DC_xishu and K_PG3DC_VCO are both conversion coefficients, PIoutput_clamp is the clamping value of the regulator output signal, Vin_AD_FF is the AD value of the clamping capacitor voltage, duty_out3 is the frequency of the control converter, and duty_out1 is the conduction time of the control converter.

2. The multi-mode control method for an active clamp converter according to claim 1, characterized in that, When the load is in the light load range, the control coefficient of the voltage-controlled oscillator mode satisfies the following condition: at the boundary between the light load range and the medium load range, the switching frequency of the converter reaches its extreme value.

3. The multi-mode control method for an active clamp converter according to claim 1, characterized in that, The boundary between the extremely light load range and the light load range is 20% of the full load, the boundary between the light load range and the medium load range is 50% of the full load, and the boundary between the medium load range and the heavy load range is 80% of the full load.

4. The multi-mode control method for an active clamp converter according to claim 1, characterized in that, Includes the following steps: S1: Acquire the input voltage V of the active clamp converter topology. in Clamping capacitor voltage V clamp And the midpoint voltage V of the two bridge arms A and V B ; S2: Select the control mode based on the real-time load status, and combine the selected control mode with the input voltage V. in Clamping capacitor voltage V clamp And the midpoint voltage V of the two bridge arms A and V B The control signals for the first to fourth switching transistors Q1, Q2, Q3 and Q4 are generated.

5. The multi-mode control method for an active clamp converter according to claim 4, characterized in that, Step S2 includes the following steps: S2.1: Based on the clamping capacitor voltage V clamp The AD value Vclamp_AD_FF and the reference voltage V ref The comparison generates an error signal V. err ; Based on the midpoint voltage V of the bridge arm B Compared with the comparator reference voltage V DAC3 The comparison generates the ZVS signal Q4_zvs and the Q4 on signal Q4_zvs_on; Based on the midpoint voltage V of the bridge arm A and V B A simulated signal for generating the excitation inductor current is generated by differential detection. This simulated signal is then amplified to generate v. Lm_sense Signal and comparator reference voltage V DAC1 The comparison generates the Q3 turn-off signal Q3_off; S2.2: Based on the error signal V err After digital loop compensation Hc(z) and clamping, the regulator output signal PIoutput is generated; S2.3: Based on the input voltage V in The AD value Vin_AD_FF and the regulator output signal PIoutput, combined with the control mode selected according to the regulator output signal PIoutput, generate two control quantities duty_out1 and duty_out3, where duty_out3 controls the converter frequency and duty_out1 controls the converter conduction time. S2.4: Generate the frequency conversion signal Sync_clk based on the ZVS signal Q4_zvs; S2.5: Based on the frequency conversion signal Sync_clk, the Q4 turn-on signal Q4_zvs_on, the Q3 turn-off signal Q3_off, and the control quantities duty_out1 and duty_out3, generate the PWM control signals for the first to fourth switching transistors Q1, Q2, Q3, and Q4. S2.6: Based on the generated PWM control signal, the current is amplified by the driver to generate the drive signals for the first to fourth switching transistors Q1, Q2, Q3 and Q4.

6. A multi-mode control system for an active clamp converter, characterized in that, include: The multi-mode control logic module is used to select the control mode of the switching transistor according to the real-time load, including four continuous load threshold ranges from light to heavy: very light load, light load, medium load, and heavy load. When the real-time load is in the very light load range, the constant on-time mode is used to control the switching transistor; when the real-time load is in the light load range, the voltage-controlled oscillator mode is used to control the switching transistor; when the real-time load is in the medium load range, the intermittent on-time mode is used to control the switching transistor; and when the real-time load is in the heavy load range, the critical on-time mode is used to control the switching transistor. When the selected control mode is critical conduction mode, intermittent conduction mode, or voltage-controlled oscillator mode: ； When the selected control mode is constant on-time mode: ； When the selected control mode is critical conduction mode or intermittent conduction mode, duty_out3 is a set value; When the selected control mode is voltage-controlled oscillator mode and constant on-time mode: ； Where K_PG2DC_xishu and K_PG3DC_VCO are both conversion coefficients, PIoutput_clamp is the clamping value of the regulator output signal, Vin_AD_FF is the AD value of the clamping capacitor voltage, duty_out3 is the frequency of the control converter, and duty_out1 is the conduction time of the control converter.

7. The multi-mode control system for the active clamp converter according to claim 6, characterized in that, Also includes: The sampling module is used to acquire the input voltage V of the converter. in Clamping capacitor voltage V clamp And the midpoint voltage V of the two bridge arms A and V B The voltage is then converted into a corresponding digital intermediate signal. The PWM module is used to generate PWM control signals for the first to fourth switching transistors based on the digital intermediate signals output by the multi-mode control logic module and the sampling module. The sampling module is built from analog circuits, while the multi-mode control logic module and PWM module are digital modules.

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