Oscillating circuit with adjustable output clock period

Abstract

The invention provides an oscillating circuit with an adjustable output clock period. The oscillation circuit realizes periodic charging and discharging of a capacitor through a feedback control mechanism so as to generate a periodic oscillation signal, and the periodic oscillation signal is shaped to generate a clock signal; and the period of the clock signal can be accurately adjusted by adjusting the charging current of the capacitor. In addition, an enabling control circuit is specially arranged and used for forbidding the oscillation circuit to work when the charging current, the power supply voltage or the related reference voltage fluctuates. The oscillation circuit provided by the invention is simple in structure, the generated clock signal period is accurate and adjustable, the driving capability is strong, and work enabling control can be conveniently carried out.

Description

Technical Field

[0001] The technical solution provided by the present invention relates to the field of integrated circuit design, and in particular to an oscillator circuit with a simple structure and an accurately adjustable output clock period. Background Art

[0002] Oscillators are an important part of many modern circuit systems, ranging from clock generation in microprocessors to carrier synthesis in cellular phones. Different application scenarios have very different requirements on the structure and performance parameters of oscillators. Therefore, designing stable and powerful oscillators has always been a topic of continuous research.

[0003] Oscillators are designed into different structures according to different needs. For example, ring oscillators, LC oscillators, cross-coupled oscillators, Colpitts oscillators, etc. Among them, the ring oscillator has no delay network, and the oscillation frequency is not easy to flexibly select. To achieve low-frequency oscillation, many NOT gates are required. In addition, due to the certain error in the gate circuit delay time, the generated frequency is not accurate enough. The disadvantages of the LC oscillator are insufficient stability and large temperature drift. It is often necessary to specially set up a corresponding temperature drift suppression circuit, resulting in a complex oscillator circuit structure. In addition to the non-negligible temperature drift, the cross-coupled oscillator has another prominent feature, which is poor load capacity. When the load resistance is large enough, it is almost impossible to start oscillation. The Colpitts oscillator circuit is limited by the resonance constraint condition that the voltage gain is at least 4. Summary of the invention

[0004] In view of the shortcomings of various existing oscillators, the present invention provides an oscillator that generates oscillations by feedback controlling the charging and discharging of a capacitor. The output oscillation signal is stable, and the period of the oscillation signal is precisely adjustable (to achieve a flexible control effect). The period accuracy of the output oscillation signal can reach microseconds or even higher.

[0005] The oscillation circuit provided by the present invention is implemented as: an oscillation circuit with adjustable output clock period, comprising: a differential amplifier circuit, a current mirror, a charge and discharge capacitor C1 and a charge and discharge switch tube, a Schmitt trigger and a shaping unit; the current mirror provides a charging current for the charge and discharge capacitor C1, and provides a constant tail current and a bias current for the differential amplifier circuit; the differential amplifier circuit amplifies the difference signal between the voltage of the charge and discharge capacitor C1 and a reference voltage and outputs it to the Schmitt trigger; the output of the Schmitt trigger is connected to the signal input end of the shaping unit and is also connected to the charge and discharge switch tube to form feedback control on the charge and discharge of the charge and discharge capacitor C1, so as to realize that the voltage of the charge and discharge capacitor C1 changes periodically within a certain range.

[0006] Furthermore, the shaping unit is implemented by an RS trigger, the inverting output terminal of the RS trigger is connected to the S terminal and outputs an oscillating clock signal, the positive output terminal and the R terminal of the RS trigger are suspended, and the clock signal input terminal of the RS trigger serves as the signal input terminal of the shaping unit.

[0007] Furthermore, the current mirror is composed of NMOS tubes MN1, MN3, MN6 and PMOS tubes MP2, MP3, MP4, MP6, MP7. The input current PI BI for controlling the charging current of the charge-discharge capacitor C1 is connected to the drain of the NMOS tube NM1. The drain of the NMOS tube NM1 is connected to the gates of the NMOS tubes NM1, NM3, and NM6, and the source of the NMOS tube NM1 is grounded. The sources of the PMOS tubes MP2, MP3, MP4, MP6, and MP7 are connected to the voltage VDD, the drain of the PMOS tube MP2 is connected to the gate, and is also connected to the drain of the NMOS tube NM3 and the gate of the PMOS tube MP3. The drain of the PMOS tube MP3 is connected to the charge-discharge capacitor C1 and the drain of the NMOS tube NM4 as the charge-discharge switch tube, and the source of the NMOS tube NM4 is grounded. The gates of the PMOS tubes MP4, MP6 and MP7 are connected to the drain of the PMOS tube MP4, the PMOS tube MP6 is used to provide tail current for the differential amplifier circuit, and the PMOS tube MP7 provides output bias for the differential amplifier circuit.

[0008] Furthermore, the differential amplifier circuit is composed of PMOS tubes MP6, MP7, MP8, MP9, and transistors Q1, Q2, and Q3. The source electrodes of the PMOS tubes MP8 and MP9 are connected to the drain electrode of the PMOS tube MP6. The gate electrode of the PMOS tube MP8 is connected to the reference voltage VREF and is AC-grounded through the filter capacitor C2, and the drain electrode is connected to the collector electrode of the transistor Q1. The gate electrode of the PMOS tube MP9 is connected to the voltage of the charging and discharging capacitor C1, and the drain electrode is connected to the collector electrode of the transistor Q2. The base electrodes of the transistors Q1 and Q2 are connected to the collector electrode of the transistor Q1 to form a current mirror, and the emitter electrode is grounded. The base electrode of the transistor Q3 is connected to the collector electrode of the transistor Q2, and the collector electrode is connected to the drain electrode of the PMOS tube MP7 as the output terminal of the differential amplifier circuit, and the emitter electrode is grounded.

[0009] Furthermore, the oscillation circuit is provided with an enable control circuit. The enable control circuit is composed of inverters INV1, INV2, PMOS tubes MP1, MP5 and NMOS tubes MN2, MN5, MN7. The enable control signal ENP is connected to the gates of the PMOS tube MP1 and the NMOS tubes MN2, MN5, MN7 via the inverter INV1, and is connected to the gate of the PMOS tube MP5 via the inverters INV1 and INV2 in turn. The source of the PMOS tube MP1 is connected to the input current PIBI, and the drain is connected to the drain of the NMOS tube MN1. The source of the PMOS tube MP5 is connected to the power supply VDD, and the drain is connected to the gates of the PMOS tubes MP4, MP6, and MP7. The drain of the NMOS tube MN2 is connected to the gates of the NMOS tubes NM1, NM3, and NM6, the drain of the NMOS tube MN5 is connected to the gate of the PMOS tube MP9, the drain of the NMOS tube MN7 is connected to the collector of the triode Q1, and the sources of the NMOS tubes MN2, MN5, and MN7 are grounded. When any of the power supply VDD, the reference voltage VREF and the input current PI BI fluctuates, the enable control circuit sets the enable control signal ENP to a low level to disable the oscillation circuit from operating.

[0010] The oscillator provided by the present invention realizes accurate and adjustable period of the oscillation signal (realizing flexible control effect) by setting a current mirror circuit to accurately control the charging size of the charging and discharging capacitors. The period accuracy of the output oscillation signal can reach microsecond level or even higher, and the output oscillation signal is stable with small temperature drift. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of an oscillator circuit provided by the present invention in one embodiment. DETAILED DESCRIPTION

[0012] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Generally, the components of the embodiments of the present invention described and shown in the accompanying drawings here can be arranged and designed in various different configurations.

[0013] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0014] like Figure 1As shown, the oscillation circuit provided by the present invention is composed of a differential amplifier circuit, a current mirror, a charge and discharge capacitor C1 and a charge and discharge switch tube, a Schmitt trigger, a shaping unit and an enable control circuit. The current mirror provides a charging current for the charge and discharge capacitor C1, and provides a constant tail current and a bias current for the differential amplifier circuit. The differential amplifier circuit amplifies the difference signal between the voltage of the charge and discharge capacitor C1 and the reference voltage and outputs it to the Schmitt trigger. The output of the Schmitt trigger is connected to the signal input end of the shaping unit and is also connected to the charge and discharge switch tube to form feedback control on the charge and discharge of the charge and discharge capacitor C1, so as to realize the periodic change of the voltage of the charge and discharge capacitor C1 within a certain range. The enable control circuit prohibits the oscillation circuit from working when any of the power supply VDD, the reference voltage and the input current PIBI used to control the charging current size of the charge and discharge capacitor C1 fluctuates.

[0015] The current mirror is composed of NMOS tubes MN1, MN3, MN6 and PMOS tubes MP2, MP3, MP4, MP6, MP7. PMOS tubes MP4, MP6, MP7 form a current mirror to provide tail current and bias current for the differential amplifier circuit. The input current PIBI for controlling the charging current of the charge and discharge capacitor C1 is connected to the drain of the NMOS tube NM1. The drain of the NMOS tube NM1 is connected to the gates of the NMOS tubes NM1, NM3, and NM6, and the source of the NMOS tube NM1 is grounded. The sources of the PMOS tubes MP2, MP3, MP4, MP6, and MP7 are connected to the voltage VDD, the drain of the PMOS tube MP2 is connected to the gate, and is also connected to the drain of the NMOS tube NM3 and the gate of the PMOS tube MP3. The drain of the PMOS tube MP3 is connected to the charge and discharge capacitor C1 and the drain of the NMOS tube NM4 as the charge and discharge switch tube, and the source of the NMOS tube NM4 is grounded. The gates of the PMOS tubes MP4, MP6 and MP7 are connected to the drain of the PMOS tube MP4, the PMOS tube MP6 is used to provide a tail current for the differential amplifier circuit, and the PMOS tube MP7 provides an output bias current for the differential amplifier circuit.

[0016] The differential amplifier circuit is composed of PMOS tubes MP6, MP7, MP8, MP9, and transistors Q1, Q2, Q3. The source electrodes of PMOS tubes MP8 and MP9 are connected to the drain electrode of PMOS tube MP6. The gate electrode of PMOS tube MP8 is connected to the reference voltage VREF and is AC-grounded through filter capacitor C2, and the drain electrode is connected to the collector electrode of transistor Q1. The gate electrode of PMOS tube MP9 is connected to the voltage of charging and discharging capacitor C1, and the drain electrode is connected to the collector electrode of transistor Q2. The base electrodes of transistors Q1 and Q2 are connected to the collector electrode of transistor Q1 to form a current mirror, and the emitter electrode is grounded. The base electrode of transistor Q3 is connected to the collector electrode of transistor Q2, and the collector electrode is connected to the drain electrode of PMOS tube MP7 as the output terminal of the differential amplifier circuit, and the emitter electrode is grounded. The above differential amplifier circuit is used to amplify the difference signal between the voltage of the charging and discharging capacitor C1 and the reference voltage, and the common mode effect of the differential amplifier circuit is used to effectively suppress temperature drift.

[0017] The enabling control circuit is composed of inverters I NV1, I NV2, PMOS tubes MP1, MP5 and NMOS tubes MN2, MN5, MN7. The enabling control signal ENP is connected to the gates of the PMOS tube MP1 and the NMOS tubes MN2, MN5, MN7 via the inverter I NV1, and is connected to the gate of the PMOS tube MP5 via the inverters I NV1 and I NV2 in turn. The source of the PMOS tube MP1 is connected to the input current PI BI, and the drain is connected to the drain of the NMOS tube MN1. The source of the PMOS tube MP5 is connected to the power supply VDD, and the drain is connected to the gates of the PMOS tubes MP4, MP6, and MP7. The drain of the NMOS tube MN2 is connected to the gates of the NMOS tubes NM1, NM3, and NM6, the drain of the NMOS tube MN5 is connected to the gate of the PMOS tube MP9, the drain of the NMOS tube MN7 is connected to the collector of the triode Q1, and the sources of the NMOS tubes MN2, MN5, and MN7 are grounded. When any of the power supply VDD, the reference voltage VREF and the input current PI BI fluctuates, the enable control circuit sets the enable control signal ENP to a low level to disable the oscillation circuit from operating.

[0018] The shaping unit is implemented by an RS trigger. The inverting output terminal of the RS trigger is connected to the S terminal and outputs an oscillating clock signal, the positive output terminal and the R terminal of the RS trigger are suspended, and the clock signal input terminal of the RS trigger serves as the signal input terminal of the shaping unit.

[0019] The basic working principle is as follows: a differential amplifier is used to amplify the difference between the charging and discharging capacitor C1 and the reference voltage VREF. The output signal of the differential amplifier is shaped by a Schmitt trigger and then fed back to the gate of the NMOS tube NM4 at the input end of the amplifier to control its conduction and cutoff, thereby forming feedback control on the charging and discharging of the capacitor C1. The shaped output signal passes through an edge trigger to obtain a regular clock signal. The period of this clock signal is determined by the current used to charge the capacitor C1 and the capacitance of the capacitor itself.

[0020] The working process of the above oscillating circuit is divided into a discharging process and a charging process of the charging and discharging capacitor C1.

[0021] The working conditions of the above oscillator circuit are divided into two states, namely, the capacitor charging state and the capacitor discharging state. The specific working modes of the two working states are described below.

[0022] Charging state: When the gate of the NMOS tube MN4 that controls the charging and discharging of the capacitor receives a low-level signal output by the Schmitt trigger, MN4 enters the cut-off region, and MP2 and MP3 in the current mirror begin to charge the charging capacitor C1, causing the voltage value at the C1 end to start rising. At the beginning of charging, the voltage value at the end of the capacitor C1, that is, the voltage value at the input end of the PMOS tube MP9 of the differential amplifier, is less than the voltage value at the input end of the PMOS tube MP8, that is, the input reference voltage VREF. At this time, the drain of the PMOS tube MP8 outputs a higher level, and the collector of the transistor Q3 outputs a lower level. This level is shaped by the Schmitt trigger to obtain a low-level signal. This low-level signal is fed back to the gate of the NMOS tube NM4 to control the charging and discharging of the capacitor C1. As the capacitor C1 continues to charge, its voltage value continues to rise until the voltage value at the C1 end is equal to the reference voltage value VREF, the drain of the PMOS tube MP8 outputs a lower level, and the collector of the transistor Q3 outputs a higher level. This higher level is shaped by the Schmitt trigger to obtain a high-level signal. This high-level signal will form feedback control on the gate of the NMOS tube MN4, prompting the NMOS tube MN4 to enter the linear region, end the charging of the charging capacitor C1, enter the discharging state, and discharge the charge on the capacitor C1.

[0023] Discharge process: When the gate of NMOS tube MN4 receives a high-level signal output by the Schmitt trigger, it will enter the linear region, and MP2 and MP3 in the current mirror begin to discharge the charging capacitor C1, and the voltage value at the end of capacitor C1 begins to decrease. At the beginning of discharge, the voltage value at the end of capacitor C1 is slightly smaller than the voltage value at the input end of PMOS tube MP8, that is, the input reference voltage value VREF. At this time, the drain of PMOS tube MP8 outputs a lower level, and the collector of transistor Q3 outputs a higher level. This higher level is shaped by the Schmitt trigger to obtain a high-level signal. This high-level signal is fed back to the gate of NMOS tube MN4 to control the charge and discharge of capacitor C1. As capacitor C1 continues to discharge, the voltage value at the end of C1 continues to drop to a value far less than the voltage value at the input end of PMOS tube MP8, that is, the input reference voltage value VREF. The drain of PMOS tube MP8 outputs a higher level, and the collector of transistor Q3 outputs a lower level. This lower level is shaped by the Schmitt trigger to obtain a low-level signal, which is then fed back to the gate of the NMOS tube NM4 that controls the charging and discharging of the capacitor C1, prompting MN4 to enter the cut-off region, and the PMOS tubes MP2 and MP3 in the current mirror begin to charge the charging capacitor C1. Due to the feedback, the circuit will switch back and forth between the two states of capacitor charging and capacitor discharging. In such a switch, the signal output by the Schmitt trigger not only controls the charging and discharging of the capacitor C1 as a feedback signal, but also connects to the RS trigger used as a frequency divider to generate a clock square wave signal with a duty cycle of 50%. Two inverters are connected in series as a buffer to the output end of the RS trigger to isolate the front and rear stages, prevent the rear stage circuit from affecting the normal operation of the oscillator, and enable the entire circuit to stably output an oscillation signal with a precise clock period.

[0024] When the power supply VDD is insufficient, the input reference voltage VREF, or the input current source PI BI fluctuates, the signal cycle of the oscillator output will change, so that the subsequent module function cannot work normally, and the oscillator itself does not have the self-regulation ability in this case. Therefore, when the above situation occurs, the control signal ENP can be set to a low level to manually control the overall circuit to be turned off. Specifically, after the control signal ENP is converted by the inverters I NV1 and I NV2, the PMOS tubes MP1, MP5, MN5, and MN7 are controlled to turn off the oscillation circuit at the same time. Among them, the PMOS tube MP1 is turned off, so that the input current PI BI cannot flow in, and at the same time, the situation that the oscillator is turned off may affect the previous stage circuit. The PMOS tube MP5 is turned on, and the tail current tube MP6 of the differential amplifier input pair tubes MP8 and MP9 is turned off, so that the amplifier no longer has an amplification function. The NMOS tube MN5 is turned on, so that the capacitor C1 can no longer be charged and is always in a discharge state; the NMOS tube MN7 is turned on, so that the input of the Schmitt trigger is always at a low level, and the circuit can no longer output an oscillation signal, so as to avoid the output of an erroneous oscillation signal affecting the operation of the subsequent stage circuit. The above can not only completely shut down the oscillation circuit to avoid affecting the previous and next stage circuits, but also give the oscillator a stable and correct initial state. When the circuit needs to be restarted, the restart of the circuit will not be affected by the abnormal state left in the circuit in the previous shutdown state.

[0025] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An oscillator circuit with adjustable output clock period, characterized in that: The oscillator circuit comprises: Differential amplifier circuit, current mirror, charge and discharge capacitor C1 and charge and discharge switch tube, Schmitt trigger and shaping unit; The current mirror provides a charging current for the charging and discharging capacitor C1, and provides a constant tail current and a bias current for the differential amplifier circuit; The differential amplifier circuit amplifies the difference signal between the voltage of the charging and discharging capacitor C1 and the reference voltage and outputs it to the Schmitt trigger; The output of the Schmitt trigger is connected to the signal input end of the shaping unit and is also connected to the charge and discharge switch tube to form feedback control on the charge and discharge of the charge and discharge capacitor C1, so as to achieve periodic changes in the voltage of the charge and discharge capacitor C1 within a certain range.

2. The oscillation circuit according to claim 1, wherein: The shaping unit is an RS trigger, the inverting output end of the RS trigger is connected to the S end and outputs an oscillating clock signal, the positive output end and the R end of the RS trigger are suspended, and the clock signal input end of the RS trigger serves as the signal input end of the shaping unit.

3. The oscillation circuit according to claim 2, wherein: The current mirror is composed of NMOS tubes MN1, MN3, MN6, and PMOS tubes MP2, MP3, MP4, MP6, and MP7; wherein the input current PIBI is connected to the drain of the NMOS tube NM1, the drain of the NMOS tube NM1 is connected to the gates of the NMOS tubes NM1, NM3, and NM6, and the drain and source of the NMOS tube NM1 are grounded; the sources of the PMOS tubes MP2, MP3, MP4, MP6, and MP7 are connected to the voltage VDD, the drain of the PMOS tube MP2 is connected to the gate The gate of the PMOS tube MP7 is connected to the drain of the NMOS tube NM3 and the gate of the PMOS tube MP3; the drain of the PMOS tube MP3 is connected to the charge and discharge capacitor C1 and the drain of the NMOS tube NM4 serving as the charge and discharge switch tube, and the source of the NMOS tube NM4 is grounded; the gates of the PMOS tubes MP4, MP6, and MP7 are connected to the drain of the PMOS tube MP4, the PMOS tube MP6 is used to provide a tail current for the differential amplifier circuit, and the PMOS tube MP7 provides an output bias for the differential amplifier circuit.

4. The method according to claim 3, characterized in that The differential amplifier circuit is composed of PMOS tubes MP6, MP7, MP8, MP9, and transistors Q1, Q2, Q3; wherein, the source electrodes of the PMOS tubes MP8 and MP9 are connected to the drain electrode of the PMOS tube MP6, the gate electrode of the PMOS tube MP8 is connected to the reference voltage VREF and is AC-grounded through the filter capacitor C2, and the drain electrode is connected to the collector electrode of the transistor Q1, the gate electrode of the PMOS tube MP9 is connected to the voltage of the charging and discharging capacitor C1, and the drain electrode is connected to the collector electrode of the transistor Q2, the base electrodes of the transistors Q1 and Q2 are connected to the collector electrode of the transistor Q1 to form a current mirror electrode, and the emitter electrode is grounded; the base electrode of the transistor Q3 is connected to the collector electrode of the transistor Q2, and the collector electrode is connected to the drain electrode of the PMOS tube MP7 as the output terminal of the differential amplifier circuit, and the emitter electrode is grounded.

5. The oscillation circuit according to claim 4, characterized in that The oscillation circuit also includes an enable control circuit for prohibiting the oscillation circuit from working when any of the power supply VDD, the reference voltage VREF and the input current PIBI fluctuates; the enable control circuit is composed of inverters INV1, INV2, PMOS tubes MP1, MP5, NMOS tubes MN2, MN5, MN7; wherein the enable control signal ENP is connected to the gates of the PMOS tube MP1 and the NMOS tubes MN2, MN5, MN7 via the inverter INV1, and is connected to the gates of the PMOS tube MP1 and the NMOS tubes MN2, MN5, MN7 via the inverters INV1, INV2, and is connected to the gates of the PMOS tubes MN2, MN5, MN7 via the inverters INV1, INV2, and is connected to the gates of the N ... The source of the PMOS tube MP1 is connected to the input current PIBI, and the drain is connected to the drain of the NMOS tube MN1; the source of the PMOS tube MP5 is connected to the power supply VDD, and the drain is connected to the gates of the PMOS tubes MP4, MP6, and MP7; the drain of the NMOS tube MN2 is connected to the gates of the NMOS tubes NM1, NM3, and NM6, the drain of the NMOS tube MN5 is connected to the gate of the PMOS tube MP9, the drain of the NMOS tube MN7 is connected to the collector of the triode Q1, and the sources of the NMOS tubes MN2, MN5, and MN7 are grounded.

Images