Low-power-consumption adjustable RC oscillator circuit

Abstract

The invention belongs to the field of analog integrated circuits, and particularly provides a low-power-consumption adjustable RC oscillator which comprises a current and voltage reference module, an RC oscillation core module and a trimming module. And the output of the current and voltage reference module is connected with the trimming module, is also connected with the RC oscillation core module, and is used for providing reference voltage and bias current for the RC oscillation core module and providing the bias current for the trimming module. And the output of the trimming module is connected with the RC oscillation core module, and the trimming module is used for outputting a current which is not sensitive to temperature change to charge a capacitor in the RC oscillation core module. The low-power-consumption RC oscillator provided by the invention not only can ensure low power consumption, but also has excellent stability. The technical problem that a traditional RC oscillator is prone to being affected by temperature and process corners is solved, performance is kept, power consumption is reduced, and the oscillator is not affected by process deviation.

Description

Technical Field

[0001] The invention patent relates to an RC oscillator, belongs to the field of analog integrated circuits, and specifically relates to a low-power RC oscillator. Background Art

[0002] With the rapid development of artificial intelligence (AI) technology and the continuous expansion of its application areas, the demand for low-power and high-stability RC oscillators is becoming increasingly greater. Low-power and high-stability RC oscillators play an important role in many applications with strict requirements on power consumption and stability, especially high-performance AI data servers, because they can provide stable frequency output while maintaining low energy consumption. AI servers and data centers require high-performance processors and accelerators, and these devices have very high requirements for stable and accurate clock signals. RC oscillators can provide this clock signal to ensure coordinated operation between various computing nodes.

[0003] Traditional RC oscillators are usually composed of capacitors, resistors, and two inverters. However, the resistance of the resistor is easily affected by temperature changes, the accuracy of the capacitor is easily affected by process deviations, and the flip voltage of the inverter is affected by the characteristics of semiconductor devices and the power supply voltage. These factors will affect the stability of the RC oscillator, causing confusion and labeling errors in AI calculation data. The technical bottlenecks faced by low-power RC oscillators mainly focus on how to reduce power consumption while maintaining performance and not being affected by process deviations. Low-power adjustable RC oscillators are also a key technology for solving clock synchronization problems in AI computing.

[0004] In order to solve the above technical bottlenecks, the present invention realizes a low-power adjustable RC oscillator only through the clever design of the circuit. By adding a current and voltage reference module, low power consumption is achieved while eliminating the influence of power supply voltage changes on the oscillation output. Using the trimming module, the frequency can be adjusted to the vicinity of the set frequency by selecting different bias currents, and the influence of temperature and process deviations on the output frequency can be trimmed. Summary of the invention

[0005] Taking into account one or more problems in the prior art, the present invention provides a low-power RC oscillator, including a current and voltage reference module, an RC core oscillation module and a trimming module. The current and voltage reference module generates two reference currents and one reference voltage after temperature compensation; the RC core oscillation module generates a sinusoidal signal; and the trimming module can trim the effects of process angles and layout parasitic parameters.

[0006] The low-power RC oscillator provided by the present invention has the following beneficial effects: Under the premise of ensuring low power consumption, it has excellent stability and can be used in a wide voltage range of 2.5V to 5.5V and a temperature range of -40 degrees to 125 degrees, and the frequency error is controlled within 12KHz.

[0007] At 25 degrees, power supply voltage 4V, tt process angle, the RC oscillator output frequency is 1.9987Mhz, the error is less than 0.25%, and the duty cycle is 49.92%.

[0008] The power consumption is 33uA and the startup time is less than 10us.

[0009] The temperature characteristics of the RC oscillator are simulated using parameter analysis, scanning from -40 degrees to 125 degrees, with a frequency change within 11KHz, and the power consumption is always less than 34uA.

[0010] A trimming module is provided to adjust the output frequency according to specific circumstances.

[0011] The technical solution of the present invention is as follows: The low-power RC oscillator of the present invention comprises a current and voltage reference module, an RC core oscillation module and a trimming module.

[0012] The current voltage reference module has IBIAS1, IBIAS2 and VREF terminals, wherein IBIAS1 is coupled to the IBIAS terminal of the trimming module, IBIAS2 is coupled to the IBIAS terminal of the RC core oscillation module, and VREF terminal is coupled to the VREF terminal of the RC core oscillation module.

[0013] The trimming module has an IBIAS terminal and an IREF terminal, wherein the IBIAS terminal is coupled to the IBIAS terminal of the current-voltage reference module, and the IREF terminal is coupled to the IREF terminal of the RC core oscillation module.

[0014] The RC core oscillation module has an IBIAS terminal, an IREF terminal and a VREF terminal, wherein the IBIAS terminal is coupled to the IBIAS terminal of the current-voltage reference module, the IREF terminal is coupled to the IREF terminal of the trimming module, and the VREF terminal is coupled to the VREF terminal of the current-voltage reference module.

[0015] The current and voltage reference module comprises: a startup circuit, a reference voltage startup circuit, a clamping operational amplifier circuit and a reference current and voltage output circuit.

[0016] Starting circuit, including: A first delay unit having an input terminal and an output terminal, wherein a first terminal of the delay unit is coupled to an input enable signal EN; A first transistor having a source, a gate and a drain, wherein the gate is coupled to the output terminal of the first delay unit; A second transistor having a source, a gate and a drain, wherein the source is coupled to the source of the first transistor; A third transistor has a source, a gate and a drain, wherein the source is coupled to the source of the first transistor and the gate is coupled to the drain of the third transistor; a fourth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the second transistor, the gate is coupled to the gate of the third transistor, and the drain is coupled to the gate of the second transistor; A first capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the drain of the first transistor; a fifth transistor having a source, a gate and a drain, wherein the source is coupled to the second end of the first capacitor, the gate is coupled to the drain of the first transistor, and the drain is coupled to the drain of the third transistor; a sixth transistor having a source, a gate and a drain, wherein the source is coupled to the second end of the first capacitor, the gate is coupled to the gate of the fifth transistor, and the drain is coupled to the drain of the fourth transistor; The first transistor, the second transistor, the third transistor and the fourth transistor are PMOS transistors, and the fifth transistor and the sixth transistor are NMOS transistors.

[0017] A reference voltage generating circuit, comprising: a seventh transistor having a source, a gate and a drain, wherein the source is coupled to the source of the first transistor and the gate is coupled to the gate of the second transistor; an eighth transistor having a source, a gate and a drain, wherein the source is coupled to the source of the first transistor and the gate is coupled to the gate of the second transistor; a ninth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the seventh transistor and the gate is coupled to the gate of the fourth transistor; a tenth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the eighth transistor and the gate is coupled to the gate of the fourth transistor; A first resistor having a first end and a second end, wherein the first end is coupled to the drain of the ninth transistor; The first PNP bipolar transistor has an emitter, a collector and a base, wherein the emitter is coupled to the second end of the first resistor, the collector is coupled to the second end of the first capacitor, and the base is coupled to the second end of the first capacitor; A second resistor having a first end and a second end, wherein the first end is coupled to the first end of the first resistor, and the second end is coupled to the second end of the first capacitor; The second PNP bipolar transistor has an emitter, a collector and a base, wherein the emitter is coupled to the drain of the tenth transistor, the collector is coupled to the second end of the first capacitor, and the base is coupled to the second end of the first capacitor; A third resistor having a first end and a second end, wherein the first end is coupled to the drain of the tenth transistor, and the second end is coupled to the second end of the first capacitor; The seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are PMOS transistors.

[0018] Clamping operational amplifier circuit, comprising: An eleventh transistor has a source, a gate and a drain, wherein the source is coupled to the source of the first transistor and the gate is coupled to the gate of the second transistor; A twelfth transistor has a source, a gate and a drain, wherein the source is coupled to the drain of the eleventh transistor and the gate is coupled to the gate of the fourth transistor; a thirteenth transistor having a source, a gate and a drain, wherein the gate is coupled to the drain of the tenth transistor, and the drain is coupled to the drain of the twelfth transistor; a fourteenth transistor having a source, a gate and a drain, wherein the gate is coupled to the drain of the ninth transistor, and the drain is coupled to the drain of the twelfth transistor; A fifteenth transistor having a source, a gate and a drain, wherein the source is coupled to the second end of the first capacitor, the gate is coupled to the drain of the fifteenth transistor, and the drain is coupled to the source of the thirteenth transistor; a sixteenth transistor having a source, a gate and a drain, wherein the source is coupled to the second end of the first capacitor, the gate is coupled to the gate of the fifteenth transistor, and the drain is coupled to the drain of the fourteenth transistor; The eleventh transistor and the twelfth transistor are PMOS transistors, and the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor are NMOS transistors.

[0019] The reference current and voltage output circuit comprises: A seventeenth transistor has a source, a gate and a drain, wherein the source is coupled to the source of the first transistor and the gate is coupled to the gate of the second transistor; An eighteenth transistor has a source, a gate and a drain, wherein the source is coupled to the source of the first transistor and the gate is coupled to the gate of the second transistor; A nineteenth transistor has a source, a gate and a drain, wherein the source is coupled to the source of the first transistor and the gate is coupled to the gate of the second transistor; a twentieth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the seventeenth transistor, the gate is coupled to the gate of the third transistor, and the drain is coupled to the output VREF; A twenty-first transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the eighteenth transistor, the gate is coupled to the gate of the third transistor, and the drain is coupled to the output IBIAS1; a twenty-second transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the nineteenth transistor, the gate is coupled to the gate of the third transistor, and the drain is coupled to the output IBIAS2; The fourth resistor has a first end and a second end, wherein the first end is coupled to the output VREF, and the second end is coupled to the second end of the first capacitor.

[0020] RC core oscillation module circuit, including: The first capacitor C1 has a first end and a second end, wherein the second end is coupled to the ground end GND; The second capacitor C2 has a first end and a second end, wherein the first end is coupled to the ground end GND; A first inverter INV1 has an input terminal and an output terminal, wherein the output terminal is coupled to the first terminal of the first capacitor; The second inverter INV2 has an input terminal and an output terminal, wherein the output terminal is coupled to the second terminal of the second capacitor; A first comparator COMP1 having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is coupled to the output terminal of the first inverter, and the negative input terminal is coupled to VREF; A second comparator COMP2 having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is coupled to the output terminal of the second inverter, and the negative input terminal is coupled to VREF; A first RS trigger has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal is coupled to the output terminal of the first comparator COMP1, and the second input terminal is coupled to the output terminal of the second comparator COMP2; A third inverter INV3 has an input terminal and an output terminal, wherein the input terminal is coupled to the first output terminal of the RS trigger; a fourth inverter INV4 having an input terminal and an output terminal, wherein the input terminal is coupled to the second output terminal of the RS trigger; a fifth inverter INV5 having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the third inverter INV3, and the output terminal is coupled to the input terminal of the first inverter; The sixth inverter INV6 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the fourth inverter INV4, and the output terminal is coupled to the input terminal of the second inverter.

[0021] Adjustment module, including: A first transmission gate having an input terminal and an output terminal; A twenty-third transistor having a source, a gate and a drain, wherein the gate is coupled to the first transmission output terminal; A twenty-fourth transistor has a source, a gate and a drain, and a gate thereof is coupled to the gate of the twenty-third transistor; A twenty-fifth transistor has a source, a gate and a drain, wherein the drain is coupled to the gate of the twenty-third transistor; A twenty-sixth transistor having a source, a gate and a drain, wherein the gate is coupled to the source of the twenty-third transistor, and the drain is coupled to the source of the twenty-third transistor; A twenty-seventh transistor has a source, a gate and a drain, wherein the gate is coupled to the gate of the twenty-sixth transistor, and the drain is coupled to the source of the twenty-fourth transistor; A twenty-eighth transistor has a source, a gate and a drain, wherein the drain is coupled to the gate of the twenty-sixth transistor; A twenty-ninth transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS; a 30th transistor having a source, a gate and a drain, wherein the source is coupled to the source of the 29th transistor and the gate is coupled to the drain of the 29th transistor; a thirty-first transistor having a source, a gate and a drain, wherein the source is coupled to the source of the twenty-ninth transistor, and the gate is coupled to the drain of the twenty-ninth transistor; a thirty-second transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirtieth transistor, the gate is coupled to the drain of the twenty-ninth transistor, and the drain is coupled to the drain of the twenty-ninth transistor; a thirty-third transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-first transistor, and the gate is coupled to the drain of the twenty-ninth transistor; A 34th transistor has a source, a gate and a drain, and a source thereof is coupled to IBIAS; a thirty-fifth transistor having a source, a gate and a drain, wherein the source is coupled to the gate of the thirty-first transistor, and the drain is coupled to the drain of the thirty-fourth transistor; a thirty-sixth transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS and the gate is coupled to the drain of the thirty-fourth transistor; a thirty-seventh transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-sixth transistor, and the gate is coupled to the drain of the thirty-fourth transistor; a thirty-eighth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-seventh transistor, and the gate is coupled to the drain of the thirty-fourth transistor; a thirty-ninth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-eighth transistor, and the gate is coupled to the drain of the thirty-fourth transistor; a 40th transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the 39th transistor, the gate is coupled to the drain of the 34th transistor, and the drain is coupled to the drain of the 33rd transistor; a forty-first transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-seventh transistor; a 42nd transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS; a 43rd transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS and the gate is coupled to the drain of the 42nd transistor; a 44th transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the 43rd transistor, and the gate is coupled to the drain of the 42nd transistor; a forty-fifth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the forty-fourth transistor, the gate is coupled to the drain of the forty-second transistor, and the drain is coupled to the drain of the thirty-third transistor; a forty-sixth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-seventh transistor; a 47th transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS; a 48th transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS and the gate is coupled to the drain of the 47th transistor; a forty-ninth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the forty-eighth transistor, the gate is coupled to the drain of the forty-seventh transistor, and the drain is coupled to the drain of the thirty-third transistor; a 50th transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the 37th transistor; a fifty-first transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS; a fifty-second transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS and the gate is coupled to the drain of the fifty-first transistor; a fifty-third transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the fifty-second transistor, the gate is coupled to the drain of the fifty-first transistor, and the drain is coupled to the drain of the thirty-third transistor; a fifty-fourth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-seventh transistor; a fifty-fifth transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS; a fifty-sixth transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS and the gate is coupled to the drain of the fifty-fifth transistor; a fifty-seventh transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the fifty-sixth transistor, the gate is coupled to the drain of the fifty-fifth transistor, and the drain is coupled to the drain of the thirty-third transistor; a fifty-eighth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-seventh transistor; a fifty-ninth transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS; a sixtieth transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS and the gate is coupled to the drain of the fifty-ninth transistor; a sixty-first transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the sixtieth transistor, the gate is coupled to the drain of the fifty-ninth transistor, and the drain is coupled to the drain of the thirty-third transistor; a sixty-second transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-seventh transistor; a sixty-third transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS; a sixty-fourth transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS and the gate is coupled to the drain of the sixty-third transistor; a sixty-fifth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the sixty-fourth transistor, the gate is coupled to the drain of the sixty-third transistor, and the drain is coupled to the drain of the thirty-third transistor; a sixty-sixth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-seventh transistor; a sixty-seventh transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS; a sixty-eighth transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS and the gate is coupled to the drain of the sixty-seventh transistor; The sixty-ninth transistor has a source, a gate and a drain, wherein the source is coupled to the drain of the sixty-eighth transistor, the gate is coupled to the drain of the sixty-third transistor, and the drain is coupled to the drain of the thirty-third transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The specific implementation of the present invention will be described in detail below with reference to the accompanying drawings, wherein the same reference numerals represent the same components or features.

[0023] Figure 1 A circuit diagram of a low-power RC oscillator according to an embodiment of the present invention is shown.

[0024] Figure 2 A schematic diagram of a current and voltage reference module according to an embodiment of the present invention is shown.

[0025] Figure 3 A schematic diagram of an RC oscillator core module according to an embodiment of the present invention is shown.

[0026] Figure 4 A schematic diagram of a trimming module according to an embodiment of the present invention is shown.

[0027] Figure 5 A simulation diagram of an RC core oscillation module according to an embodiment of the present invention is shown.

[0028] Figure 6 A circuit diagram of a low-power RC oscillator according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0029] The specific embodiments below represent exemplary embodiments of the present invention and are essentially illustrative rather than limiting. In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present invention. However, it is obvious to those of ordinary skill in the art that these specific details are not necessary for the present invention. In other examples, in order to avoid confusing the present invention, known circuits, materials or methods are not specifically described.

[0030] In the specification, the reference to "one embodiment" or "embodiment" means that the specific features, structures or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. The term "in one embodiment" appears in various places in the specification and does not refer to the same embodiment, nor does it exclude other embodiments or variable embodiments. All features disclosed in this specification, or steps in all methods or processes disclosed, except for mutually exclusive features and / or steps, can be combined in any way. In addition, it should be understood by those of ordinary skill in the art that the diagrams provided herein are for illustrative purposes and that the diagrams are not necessarily drawn to scale. It should be understood that when an "element" is said to be "connected to" or "coupled" to another element, it can be directly connected or coupled to another element or there can be an intermediate element. On the contrary, when an element is said to be "directly connected to" or "directly coupled to" another element, there is no intermediate element. The same reference numerals indicate the same element. When an "element" is said to "receive" a signal, it can be received directly or through a switch, a resistor, a level shifter, a signal processing unit, etc. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0031] like Figure 1 The present invention provides a low-power adjustable RC oscillator including a current and voltage reference module, an RC core oscillation module and a trimming module; The current and voltage reference module is used to provide reference voltage and bias current for the RC core oscillation module, and bias current for the trimming module. The current and voltage reference module uses a low-power startup circuit, which does not consume additional power after startup. The reference current mirror loads all use a pseudo-common source common gate structure to achieve a good power supply rejection ratio. The output voltage reference uses a second-order compensation mode, and the first-order compensated current generates a reference voltage on a resistor with an opposite temperature coefficient. Specifically, the current and voltage reference module uses an op amp clamped bandgap reference circuit, and its schematic diagram is as follows: Figure 2 As shown in the figure, some enabling tubes are omitted. The whole circuit is divided into four parts: startup circuit, reference voltage generation circuit, clamping amplifier circuit and reference current and voltage output circuit.

[0032] In the startup circuit, the EN signal controls the switch of the M1 tube through the delay unit. When EN is high, END is still low, so that the M1 tube is turned on, charging C1, increasing the potential in the M6 ​​gate and the op amp, and turning on the reference voltage generation circuit. When the reference voltage generation circuit is turned on, the EN signal passes through the delay unit, END changes from low level to high level, and turns off the M1 tube.

[0033] Above the current and voltage reference module circuit is a matched cascode current mirror. Compared with the traditional cascode current mirror, the gate of the upper tube is connected to the drain of the lower tube, which increases the output impedance of the current mirror and ensures the accuracy of the mirror current while reducing the voltage drop, ensuring that the reference voltage generation circuit can still work normally at 2.5V.

[0034] The reference voltage generation circuit adopts the traditional bandgap reference structure. The emitter junction area of ​​PNP1 is eight times that of PNP2. By using the clamping operational amplifier circuit, the voltages at points a and b can be made equal. The voltage of R1 is the emitter junction voltage difference of the two tubes. The emitter junction voltage difference increases with the increase of temperature. A PTAT (proportional to absolute temperature) current is generated on R1, which is superimposed with the CTAT (complementary to absolute temperature) current on R2 and R3 to obtain the temperature compensated current IBIAS.

[0035] In order to ensure the accuracy of temperature compensation, R1, R2 and R3 are required to be resistors that do not change significantly with temperature. At the output end, the bias current is directly output through the current mirror. Resistor R4 uses two resistors to compensate each other to obtain a resistor whose resistance does not change significantly with temperature. The temperature-compensated current generates a reference voltage on resistor R4.

[0036] The RC core oscillator module adopts a ring oscillator and RC oscillator composite structure, with two symmetrical paths, which can achieve an operating frequency from 2MHz to more than 10MHz. The RC core oscillator module signal only uses the part of the capacitor charging, which can ensure a constant duty cycle of 50% while using only one reference. The addition of a three-stage inverter ensures the stability of the loop, and the output waveform can be adjusted by selecting different bias currents.

[0037] Specifically, if Figure 3 As shown, the RC core oscillator module uses a current charging RC oscillator, including three inverters, two comparators, two capacitors and an RS trigger. The principle of the RC core oscillator module is that when the power is turned on, the inverter above C1 outputs 1, and the adjusted IREF starts to charge capacitor C1. The inverter below C2 outputs 0, and the potential of C2 remains unchanged. When the potential on C1 reaches the flip voltage VREF, the comparator flips, the RS trigger jumps, and the CLKOUT output is 1. The inverter above C1 outputs 0, C1 starts to discharge, and the discharge current is uncontrolled. At this time, the inverter below C2 outputs 1 to charge C2. When the potential of C2 reaches the reference voltage, the RS trigger jumps again. The CLKOUT output is 0.

[0038] The high level time and low level time of the output waveform are determined by the reference current charging the capacitor, so the duty cycle of the output signal can be maintained at 50%. The frequency of the RC core oscillator module is determined by the reference current, reference voltage, capacitor and comparator delay time.

[0039] The transmission delay of the comparator is affected by temperature changes, so the comparator is powered by the current output by the current voltage reference module. To address the impact of voltage changes, both the reference and trim modules use a pseudo-common source structure to increase the voltage operating range.

[0040] The three-stage inverter in the loop ensures that the loop meets the Barkhausen criterion. The width-to-length ratio of the three-stage inverter is 1:2:4, in order to ensure sufficient driving capability and response speed.

[0041] The trimming module uses a current mirror circuit. The module is provided with a reference current by a current and voltage reference module, and a mirror output is a current that is insensitive to temperature changes to charge the capacitor in the RC core oscillation module.

[0042] like Figure 4As shown in the figure, in the trimming module, eight trimming bits are designed with an accuracy range of 45~55nA and a trimming range of 4uA to 12.75uA. The module inputs 1uA of current from the current and voltage reference module as a reference. The NMOS current mirror adopts a common source and common gate structure, and the upper PMOS current mirror adopts a pseudo common source and common gate structure. The mirror current of the first BIAS of the mirror is 4uA, and the currents of 0 to 7 are 50, 100, 200, 400, 800, 1600, 3200, and 6400nA respectively. The nine currents are superimposed and output to charge the capacitor. In this way, the accuracy of the overall trimming range and precision can be guaranteed, and compared with the resistance trimming mode, the current trimming has smaller requirements on the layout and process, and the occupied area is also smaller.

[0043] The basic idea of ​​the present invention is that the traditional RC oscillator has a simple structure but poor stability. The present invention improves the stability of the RC oscillator while reducing power consumption by adding a low-power current and voltage reference module, modifying the current charging RC core, and adding a high-precision wide-range trim module.

[0044] like Figure 5 As shown in the figure, the RC core oscillator module output frequency is 1.9983Mhz and the duty cycle is 49.92% at 25 degrees, power supply voltage 4V, and tt process angle. The power consumption is 33uA and the startup time is 15us. The temperature characteristics of the RC oscillator are simulated by parameter analysis. The frequency changes within 11KHz from -40 degrees to 125 degrees, and the power consumption is always less than 34uA. The duty cycle is also greater than 49.5% and less than 50.5%.

[0045] The quantifiers "a", "an", etc. used in the present disclosure do not exclude plural references. "First", "second", etc. in the text only indicate the order of appearance in the description of the embodiments, so as to distinguish similar components. The appearance of "first" and "second" in the claims is only to facilitate the quick understanding of the claims and is not intended to limit them. Any figure marks in the claims should not be interpreted as limiting the scope.

[0046] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A low power adjustable RC oscillator circuit, characterized in that: include: Current and voltage reference module, RC core oscillation module and trimming module; A current voltage reference module having an IBIAS1 terminal, an IBIAS2 terminal and a VREF terminal, wherein IBIAS1 is coupled to the IBIAS terminal of the trimming module, IBIAS2 is coupled to the IBIAS terminal of the RC core oscillator module, and VREF is coupled to the VREF terminal of the RC core oscillator module; The trimming module has an IBIAS terminal and an IREF terminal, wherein the IBIAS terminal is coupled to the IBIAS terminal of the current voltage reference module, and the IREF terminal is coupled to the IREF terminal of the RC core oscillation module; The RC core oscillation module has an IBIAS terminal, an IREF terminal and a VREF terminal, wherein the IBIAS terminal is coupled to the IBIAS terminal of the current-voltage reference module, the IREF terminal is coupled to the IREF terminal of the trimming module, and the VREF terminal is coupled to the VREF terminal of the current-voltage reference module.

2. The current and voltage reference module according to claim 1, characterized in that: include: A start-up circuit, a reference voltage generating circuit, a clamping operational amplifier circuit and a reference current and voltage output circuit; In the current and voltage reference module, a low-power startup circuit is used, and the startup circuit does not consume additional power after startup; the reference current mirror loads all adopt a pseudo-common source and common gate structure to achieve a good power supply rejection ratio; the output voltage reference adopts a second-order compensation mode, and the first-order compensated current generates a reference voltage on a resistor with a temperature coefficient opposite to it.

3. The starting circuit according to claim 2, characterized in that: include: A first delay unit having an input terminal and an output terminal, wherein a first terminal of the delay unit is coupled to an input enable signal EN; A first transistor having a source, a gate and a drain, wherein the gate is coupled to the output terminal of the first delay unit; A second transistor having a source, a gate and a drain, wherein the source is coupled to the source of the first transistor; A third transistor has a source, a gate and a drain, wherein the source is coupled to the source of the first transistor and the gate is coupled to the drain of the third transistor; a fourth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the second transistor, the gate is coupled to the gate of the third transistor, and the drain is coupled to the gate of the second transistor; A first capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the drain of the first transistor; a fifth transistor having a source, a gate and a drain, wherein the source is coupled to the second end of the first capacitor, the gate is coupled to the drain of the first transistor, and the drain is coupled to the drain of the third transistor; a sixth transistor having a source, a gate and a drain, wherein the source is coupled to the second end of the first capacitor, the gate is coupled to the gate of the fifth transistor, and the drain is coupled to the drain of the fourth transistor; The first transistor, the second transistor, the third transistor and the fourth transistor are PMOS transistors, and the fifth transistor and the sixth transistor are NMOS transistors.

4. The reference voltage generating circuit according to claim 2, wherein: include: a seventh transistor having a source, a gate and a drain, wherein the source is coupled to the source of the first transistor and the gate is coupled to the gate of the second transistor; an eighth transistor having a source, a gate and a drain, wherein the source is coupled to the source of the first transistor and the gate is coupled to the gate of the second transistor; a ninth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the seventh transistor and the gate is coupled to the gate of the fourth transistor; a tenth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the eighth transistor and the gate is coupled to the gate of the fourth transistor; A first resistor having a first end and a second end, wherein the first end is coupled to the drain of the ninth transistor; The first PNP bipolar transistor has an emitter, a collector and a base, wherein the emitter is coupled to the second end of the first resistor, the collector is coupled to the second end of the first capacitor, and the base is coupled to the second end of the first capacitor; A second resistor having a first end and a second end, wherein the first end is coupled to the first end of the first resistor, and the second end is coupled to the second end of the first capacitor; The second PNP bipolar transistor has an emitter, a collector and a base, wherein the emitter is coupled to the drain of the tenth transistor, the collector is coupled to the second end of the first capacitor, and the base is coupled to the second end of the first capacitor; A third resistor having a first end and a second end, wherein the first end is coupled to the drain of the tenth transistor, and the second end is coupled to the second end of the first capacitor; The seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are PMOS transistors.

5. The clamping operational amplifier circuit according to claim 2, characterized in that: include: An eleventh transistor has a source, a gate and a drain, wherein the source is coupled to the source of the first transistor and the gate is coupled to the gate of the second transistor; A twelfth transistor has a source, a gate and a drain, wherein the source is coupled to the drain of the eleventh transistor and the gate is coupled to the gate of the fourth transistor; a thirteenth transistor having a source, a gate and a drain, wherein the gate is coupled to the drain of the tenth transistor, and the drain is coupled to the drain of the twelfth transistor; a fourteenth transistor having a source, a gate and a drain, wherein the gate is coupled to the drain of the ninth transistor, and the drain is coupled to the drain of the twelfth transistor; A fifteenth transistor having a source, a gate and a drain, wherein the source is coupled to the second end of the first capacitor, the gate is coupled to the drain of the fifteenth transistor, and the drain is coupled to the source of the thirteenth transistor; a sixteenth transistor having a source, a gate and a drain, wherein the source is coupled to the second end of the first capacitor, the gate is coupled to the gate of the fifteenth transistor, and the drain is coupled to the drain of the fourteenth transistor; The eleventh transistor and the twelfth transistor are PMOS transistors, and the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor are NMOS transistors.

6. The reference current and voltage output circuit according to claim 2, wherein: include: A seventeenth transistor has a source, a gate and a drain, wherein the source is coupled to the source of the first transistor and the gate is coupled to the gate of the second transistor; An eighteenth transistor has a source, a gate and a drain, wherein the source is coupled to the source of the first transistor and the gate is coupled to the gate of the second transistor; A nineteenth transistor has a source, a gate and a drain, wherein the source is coupled to the source of the first transistor and the gate is coupled to the gate of the second transistor; a twentieth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the seventeenth transistor, the gate is coupled to the gate of the third transistor, and the drain is coupled to the output VREF; A twenty-first transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the eighteenth transistor, the gate is coupled to the gate of the third transistor, and the drain is coupled to the output IBIAS1; a twenty-second transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the nineteenth transistor, the gate is coupled to the gate of the third transistor, and the drain is coupled to the output IBIAS2; The fourth resistor has a first end and a second end, wherein the first end is coupled to the output VREF, and the second end is coupled to the second end of the first capacitor.

7. The RC core oscillator module according to claim 1, characterized in that: include: The first capacitor C1 has a first end and a second end, wherein the second end is coupled to the ground end GND; The second capacitor C2 has a first end and a second end, wherein the first end is coupled to the ground end GND; A first inverter INV1 has an input terminal and an output terminal, wherein the output terminal is coupled to the first terminal of the first capacitor; The second inverter INV2 has an input terminal and an output terminal, wherein the output terminal is coupled to the second terminal of the second capacitor; A first comparator COMP1 having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is coupled to the output terminal of the first inverter, and the negative input terminal is coupled to VREF; A second comparator COMP2 having a positive input terminal, a negative input terminal and an output terminal, wherein the positive input terminal is coupled to the output terminal of the second inverter, and the negative input terminal is coupled to VREF; A first RS trigger has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal is coupled to the output terminal of the first comparator COMP1, and the second input terminal is coupled to the output terminal of the second comparator COMP2; A third inverter INV3 has an input terminal and an output terminal, wherein the input terminal is coupled to the first output terminal of the RS trigger; a fourth inverter INV4 having an input terminal and an output terminal, wherein the input terminal is coupled to the second output terminal of the RS trigger; a fifth inverter INV5 having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the third inverter INV3, and the output terminal is coupled to the input terminal of the first inverter; The sixth inverter INV6 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the fourth inverter INV4, and the output terminal is coupled to the input terminal of the second inverter.

8. The adjustment module according to claim 1, characterized in that: include: A first transmission gate having an input terminal and an output terminal; A twenty-third transistor having a source, a gate and a drain, wherein the gate is coupled to the first transmission output terminal; A twenty-fourth transistor has a source, a gate and a drain, and a gate thereof is coupled to the gate of the twenty-third transistor; A twenty-fifth transistor has a source, a gate and a drain, wherein the drain is coupled to the gate of the twenty-third transistor; A twenty-sixth transistor having a source, a gate and a drain, wherein the gate is coupled to the source of the twenty-third transistor, and the drain is coupled to the source of the twenty-third transistor; A twenty-seventh transistor has a source, a gate and a drain, wherein the gate is coupled to the gate of the twenty-sixth transistor, and the drain is coupled to the source of the twenty-fourth transistor; A twenty-eighth transistor has a source, a gate and a drain, wherein the drain is coupled to the gate of the twenty-sixth transistor; A twenty-ninth transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS; a 30th transistor having a source, a gate and a drain, wherein the source is coupled to the source of the 29th transistor and the gate is coupled to the drain of the 29th transistor; a thirty-first transistor having a source, a gate and a drain, wherein the source is coupled to the source of the twenty-ninth transistor, and the gate is coupled to the drain of the twenty-ninth transistor; a thirty-second transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirtieth transistor, the gate is coupled to the drain of the twenty-ninth transistor, and the drain is coupled to the drain of the twenty-ninth transistor; a thirty-third transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-first transistor, and the gate is coupled to the drain of the twenty-ninth transistor; A 34th transistor has a source, a gate and a drain, and a source thereof is coupled to IBIAS; a thirty-fifth transistor having a source, a gate and a drain, wherein the source is coupled to the gate of the thirty-first transistor, and the drain is coupled to the drain of the thirty-fourth transistor; a thirty-sixth transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS and the gate is coupled to the drain of the thirty-fourth transistor; a thirty-seventh transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-sixth transistor, and the gate is coupled to the drain of the thirty-fourth transistor; a thirty-eighth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-seventh transistor, and the gate is coupled to the drain of the thirty-fourth transistor; a thirty-ninth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-eighth transistor, and the gate is coupled to the drain of the thirty-fourth transistor; a 40th transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the 39th transistor, the gate is coupled to the drain of the 34th transistor, and the drain is coupled to the drain of the 33rd transistor; a forty-first transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-seventh transistor; a 42nd transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS; a 43rd transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS and the gate is coupled to the drain of the 42nd transistor; a 44th transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the 43rd transistor, and the gate is coupled to the drain of the 42nd transistor; a forty-fifth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the forty-fourth transistor, the gate is coupled to the drain of the forty-second transistor, and the drain is coupled to the drain of the thirty-third transistor; a forty-sixth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-seventh transistor; a 47th transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS; a 48th transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS and the gate is coupled to the drain of the 47th transistor; a forty-ninth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the forty-eighth transistor, the gate is coupled to the drain of the forty-seventh transistor, and the drain is coupled to the drain of the thirty-third transistor; a 50th transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the 37th transistor; a fifty-first transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS; a fifty-second transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS and the gate is coupled to the drain of the fifty-first transistor; a fifty-third transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the fifty-second transistor, the gate is coupled to the drain of the fifty-first transistor, and the drain is coupled to the drain of the thirty-third transistor; a fifty-fourth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-seventh transistor; a fifty-fifth transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS; a fifty-sixth transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS and the gate is coupled to the drain of the fifty-fifth transistor; a fifty-seventh transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the fifty-sixth transistor, the gate is coupled to the drain of the fifty-fifth transistor, and the drain is coupled to the drain of the thirty-third transistor; a fifty-eighth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-seventh transistor; a fifty-ninth transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS; A sixtieth transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS and the gate is coupled to the drain of the fifty-ninth transistor; a sixty-first transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the sixtieth transistor, the gate is coupled to the drain of the fifty-ninth transistor, and the drain is coupled to the drain of the thirty-third transistor; a sixty-second transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-seventh transistor; a sixty-third transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS; a sixty-fourth transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS and the gate is coupled to the drain of the sixty-third transistor; a sixty-fifth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the sixty-fourth transistor, the gate is coupled to the drain of the sixty-third transistor, and the drain is coupled to the drain of the thirty-third transistor; a sixty-sixth transistor having a source, a gate and a drain, wherein the source is coupled to the drain of the thirty-seventh transistor; a sixty-seventh transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS; a sixty-eighth transistor having a source, a gate and a drain, wherein the source is coupled to IBIAS and the gate is coupled to the drain of the sixty-seventh transistor; The sixty-ninth transistor has a source, a gate and a drain, wherein the source is coupled to the drain of the sixty-eighth transistor, the gate is coupled to the drain of the sixty-third transistor, and the drain is coupled to the drain of the thirty-third transistor.

9. The RC core oscillator module according to claim 1, wherein: In the RC core oscillator module, a ring oscillator and RC oscillator composite structure is adopted, and the two paths are symmetrical to improve the frequency accuracy. A three-level inverter is used to ensure the stability of the loop. At the same time, the output waveform is adjusted by selecting different bias currents.

10. The adjustment module according to claim 1, characterized in that: In the trimming module, a current mirror circuit is used. The NMOS current mirror adopts a common source and common gate structure, and the PMOS current mirror adopts a pseudo common source and common gate structure. The trimming module is provided with a reference current by the current and voltage reference module, and the mirror outputs a current that is insensitive to temperature changes to charge the capacitor in the core oscillation. The trimming module can generate a bias current with an accuracy range of 45~50nA and a trimming range of 4uA to 12.75uA. The output frequency can be adjusted by adjusting the bias current, and this can solve the influence of different process angles and layout parasitic parameters on the output signal and duty cycle.

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