Leakage current control circuit
By designing a leakage current control circuit in the current sense amplifier circuit, and using differential amplifier units and switching devices to control the current leakage path of the feedback loop, the problem of leakage current in the current sense amplifier circuit is solved, and effective control of leakage current and improved circuit stability is achieved.
Patent Information
- Application Number
- CN202411998859.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-05-06
AI Technical Summary
There is a leakage circuit problem in the current sense amplifier circuit, causing leakage current to flow into the next stage of the circuit, causing serious impact.
A leakage current control circuit is designed, including a differential amplifier unit and a switching device. By controlling the on- or off of the switching device, the current leakage path of the feedback loop is synchronized to prevent leakage current from flowing into the next stage of the circuit.
Effectively prevent leakage current from flowing into the next stage of circuit, improve the leakage current phenomenon of the current sense amplifier circuit, and improve the stability and reliability of the circuit.
Smart Images
Figure CN119945345A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the technical field of leakage current testing, and in particular to a leakage current control circuit. Background Art
[0002] The resistor feedback current sense amplifier (CSA) can realize the current sensing of high side and low side. The gain of the known amplifier is A. V , the load is Load, the output voltage is Vout, and the detection resistor is R sense By measuring the output signal, the input current can be accurately detected, that is: I sense =
[0003] V OUT / A V / R sense . When the power supply voltage is 0V and the input common mode is greater than 0V, there will be two leakage paths. The in-phase input signal IN+ flows into the ground GND through R1 and R3; IN- flows into the power supply or directly into the next stage circuit through R2, R4, VOUT, and the body diode D1 of the output stage transistor Mp1, and as the common mode voltage (Vcm) increases, the leakage current increases linearly. Example: When the in-phase input signal IN+ = the inverting input IN- = 36V, R1 = R2 = 10kΩ, R3 = R4 = 500kΩ, the leakage of the two branches reaches about 72uA respectively. In the circuit driven by CSA, I leakage1 Some of it may flow into the next-level circuit, causing serious consequences that need to be resolved. Summary of the invention
[0004] The main purpose of the embodiments of the present application is to provide a leakage current control circuit to solve the problem of leakage current in the current detection amplifier circuit in the related art.
[0005] According to one aspect of an embodiment of the present application, a leakage current control circuit is provided, comprising: a differential amplifier unit, configured to be provided with a switching device in a feedback loop, wherein the power input terminal of the differential amplifier unit is connected to a driving power supply; the driving power supply is also connected to a control terminal of the switching device, and the control terminal is used to control the on or off of the switching device; by controlling the on or off of the switching device, the current discharge path of the feedback loop is synchronously turned on or off.
[0006] According to at least one specific implementation of the embodiment of the present application, a current detection amplifier is provided in the differential amplifier unit, a non-inverting input terminal of the current detection amplifier is connected to the first resistor, and an inverting input terminal of the current detection amplifier is connected to the second resistor.
[0007] According to at least one specific implementation of the embodiment of the present application, a fourth resistor is arranged on the feedback loop, the switching device includes a first switching device, one end of the fourth resistor is connected between the second resistor and the inverting input terminal, and the other end is connected to the first switching device, and the first switching device is connected to the output terminal of the current detection amplifier.
[0008] According to at least one specific implementation of the embodiment of the present application, the first switching device is a first MOS tube, the gate of the first MOS tube is connected to the driving power supply, the drain of the first MOS tube is connected to the fourth resistor, and the source of the first MOS tube is connected to the output end of the current detection amplifier.
[0009] According to at least one specific implementation of the embodiment of the present application, it also includes a first voltage-resistant device connected between the fourth resistor and the first switching device.
[0010] According to at least one specific embodiment of the embodiments of the present application, the first voltage-withstand device is a first high-voltage depletion-type NMOS tube, the gate of the first high-voltage depletion-type NMOS tube is connected to a driving power supply, the source of the first high-voltage depletion-type NMOS tube is connected to the drain of the first MOS tube, and the drain of the first high-voltage depletion-type NMOS tube is connected to the fourth resistor.
[0011] According to at least one specific implementation of the embodiments of the present application, the switching device also includes a second switching device and a third resistor, one end of the third resistor is connected between the first resistor and the in-phase end of the current detection amplifier, and the other end is connected to the second switching device, and the second switching device is grounded.
[0012] According to at least one specific implementation of the embodiments of the present application, the second switching device is a second MOS tube, the gate of the second MOS tube is connected to the driving power supply, the source of the second MOS tube is grounded, the drain of the second MOS tube is connected to the third resistor, and also includes a second voltage-resistant device, which is connected between the second switching device and the third resistor.
[0013] According to at least one specific embodiment of the embodiments of the present application, the second voltage-withstand device is a second high-voltage depletion-type NMOS tube, the gate of the second high-voltage depletion-type NMOS tube is connected to the driving power supply, the source of the second high-voltage depletion-type NMOS tube is connected to the drain of the second MOS tube, and the drain of the second high-voltage depletion-type NMOS tube is connected to the third resistor.
[0014] According to at least one specific implementation of the embodiment of the present application, it also includes a common-mode circuit unit, which is connected to the differential amplifier unit, the common-mode circuit unit is configured to process a common-mode input signal, and the ground terminal of the differential amplifier unit is grounded.
[0015] The beneficial technical effects of the embodiments of the present application are:
[0016] The leakage current control circuit provided in the embodiment of the present application can be used to perform leakage detection on a current detection amplifier. A differential amplifier unit is configured in the leakage current control circuit, and a switching device is configured in the differential amplifier unit. By controlling the on or off state of the switching device, the on or off state of the current discharge path in the differential amplifier unit is synchronously controlled to prevent the leakage current from flowing into the next-level circuit, thereby improving the leakage current phenomenon of the current detection amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the specific implementation methods of the embodiments of the present application or the technical solutions in the related technologies, the drawings required for use in the specific implementation methods or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some implementation methods of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0018] Figure 1 This is the leakage current schematic of a basic resistor feedback current sense amplifier.
[0019] Figure 2 This is a circuit schematic diagram of a leakage current control circuit and a current detection amplifier circuit.
[0020] Figure 3 This is the circuit schematic diagram of the leakage current control circuit and the current detection amplifier after adding the voltage-withstand device. DETAILED DESCRIPTION
[0021] In order to enable those skilled in the art to better understand the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only implementation methods of a part of the embodiments of the present application, rather than all implementation methods. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the embodiments of the present application.
[0022] It should be noted that the terms "first", "second", etc. in the specification and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0023] In addition, the terms "installed", "set", "provided with", "connected", "connected", and "socketed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.
[0024] It should be noted that, in the absence of conflict, the implementation methods and features in the embodiments of the present application can be combined with each other. The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0025] like Figure 1 As shown, the output stage transistor Mp1 and the output lower tube Mn1 are connected between the driving power supply VCC and the ground GND. When the power supply voltage is 0V and the input common mode is greater than 0V, there will be multiple leakage paths. The leakage path I leakage2 The input signal IN+ through the in-phase terminal flows into the ground GND through the first resistor R1 and the third resistor R3, and the leakage path I leakage1 The inverting input signal IN- flows into the driving power supply VCC through the second resistor R2, the fourth resistor R4, the output terminal VOUT, and the body diode D1 of the output stage transistor Mp1, or directly flows into the next stage circuit, and the power direction leakage current I flows to the driving power supply VCC. leakage1_vcc , the output leakage current I flows into the next stage circuit leakage1_VOUT , and as the common mode voltage (Vcm) increases, the leakage current increases linearly. Example: When IN+=IN-=36V, R1=R2=10kΩ, R3=R4=500kΩ, the leakage current of the two branches reaches about 72uA respectively. The circuit driven by the current detection amplifier circuit CSA, I leakage1 Some of the leakage current may flow into the next level circuit, causing serious impact. Therefore, a solution that can greatly improve the leakage current is proposed.
[0026] like Figure 2 and Figure 3 As shown, an embodiment of the present application provides a leakage current control circuit, including:
[0027] The differential amplifier unit I is configured to be configured to be provided with a switching device in the feedback loop, and the power input end of the differential amplifier unit I is connected to the driving power supply. The function of the differential amplifier unit I is to amplify the differential signal, that is, to process the voltage difference between the non-inverting input end and the inverting input end. In some specific implementations of the embodiments of the present application, a resistive feedback current detection amplifier CSA is selected as the differential amplifier. In other specific implementations, the differential amplifier unit I can also use a matching transistor or other types of operational amplifiers. A switching device is provided in the feedback loop of the differential amplifier unit I. In the embodiments of the present application, the switching device mainly uses a MOS tube, but it does not mean that the selection of the switching device is limited to the MOS tube. In other specific implementations, the switching device can also be selected to include other types of electronic switches such as triodes and transistors. The conduction and shutdown of the feedback loop of the differential amplifier unit I can also be controlled by electronic switching devices such as triodes.
[0028] Common-mode circuit unit II, common-mode circuit unit II is connected to differential amplifier unit I, and common-mode circuit unit II is configured to process common-mode input signals. The main function of common-mode circuit unit II is to suppress or filter out common-mode input noise, reduce the influence of common-mode noise on differential signals, and provide high-quality differential input signals for differential amplifier unit I.
[0029] The driving power supply is configured to be connected to the control end of the switching device, and the control end is used to control the on or off of the switching device. The function of the driving power supply is to provide the switching device with a voltage or current for on or off. For the convenience of understanding, in the embodiment of the present application, the driving power supply is directly connected to the gate or base of the switching device, and the peripheral circuit of the switching device is omitted. Those skilled in the art can configure the peripheral circuit corresponding to the switching device by themselves according to the common technical knowledge in this field to realize the function of the switching circuit, and by controlling the on or off of the switching device, the current discharge path of the feedback loop is synchronously turned on or off.
[0030] In the main implementation manner provided in the embodiment of the present application, a current detection amplifier CSA is provided in the differential amplifier unit I, a first resistor R1 and a second resistor R2 are provided between the current detection amplifier CSA and the common mode circuit unit II, the non-inverting input terminal of the current detection amplifier CSA is connected to the first resistor R1, and the inverting input terminal of the current detection amplifier CSA is connected to the second resistor R2. A fourth resistor R4 is provided on the feedback loop, and the switch device includes a first switch device III, one end of the fourth resistor R4 is connected between the second resistor R2 and the inverting input terminal of the current detection amplifier CAS, and the other end is connected to the first switch device III, and the first switch device III is connected to the output terminal of the current detection amplifier CSA.
[0031] Exemplarily, the first switch device III is a first MOS transistor Q1, the gate of the first MOS transistor Q1 is connected to the driving power supply VCC, the drain of the first MOS transistor is connected to the fourth resistor R4, and the source of the first MOS transistor Q1 is connected to the output end of the current detection amplifier CSA. As mentioned in the above text, the selection of the switch device is not limited to the MOS transistor. In other embodiments, by reasonably configuring the peripheral circuit, the transistor can be configured as a switch device in the feedback loop of the current detection amplifier CSA. Taking the NPN transistor as an example, when the first switch device III uses the NPN transistor, the base of the transistor is connected to the driving power supply VCC, the emitter of the transistor is connected to the output end of the current detection amplifier CSA, and the collector of the transistor is connected to the fourth resistor R4.
[0032] The leakage current control circuit provided in the embodiment of the present application can be applied to a current detection amplifier circuit, wherein the power input terminal of the resistor feedback current detection amplifier is connected to the driving power supply, and the ground terminal of the resistor feedback current detection amplifier is connected to the ground.
[0033] As a further improvement of the technical solution of the embodiment of the present application, the switching device also includes a second switching device IV, one end of the third resistor R3 is connected between the first resistor R1 and the in-phase input terminal of the current detection amplifier CSA, the other end of the third resistor R3 is connected to the second switching device IV, and the second switching device IV is grounded.
[0034] Exemplarily, the second switch device IV is a second MOS transistor Q2, the gate of the second MOS transistor Q2 is connected to the driving power supply VCC, the source of the second MOS transistor Q2 is grounded, and the drain of the second MOS transistor Q2 is connected to the third resistor R3. Similar to the situation when the first switch device is selected in the above text, the selection of the second switch device IV is not limited to the MOS transistor. In other embodiments, the transistor is configured as a switch device in the circuit branch where the third resistor R3 is located by reasonably configuring the peripheral circuit. Taking the NPN transistor as an example, when the second switch device IV uses the NPN transistor, the base connection of the transistor is connected to the driving power supply VCC, the emitter of the transistor is grounded, and the collector of the transistor is connected to the third resistor R3.
[0035] In the above implementation, native devices such as the first MOS tube Q1 and the second MOS tube Q2 are introduced into the corresponding branch. The substrate doping concentration of the native device is low, and the threshold voltage of the first MOS tube Q1 and the second MOS tube Q2 shows a property close to 0V. The native device refers to a device with a threshold voltage approximately equal to zero, for example, the threshold voltage of the first and second MOS tubes Q1 and Q2 is close to 0V, and when its gate-source voltage Vgs=0V, the switch device is in the off state. The reason for selecting native devices in the implementation here is that the threshold voltage of the native device is approximately 0V. Under the same gate-source voltage Vgs, the on-resistance of the native device is smaller than that of the conventional NMOS tube, and when Vgs=0V, it can be turned off to achieve the function of cutting off the current discharge path. Taking the driving power supply VCC=5V as an example, during normal operation, the first and second MOS tubes Q1 and Q2 are turned on. At this time, the first MOS tube Q1 and the second MOS tube Q2 are in the linear region, which is equivalent to a closed switch, and the nodes A and C are connected to the ground GND and the output terminal Vout respectively. When the driving power supply VCC=0v, the current detection amplifier CSA is in the off state, the non-inverting input terminal IN+ and the inverting input terminal IN- can be powered independently of the power supply, the non-inverting input terminal IN+ and the inverting input terminal IN- are greater than 0v, the gate-source voltage Vgs of the first MOS tube Q1 and the second MOS tube Q2 is ≤0V, the switching device is in the off state, and the current discharge path can be effectively cut off.
[0036] As a further improvement to the technical solution of the embodiment of the present application, it also includes a first voltage-resistant device and a second voltage-resistant device, the first voltage-resistant device is connected between the fourth resistor R4 and the first switching device, and the second voltage-resistant device is connected between the second switching device and the third resistor R3.
[0037] Exemplarily, the first withstand voltage device is a first high-voltage depletion-type NMOS tube V1, the gate of the first high-voltage depletion-type NMOS tube V1 is connected to the driving power supply VCC, the source of the first high-voltage depletion-type NMOS tube V1 is connected to the drain of the first MOS tube Q1, and the drain of the first high-voltage depletion-type NMOS tube V1 is connected to the fourth resistor R4. The second withstand voltage device is a second high-voltage depletion-type NMOS tube V2, the gate of the second high-voltage depletion-type NMOS tube V2 is connected to the driving power supply VCC, the source of the second high-voltage depletion-type NMOS tube V2 is connected to the drain of the second MOS tube Q2, and the drain of the second high-voltage depletion-type NMOS tube V2 is connected to the third resistor R3.
[0038] In this specific implementation, breakdown protection of the switch device is achieved by adding a withstand voltage device. Before the withstand voltage device is added, the embodiment of the present application faces a possible problem: the low-voltage device cannot withstand high voltage. When the voltage of the same-direction signal terminal and the reverse-phase signal terminal provided by the common-mode circuit unit II is higher than the breakdown voltage of the switch device, the first MOS tube Q1 and the second MOS tube Q2 may be broken down. Therefore, in order to achieve breakdown protection of the switch device, a first high-voltage depletion-type NMOS tube V1 is installed between the fourth resistor R4 and the first MOS tube Q1, and a second high-voltage depletion-type NMOS tube V2 is installed between the third resistor R3 and the second MOS tube. The first high-voltage depletion-type NMOS tube V1 and the second high-voltage depletion-type NMOS tube V2 are both high-voltage depletion-type NMOS tubes, and the drain-source and drain-gate can withstand high voltage, which can be used to protect the first MOS tube Q1 and the second MOS tube Q2, and prevent the first and second MOS tubes from being broken down by high voltage. Another advantage of using a high-voltage depletion-type NMOS tube is that the threshold voltages of the first and second high-voltage depletion-type NMOS tubes V1 and V2 are negative voltages, which will not affect the switching function of the first MOS tube Q1 and the second MOS tube Q2. For example, when the driving power supply VCC = 5V, the switching circuit works normally, the first and second MOS tubes are turned on, and the first and second high-voltage depletion-type NMOS tubes are also turned on. At this time, Q1 and Q2 are in the linear region, which is equivalent to a closed switch, connecting node A and node C to the ground GND and the output terminal Vout respectively. When the driving power supply VCC = 0V, the current detection amplifier circuit CAS is in the off state, the in-phase input terminal IN+ and the inverting input terminal IN- are high potentials, and the drains of the first high-voltage depletion-type NMOS tube V1 and the second high-voltage depletion-type NMOS tube V2 are subjected to high voltage, protecting the first MOS tube Q1 and the second MOS tube Q2. The source potentials of the first and second high-voltage depletion-type NMOS tubes V1 and V2 are approximately |vth 1，2 |, due to |vth 1，2The value of | is about 1V, that is, the drains of the first and second MOS tubes Q1 and Q2 are both at a low potential of 1V. The existence of the first and second high-voltage depletion-type NMOS tubes V1 and V2 can effectively isolate the high-voltage potentials of nodes A and C, protecting the first and second MOS tubes Q1 and Q2. At this time, the gate-source voltage Vgs of the first and second MOS tubes Q1 and Q2 is ≤ 0V, and the first and second MOS tubes Q1 and Q2 are in the off state, which can effectively cut off the discharge path of the current branch of the current detection amplifier. The source potential is about |vth 1，2 |, here vth1,2 refers to the threshold voltage of the high-voltage depletion-type device. The characteristic of this device is that the threshold vth1,2 is a negative value. The threshold voltage of the MOS tube can be simply understood as: when Vgs>threshold, the device is turned on, and when it is less than the threshold, it is turned off. Specifically: Assume VCC=0V, the threshold of the high-voltage depletion-type device is -1V, at this time, the gate voltage of the first and second high-voltage depletion-type NMOS tubes V1 and V2 is 0V, when the source voltage is less than or equal to 1V, the drain and source of the first and second high-voltage depletion-type NMOS tubes V1 and V2 can still conduct signals, and the gate-source voltage is 0V-1V=-1V at this time. When the source voltage is greater than 1V, Vgs is less than the threshold voltage, and the first and second high-voltage depletion-type NMOS tubes V1 and V2 are turned off. Therefore, in the circuit diagram, the potential of point B and the potential of point D (the source of the first and second high-voltage depletion-type NMOS tubes V1 and V2) are 1V when VCC=0V, which is the absolute value of the threshold voltage.
[0039] As a further improvement to the specific implementation of the embodiment of the present application, the on-resistance of the first and second MOS tubes, and the first and second high-voltage depletion-type NMOS tubes should be designed to be much smaller than the resistance of the third resistor R3 and the fourth resistor R4, so as to weaken the influence of the on-resistance of the above-mentioned switch device on the gain error of the current detection amplifier CSA. When the on-resistance of the switch device is much smaller than the third resistor R3 and the fourth resistor R4, the current change of the switch device has little influence on the gain error of the current detection amplifier CSA, and the output error of the current detection amplifier CSA is mainly affected by device errors such as offset voltage, gain error and nonlinearity. In the large current range, the output error is mainly determined by the gain error, and in the low current range, the influence of the offset voltage on the output error is more significant. As an example, the on-resistance of the first high-voltage depletion-type NMOS tube V1 and the second high-voltage depletion-type NMOS tube V2 should be much smaller than one thousandth or even one ten-thousandth of the third resistor R3 and the fourth resistor R4.
[0040] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0041] In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, any one of the embodiments claimed in the claims can be used in any combination in the embodiments of the present invention.
[0042] In the description of this specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.
[0043] In this application, the word "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described in this application as "exemplary" is not necessarily to be construed as being preferred or advantageous over other embodiments. The following description is given to enable any technician in the field to implement and use the present application. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other instances, well-known structures and processes will not be elaborated in detail to avoid obscuring the description of the present application with unnecessary details. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in the present application.
[0044] Although the implementation methods of the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the embodiments of the present application, and such modifications and variations are all within the scope defined by the appended claims.
Claims
1. A leakage current control circuit, characterized in that: include: A differential amplifier unit is configured to have a switch device in a feedback loop, wherein a power input terminal of the differential amplifier unit is connected to a driving power supply; The driving power supply is also connected to the control end of the switch device, and the control end is used to control the on or off of the switch device; By controlling the on or off of the switch device, the current discharge path of the feedback loop is synchronously turned on or off.
2. The leakage current control circuit according to claim 1, characterized in that: A current detection amplifier is provided in the differential amplifier unit, a non-inverting input terminal of the current detection amplifier is connected to the first resistor, and an inverting input terminal of the current detection amplifier is connected to the second resistor.
3. The leakage current control circuit according to claim 2, characterized in that: A fourth resistor is arranged on the feedback loop, the switching device comprises a first switching device, one end of the fourth resistor is connected between the second resistor and the inverting input terminal, and the other end is connected to the first switching device, and the first switching device is connected to the output terminal of the current detection amplifier.
4. The leakage current control circuit according to claim 3, characterized in that: The first switch device is a first MOS tube, a gate of the first MOS tube is connected to the driving power supply, a drain of the first MOS tube is connected to the fourth resistor, and a source of the first MOS tube is connected to the output end of the current detection amplifier.
5. The leakage current control circuit according to claim 4, characterized in that: It also includes a first voltage-resistant device connected between the fourth resistor and the first switching device.
6. The leakage current control circuit according to claim 5, characterized in that: The first voltage-withstand device is a first high-voltage depletion-type NMOS tube, a gate of the first high-voltage depletion-type NMOS tube is connected to a driving power supply, a source of the first high-voltage depletion-type NMOS tube is connected to a drain of the first MOS tube, and a drain of the first high-voltage depletion-type NMOS tube is connected to the fourth resistor.
7. The leakage current control circuit according to claim 4, characterized in that: The switch device further includes a second switch device and a third resistor, one end of the third resistor is connected between the first resistor and the in-phase terminal of the current detection amplifier, and the other end is connected to the second switch device, and the second switch device is grounded.
8. The leakage current control circuit according to claim 7, characterized in that: The second switching device is a second MOS tube, the gate of the second MOS tube is connected to the driving power supply, the source of the second MOS tube is grounded, the drain of the second MOS tube is connected to the third resistor, and also includes a second voltage-resistant device, which is connected between the second switching device and the third resistor.
9. The leakage current control circuit according to claim 8, characterized in that: The second voltage-resistant device is a second high-voltage depletion-type NMOS tube, the gate of the second high-voltage depletion-type NMOS tube is connected to the driving power supply, the source of the second high-voltage depletion-type NMOS tube is connected to the drain of the second MOS tube, and the drain of the second high-voltage depletion-type NMOS tube is connected to the third resistor.
10. The leakage current control circuit according to claim 1, characterized in that: It also includes a common mode circuit unit, which is connected to the differential amplifier unit. The common mode circuit unit is configured to process a common mode input signal. The ground terminal of the differential amplifier unit is grounded.