MOS attenuator based on transistor stray capacitance compensation phase and control method

Abstract

The invention discloses an MOS attenuator based on a transistor parasitic capacitance compensation phase and a control method. The attenuator comprises a digital logic module, a grid bias and capacitance switch module, a substrate capacitance switch module, a side capacitance module, a radio frequency attenuation module and a detection feedback loop module. The method comprises the following steps: controlling the radio frequency attenuation module to generate attenuation and compensating a phase error of the radio frequency attenuation module in an attenuation state; performing feedback gate bias voltage regulation processing on the compensated radio frequency attenuation module through an off-chip differential signal; and controlling the additional phase shift of the adjusted radio frequency attenuation module in the attenuation state, and carrying out numerical control attenuation processing on the radio frequency signal of the input end. According to the invention, the increase degree of additional phase shift can be reduced, and the influence of the change of the process corner on the source-drain resistance when the MOS transistor is in the resistance region can be reduced. The MOS attenuator based on the transistor parasitic capacitance compensation phase and the control method can be widely applied to the technical field of CMOS transceiver gain control.

Description

Technical Field

[0001] The present invention relates to the technical field of CMOS transceiver gain control, and in particular to a MOS attenuator based on transistor parasitic capacitance compensation phase and a control method. Background Art

[0002] Traditional resistor network passive attenuators are composed of multiple attenuation units cascaded, each with a different attenuation amount. When the temperature and process angle change, the attenuation accuracy of each attenuation unit will deteriorate, and the additional phase shift will increase. The degree of this attenuation accuracy deterioration and additional phase shift increase will accumulate step by step with the increase of cascaded units. Ultimately, the RMS gain error and RMS phase error of the entire attenuator will increase with changes in process angle and temperature. Summary of the invention

[0003] In order to solve the above technical problems, the purpose of the present invention is to provide a MOS attenuator and control method based on transistor parasitic capacitance compensation phase, which can reduce the degree of additional phase shift increase and reduce the impact of changes in process angle on the source-drain resistance of the MOS transistor when it is in the resistance region.

[0004] The first technical solution adopted by the present invention is: a MOS attenuator based on transistor parasitic capacitance compensation phase, including a digital logic module, a gate bias and capacitance switch module, a substrate capacitance switch module, a side capacitance module, a radio frequency attenuation module and a detection feedback loop module, wherein the first output end of the digital logic module is connected to the input end of the gate bias and capacitance switch module, the first output end of the digital logic module is connected to the input end of the substrate capacitance switch module, the third output end of the digital logic module is connected to the first input end of the radio frequency attenuation module, the output end of the gate bias and capacitance switch module is connected to the first input end of the side capacitance module, the output end of the side capacitance module is connected to the second input end of the radio frequency attenuation module, the output end of the radio frequency attenuation module is connected to the second input end of the side capacitance module, and the output end of the detection feedback loop module is connected to the third input end of the radio frequency attenuation module, wherein:

[0005] The digital logic module is used to control the operation of the gate bias and capacitance switch module, the substrate capacitance switch module and the radio frequency attenuation module;

[0006] The gate bias and capacitance switch module is used to control the RF attenuation module to produce different attenuation amounts and compensate for the phase error of the RF attenuation module in the attenuation state;

[0007] The substrate capacitance switch module is used to compensate the phase error of the radio frequency attenuation module in the attenuation state by switching the parasitic capacitance mode, and the parasitic capacitance mode includes a high-pass network mode and a low-pass network mode;

[0008] The side capacitance module is used to adjust the additional phase shift of the radio frequency attenuation module in the attenuation state;

[0009] The radio frequency attenuation module is used to perform digital control attenuation processing on the radio frequency signal at the input end to obtain a deleted radio frequency signal;

[0010] The detection feedback loop module is used to obtain an off-chip differential signal to adjust a feedback gate bias voltage and generate a feedback gate bias voltage signal.

[0011] Furthermore, the digital logic module is a decoder unit array composed of digital logic gates and inverters.

[0012] Further, the gate bias and capacitor switch module specifically includes a series MOS array gate control and capacitor switch module and a parallel MOS array gate control module, the series MOS array gate control and capacitor switch module is composed of a plurality of MOS switch tubes and high resistance, and the parallel MOS array gate control module is composed of a plurality of transmission gates and a plurality of MOS switch tubes, wherein:

[0013] The series MOS array gate control and capacitor switch module is used to control the gate potential value of the series MOS array;

[0014] The parallel MOS array gate control module is used to control the gate potential value of the parallel MOS array and control the working state of the parallel MOS array. The working state of the parallel MOS array includes a cut-off state and a resistance state.

[0015] Further, the RF attenuation module specifically includes a series MOS array and a parallel MOS array, the series MOS array is formed by a plurality of MOS transistors connected in series, the gate of the series MOS array is connected to the gate bias and capacitor switch module, the substrate of the series MOS array is connected to the substrate capacitor switch module, the series MOS array is arranged in the series branch of the RF attenuation module, the parallel MOS array is formed by a plurality of MOS transistors connected in parallel, the gate of the parallel MOS array is connected to the gate bias and capacitor switch module, wherein:

[0016] The series MOS array is formed by arranging a number of transistor layouts according to a common centroid layout, and adding dummy transistors on the periphery of the transistor layout, laying grounding metals on the source metal and the drain metal of the MOS transistors in the transistor layout, respectively, using N wells and deep N wells to isolate the series MOS array from an external P substrate, and selectively connecting the internal P substrate of the series MOS array directly to an external substrate or connecting it to an external substrate after being connected in series with a high resistance through a substrate capacitor switch module;

[0017] The parallel MOS array is formed by arranging a plurality of transistor layouts in a common centroid layout, and adding dummy transistors at the periphery of the transistor layout.

[0018] Furthermore, it also includes:

[0019] When the gate of the series MOS array is biased by a high impedance, the Cgs capacitor and the Cgd capacitor are connected in series between the source and the drain to form a high-pass network;

[0020] When the gate of the series MOS array is biased by a DC power supply, the Cgs capacitor and the Cgd capacitor are converted into source and drain electrodes connected in parallel to the ground capacitor to form a low-pass network;

[0021] When the substrate of the series MOS array is grounded through a high impedance, the Cbs capacitor and the Cbd capacitor are connected in series between the source and the drain to form a high-pass network;

[0022] When the substrate of the series MOS array is grounded, the Cbs capacitor and the Cbd capacitor are converted into source and drain capacitors connected in parallel to the ground capacitor to form a low-pass network.

[0023] Further, the detection feedback loop module specifically includes a detection feedback module, an off-chip resistor module and an on-chip MOS module, the output end of the off-chip resistor module is connected to the input end of the on-chip MOS module, the detection feedback module and the on-chip MOS module are connected to each other, and the output end of the detection feedback module is connected to the third input end of the RF attenuation module, wherein:

[0024] The off-chip resistance module is used to obtain an off-chip positive phase differential signal, and the on-chip MOS module is used to obtain an off-chip negative phase differential signal, and the off-chip positive phase differential signal is superimposed with the off-chip negative phase differential signal to obtain a superimposed differential signal;

[0025] The detection feedback module is used to obtain the off-chip positive phase differential signal and the superimposed differential signal to adjust the feedback gate bias voltage and generate a feedback gate bias voltage signal.

[0026] Further, the detection feedback module specifically includes a signal buffer module, a CHOP module and a DC voltage comparator module, the output end of the signal buffer module is connected to the input end of the CHOP module, and the output end of the CHOP module is connected to the input end of the DC voltage comparator module, wherein:

[0027] The signal buffer module is used to amplify the superimposed differential signal to obtain an amplified differential signal;

[0028] The CHOP module is used to convert the off-chip positive phase differential signal and the amplified differential signal into an AC square wave signal to obtain a first DC potential signal and a second DC potential signal;

[0029] The DC voltage comparator module is used to compare the first DC potential signal with the second DC potential signal to obtain a feedback gate bias voltage signal.

[0030] The second technical solution adopted by the present invention is: a control method of a MOS attenuator based on transistor parasitic capacitance compensation phase, comprising the following steps:

[0031] Controlling the radio frequency attenuation module to generate different attenuation amounts and compensating for the phase error of the radio frequency attenuation module in the attenuation state to obtain a compensated radio frequency attenuation module;

[0032] Performing feedback gate bias voltage adjustment processing on the compensated RF attenuation module through an off-chip differential signal to obtain an adjusted RF attenuation module;

[0033] The additional phase shift of the adjusted radio frequency attenuation module in the attenuation state is controlled to perform digital controlled attenuation processing on the radio frequency signal at the input end to obtain the deleted radio frequency signal.

[0034] The beneficial effects of the method and system of the present invention are as follows: the present invention controls the radio frequency attenuation module to produce different attenuation amounts and compensates for the phase error of the radio frequency attenuation module in the attenuation state through the gate bias and capacitance switch module and the substrate capacitance switch module, so as to realize the gain control of the transceiver transceiver path, and at the same time, the phase is compensated by using the parasitic capacitance of the MOS transistor, so as not to introduce a large phase error, and further obtains the off-chip differential signal through the detection feedback loop module to adjust the feedback gate bias voltage, and generates a feedback gate bias voltage signal, so as to realize the precise control of the source-drain resistance when the MOS transistor is in the resistance region, and reduce the influence of the change of the process angle on the source-drain resistance when the MOS transistor is in the resistance region. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a structural schematic diagram of a MOS attenuator based on transistor parasitic capacitance compensation phase of the present invention;

[0036] Figure 2 It is a flow chart of the steps of a control method of a MOS attenuator based on transistor parasitic capacitance compensation phase of the present invention;

[0037] Figure 3 is a circuit topology diagram of a radio frequency attenuation module provided in a specific embodiment of the present invention;

[0038] Figure 4 It is a schematic diagram of the common centroid arrangement of MOS transistors in a series and parallel MOS array provided by a specific embodiment of the present invention;

[0039] Figure 5 It is a parasitic model of a transistor provided by a specific embodiment of the present invention and a schematic diagram of phase compensation using parasitic capacitance;

[0040] Figure 6 It is a structural diagram of a detection feedback module provided in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0041] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only provided for the convenience of explanation and description, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0042] The development of wireless communication technology has had a profound impact on people's lifestyles. In order to meet the demand for high data transmission rate, high spectrum efficiency and low latency communication technology, wireless communication systems are moving towards higher frequency bands, such as millimeter wave bands. The millimeter wave band has advantages such as rich spectrum resources and fast data transmission rate, and due to its short wavelength, it is easy to achieve miniaturization and low-cost application. With the continuous development of communication technology, phased array technology has been introduced as an emerging technology. Phased array technology uses an antenna array composed of multiple antenna units to replace the traditional reflector antenna, and adjusts the beam direction and amplitude through beamforming technology, thereby obtaining multiple highly directional narrow beams to combat propagation loss and achieve better signal coverage. The introduction of phased array technology has brought new possibilities for the development of wireless communication systems.

[0043] Phased array radar is a device that integrates multiple functions. It is composed of a unit circuit array composed of multiple groups of antenna units. Among them, active phased array radar (APAR) is the most popular type. Compared with traditional passive phased array technology, active phased array radar has many advantages and can be widely used in aerospace and military radar fields. In recent years, with the rapid development of radio frequency integrated circuit technology and remote sensing technology, active phased array technology has possessed excellent stability and strong robustness, ultra-long-range sensitive control and self-adaptation to the surrounding environment. It has become the focus of phased array radar technology and has been widely discussed and studied.

[0044] Active phased array radar consists of many unit circuits, each of which includes active circuits at the transmitting and receiving ends, which directly determine the performance of each antenna unit. Specifically, the attenuator mainly implements two functions: first, it balances the total gain of the receiving channel to ensure that all T / R components have the same amplitude at the output; second, it adjusts the amplitude of the signal to better limit the sidelobe level of the receiving channel.

[0045] In phased array transceiver chips, the amplitude control unit is very important. The attenuator plays a key role in amplitude control, which is mainly reflected in two aspects: first, amplitude control. The attenuator can adjust the amplitude of the transmitted or received signal to achieve better amplitude control; second, gain compensation. The attenuator can be used to compensate for the amplitude error introduced by the phase shifter. In order to adapt to applications such as millimeter-wave communications and high-performance radars, the attenuator needs to have higher step accuracy and smaller additional phase shift to reduce tracking errors and calibration difficulties. In addition, considering the overall performance of the system, the attenuator also needs to have high linearity.

[0046] As an important component of the millimeter-wave phased array system, the digitally controlled attenuator has important applications in the fields of 5G millimeter-wave communication systems, millimeter-wave phased array radars, and millimeter-wave broadband satellite communication systems. It can adjust or compensate the power and amplitude of the received or transmitted signal and meet the requirements of the phased array system for beam pointing flexibility. Therefore, the research on the digitally controlled attenuator in the millimeter-wave phased array is of great significance.

[0047] Traditional resistor network passive attenuators are composed of multiple attenuation units cascaded, each with a different attenuation amount. When the temperature and process angle change, the attenuation accuracy of each attenuation unit will deteriorate, and the additional phase shift will increase. The degree of this attenuation accuracy deterioration and additional phase shift increase will accumulate step by step with the increase of cascaded units. Ultimately, the RMS gain error and RMS phase error of the entire attenuator will increase with changes in process angle and temperature.

[0048] Based on this, refer to Figure 1The present invention provides a MOS attenuator based on transistor parasitic capacitance compensation phase, the attenuator comprises a digital logic module, a gate bias and capacitance switch module, a substrate capacitance switch module, a side capacitance module, a radio frequency attenuation module and a detection feedback loop module, the first output end of the digital logic module is connected to the input end of the gate bias and capacitance switch module, the first output end of the digital logic module is connected to the input end of the substrate capacitance switch module, the third output end of the digital logic module is connected to the first input end of the radio frequency attenuation module, the output end of the gate bias and capacitance switch module is connected to the first input end of the side capacitance module, the output end of the side capacitance module is connected to the second input end of the radio frequency attenuation module, the output end of the radio frequency attenuation module is connected to the second input end of the side capacitance module, the output end of the detection feedback loop module is connected to the third input end of the radio frequency attenuation module, wherein:

[0049] The digital logic module is used to control the operation of the gate bias and capacitance switch module, the substrate capacitance switch module and the radio frequency attenuation module;

[0050] Specifically, the digital logic module is a decoder unit array composed of digital logic gates and inverters.

[0051] In this embodiment, the main structure of the digital logic module is a decoder unit array composed of digital logic gates and inverters, which mainly realizes the function of the decoder. Each decoder unit controls one of the units in the series MOS array. When the output control word of the shift register is input to the decoder unit, the decoder unit can output and control one of the units in the series MOS array, so that its attenuation state works in: on state, resistance state, off state, and the capacitance compensation state works in: compensation state or non-compensation state.

[0052] The gate bias and capacitance switch module is used to control the RF attenuation module to produce different attenuation amounts and compensate for the phase error of the RF attenuation module in the attenuation state;

[0053] Specifically, the gate bias and capacitor switch module specifically includes a series MOS array gate control and capacitor switch module and a parallel MOS array gate control module, the series MOS array gate control and capacitor switch module is composed of a number of MOS switch tubes and a high resistor, and the parallel MOS array gate control module is composed of a number of transmission gates and a number of MOS switch tubes, wherein the series MOS array gate control and capacitor switch module is used to control the gate potential value of the series MOS array; the parallel MOS array gate control module is used to control the gate potential value of the parallel MOS array and control the working state of the parallel MOS array, and the working state of the parallel MOS array includes a cut-off state and a resistance state.

[0054] In this embodiment, the gate bias and capacitor switch module includes a series MOS array gate control and capacitor switch module and a parallel MOS array gate control module, wherein the series MOS array gate control and capacitor switch module is composed of a MOS switch tube and a high resistor, and the series MOS array gate control module can independently control the gate potential value of each MOS transistor in the series MOS array, and whether the potential is given to the transistor gate through the high resistor. The parallel MOS array gate control module is composed of a transmission gate composed of a plurality of PMOS and MOS and a plurality of MOS switch tubes. The parallel MOS array gate control module can independently control the gate potential value of each MOS transistor in the parallel MOS array, thereby controlling the working state of each MOS transistor in the parallel MOS array to be a cut-off state or a resistance state.

[0055] The substrate capacitance switch module is used to compensate the phase error of the radio frequency attenuation module in the attenuation state by switching the parasitic capacitance mode, and the parasitic capacitance mode includes a high-pass network mode and a low-pass network mode;

[0056] In this embodiment, the substrate capacitance switch module specifically includes a MOS switch tube, which connects the deep N-well below the series MOS array in the layout to the on-chip ground. If the switch tube is turned on, the deep N-well is the on-chip ground. At this time, the capacitance Cdb and Csb of the MOS tube source and drain to the substrate are converted into ground capacitance. At this time, there are ground capacitances at both the source and drain nodes of the MOS tube, forming a low-pass network; if the switch tube is turned off, the deep N-well is the on-chip ground. At this time, the capacitance Cdb and Csb of the MOS tube source and drain to the substrate are connected in series between the MOS tube source and drain, forming a high-pass network. By switching these two parasitic capacitance models, compensation for the additional phase shift of the attenuation state of the RF attenuation module can be achieved.

[0057] The side capacitance module is used to adjust the additional phase shift of the radio frequency attenuation module in the attenuation state;

[0058] In this embodiment, the side capacitor module specifically includes a plurality of switch capacitor units connected in parallel to the ground, each switch capacitor unit is composed of a metal finger capacitor (MOM capacitor) connected in series with a switch MOS tube, and the gate potential of the series switch MOS tube is directly controlled by the shift register output control word. When the shift register output potential is VDD, the working state of the series switch MOS tube is on, and the switch capacitor unit presents a capacitor property to the node. When the shift register output potential is 0, the switch capacitor unit presents a high impedance characteristic to the node. By controlling whether the switch capacitor unit presents a capacitor property or a high impedance property to the node, the phase compensation function can be achieved.

[0059] The radio frequency attenuation module is used to perform digital control attenuation processing on the radio frequency signal at the input end to obtain a deleted radio frequency signal;

[0060] Specifically, Figure 3 As shown, the RF attenuation module specifically includes a series MOS array and a parallel MOS array, the series MOS array is formed by connecting several MOS transistors in series, the gate of the series MOS array is connected to the gate bias and capacitor switch module, the substrate of the series MOS array is connected to the substrate capacitor switch module, the series MOS array is arranged in the series branch of the RF attenuation module, the parallel MOS array is formed by connecting several MOS transistors in parallel, the gate of the parallel MOS array is connected to the gate bias and capacitor switch module, wherein the series MOS array is formed by arranging several transistor layouts in a common centroid layout, and Dummy transistors are added to the periphery of the transistor layout, and grounding metals are respectively laid above the source metal and drain metal of the MOS transistor in the transistor layout, and the series MOS array is isolated from the external P substrate by using N wells and deep N wells, and the internal P substrate of the series MOS array is selectively connected directly to the external substrate or connected to the external substrate after being connected in series with a high resistance through the substrate capacitor switch module; the parallel MOS array is formed by arranging several transistor layouts in a common centroid layout, and Dummy transistors are added to the periphery of the transistor layout.

[0061] It should also be noted that when the gate of the series MOS array is biased by a high resistor, the Cgs capacitor and the Cgd capacitor are connected in series between the source and the drain to form a high-pass network; when the gate of the series MOS array is biased by a DC power supply, the Cgs capacitor and the Cgd capacitor are converted into a source and a drain and connected in parallel to the ground capacitor to form a low-pass network; when the substrate of the series MOS array is grounded by a high resistor, the Cbs capacitor and the Cbd capacitor are connected in series between the source and the drain to form a high-pass network; when the substrate of the series MOS array is grounded, the Cbs capacitor and the Cbd capacitor are converted into a source and a drain and connected in parallel to the ground capacitor to form a low-pass network.

[0062] In this embodiment, the RF attenuation module specifically includes a series MOS array and a parallel MOS array. More specifically, the series MOS array is formed by connecting a plurality of MOS transistors in parallel and is placed in the series path of the RF signal of the RF attenuation module. The size ratio of the MOS transistors in the array is selected as Nm1: Nm2: Nm3: Nm4: Nm5: Nm6: Nm7: Nm8: ...: Nmi (where mi can be any positive integer greater than or equal to 1, and Nmi is a positive real number). The gate of each MOS transistor is independently controlled by the gate bias and the capacitor switch module, and the substrates (sources) of all the MOS transistors in the array are connected, and then connected to the substrate capacitor switch module and controlled by the substrate capacitor switch module.

[0063] Reference Figure 5 , when the gate of the transistor is biased by a high impedance, the Cgs and Cgd capacitors are connected in series between the source and drain to form a high-pass network. When the gate of the transistor is biased by a DC power supply (AC ground), the gate node is AC ground, so the Cgs and Cgd capacitors are converted into source and drain capacitors connected in parallel to the ground capacitor to form a low-pass network. By switching between these two parasitic capacitance models, compensation for the additional phase shift of the attenuation state of the RF attenuation module can be achieved. Similarly, when the substrate of the series MOS array is grounded through a high impedance, the Cbs and Cbd capacitors are connected in series between the source and drain to form a high-pass network. When the substrate of the series MOS array is directly grounded (AC ground), the substrate node of the series MOS array is AC ground, so the Cbs and Cbd capacitors are converted into source and drain capacitors connected in parallel to the ground capacitor to form a low-pass network. By switching between these two parasitic capacitance models, compensation for the additional phase shift of the attenuation state of the RF attenuation module can be achieved. In summary, different binary control words can be used to control the gate bias and the outputs of the capacitor switch module and the substrate capacitor switch module to control the resistance value between the source and drain of the series MOS array, the series capacitance value between the source and drain nodes, and the parasitic capacitance value of the source and drain nodes in parallel to the ground, thereby adjusting the resistance between the two nodes in the series signal path of the RF attenuation module and switching the capacitance model between the two nodes.

[0064] Reference Figure 4 The embodiment of the present invention has the following improvements in the layout design of the series MOS array:

[0065] 1) Arrange multiple transistor layouts in the series MOS array according to a common centroid layout scheme to reduce the impact of process gradients on transistor performance.

[0066] 2) Add dummy transistors at the periphery of the transistor layout of the series MOS array to reduce the influence of edge effects on the peripheral transistors in the series MOS array.

[0067] 3) Use N-well and deep N-well to completely isolate the series MOS array from the external P substrate, and use the substrate capacitor switch module to select whether to connect the internal P substrate of the series MOS array directly to the external substrate or to connect it to the external substrate after connecting a high resistance in series.

[0068] 4) In the series MOS array layout, a layer of grounding metal is laid on the source metal and drain metal of the MOS transistor, so as to convert part of the series parasitic capacitance between the source and drain metal in the layout into the source and drain capacitance to ground respectively. In this way, the influence of the series parasitic capacitance between the source and drain nodes on the bandwidth and additional phase shift of the RF attenuation module in the attenuation state is reduced.

[0069] The parallel MOS array is formed by connecting multiple MOS transistors in parallel and placed in the parallel to ground path of the RF signal of the RF attenuation module. The size ratio of the MOS transistors in the array is selected as Nm1:Nm2:Nm3:Nm4:Nm5:Nm6:Nm7:Nm8:…:Nmi (where mi can be any positive integer greater than or equal to 1, and Nmi is a positive real number). The gate of each MOS transistor is independently controlled by the gate bias and capacitor switch module. The resistance value between the source and drain of the parallel MOS array can be controlled by different binary control words, so that the node parallel to the ground resistance value of the RF attenuation module can be adjusted.

[0070] Reference Figure 4 The embodiments of the present invention have the following improvements in the layout design of the parallel MOS array:

[0071] 1) Arrange multiple transistor layouts in a parallel MOS array according to a common centroid layout scheme to reduce the impact of process gradients on transistor performance.

[0072] 2) Dummy transistors are added to the periphery of the transistor layout of the parallel MOS array to reduce the influence of edge effects on the peripheral transistors in the parallel MOS array.

[0073] The detection feedback loop module is used to obtain an off-chip differential signal to adjust a feedback gate bias voltage and generate a feedback gate bias voltage signal.

[0074] Specifically, the detection feedback loop module specifically includes a detection feedback module, an off-chip resistor module and an on-chip MOS module, the output end of the off-chip resistor module is connected to the input end of the on-chip MOS module, the detection feedback module and the on-chip MOS module are connected to each other, and the output end of the detection feedback module is connected to the third input end of the RF attenuation module, wherein the off-chip resistor module is used to obtain an off-chip positive phase differential signal, and the on-chip MOS module is used to obtain an off-chip negative phase differential signal, and the off-chip positive phase differential signal is superimposed with the off-chip negative phase differential signal to obtain a superimposed differential signal; the detection feedback module is used to obtain the off-chip positive phase differential signal and the superimposed differential signal to adjust the feedback gate bias voltage to generate a feedback gate bias voltage signal.

[0075] Furthermore, it should be noted that the detection feedback module specifically includes a signal buffer module, a CHOP module and a DC voltage comparator module, the output end of the signal buffer module is connected to the input end of the CHOP module, and the output end of the CHOP module is connected to the input end of the DC voltage comparator module, wherein the signal buffer module is used to amplify the superimposed differential signal to obtain an amplified differential signal; the CHOP module is used to convert the off-chip positive phase differential signal and the amplified differential signal into an AC square wave signal to obtain a first DC potential signal and a second DC potential signal; the DC voltage comparator module is used to compare the first DC potential signal with the second DC potential signal to obtain a feedback gate bias voltage signal.

[0076] In this embodiment, refer to Figure 6 The detection feedback module specifically includes a signal buffer module, which is mainly composed of a multi-stage inverter cascade, and plays the role of amplifying small AC signals. The CHOP module is mainly composed of an inverter and a transmission gate. Its main function is to convert the node AC signal level after the amplified off-chip differential signal is superimposed into two DC levels. The DC voltage comparator module is used to compare the size relationship of the two DC levels and output the feedback gate bias voltage at the same time.

[0077] Each circuit module in the detection feedback module is connected in sequence. The off-chip differential clock signal is transmitted to the off-chip resistor and the on-chip MOS through the PCB routing, wherein the off-chip positive phase differential signal is transmitted to the positive end of the off-chip resistor, and the off-chip negative phase differential signal is transmitted to the source end (drain end) of the on-chip MOS module. The negative end of the off-chip resistor is connected to the drain end (source end) of the on-chip MOS. This node is the node where the differential positive phase signal and the differential signal are superimposed. The differential positive phase signal and the differential signal are superimposed at this node. If the source-drain on-resistance of the off-chip resistor and the on-chip MOS is the same, then this node is a virtual ground point. If the value of the off-chip resistor is smaller than the value of the on-resistance, the node where the negative end of the off-chip resistor is connected to the drain end (source end) of the on-chip MOS will present a positive phase differential signal. On the contrary, if the value of the off-chip resistor is larger than the value of the on-resistance, the node where the negative end of the off-chip resistor is connected to the drain end (source end) of the on-chip MOS will present a negative phase differential signal. The node voltage after the differential signal superposition on the node connecting the negative end of the off-chip resistor and the drain end (source end) of the on-chip MOS is transmitted to the detection feedback module. The signal is first amplified by the signal buffer module, and then converted from an AC square wave signal to the relative size of two DC potentials through the clock-modulated CHOP module, and then adjusted by the DC voltage comparator module to change the feedback gate bias voltage. The final detection module adjusts the output feedback gate bias voltage according to the phase of the signal until the source-drain on-resistance of the on-chip MOS is equal to the off-chip resistance. The accuracy of the off-chip PCB resistance can be achieved to ±1%, so the MOS gate bias voltage output after the feedback loop can make the on-resistance of the MOS approach the accuracy of the chip resistor on the off-chip PCB.

[0078] In summary, the embodiment of the present invention provides a MOS attenuator that uses transistor parasitic capacitance to compensate for phase, which is used to achieve gain control of the transceiver transceiver path, and at the same time, the parasitic capacitance of the MOS transistor is used to compensate for the phase, so as not to introduce a large phase error. At the same time, an on-chip MOS resistor self-locking loop circuit design is provided to achieve precise control of the source-drain resistance when the MOS transistor is in the resistance region, and reduce the influence of the change of the process angle on the source-drain resistance when the MOS transistor is in the resistance region, wherein the RF attenuation module includes a plurality of MOS transistor arrays, which are used to digitally control the attenuation and output of the RF signal at the input end. The gate bias and capacitance switch module controls the gate voltage of the transistor in the attenuation module through a digital signal, thereby controlling the transistor in the digital control signal attenuation module to achieve different conduction states: conduction state, resistance state, and off state, thereby controlling the RF attenuation module to produce different attenuation amounts; in addition, the gate of the transistor in the attenuation module is controlled by a digital signal to add a bias voltage through a high resistance, thereby realizing the switching of the two parasitic capacitance modes, and realizing the compensation of the phase error of the RF attenuation module in the attenuation state. The substrate capacitance switch module controls whether the substrate of the transistor in the attenuation module is grounded through high resistance through digital signals, thereby realizing the switching of two parasitic capacitance modes, which is used to compensate for the phase error of the RF attenuation module in the attenuation state. The side capacitance module controls the opening and closing of the switch capacitor in the RF attenuation module through digital signals, which is used to adjust the additional phase shift generated by the RF attenuation module in the attenuation state. The digital logic module is used to control the gate bias and capacitance switch module, the substrate capacitance switch module, and the side capacitance module with different encodings of each group of digital control words, which is used to realize the attenuation switching of the RF attenuation module and the adjustment of the additional phase shift in the attenuation state. The detection feedback module is used to detect the node voltage after the off-chip differential signal is superimposed, and output the feedback gate bias voltage to the on-chip MOS module.

[0079] Reference Figure 2 , a control method of a MOS attenuator based on transistor parasitic capacitance compensation phase, comprising the following steps:

[0080] S100, controlling the radio frequency attenuation module to generate different attenuation amounts and compensating for the phase error of the radio frequency attenuation module in the attenuation state to obtain a compensated radio frequency attenuation module;

[0081] S200, performing feedback gate bias voltage adjustment processing on the compensated RF attenuation module through an off-chip differential signal to obtain an adjusted RF attenuation module;

[0082] S300, controlling the additional phase shift of the adjusted radio frequency attenuation module in the attenuation state, performing digital controlled attenuation processing on the radio frequency signal at the input end, and obtaining a deleted radio frequency signal.

[0083] The contents of the above method embodiments are all applicable to the present system embodiments. The functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0084] The above is a specific description of the preferred implementation of the present invention, but the invention is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A MOS attenuator based on transistor parasitic capacitance compensation phase, characterized in that: It includes a digital logic module, a gate bias and capacitance switch module, a substrate capacitance switch module, a side capacitance module, a radio frequency attenuation module and a detection feedback loop module, wherein the first output end of the digital logic module is connected to the input end of the gate bias and capacitance switch module, the first output end of the digital logic module is connected to the input end of the substrate capacitance switch module, the third output end of the digital logic module is connected to the first input end of the radio frequency attenuation module, the output end of the gate bias and capacitance switch module is connected to the first input end of the side capacitance module, the output end of the side capacitance module is connected to the second input end of the radio frequency attenuation module, the output end of the radio frequency attenuation module is connected to the second input end of the side capacitance module, and the output end of the detection feedback loop module is connected to the third input end of the radio frequency attenuation module, wherein: The digital logic module is used to control the operation of the gate bias and capacitance switch module, the substrate capacitance switch module and the radio frequency attenuation module; The gate bias and capacitance switch module is used to control the RF attenuation module to produce different attenuation amounts and compensate for the phase error of the RF attenuation module in the attenuation state; The substrate capacitance switch module is used to compensate the phase error of the radio frequency attenuation module in the attenuation state by switching the parasitic capacitance mode, and the parasitic capacitance mode includes a high-pass network mode and a low-pass network mode; The side capacitance module is used to adjust the additional phase shift of the radio frequency attenuation module in the attenuation state; The radio frequency attenuation module is used to perform digital control attenuation processing on the radio frequency signal at the input end to obtain a deleted radio frequency signal; The detection feedback loop module is used to obtain an off-chip differential signal to adjust a feedback gate bias voltage and generate a feedback gate bias voltage signal.

2. A MOS attenuator based on transistor parasitic capacitance compensation phase according to claim 1, characterized in that: The digital logic module is a decoder unit array composed of digital logic gates and inverters.

3. A MOS attenuator based on transistor parasitic capacitance compensation phase according to claim 2, characterized in that: The gate bias and capacitor switch module specifically includes a series MOS array gate control and capacitor switch module and a parallel MOS array gate control module, wherein the series MOS array gate control and capacitor switch module is composed of a plurality of MOS switch tubes and high resistance, and the parallel MOS array gate control module is composed of a plurality of transmission gates and a plurality of MOS switch tubes, wherein: The series MOS array gate control and capacitor switch module is used to control the gate potential value of the series MOS array; The parallel MOS array gate control module is used to control the gate potential value of the parallel MOS array and control the working state of the parallel MOS array. The working state of the parallel MOS array includes a cut-off state and a resistance state.

4. A MOS attenuator based on transistor parasitic capacitance compensation phase according to claim 3, characterized in that: The RF attenuation module specifically includes a series MOS array and a parallel MOS array, the series MOS array is formed by connecting a number of MOS transistors in parallel, the gate of the series MOS array is connected to the gate bias and capacitor switch module, the substrate of the series MOS array is connected to the substrate capacitor switch module, the series MOS array is arranged in the series branch of the RF attenuation module, the parallel MOS array is formed by connecting a number of MOS transistors in parallel, the gate of the parallel MOS array is connected to the gate bias and capacitor switch module, wherein: The series MOS array is formed by arranging a number of transistor layouts according to a common centroid layout, and adding dummy transistors on the periphery of the transistor layout, laying grounding metals on the source metal and the drain metal of the MOS transistors in the transistor layout, respectively, using N wells and deep N wells to isolate the series MOS array from an external P substrate, and selectively connecting the internal P substrate of the series MOS array directly to an external substrate or connecting it to an external substrate after being connected in series with a high resistance through a substrate capacitor switch module; The parallel MOS array is formed by arranging a plurality of transistor layouts in a common centroid layout, and adding dummy transistors at the periphery of the transistor layout.

5. A MOS attenuator based on transistor parasitic capacitance phase compensation according to claim 4, characterized in that: Also includes: When the gate of the series MOS array is biased by a high impedance, the Cgs capacitor and the Cgd capacitor are connected in series between the source and the drain to form a high-pass network; When the gate of the series MOS array is biased by a DC power supply, the Cgs capacitor and the Cgd capacitor are converted into source and drain electrodes connected in parallel to the ground capacitor to form a low-pass network; When the substrate of the series MOS array is grounded through a high resistance, the Cbs capacitor and the Cbd capacitor are connected in series between the source and the drain to form a high-pass network; When the substrate of the series MOS array is grounded, the Cbs capacitor and the Cbd capacitor are converted into source and drain capacitors connected in parallel to the ground capacitor to form a low-pass network.

6. A MOS attenuator based on transistor parasitic capacitance phase compensation according to claim 5, characterized in that: The detection feedback loop module specifically includes a detection feedback module, an off-chip resistor module and an on-chip MOS module, the output end of the off-chip resistor module is connected to the input end of the on-chip MOS module, the detection feedback module and the on-chip MOS module are connected to each other, and the output end of the detection feedback module is connected to the third input end of the RF attenuation module, wherein: The off-chip resistance module is used to obtain an off-chip positive phase differential signal, and the on-chip MOS module is used to obtain an off-chip negative phase differential signal, and the off-chip positive phase differential signal is superimposed with the off-chip negative phase differential signal to obtain a superimposed differential signal; The detection feedback module is used to obtain the off-chip positive phase differential signal and the superimposed differential signal to adjust the feedback gate bias voltage and generate a feedback gate bias voltage signal.

7. A MOS attenuator based on transistor parasitic capacitance phase compensation according to claim 6, characterized in that: The detection feedback module specifically includes a signal buffer module, a CHOP module and a DC voltage comparator module, the output end of the signal buffer module is connected to the input end of the CHOP module, and the output end of the CHOP module is connected to the input end of the DC voltage comparator module, wherein: The signal buffer module is used to amplify the superimposed differential signal to obtain an amplified differential signal; The CHOP module is used to convert the off-chip positive phase differential signal and the amplified differential signal into an AC square wave signal to obtain a first DC potential signal and a second DC potential signal; The DC voltage comparator module is used to compare the first DC potential signal with the second DC potential signal to obtain a feedback gate bias voltage signal.

8. A control method for a MOS attenuator based on transistor parasitic capacitance compensation phase, characterized in that: The following steps are involved: Controlling the radio frequency attenuation module to generate different attenuation amounts and compensating for the phase error of the radio frequency attenuation module in the attenuation state to obtain a compensated radio frequency attenuation module; Performing feedback gate bias voltage adjustment processing on the compensated RF attenuation module through an off-chip differential signal to obtain an adjusted RF attenuation module; The additional phase shift of the adjusted radio frequency attenuation module in the attenuation state is controlled to perform digital controlled attenuation processing on the radio frequency signal at the input end to obtain the deleted radio frequency signal.

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