MOS attenuator based on transistor parasitic capacitance compensation phase and control method

Abstract

The application discloses a MOS attenuator based on transistor parasitic capacitance compensation phase and a control method, and the attenuator comprises a digital logic module, a gate bias and a capacitor switch module, a substrate capacitor switch module, a side edge capacitor module, a radio frequency attenuation module and a detection feedback loop module. The method comprises the following steps: controlling the radio frequency attenuation module to generate an attenuation amount and to compensate for the phase error of the radio frequency attenuation module in an attenuation state; performing feedback gate bias voltage adjustment processing on the compensated radio frequency attenuation module through an off-chip differential signal; and controlling the adjusted radio frequency attenuation module to have an additional phase shift in the attenuation state, and performing digital control attenuation processing on the radio frequency signal at the input end. The application can reduce the increase of the additional phase shift and reduce the influence of the change of the process angle on the source-drain resistance of the MOS transistor in the resistance region. The application, as a MOS attenuator based on transistor parasitic capacitance compensation phase and a control method, can be widely applied to the field of CMOS transceiver gain control technology.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of CMOS transceiver gain control technology, and particularly relates to a MOS attenuator based on transistor parasitic capacitance compensation phase and a control method. BACKGROUND

[0002] A conventional resistor network type passive attenuator is formed by cascading multiple attenuation units, each unit having different attenuation amounts. When temperature and process corner change, the attenuation accuracy of each attenuation unit will deteriorate, and the additional phase shift will also increase. The degree of attenuation accuracy deterioration and additional phase shift increase will be accumulated step by step with the increase of cascaded units. Finally, the RMS gain error and RMS phase error of the entire attenuator will increase with the change of process corner and temperature. SUMMARY

[0003] In order to solve the above technical problems, the purpose of the present application is to provide a MOS attenuator based on transistor parasitic capacitance compensation phase and a control method, which can reduce the degree of additional phase shift increase and reduce the influence of process corner change on the source-drain resistance of the MOS transistor in the resistance region.

[0004] The first technical solution adopted by the present application is: a MOS attenuator based on transistor parasitic capacitance compensation phase, comprising a digital logic module, a gate bias and capacitance switch module, a substrate capacitance switch module, a side capacitance module, a radio frequency attenuation module and a detection feedback loop module, a first output end of the digital logic module is connected with an input end of the gate bias and capacitance switch module, a first output end of the digital logic module is connected with an input end of the substrate capacitance switch module, a third output end of the digital logic module is connected with a first input end of the radio frequency attenuation module, an output end of the gate bias and capacitance switch module is connected with a first input end of the side capacitance module, an output end of the side capacitance module is connected with a second input end of the radio frequency attenuation module, an output end of the radio frequency attenuation module is connected with a second input end of the side capacitance module, an output end of the detection feedback loop module is connected with a third input end of the radio frequency attenuation module, wherein:

[0005] The digital logic module is used for controlling the work of the gate bias and capacitance switch module, the substrate capacitance switch module and the radio frequency attenuation module;

[0006] The gate bias and capacitance switch module is used for controlling the radio frequency attenuation module to generate different attenuation amounts and compensate the phase error of the radio frequency attenuation module in the attenuation state;

[0007] The substrate capacitance switch module is used for compensating phase error of the radio frequency attenuation module in an attenuation state by switching a parasitic capacitance mode, and the parasitic capacitance mode includes a high-pass network mode and a low-pass network mode.

[0008] The side capacitance module is used for adjusting additional phase shift of the radio frequency attenuation module in an attenuation state.

[0009] The radio frequency attenuation module is used for digitally controlling attenuation processing of a radio frequency signal at an input end to obtain a pruned radio frequency signal.

[0010] The detection feedback loop module is used for acquiring an off-chip differential signal to adjust a feedback gate bias voltage and generate a feedback gate bias voltage signal.

[0011] Further, the digital logic module is a decoder unit array composed of digital logic gates and inverters.

[0012] Further, the gate bias and capacitance switch module specifically includes a series MOS array gate control and capacitance switch module and a parallel MOS array gate control module, the series MOS array gate control and capacitance switch module is composed of a plurality of MOS switch tubes and high resistance, and the parallel MOS array gate control module is composed of a plurality of transmission gates and a plurality of MOS switch tubes, wherein:

[0013] The series MOS array gate control and capacitance switch module is used for controlling a gate potential value of the series MOS array.

[0014] The parallel MOS array gate control module is used for controlling a gate potential value of the parallel MOS array and controlling a working state of the parallel MOS array, and the working state of the parallel MOS array includes an off state and a resistance state.

[0015] Further, the radio frequency attenuation module specifically includes a series MOS array and a parallel MOS array, the series MOS array is composed of a plurality of MOS transistors in series, a gate of the series MOS array is connected with the gate bias and capacitance switch module, a substrate of the series MOS array is connected with the substrate capacitance switch module, and the series MOS array is arranged in a series branch of the radio frequency attenuation module, the parallel MOS array is composed of a plurality of MOS transistors in parallel, a gate of the parallel MOS array is connected with the gate bias and capacitance switch module, and wherein:

[0016] The series MOS array is formed by arranging a plurality of transistor layouts in a common centroid layout, dummy transistors are added to the periphery of the transistor layouts, ground metal is laid on the source metal and drain metal of the MOS transistors in the transistor layouts respectively, the series MOS array is isolated from the external P substrate by using N well and deep N well, and the internal P substrate of the series MOS array is selectively connected to the external substrate directly or connected to the external substrate after being connected in series with a high resistance through a substrate capacitor switch module.

[0017] The parallel MOS array is formed by arranging a plurality of transistor layouts in a common centroid layout, and dummy transistors are added to the periphery of the transistor layouts.

[0018] Further, it further comprises:

[0019] When the gate of the series MOS array is biased by a high resistance, the Cgs capacitor and the Cgd capacitor are connected in series between the source and the drain, forming a high-pass network.

[0020] When the gate of the series MOS array is biased by a DC power supply, the Cgs capacitor and the Cgd capacitor are converted into a source and a drain parallel to ground capacitor, forming a low-pass network.

[0021] When the substrate of the series MOS array is grounded through a high resistance, the Cbs capacitor and the Cbd capacitor are connected in series between the source and the drain, forming a high-pass network.

[0022] When the substrate of the series MOS array is grounded, the Cbs capacitor and the Cbd capacitor are converted into a source and a drain parallel to ground capacitor, forming a low-pass network.

[0023] Further, the detection feedback loop module specifically comprises a detection feedback module, an off-chip resistance module and an on-chip MOS module, the output end of the off-chip resistance module is connected with the input end of the on-chip MOS module, the detection feedback module and the on-chip MOS module are connected with each other, and the output end of the detection feedback module is connected with the third input end of the radio frequency attenuation module.

[0024] The off-chip resistance module is used to obtain an off-chip positive-phase differential signal, the on-chip MOS module is used to obtain an off-chip negative-phase differential signal, the off-chip positive-phase differential signal and the off-chip negative-phase differential signal are superimposed to obtain a superimposed differential signal.

[0025] The detection feedback module is used to obtain an off-chip positive-phase differential signal and a superimposed differential signal, and adjust and feed back a gate bias voltage to generate a feedback gate bias voltage signal.

[0026] Further, the detection feedback module specifically comprises a signal buffering module, a CHOP module and a direct current voltage comparator module, an output end of the signal buffering module is connected with an input end of the CHOP module, an output end of the CHOP module is connected with an input end of the direct current voltage comparator module, wherein:

[0027] The signal buffering module is used for amplifying the superimposed differential signal to obtain an amplified differential signal.

[0028] The CHOP module is used for converting the off-chip positive differential signal and the amplified differential signal into alternating square wave signals to obtain a first direct current potential signal and a second direct current potential signal.

[0029] The direct current voltage comparator module is used for comparing the first direct current potential signal and the second direct current potential signal to obtain a feedback gate bias voltage signal.

[0030] The second technical solution adopted by the application is a control method of a MOS attenuator based on transistor parasitic capacitance compensation phase, comprising the following steps:

[0031] Controlling the radio frequency attenuation module to generate different attenuation amounts and compensating for the phase error of the radio frequency attenuation module in the attenuation state to obtain a compensated radio frequency attenuation module.

[0032] Adjusting the feedback gate bias voltage of the compensated radio frequency attenuation module through the off-chip differential signal to obtain an adjusted radio frequency attenuation module.

[0033] Controlling the additional phase shift of the adjusted radio frequency attenuation module in the attenuation state to perform digital control attenuation processing on the input radio frequency signal to obtain a pruned radio frequency signal.

[0034] The method and system have the following beneficial effects: the application controls the radio frequency attenuation module to generate different attenuation amounts and compensates for the phase error of the radio frequency attenuation module in the attenuation state through the gate bias and the capacitance switch module and the substrate capacitance switch module to realize the gain control of the transceiver transceiver path, compensates for the phase by using the parasitic capacitance of the MOS transistor, so that no large phase error is introduced, further adjusts the feedback gate bias voltage by acquiring the off-chip differential signal through the detection feedback loop module, generates the feedback gate bias voltage signal, realizes the accurate control of the source-drain resistance of the MOS transistor in the resistance region, and reduces the influence of the process angle change on the source-drain resistance of the MOS transistor in the resistance region. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 is a structural schematic diagram of a MOS attenuator based on transistor parasitic capacitance compensation phase.

[0036] Figure 2 is a step flow chart of a control method of a MOS attenuator based on transistor parasitic capacitance compensation phase of the application;

[0037] Figure 3 is a circuit topology schematic diagram of a radio frequency attenuation module provided by an embodiment of the application;

[0038] Figure 4 is a centroid swing diagram of MOS transistors in a series-parallel MOS array provided by an embodiment of the application;

[0039] Figure 5 is a transistor parasitic model and a phase compensation schematic diagram using parasitic capacitance provided by an embodiment of the application;

[0040] Figure 6 is a structure schematic diagram of a detection feedback module provided by an embodiment of the application. DETAILED DESCRIPTION

[0041] The application will be further described in detail below in combination with the drawings and specific embodiments. For the step numbers in the following embodiments, they are only set for the convenience of description, and the order between the steps is not limited in any way, and the execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0042] The development of wireless communication technology has a profound impact on people's way of life. In order to meet the demand for high data transmission rate, high spectrum efficiency and low latency communication technology, wireless communication systems are developing towards higher frequency bands, such as millimeter wave frequency bands. Millimeter wave frequency bands have the advantages of abundant spectrum resources and fast data transmission rate, and because of the short wavelength, it is easy to realize miniaturization and low-cost application. With the continuous development of communication technology, phased array technology as a new technology is introduced. Phased array technology uses an antenna array composed of multiple antenna elements to replace the traditional reflector antenna, and adjusts the direction and amplitude of the beam through beamforming technology, so as to obtain multiple high-directivity narrow beams to combat propagation loss and achieve better signal coverage. The introduction of phased array technology brings new possibilities for the development of wireless communication systems.

[0043] Phased array radar is a device with multiple functions, which is composed of unit circuit array composed of multiple antenna unit groups. Among them, active phased array radar (APAR) is the most popular type. Compared with traditional passive phased array technology, active phased array radar has many advantages and can be widely used in aerospace and military radar fields. In recent years, with the rapid development of radio frequency integrated circuit technology and remote sensing technology, active phased array technology has excellent stability and strong robustness, super-long range sensitivity control and self-adaptation to the surrounding environment, etc. It has become the focus of phased array radar technology and has been widely discussed and researched.

[0044] The active phased array radar is composed of many unit circuits, each of which includes active circuits for transmitting and receiving ends, which directly determine the performance of each antenna unit. Specifically, the attenuator mainly realizes two functions: first, it balances the total gain of the receiving channel to ensure that all T / R components have the same amplitude at the output end; second, it adjusts the amplitude of the signal to better limit the sidelobe level of the receiving channel.

[0045] In the phased array transceiver chip, the amplitude control unit is very important. The attenuator plays a key role in amplitude control, mainly in two aspects: first, amplitude control, the attenuator can adjust the amplitude of the transmit or receive signal to achieve better amplitude control; second, gain compensation, the attenuator can be used to compensate for the amplitude error introduced by the phase shifter. In order to adapt to millimeter wave communication and high-performance radar applications, the attenuator needs to have higher step precision and smaller additional phase shift to reduce tracking error and calibration difficulty. In addition, from the overall system performance, the attenuator also needs to have high linearity.

[0046] Digital attenuator as an important part of millimeter wave phased array system, has important application in 5G millimeter wave communication system, millimeter wave phased array radar and millimeter wave broadband satellite communication system, etc. It can realize the adjustment or compensation of the power and amplitude of the received or transmitted signal, and meet the requirements of phased array system for beam pointing flexibility. Therefore, the research on digital attenuator in millimeter wave phased array has great significance.

[0047] Traditional resistive network type passive attenuator is composed of multiple attenuation units in cascade, each unit has different attenuation amount. When the temperature and process angle change, the attenuation accuracy of each attenuation unit will deteriorate, and the additional phase shift will also increase. The degree of attenuation accuracy deterioration and additional phase shift increase will be accumulated step by step with the increase of cascaded units. Finally, the RMS gain error and RMS phase error of the whole attenuator will increase with the change of process angle and temperature.

[0048] Based on this, referring to Figure 1The application provides a MOS attenuator based on transistor parasitic capacitance compensation phase, which comprises a digital logic module, a gate bias and capacitance switch module, a substrate capacitance switch module, a side capacitance module, an RF attenuation module and a detection feedback loop module, a first output end of the digital logic module is connected with an input end of the gate bias and capacitance switch module, a first output end of the digital logic module is connected with an input end of the substrate capacitance switch module, a third output end of the digital logic module is connected with a first input end of the RF attenuation module, an output end of the gate bias and capacitance switch module is connected with a first input end of the side capacitance module, an output end of the side capacitance module is connected with a second input end of the RF attenuation module, an output end of the RF attenuation module is connected with a second input end of the side capacitance module, and an output end of the detection feedback loop module is connected with a third input end of the RF attenuation module.

[0049] The digital logic module is used for controlling the working of the gate bias and capacitance switch module, the substrate capacitance switch module and the RF attenuation module.

[0050] Specifically, the digital logic module is a decoder unit array composed of digital logic gates and inverters.

[0051] In the embodiment, the main structure of the digital logic module is a decoder unit array composed of digital logic gates and inverters, which mainly realizes the function of the decoder. Each decoder unit controls one of the MOS arrays in series. When the output control word of the shift register is input into the decoder unit, the decoder unit can output the control of one of the MOS arrays in series, so that the attenuation state works in the on state, the resistance state and the off state, and the capacitance compensation state works in the compensation state or the non-compensation state.

[0052] The gate bias and capacitance switch module is used for controlling the RF attenuation module to generate different attenuation amounts and compensating the phase error of the RF attenuation module in the attenuation state.

[0053] Specifically, the gate bias and capacitance switch module specifically comprises a series MOS array gate control and capacitance switch module and a parallel MOS array gate control module, the series MOS array gate control and capacitance switch module is composed of a plurality of MOS switch tubes and high resistance, and the parallel MOS array gate control module is composed of a plurality of transmission gates and a plurality of MOS switch tubes, wherein the series MOS array gate control and capacitance switch module is used for controlling the gate potential value of the series MOS array; the parallel MOS array gate control module is used for controlling the gate potential value of the parallel MOS array and the working state of the parallel MOS array, and the working state of the parallel MOS array includes the cut-off state and the resistance state.

[0054] In the embodiment, the gate biasing and capacitance switching module comprises a series MOS array gate control and capacitance switching module and a parallel MOS array gate control module, wherein the series MOS array gate control and capacitance switching module is composed of a MOS switch tube and a high resistance, the series MOS array gate control module can independently control the gate potential value of each MOS transistor in the series MOS array and whether the potential is given to the transistor gate through the high resistance, and the parallel MOS array gate control module is composed of a plurality of PMOS, a transmission gate composed of a plurality of MOS and a plurality of MOS switch tubes. The parallel MOS array gate control module can independently control the gate potential value of each MOS transistor in the parallel MOS array, so as to control the working state of each MOS transistor in the parallel MOS array to be a cut-off state or a resistance state.

[0055] The substrate capacitance switching module is used for compensating the phase error of the radio frequency attenuation module in the attenuation state by switching the parasitic capacitance mode, and the parasitic capacitance mode includes a high-pass network mode and a low-pass network mode.

[0056] In the embodiment, the substrate capacitance switching module specifically comprises a MOS switch tube, which connects a deep N well below the series MOS array in the layout and an on-chip ground. If the switch tube is opened, the deep N well is the on-chip ground, at this time, the capacitances Cdb and Csb of the MOS tube source and drain to the substrate are converted into ground capacitances, at this time, there are ground capacitances at the nodes of the MOS tube source and drain, forming a low-pass network. If the switch tube is closed, the deep N well is the on-chip ground, at this time, the capacitances Cdb and Csb of the MOS tube source and drain to the substrate are connected in series between the MOS tube source and drain, forming a high-pass network. By switching the two parasitic capacitance models, compensation of the additional phase shift of the radio frequency attenuation module in the attenuation state can be realized.

[0057] The side capacitance module is used for adjusting the additional phase shift of the radio frequency attenuation module in the attenuation state.

[0058] In the embodiment, the side capacitance module specifically comprises a plurality of switch capacitance units connected in parallel to the ground, each switch capacitance unit is composed of a metal interdigital capacitance (MOM capacitance) and a series switch MOS tube, the gate potential of the series switch MOS tube is directly controlled by a control word output by a shift register, when the shift register output potential is VDD, the working state of the series switch MOS tube is a conductive state, at this time, the switch capacitance unit presents a capacitive property to the node, when the shift register output potential is 0, at this time, the switch capacitance unit presents a high resistance characteristic to the node. By controlling whether the switch capacitance unit presents a capacitive property or a high resistance characteristic to the node, the phase compensation function can be realized.

[0059] The radio frequency attenuation module is used to perform digitally controlled attenuation processing on the input radio frequency signal to obtain the ablated radio frequency signal;

[0060] Specifically, such as Figure 3 As shown, the RF attenuation module specifically includes a series MOS array and a parallel MOS array. The series MOS array is composed of several MOS transistors connected in series. The gate of the series MOS array is connected to the gate bias and capacitor switching module, and the substrate of the series MOS array is connected to the substrate capacitor switching module. The series MOS array is disposed in the series branch of the RF attenuation module. The parallel MOS array is composed of several MOS transistors connected in parallel. The gate of the parallel MOS array is connected to the gate bias and capacitor switching module. The series MOS array is formed by arranging several transistors in a common centroid layout, and dummy transistors are added around the transistor layout. Ground metal is laid on top of the source metal and drain metal of the MOS transistors in the transistor layout. N-wells and deep N-wells are used to isolate the series MOS array from the external P substrate. The substrate capacitor switching module selectively connects the internal P substrate of the series MOS array directly to the external substrate or connects it to the external substrate after connecting a high impedance in series. The parallel MOS array is formed by arranging several transistors in a common centroid layout, and dummy transistors are added around the transistor layout.

[0061] It should also be noted that when the gate of the series MOS array is biased by a high-impedance voltage, the Cgs and Cgd capacitors are connected in series between the source and drain to form a high-pass network; when the gate of the series MOS array is biased by a DC power supply, the Cgs and Cgd capacitors become source and drain capacitors connected in parallel to ground to form a low-pass network; when the substrate of the series MOS array is grounded by a high-impedance voltage, the Cbs and Cbd capacitors are connected in series between the source and drain to form a high-pass network; when the substrate of the series MOS array is grounded, the Cbs and Cbd capacitors become source and drain capacitors connected in parallel to ground to form a low-pass network.

[0062] In this embodiment, the RF attenuation module specifically includes a series MOS array and a parallel MOS array. More specifically, the series MOS array consists of multiple MOS transistors connected in parallel and placed in the series path of the RF signal in the RF attenuation module. The size ratio of the MOS transistors in the array is selected as Nm1:Nm2:Nm3:Nm4:Nm5:Nm6:Nm7:Nm8:…:Nmi (where mi can be any positive integer greater than or equal to 1, and Nmi is a positive real number). The gate of each MOS transistor is independently controlled by the gate bias and capacitor switching module. The substrates (sources) of all MOS transistors in the array are connected and then connected to the substrate capacitor switching module, and are controlled by the substrate capacitor switching module.

[0063] Referring to Figure 5 When the gate of the transistor is biased by a high resistance voltage, the Cgs and Cgd capacitances are in series between the source and the drain, forming a high-pass network. When the gate of the transistor is directly biased by a DC voltage (AC ground), the gate node is AC ground, so the Cgs and Cgd capacitances are converted into source and drain parallel-to-ground capacitances, forming a low-pass network. By switching between these two parasitic capacitance models, compensation for the additional phase shift of the RF attenuation module in the attenuation state can be achieved. Similarly, when the substrate of the series MOS array is grounded through a high resistance, the Cbs and Cbd capacitances are in series between the source and the drain, forming a high-pass network. When the substrate of the series MOS array is directly grounded (AC ground), the substrate node of the series MOS array is AC ground, so the Cbs and Cbd capacitances are converted into source and drain parallel-to-ground capacitances, forming a low-pass network. By switching between these two parasitic capacitance models, compensation for the additional phase shift of the RF attenuation module in the attenuation state can be achieved. In summary, by using different binary control words, the resistance value between the source and the drain of the series MOS array, as well as the series capacitance value between the source and the drain nodes and the respective parallel-to-ground parasitic capacitance values of the source and drain nodes, can be controlled by controlling the output of the gate biasing and capacitance switching module and the substrate capacitance switching module, thereby enabling resistance adjustment between the two nodes in the series signal path of the RF attenuation module and switching between the capacitance models of the two nodes.

[0064] Referring to Figure 4 The embodiment of the present application has the following improvements in the layout design of the series MOS array:

[0065] 1) The layout of the multiple transistors in the series MOS array is arranged according to the common centroid layout scheme, thereby reducing the impact of process gradients on the performance of the transistors.

[0066] 2) A Dummy transistor is added to the periphery of the transistor layout of the series MOS array, thereby reducing the impact of edge effects on the peripheral transistors in the series MOS array.

[0067] 3) The series MOS array is completely isolated from the external P substrate using N-well and deep N-well, and the internal P substrate of the series MOS array is selected by the substrate capacitance switching module to be directly connected to the external substrate or connected to the external substrate through a high resistance.

[0068] 4) In the layout of the series MOS array, a layer of ground metal is laid on top of the source metal and the drain metal of the MOS transistor, respectively, thereby converting part of the series parasitic capacitance between the source and drain metals in the layout into source-to-ground and drain-to-ground capacitances. This reduces the impact of the series parasitic capacitance between the source and drain nodes on the bandwidth and additional phase shift of the RF attenuation module in the attenuation state.

[0069] Parallel MOS array, which is composed of multiple MOS transistors in parallel and is placed in the parallel-to-ground path of the RF signal of the RF attenuation module. The MOS transistor size in the array is selected as Nm1: Nm2: Nm3: Nm4: Nm5: Nm6: Nm7: Nm8: …: Nmi (where mi can be any positive integer greater than or equal to 1, and Nmi is a positive real number). The gate of each MOS transistor is independently controlled by the gate bias and the capacitor switch module. By using different binary control words, the resistance value between the source and the drain of the parallel MOS array can be controlled, so that the node resistance value of the RF attenuation module connected to the ground can be adjusted.

[0070] Referring to Figure 4 The embodiment of the present application has the following improvements in the layout design of the parallel MOS array:

[0071] 1) The multiple transistor layouts in the parallel MOS array are arranged according to the common centroid layout scheme, so as to reduce the influence of process gradient on the performance of the transistors.

[0072] 2) Dummy transistors are added to the periphery of the transistor layout of the parallel MOS array, so as to reduce the influence of the edge effect on the peripheral transistors in the parallel MOS array.

[0073] The detection feedback loop module is used to obtain an off-chip differential signal to adjust and feed back the gate bias voltage, and generate a feedback gate bias voltage signal.

[0074] Specifically, the detection feedback loop module specifically includes a detection feedback module, an off-chip resistance module, and an on-chip MOS module, the output end of the off-chip resistance module is connected with the input end of the on-chip MOS module, the detection feedback module and the on-chip MOS module are connected with each other, and the output end of the detection feedback module is connected with the third input end of the RF attenuation module, wherein the off-chip resistance module is used to obtain an off-chip positive-phase differential signal, the on-chip MOS module is used to obtain an off-chip negative-phase differential signal, the off-chip positive-phase differential signal and the off-chip negative-phase differential signal are superimposed to obtain a superimposed differential signal; the detection feedback module is used to obtain the off-chip positive-phase differential signal and the superimposed differential signal to adjust and feed back the gate bias voltage, and generate a feedback gate bias voltage signal.

[0075] Further, it needs to be explained that the detection feedback module specifically includes a signal buffer module, a CHOP module and a direct current voltage comparator module, an output end of the signal buffer module is connected with an input end of the CHOP module, an output end of the CHOP module is connected with an input end of the direct current voltage comparator module, wherein the signal buffer module is used for amplifying the superimposed differential signal to obtain an amplified differential signal; the CHOP module is used for converting the off-chip positive differential signal and the amplified differential signal into an alternating square wave signal to obtain a first direct current potential signal and a second direct current potential signal; and the direct current voltage comparator module is used for comparing the first direct current potential signal with the second direct current potential signal to obtain a feedback gate bias voltage signal.

[0076] In the embodiment, referring to Figure 6 , the detection feedback module specifically includes a signal buffer module, mainly composed of multiple inverter cascades, which plays a role of amplifying alternating small signals. The CHOP module is mainly composed of inverters and transmission gates, and the main function is to convert the alternating signal level of the node after superimposing the amplified off-chip differential signal into two direct current levels. The direct current voltage comparator module is used for comparing the size relationship of the two direct current levels, and simultaneously outputting a feedback gate bias voltage.

[0077] The circuit modules in the detection feedback module are connected in sequence. The off-chip differential clock signal is transmitted to the off-chip resistor and the on-chip MOS through PCB wiring, wherein the off-chip non-inverted differential signal is transmitted to the positive terminal of the off-chip resistor, the off-chip inverted differential signal is transmitted to the source terminal (drain terminal) of the on-chip MOS module, the negative terminal of the off-chip resistor is connected with the drain terminal (source terminal) of the on-chip MOS, and the node is the node where the differential non-inverted signal and the differential signal are superimposed. The differential non-inverted signal and the differential signal are superimposed at the node, and if the source-drain on-resistance of the off-chip resistor and the on-chip MOS is the same, the node is a virtual ground. If the value of the off-chip resistor is smaller than the value of the on-resistance, the node where the negative terminal of the off-chip resistor is connected with the drain terminal (source terminal) of the on-chip MOS will present the non-inverted differential signal. Conversely, if the value of the off-chip resistor is larger than the value of the on-resistance, the node where the negative terminal of the off-chip resistor is connected with the drain terminal (source terminal) of the on-chip MOS will present the inverted differential signal. The voltage of the node where the differential signal after superimposition at the node where the negative terminal of the off-chip resistor is connected with the drain terminal (source terminal) of the on-chip MOS is transmitted to the detection feedback module, the signal is first amplified by the signal buffer module, then the signal is converted from an alternating square wave signal to the relative size of two direct current potentials by the clock-modulated CHOP module, and then the change of the feedback gate bias voltage is adjusted by the direct current voltage comparator module. Finally, the detection module adjusts the output feedback gate bias voltage according to the phase of the signal until the source-drain on-resistance of the on-chip MOS and the off-chip resistor are equal. The accuracy of the off-chip PCB resistor can be ±1%, so the MOS gate bias voltage output after the feedback loop can make the on-resistance of the MOS tend to the accuracy of the off-chip PCB resistor.

[0078] In summary, the embodiment of the present application provides a MOS attenuator using transistor parasitic capacitance to compensate phase, which is used to realize gain control of the transceiver transceiver channel, and at the same time, the parasitic capacitance of the MOS transistor is used to compensate the phase, so as to not introduce large phase error. At the same time, a MOS resistance self-locking loop circuit design on chip is provided, which is used to realize accurate control of the source-drain resistance of the MOS transistor in the resistance region, and reduce the influence of the process angle change on the source-drain resistance of the MOS transistor in the resistance region. The radio frequency attenuation module comprises a plurality of MOS transistor arrays, which are used to digitally attenuate and output the radio frequency signal at the input end. The gate bias and capacitor switch module controls the gate voltage of the transistor in the attenuation module through a digital signal, so as to control the transistor in the digital attenuating module to realize different conduction states: conduction state, resistance state and off state, so as to control the radio frequency attenuation module to produce different attenuation amounts. In addition, the gate of the transistor in the attenuation module is controlled by the digital signal to pass through the high resistance bias voltage or not, so as to realize the switching of the two parasitic capacitance modes and compensate the phase error of the radio frequency attenuation module in the attenuation state. The substrate capacitor switch module controls whether the substrate of the transistor in the attenuation module is grounded through the high resistance, so as to realize the switching of the two parasitic capacitance modes and compensate the phase error of the radio frequency attenuation module in the attenuation state. The side capacitance module controls the opening and closing of the switch capacitor in the radio frequency attenuation module through a digital signal, which is used to adjust the additional phase shift of the radio frequency attenuation module in the attenuation state. The digital logic module is used to control the gate bias and capacitor switch module, the substrate capacitor switch module and the side capacitance module through different encodings of each group of digital control words, so as to realize the attenuation amount switching of the radio frequency attenuation module and the adjustment of the additional phase shift in the attenuation state. The detection feedback module is used to detect the node voltage after the superposition of the off-chip differential signal, and output the feedback gate bias voltage to the on-chip MOS module.

[0079] Reference Figure 2 A control method of a MOS attenuator based on transistor parasitic capacitance to compensate phase, comprising the following steps:

[0080] S100, control the radio frequency attenuation module to produce different attenuation amounts and compensate the phase error of the radio frequency attenuation module in the attenuation state, to obtain a compensated radio frequency attenuation module;

[0081] S200, adjust the feedback gate bias voltage of the compensated radio frequency attenuation module through the off-chip differential signal, to obtain an adjusted radio frequency attenuation module;

[0082] S300, control the additional phase shift of the adjusted radio frequency attenuation module in the attenuation state, to digitally attenuate the radio frequency signal at the input end, to obtain the pruned radio frequency signal.

[0083] The contents in the method embodiments are applicable to the system embodiments, the system embodiments specifically implement the same functions as the method embodiments, and achieve the same beneficial effects as the method embodiments.

[0084] The above is a specific description of the preferred embodiments of the application, but the application is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the application. These equivalent modifications or replacements are all included in the scope defined by the claims of the application.

Claims

1. A MOS attenuator based on transistor parasitic capacitance phase compensation, characterized in that, The system includes a digital logic module, a gate bias and capacitor switching module, a substrate capacitor switching module, a side capacitor module, an RF attenuation module, and a detection feedback loop module. The first output of the digital logic module is connected to the input of the gate bias and capacitor switching module; the second output of the digital logic module is connected to the input of the substrate capacitor switching module; the third output of the digital logic module is connected to the first input of the RF attenuation module; the output of the gate bias and capacitor switching module is connected to the first input of the side capacitor module; the output of the side capacitor module is connected to the second input of the RF attenuation module; the output of the RF attenuation module is connected to the second input of the side capacitor module; and the output of the detection feedback loop module is connected to the third input of the RF attenuation module. Wherein: The digital logic module is used to control the operation of the gate bias and capacitor switching module, the substrate capacitor switching module and the RF attenuation module; The gate bias and capacitor switching module is used to control the RF attenuation module to generate different attenuation amounts and to compensate for the phase error of the RF attenuation module in the attenuation state. The substrate capacitor switching module is used to compensate for the phase error of the RF attenuation module in the attenuation state by switching the parasitic capacitance mode. The parasitic capacitance mode includes a high-pass network mode and a low-pass network mode. The side capacitor module is used to adjust the additional phase shift of the RF attenuation module in the attenuation state; The radio frequency attenuation module is used to perform digitally controlled attenuation processing on the input radio frequency signal to obtain the ablated radio frequency signal; The detection feedback loop module is used to acquire the off-chip differential signal to adjust the feedback gate bias voltage and generate the feedback gate bias voltage signal.

2. The MOS attenuator based on transistor parasitic capacitance phase compensation according to claim 1, characterized in that, The digital logic module is a decoder unit array composed of digital logic gates and inverters.

3. The MOS attenuator based on transistor parasitic capacitance phase compensation according to claim 2, characterized in that, The gate biasing and capacitor switching module specifically includes a series MOS array gate control and capacitor switching module and a parallel MOS array gate control module. The series MOS array gate control and capacitor switching module consists of several MOS switches and high impedance transistors, and the parallel MOS array gate control module consists of several transmission gates and several MOS switches, wherein: The series MOS array gate control and capacitor switching module is used to control the gate potential value of the series MOS array; The parallel MOS array gate control module is used to control the gate potential value of the parallel MOS array and control the operating state of the parallel MOS array, which includes a cutoff state and a resistive state.

4. A MOS attenuator based on transistor parasitic capacitance phase compensation according to claim 3, characterized in that, The RF attenuation module specifically includes a series MOS array and a parallel MOS array. The series MOS array is composed of several MOS transistors connected in parallel. The gate of the series MOS array is connected to the gate bias and capacitor switching module, and the substrate of the series MOS array is connected to the substrate capacitor switching module. The series MOS array is disposed in the series branch of the RF attenuation module. The parallel MOS array is composed of several MOS transistors connected in parallel. The gate of the parallel MOS array is connected to the gate bias and capacitor switching module, wherein: The series MOS array is formed by arranging several transistor layouts in a common centroid layout, and Dummy transistors are added around the transistor layouts. Ground metals are laid on the source and drain metals of the MOS transistors in the transistor layouts. N-wells and deep N-wells are used to isolate the series MOS array from the external P substrate. The internal P substrate of the series MOS array is selectively connected to the external substrate directly or connected to the external substrate after being connected in series with high resistance through a substrate capacitor switching module. The parallel MOS array is formed by arranging several transistor layouts in a common centroid layout, and dummy transistors are added around the outer periphery of the transistor layouts.

5. A MOS attenuator based on transistor parasitic capacitance phase compensation according to claim 4, characterized in that, Also includes: When the gate of the series MOS array is biased by a high impedance voltage, the Cgs capacitor and the Cgd capacitor are connected in series between the source and drain to form a high-pass network. When the gate of the series MOS array is biased by a DC power supply, the Cgs capacitor and the Cgd capacitor are converted into source and drain capacitors connected in parallel to ground, forming a low-pass network. When the substrate of the series MOS array is grounded through a high impedance, the Cbs capacitor and the Cbd capacitor are connected in series between the source and drain to form a high-pass network; When the substrate of the series MOS array is grounded, the Cbs and Cbd capacitors are converted into source and drain capacitors connected in parallel to ground, forming a low-pass network.

6. A MOS attenuator based on transistor parasitic capacitance phase compensation according to claim 5, characterized in that, The detection feedback loop module specifically includes a detection feedback module, an external resistor module, and an on-chip MOS module. The output terminal of the external resistor module is connected to the input terminal of the on-chip MOS module. The detection feedback module and the on-chip MOS module are interconnected. The output terminal of the detection feedback module is connected to the third input terminal of the RF attenuation module. The off-chip resistor module is used to acquire the off-chip positive phase differential signal, and the on-chip MOS module is used to acquire the off-chip negative phase differential signal. The off-chip positive phase differential signal and the off-chip negative phase differential signal are superimposed to obtain the superimposed differential signal. The detection feedback module is used to acquire the off-chip positive phase differential signal and the superimposed differential signal to adjust the feedback gate bias voltage and generate a feedback gate bias voltage signal.

7. A MOS attenuator based on transistor parasitic capacitance phase compensation according to claim 6, characterized in that, The detection feedback module specifically includes a signal buffer module, a CHOP module, and a DC voltage comparator module. The output terminal of the signal buffer module is connected to the input terminal of the CHOP module, and the output terminal of the CHOP module is connected to the input terminal of the DC voltage comparator module. The signal buffer module is used to amplify the superimposed differential signal to obtain an amplified differential signal. The CHOP module is used to convert the off-chip positive phase differential signal and the amplified differential signal into AC square wave signals to obtain a first DC potential signal and a second DC potential signal. The DC voltage comparator module is used to compare the first DC potential signal with the second DC potential signal to obtain a feedback gate bias voltage signal.

8. A control method for a MOS attenuator based on transistor parasitic capacitance phase compensation as described in any one of claims 1-7, characterized in that, Includes the following steps: The radio frequency attenuation module is controlled to generate different attenuation amounts and the phase error of the radio frequency attenuation module in the attenuation state is compensated to obtain a compensated radio frequency attenuation module. The adjusted RF attenuation module is obtained by adjusting the feedback gate bias voltage of the compensated RF attenuation module using an external differential signal. The additional phase shift of the adjusted RF attenuation module in the attenuation state is controlled to perform digitally controlled attenuation processing on the input RF signal to obtain the ablated RF signal.

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