Low-power-consumption and high-reliability anti-radiation D trigger
By adopting a differential signal and cross-coupled interlocking structure in the radiation-resistant D trigger, the contradiction between radiation resistance and low power consumption in the prior art is solved, and high-efficiency and low-power radiation resistance is achieved.
Patent Information
- Application Number
- CN202510058132.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-14
- Publication Date
- 2025-05-06
AI Technical Summary
While improving radiation resistance, existing radiation-resistant D triggers face the problem of increasing power and area, especially under the demands of high frequency and low power consumption, the existing technology is difficult to take into account.
A low-power and high-reliability anti-irradiation D trigger is designed, using clock-controlled input module, data input module, main-stage latch module, master-slave transmission control module, slave-stage latch module and data output module. Through the interlocking structure of differential signals and cross-coupled, the performance of anti-SETs and SEU is improved while reducing power consumption.
A balance between radiation resistance and low power consumption is achieved, significantly reducing power consumption, and improving operating speed and operating frequency, with better performance against SETs and SEUs.
Smart Images
Figure CN119945386A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuit design, and in particular to a low-power, high-reliability radiation-resistant D-type flip-flop. Background Art
[0002] With the development of space exploration and aerospace, integrated circuit chips are more widely used in space. When working in high-radiation environments such as space, the radiation resistance and functional reliability of integrated circuit chips need to be strictly guaranteed. In order to achieve the requirements of lightweight, low-power and high-speed electronic components for space, advanced processes need to be used to achieve this. However, with the improvement of processes, the feature size continues to decrease, and the node parasitic capacitance will also decrease, which will lead to a higher probability of single event transients (SETs) occurring on the chip due to space radiation. After semiconductor devices are subjected to SETs, when SETs pass through the silicon substrate, electron-hole pairs will be generated on their energy deposition path. These electron-hole pairs will be collected by the sensitive nodes of the circuit, resulting in a transient mutation of the voltage of the sensitive nodes. When the amplitude of the transient signal is too large or the duration is too long, it may cause a single event upset (SEU). Unlike SETs, which only generate small voltage faults at sensitive nodes, SEU is a soft error that causes the latch to reverse and lock until the next circuit refresh. Although SEU will not cause catastrophic damage to the circuit system, it can also cause serious system failures. Therefore, relevant anti-radiation measures must be taken in the core chips of integrated circuits such as microprocessors to avoid the occurrence of SEU.
[0003] D flip-flop (DFF) is a common sequential device in circuits. In sequential circuits, due to the presence of feedback signals, if a node flips due to SETs, the circuit will incorrectly latch the state value of the node after the flip through the feedback line, causing the sequential circuit state to be wrong, thus affecting the normal function of the entire circuit. Therefore, a radiation-resistant reinforced DFF design is needed.
[0004] Redundancy design is a commonly used technology in radiation hardening by design (RHBD) DFF. Triple modular redundancy (TMR) is one of the most famous and widely used redundant topologies, with strong redundancy robustness. In the TMR structure, the circuit is copied into three modules, which perform the same operation at the same time, and finally judge in the voting device (VOTE), and the majority of the same output is used as the final output of the system. Since the probability of SET or SEU events occurring in two modules at the same time is extremely small, the robustness of the system can be greatly improved. The circuit structure diagram of TMR RHBDDFF is shown in the figure. Figure 1 shown. Figure 1 The TMR DFF shown has the following disadvantages: (1) Since the DFF circuit is replicated into three identical modules, which work simultaneously, the chip area and power consumption increase threefold. (2) The TMR DFF introduces a VOTE module and a new sensitive node. If the transistor that determines the VOTE output is subjected to SETs and SEUs, the output signal may be erroneous.
[0005] Another commonly used radiation hardened DFF is composed of dual interlocked storage cells (DICE) and Muller-C cells. The circuit structure diagram based on the DICE unit and Muller-C unit is shown in the figure. Figure 2 As shown. In the DICE structure, the storage unit with four internal output nodes has a strong ability to resist single-node flipping. When space particles bombard a single sensitive node of the DICE structure, other nodes will repair the erroneous flipping of the circuit and will not cause the erroneous flipping of the output signal to achieve soft error tolerance. In the path composed of the delay module and the Muller-C unit, the Muller-C unit has two inputs. When the two inputs are consistent, the output is a copy of its input. When the two inputs are inconsistent, the output keeps the input value unchanged. The circuit schematic and working timing diagram of the Muller-C unit are shown in the figure below. Figure 3 (a) and Figure 3As shown in (b). The RHBD DFF composed of DICE and Muller-C units effectively reduces SETs and SEUs. However, the DFF composed of DICE units and Muller-C units still has the following disadvantages: (1) There is a delay of Td in the delay unit module. At the same time, in order to suppress SETs with a width of ΔT, the latch requires a long setup time, which limits the maximum operating frequency of the DFF and also has a large performance loss. (2) It is necessary to strictly meet the requirement that the Td of the delay unit module is greater than the width ΔT of the SETs, otherwise the Muller-C unit will mistakenly capture SETs and SEUs, resulting in output signal errors and being latched by the DICE unit. (3) The introduction of DICE units, Muller-C units and delay modules results in large losses in area and power consumption. Summary of the invention
[0007] A low-power, high-reliability radiation-resistant D trigger comprises: a clock input module, a data input module, a master latch module, a master-slave transmission control module, a slave latch module and a data output module.
[0008] The clock-controlled input module is used to provide clock signals to the data input module, the master-level latch module, the master-slave transmission control module, the slave-level latch module and the data output module.
[0009] The data input module is used to convert the input signal into a differential input by using two independent, mutually inverted, and different delay transmission paths, and transmit the differential input to the main latch module.
[0010] The master-level latch module is used to process the differential input using a cross-coupled interlocking structure and transmit the obtained master-level output signal to the master-slave transmission control module.
[0011] The master-slave transmission control module is used to convert the master output signal into a first differential signal, and transmit the first differential signal to the slave latch module.
[0012] The slave latch module is used to process the first differential signal by adopting a cross-coupled interlocking structure, and transmit the obtained slave output signal to the data output module.
[0013] The data output module is used to convert the slave output signal through two independent output transmission paths with different delays, and output latch signals through clock control.
[0014] In one embodiment, the data input module includes: a first delay unit, a first Muller-C unit, a first PMOS transistor, a first NMOS transistor, a first inverter, a second inverter and a third inverter.
[0015] The input end of the first delay and one input end of the first Muller-C unit are both connected to the data input signal node, the output end of the first delay is connected to the other input end of the first Muller-C unit, the output end of the first Muller-C unit is connected to the source of the first PMOS transistor and the source of the NMOS transistor, the gate of the first PMOS transistor is connected to the internal positive clock signal node, the gate of the first NMOS transistor is connected to the internal negative clock signal node, the source of the first PMOS transistor and the source of the NMOS transistor are connected and then connected to the input ends of the first inverter and the second inverter, the output ends of the second inverter and are connected to the input end of the third inverter, and the output end of the third inverter and the output end of the first inverter are both connected to the master-slave transmission control module.
[0016] In one embodiment, the clock-controlled input module includes: a second PMOS transistor, a second NMOS transistor, and a fourth inverter.
[0017] The gate of the second PMOS transistor is connected to the ground voltage VSS terminal, the gate of the second NMOS transistor is connected to the power supply voltage VDD terminal, the source of the second PMOS transistor, the source of the second NMOS transistor and the input terminal of the fourth inverter are all connected to the external clock signal node, the drain of the second PMOS transistor and the drain of the second NMOS transistor are both connected to the internal positive clock signal node, and the output terminal of the fourth inverter is connected to the internal negative clock signal node.
[0018] In one embodiment, the primary latch module includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a third NMOS transistor and a fourth NMOS transistor.
[0019] The gate of the third PMOS transistor and the gate of the third NMOS transistor are both connected to the first output end of the data input module, the source of the third PMOS transistor and the source of the fourth PMOS transistor are both connected to the power supply voltage VDD, the gate of the fourth PMOS transistor and the gate of the fourth NMOS transistor are both connected to the second output end of the data input module, the drain of the third PMOS transistor is connected to the source of the fifth PMOS transistor and the source of the sixth PMOS transistor, the gate of the fifth PMOS transistor is connected to the internal inverted clock signal node, the drain of the sixth PMOS transistor is connected to the gate of the seventh PMOS transistor and the drain of the third NMOS transistor, the drain of the seventh PMOS transistor is connected to the gate of the sixth PMOS transistor and the drain of the fourth NMOS transistor, the source of the third NMOS transistor and the source of the fourth NMOS transistor are both connected to the ground voltage VSS; the drain of the fourth PMOS transistor is connected to the drain of the fifth PMOS transistor and the source of the seventh PMOS transistor, and the connection point is used as the output end of the master latch module and connected to the input end of the master-slave transmission control module.
[0020] In one embodiment, the master-slave transmission control module includes: an eighth PMOS transistor, a fifth NMOS transistor, a first NAND gate, a fifth inverter, a sixth inverter and a seventh inverter.
[0021] One input end of the first NAND gate is connected to the output end of the master latch module, and the other input end of the first NAND gate is connected to the reset signal node; the output end of the first NAND gate is connected to the source of the eighth PMOS transistor and the source of the fifth NMOS transistor, the drain of the eighth PMOS transistor, the drain of the fifth NMOS transistor, the input end of the fifth inverter and the input end of the sixth inverter, the output end of the sixth inverter INV6 is connected to the input end of the seventh inverter INV7, the gate of the fifth NMOS transistor is connected to the internal positive clock signal node, the gate of the eighth PMOS transistor is connected to the internal inverted clock signal node, the gate of the sixth NMOS transistor is connected to the internal inverted clock signal node, the output end of the fifth inverter serves as the first output end of the master-slave transmission control module, the output end of the sixth inverter serves as the second output end of the master-slave transmission control module, and the first output end and the second output end are connected to the slave latch module.
[0022] In one embodiment, the slave latch module includes: a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor.
[0023] The gate of the ninth PMOS transistor and the gate of the sixth NMOS transistor are both connected to the first output end of the master-slave transmission control module, the source of the ninth PMOS transistor and the source of the tenth PMOS transistor are both connected to the power supply voltage VDD, the gate of the tenth PMOS transistor and the gate of the seventh NMOS transistor are both connected to the second output end of the master-slave transmission control module, the drain of the ninth PMOS transistor is connected to the source of the eleventh PMOS transistor and the source of the twelfth PMOS transistor, the gate of the eleventh PMOS transistor P11 is connected to the internal positive phase clock signal node, the drain of the tenth PMOS transistor is connected to the drain of the eleventh PMOS transistor and the source of the thirteenth PMOS transistor, the drain of the twelfth PMOS transistor is connected to the gate of the thirteenth PMOS transistor and the drain of the sixth NMOS transistor, the source of the sixth NMOS transistor and the source of the seventh NMOS transistor are both connected to the ground voltage VSS; the drain of the thirteenth PMOS transistor is connected to the gate of the twelfth PMOS transistor and the drain of the seventh NMOS transistor, and the connection point is connected to the data output module as the output end of the slave latch module.
[0024] In one embodiment, the data output module includes: a second delay unit, a second Muller-C unit, a second NAND gate, an eighth inverter and a ninth inverter.
[0025] The input end of the second delay unit is connected to the output end of the slave-level latch module, the output end of the second delay unit is connected to an input end of the second Muller-C unit, the other input end of the second Muller-C unit is connected to the output end of the slave-level latch module, the output end of the second Muller-C unit is connected to an input end of the second NAND gate, the other input end of the second NAND gate is connected to the reset signal node, the output end of the second NAND gate is connected to the input end of the eighth inverter, the output end of the eighth inverter is connected to the input end of the ninth inverter, and the output end of the ninth inverter is used for data output.
[0026] The above-mentioned low-power, high-reliability radiation-resistant D flip-flop includes: a clock-controlled input module for providing a clock signal; a data input module for converting the input signal into a differential input by using two independent, mutually inverted, and different-delay transmission paths; a master-level latch module for processing the differential input by using a cross-coupled interlocking structure; a master-slave transmission control module for converting the master-level output signal into a first differential signal; a slave-level latch module for processing the first differential signal by using a cross-coupled interlocking structure; a data output module for converting the slave-level output signal through two independent output transmission paths with different delays, and outputting a latch signal through clock control. The radiation-resistant D flip-flop uses a differential signal as the input of the latch in the master-level latch module and the slave-level latch module, has better performance against SETs and SEUs, and uses a cross-coupled interlocking structure to improve the working speed and working frequency, and greatly reduce power consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 It is the schematic diagram of TMR DFF circuit in the prior art; Figure 2 It is a circuit structure diagram based on DICE unit and Muller-C unit in the prior art; Figure 3 The circuit principle and working timing diagram of the Muller-c unit in the prior art, wherein (a) is the circuit principle diagram of the Muller-c unit, and (b) is the working timing diagram of the Muller-c unit; Figure 4 A structural diagram of a low-power, high-reliability radiation-resistant D flip-flop in one embodiment; Figure 5 A schematic diagram of a clock-controlled input module in another embodiment; Figure 6 A schematic diagram of a data input module in another embodiment; Figure 7 A schematic diagram of a main latch module in another embodiment; Figure 8 It is a schematic diagram of a master-slave transmission control module in another embodiment; Fig. 9 A schematic diagram of a slave latch module in another embodiment; Fig.10 A schematic diagram of a data output module in another embodiment; Fig.11 FIG. 1 is a diagram showing the effect of a radiation-resistant D flip-flop in suppressing SETs and SEU in one embodiment. DETAILED DESCRIPTION
[0028] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0029] In one embodiment, Figure 4 As shown, a low-power, high-reliability radiation-resistant D trigger is provided, which includes: a clock input module 10, a data input module 20, a master latch module 30, a master-slave transmission control module 40, a slave latch module 50 and a data output module 60.
[0030] The clock input module 10 is used to provide a clock signal to the data input module 20 , the master latch module 30 , the master-slave transmission control module 40 , the slave latch module 50 and the data output module 60 .
[0031] Specifically, the clock-controlled input module 10 is connected to the data input module 20 , the master latch module 30 , the master-slave transmission control module 40 , the slave latch module 50 and the data output module 60 .
[0032] The clock input module 10 receives an external clock signal CLK.
[0033] The data input module 20 is used to convert the input signal into a differential input by using two independent, mutually inverted transmission paths with different delays, and transmit the differential input to the main latch module 30.
[0034] Specifically, the input signal is in differential form, and the output has a natural anti-interference property, which can be used to suppress SETs and SEUs of the input signal and ensure the stability of the output signal.
[0035] By setting up two input transmission paths in the data input module, the two paths are independent of each other and have different delays. Even if the transient pulse current generated by single-particle irradiation affects one input signal, it will be filtered out by the Muller-C unit, thereby increasing the circuit's input signal's ability to resist single-particle transient pulses.
[0036] The master latch module 30 is used to process the differential input using a cross-coupled interlocking structure and transmit the obtained master output signal to the master-slave transmission control module 40.
[0037] The master-slave transmission control module 40 is used to convert the master output signal into a first differential signal, and transmit the first differential signal to the slave latch module 50 .
[0038] The slave latch module 50 is used to process the first differential signal by adopting a cross-coupled interlocking structure, and transmit the obtained slave output signal to the data output module 60 .
[0039] Specifically, the input signals in the master latch module and the slave latch module are differential inputs, which have natural anti-interference properties. When one of the input signal nodes is hit by high-energy particles and causes SEU, the circuit can restore it to the correct logic value through the internal feedback of another differential input signal, thereby completing the fault-tolerant process from logic state error to self-recovery, effectively improving the D flip-flop unit's ability to resist radiation.
[0040] The data output module 60 is used to convert the slave output signal through two independent output transmission paths with different delays, and output a latch signal through clock control.
[0041] Specifically, in the data output module 60, two output transmission paths are also set. The two paths are independent of each other and have different delays. Even if the transient pulse current generated by single-particle irradiation affects the output signal of one path, it will also be filtered out by the Muller-C unit, thereby increasing the circuit output signal's ability to resist single-particle transient pulses.
[0042] In the above-mentioned low-power, high-reliability radiation-resistant D flip-flop, the radiation-resistant D flip-flop includes: a clock-controlled input module for providing a clock signal; a data input module for converting the input signal into a differential input by using two independent, mutually inverted, and different-delay transmission paths; a master-level latch module for processing the differential input by using a cross-coupled interlocking structure, a master-slave transmission control module for converting the master-level output signal into a first differential signal, a slave-level latch module for processing the first differential signal by using a cross-coupled interlocking structure, and a data output module for converting the slave-level output signal through two independent output transmission paths with different delays, and outputting a latch signal through clock control. The radiation-resistant D flip-flop uses a differential signal as the input of the latch in the master-level latch module and the slave-level latch module, has better performance against SETs and SEUs, and uses a cross-coupled interlocking structure to improve the working speed and working frequency, and greatly reduce power consumption.
[0043] The radiation-resistant D flip-flop proposed in the present application solves the power consumption and area problems currently faced by the radiation-resistant DFF based on the TMR structure and the DICE unit.
[0044] In one embodiment, if Figure 5 As shown, the clock-controlled input module 10 includes: a second PMOS transistor P2, a second NMOS transistor N2 and a fourth inverter INV4.
[0045] The gate of the second PMOS transistor P2 is connected to the ground voltage VSS terminal, the gate of the second NMOS transistor N2 is connected to the power supply voltage VDD terminal, the source of the second PMOS transistor P2, the source of the second NMOS transistor N2 and the input terminal of the fourth inverter INV4 are all connected to the external clock signal node CLK, the drain of the second PMOS transistor P2 and the drain of the second NMOS transistor N2 are all connected to the internal positive clock signal node CLKp, and the output terminal of the fourth inverter INV4 is connected to the internal negative clock signal node CLKb.
[0046] In one embodiment, if Figure 6 As shown, the data input module 20 includes: a first delay unit Td1, a first Muller-C unit M1, a first PMOS transistor P1, a first NMOS transistor N1, a first inverter INV1, a second inverter INV2 and a third inverter INV3.
[0047] The input end of the first delay unit Td1 and one input end of the first Muller-C unit are both connected to the data input signal node D, the output end of the first delay unit Td1 is connected to the other input end of the first Muller-C unit M1, the output end of the first Muller-C unit M1 is connected to the source of the first PMOS transistor P1 and the source of the NMOS transistor N1, the gate of the first PMOS transistor P1 is connected to the internal positive clock signal node, the gate of the first NMOS transistor N1 is connected to the internal negative clock signal node, the source of the first PMOS transistor P1 and the source of the first NMOS transistor N1 are connected to the input ends of the first inverter INV1 and the second inverter INV2, the output ends of the second inverter INV2 and are connected to the input end of the third inverter, and the output end INV3 of the third inverter and the output end of the first inverter INV1 are both connected to the master-slave transmission control module 40.
[0048] Specifically, the output end of the output end INV1 of the first inverter is the node L1, and the output end of the output end INV3 of the third inverter is the node L1b.
[0049] In one embodiment, if Figure 7 As shown, the primary latch module 30 includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, a third NMOS transistor N3 and a fourth NMOS transistor N4.
[0050] The gate of the third PMOS transistor P3 and the gate of the third NMOS transistor N3 are both connected to the first output terminal (node L1) of the data input module 20, the source of the third PMOS transistor P3 and the source of the fourth PMOS transistor P4 are both connected to the power supply voltage VDD, the gate of the fourth PMOS transistor P4 and the gate of the fourth NMOS transistor N4 are both connected to the second output terminal (node L1b) of the data input module 20, the drain of the third PMOS transistor P3 is connected to the source of the fifth PMOS transistor P5 and the source of the sixth PMOS transistor P6, the gate of the fifth PMOS transistor P5 is connected to the internal inverted clock signal node The drain of the fourth PMOS transistor P4 is connected to the drain of the fifth PMOS transistor P5 and the source of the seventh PMOS transistor P7, the drain of the sixth PMOS transistor P6 is connected to the gate of the seventh PMOS transistor P7 and the drain of the third NMOS transistor N3, the source of the third NMOS transistor N3 and the source of the fourth NMOS transistor N4 are both connected to the ground voltage VSS; the drain of the seventh PMOS transistor P7 is connected to the gate of the sixth PMOS transistor P6 and the drain of the fourth NMOS transistor N4, and the connection point is used as the output end of the master-slave transmission control module 40 to be connected to the input end of the master-slave transmission control module 40.
[0051] Specifically, the connection point between the drain of the third PMOS transistor P3 and the source of the fifth PMOS transistor P5 and the source of the sixth PMOS transistor P6 is the node X1b.
[0052] A connection point between the drain of the fourth PMOS transistor P4 , the drain of the fifth PMOS transistor P5 , and the source of the seventh PMOS transistor P7 is a node X1 .
[0053] A connection point between the drain of the seventh PMOS transistor P7 , the gate of the sixth PMOS transistor P6 and the drain of the fourth NMOS transistor N4 is a node H1 , and the node H1 is an output end of the primary latch module 30 .
[0054] A connection point between the drain of the sixth PMOS transistor P6 , the gate of the seventh PMOS transistor P7 , and the drain of the third NMOS transistor N3 is a node H1 b .
[0055] Related research shows that under sub-20nm FinFET process, the sensitivity of PMOS transistors to SETs and SEU is much higher than that of NMOS. Therefore, the input signal of the radiation-resistant D flip-flop of the present application adopts a differential form, the number of PMOS transistors is much higher than the number of NMOS transistors, and the radiation-resistant D flip-flop with reset function is provided. The present application can ensure high robustness and radiation resistance performance, and also has the characteristics of low power consumption and high operating frequency.
[0056] In one embodiment, if Figure 8 As shown, the master-slave transmission control module 40 includes: an eighth PMOS transistor P8, a fifth NMOS transistor N5, a first NAND gate NAND1, a fifth inverter INV5, a sixth inverter INV6 and a seventh inverter INV7.
[0057] One input end of the first NAND gate NAND1 is connected to the output end of the primary latch module 30, and the other input end of the first NAND gate NAND1 is connected to the reset signal node R; the output end of the first NAND gate NAND1 is connected to the source of the eighth PMOS transistor P8 and the source of the fifth NMOS transistor N5, the drain of the eighth PMOS transistor P8, the drain of the fifth NMOS transistor N5, the input end of the fifth inverter INV5 and the input end of the sixth inverter INV6 are connected, and the output end of the sixth inverter INV6 is connected to the seventh inverter. The input end of the phase inverter INV7 is connected, the gate of the eighth PMOS transistor P8 is connected to the internal inverting clock signal node, the gate of the fifth NMOS transistor N5 is connected to the internal positive clock signal node, the gate of the sixth NMOS transistor is connected to the internal inverting clock signal node, the output end of the fifth inverter INV5 serves as the first output end of the master-slave transmission control module 40, the output end of the seventh inverter INV7 serves as the second output end of the master-slave transmission control module 40, and the first output end and the second output end are connected to the slave latch module 50.
[0058] In one embodiment, if Fig. 9 As shown, the slave latch module 50 includes: a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a sixth NMOS transistor N6 and a seventh NMOS transistor N7.
[0059] The gate of the ninth PMOS transistor P9 and the gate of the sixth NMOS transistor N6 are both connected to the first output terminal of the master-slave transmission control module 40, the source of the ninth PMOS transistor P9 and the source of the tenth PMOS transistor P10 are both connected to the power supply voltage VDD, the gate of the tenth PMOS transistor P10 and the gate of the seventh NMOS transistor N7 are both connected to the second output terminal of the master-slave transmission control module 40, the drain of the ninth PMOS transistor P9 is connected to the source of the eleventh PMOS transistor P11 and the source of the twelfth PMOS transistor P12, the gate of the eleventh PMOS transistor P11 is connected to the internal positive phase clock signal node, The drain of the tenth PMOS transistor P10 is connected to the drain of the eleventh PMOS transistor P11 and the source of the thirteenth PMOS transistor P13, the drain of the twelfth PMOS transistor P12 is connected to the gate of the thirteenth PMOS transistor P13 and the drain of the sixth NMOS transistor N6, the source of the sixth NMOS transistor N6 and the source of the seventh NMOS transistor N7 are both connected to the ground voltage VSS; the drain of the thirteenth PMOS transistor P13 is connected to the gate of the twelfth PMOS transistor P12 and the drain of the seventh NMOS transistor N7, and the connection point is connected to the data output module 60 as the output end of the slave latch module 50.
[0060] Specifically, the connection point of the drain of the twelfth PMOS transistor P12, the gate of the thirteenth PMOS transistor P13 and the drain of the sixth NMOS transistor N6 is Z1b, and the connection point of the drain of the thirteenth PMOS transistor P13, the gate of the twelfth PMOS transistor P12 and the drain of the seventh NMOS transistor N7 is recorded as node Z1, and node Z1 is the output end of the slave latch module 50.
[0061] In the master latch module and the slave latch module, a cross-coupled interlocking structure is used, which can greatly reduce the power consumption generated by DFF during latching, thereby achieving the goal of low power consumption. In addition, the cross-coupled interlocking structure can also speed up the signal conversion time and increase the operating frequency of the circuit.
[0062] In one embodiment, if Fig.10 As shown, the data output module 60 includes: a second delay unit TD2, a second Muller-C unit M2, a second NAND gate NAND2, an eighth inverter INV8 and a ninth inverter INV9.
[0063] The input end of the second delay unit TD2 is connected to the output end (node Z1) of the slave-level latch module 50, the output end of the second delay unit TD2 is connected to an input end of the second Muller-C unit M2, the other input end of the second Muller-C unit M2 is connected to the output end (node Z1) of the slave-level latch module 50, the output end of the second Muller-C unit M2 is connected to an input end of the second NAND gate NAND2, the other input end of the second NAND gate NAND2 is connected to the reset signal node R, the output end of the second NAND gate NAND2 is connected to the input end of the eighth inverter INV8, the output end of the eighth inverter INV8 is connected to the input end of the ninth inverter INV9, and the output end of the ninth inverter INV9 is used for data output.
[0064] In a simulation embodiment, the effect diagram of the radiation-resistant D flip-flop of the present application in suppressing SETs and SEU is shown in FIG. Fig.11 As shown, Fig.11 In which Q is the data output signal of the radiation-resistant D flip-flop, D is the data input signal of the radiation-resistant D flip-flop, and CLKp is the internal positive-phase clock signal of the radiation-resistant D flip-flop.
[0065] Compared with the radiation-resistant D flip-flop based on the DICE unit and the Muller-C unit in the radiation-resistant D flip-flop adopting the TMR structure, the technical effects of the radiation-resistant D flip-flop proposed in the present application are as follows: (1) It has the advantage of low power consumption. Specifically, in the master latch module and the slave latch module, a cross-coupled interlocking structure is adopted. No branch is turned on during the latching period, which can greatly reduce the power consumption generated by the DFF during the latching period. After relevant verification, the power consumption of the classic DFF in one input signal cycle is 12.135 uA, and the power consumption of the radiation-resistant D flip-flop provided in the embodiment of the present application in one input signal cycle is 8.933 uA.
[0066] (2) It has the advantages of higher operating speed and operating frequency, which is specifically reflected in: a cross-coupled interlocking structure is adopted in the master-level latch module and the slave-level latch module. The cross-coupled interlocking structure will speed up the signal conversion, thus having a higher operating speed and operating frequency.
[0067] (3) It has better performance against SETs and SEUs. Specifically, in the master latch module and the slave latch module, differential signals are used as the input of the latch. Differential signals have natural anti-interference characteristics. Even if Muller-C units are not used for reinforcement at the input and output ends, the input signals are still able to resist SETs and SEUs.
[0068] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0069] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.
Claims
1. A low-power, high-reliability radiation-resistant D flip-flop, characterized in that: The radiation-resistant D flip-flop comprises: a clock input module, a data input module, a master latch module, a master-slave transmission control module, a slave latch module and a data output module; The clock-controlled input module is used to provide a clock signal to the data input module, the master latch module, the master-slave transmission control module, the slave latch module and the data output module; The data input module is used to convert the input signal into a differential input by using two independent, mutually inverted and different delay transmission paths, and transmit the differential input to the main latch module; The master latch module is used to process the differential input using a cross-coupled interlocking structure and transmit the obtained master output signal to the master-slave transmission control module; The master-slave transmission control module is used to convert the master output signal into a first differential signal, and transmit the first differential signal to the slave latch module; The slave latch module is used to process the first differential signal using a cross-coupled interlocking structure, and output the obtained slave output signal to the data output module; The data output module is used to convert the slave output signal through two independent output transmission paths with different delays, and output a latch signal through clock control.
2. A low-power, high-reliability radiation-resistant D flip-flop according to claim 1, characterized in that: The data input module includes: a first delay unit, a first Muller-C unit, a first PMOS transistor, a first NMOS transistor, a first inverter, a second inverter and a third inverter; The input end of the first delay and one input end of the first Muller-C unit are both connected to the data input signal node, the output end of the first delay is connected to the other input end of the first Muller-C unit, the output end of the first Muller-C unit is connected to the source of the first PMOS transistor and the source of the NMOS transistor, the gate of the first PMOS transistor is connected to the internal positive clock signal node, the gate of the first NMOS transistor is connected to the internal negative clock signal node, the source of the first PMOS transistor is connected to the source of the NMOS transistor and then connected to the input ends of the first inverter and the second inverter, the output ends of the second inverter and are connected to the input end of the third inverter, and the output end of the third inverter and the output end of the first inverter are both connected to the master-slave transmission control module.
3. The low-power, high-reliability radiation-resistant D flip-flop according to claim 1, characterized in that: The clock-controlled input module includes: a second PMOS transistor, a second NMOS transistor and a fourth inverter; The gate of the second PMOS transistor is connected to the ground voltage VSS terminal, the gate of the second NMOS transistor is connected to the power supply voltage VDD terminal, the source of the second PMOS transistor, the source of the second NMOS transistor and the input terminal of the fourth inverter are all connected to the external clock signal node, the drain of the second PMOS transistor and the drain of the second NMOS transistor are both connected to the internal positive clock signal node, and the output terminal of the fourth inverter is connected to the internal negative clock signal node.
4. The low-power, high-reliability radiation-resistant D flip-flop according to claim 1, characterized in that: The primary latch module includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a third NMOS transistor and a fourth NMOS transistor; The gate of the third PMOS transistor and the gate of the third NMOS transistor are both connected to the first output terminal of the data input module, the source of the third PMOS transistor and the source of the fourth PMOS transistor are both connected to the power supply voltage VDD, the gate of the fourth PMOS transistor and the gate of the fourth NMOS transistor are both connected to the second output terminal of the data input module, the drain of the third PMOS transistor is connected to the source of the fifth PMOS transistor and the source of the sixth PMOS transistor, the gate of the fifth PMOS transistor is connected to the internal inverted clock signal node, and the The drain of the fourth PMOS transistor is connected to the drain of the fifth PMOS transistor and the source of the seventh PMOS transistor, the drain of the sixth PMOS transistor is connected to the gate of the seventh PMOS transistor and the drain of the third NMOS transistor, the source of the third NMOS transistor and the source of the fourth NMOS transistor are both connected to the ground voltage VSS; the drain of the seventh PMOS transistor is connected to the gate of the sixth PMOS transistor and the drain of the fourth NMOS transistor, and the connection point is connected as the output end of the master-stage latch module to the input end of the master-slave transmission control module.
5. The low-power, high-reliability radiation-resistant D flip-flop according to claim 1, characterized in that: The master-slave transmission control module includes: an eighth PMOS transistor, a fifth NMOS transistor, a first NAND gate, a fifth inverter, a sixth inverter and a seventh inverter; One input end of the first NAND gate is connected to the output end of the master latch module, and the other input end of the first NAND gate is connected to the reset signal node; the output end of the first NAND gate is connected to the source of the eighth PMOS transistor and the source of the fifth NMOS transistor, the drain of the eighth PMOS transistor, the drain of the fifth NMOS transistor, the input end of the fifth inverter and the input end of the sixth inverter, the output end of the sixth inverter INV6 is connected to the input end of the seventh inverter INV7, the gate of the fifth NMOS transistor is connected to the internal positive clock signal node, the gate of the eighth PMOS transistor is connected to the internal inverted clock signal node, the gate of the sixth NMOS transistor is connected to the internal inverted clock signal node, the output end of the fifth inverter serves as the first output end of the master-slave transmission control module, the output end of the seventh inverter serves as the second output end of the master-slave transmission control module, and the first output end and the second output end are connected to the slave latch module.
6. The low-power, high-reliability radiation-resistant D flip-flop according to claim 1, characterized in that: The slave latch module includes: a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor; The gate of the ninth PMOS transistor and the gate of the sixth NMOS transistor are both connected to the first output terminal of the master-slave transmission control module, the source of the ninth PMOS transistor and the source of the tenth PMOS transistor are both connected to the power supply voltage VDD, the gate of the tenth PMOS transistor and the gate of the seventh NMOS transistor are both connected to the second output terminal of the master-slave transmission control module, the drain of the ninth PMOS transistor is connected to the source of the eleventh PMOS transistor and the source of the twelfth PMOS transistor, the drain of the tenth PMOS transistor is connected to the drain of the eleventh PMOS transistor, and the drain of the tenth PMOS transistor is connected to the drain of the eleventh PMOS transistor. The gate of the eleventh PMOS transistor P11 is connected to the internal positive clock signal node, the drain of the twelfth PMOS transistor is connected to the gate of the thirteenth PMOS transistor and the drain of the sixth NMOS transistor, the source of the sixth NMOS transistor and the source of the seventh NMOS transistor are both connected to the ground voltage VSS; the drain of the thirteenth PMOS transistor is connected to the gate of the twelfth PMOS transistor and the drain of the seventh NMOS transistor, and the connection point is connected to the data output module as the output end of the slave latch module.
7. The low-power, high-reliability radiation-resistant D flip-flop according to claim 1, characterized in that: The data output module includes: a second delay unit, a second Muller-C unit, a second NAND gate, an eighth inverter and a ninth inverter; The input end of the second delay unit is connected to the output end of the slave latch module, the output end of the second delay unit is connected to an input end of the second Muller-C unit, the other input end of the second Muller-C unit is connected to the output end of the slave latch module, the output end of the second Muller-C unit is connected to an input end of the second NAND gate, the other input end of the second NAND gate is connected to the reset signal node, the output end of the second NAND gate is connected to the input end of the eighth inverter, the output end of the eighth inverter is connected to the input end of the ninth inverter, and the output end of the ninth inverter is used for data output.