Power-on reset circuit

Abstract

The invention relates to the technical field of integrated circuits and provides a power-on reset circuit. The power-on reset circuit comprises a voltage division module used for providing a voltage division result of a power supply voltage on a voltage division output node of the voltage division module according to an adjustable voltage division coefficient; the high-frequency signal coupling network comprises a first capacitor and a second capacitor; the comparison module is used for comparing the voltage of the partial voltage output node with the threshold voltage so as to generate an output logic signal; and the output buffer module is used for performing driving enhancement so as to generate a reset signal. Therefore, through the design of the high-frequency signal coupling network, the anti-interference capability is enhanced, and the high-precision control of the reset trigger point voltage in a wide frequency range is realized.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a power-on reset circuit. Background Art

[0002] The power-on reset circuit is a circuit module in an integrated circuit chip. The power-on reset circuit is used to detect changes in the power supply voltage and generate a valid reset signal before the power supply voltage reaches a preset stable value, so as to ensure that each functional module in the chip can receive a valid reset signal and complete a reliable initialization reset operation, so that the entire chip can start and run from a certain power-on initial state. Electronic equipment is affected by interference voltage during use, and its source may be electrostatic discharge (ESD) interference, such as ESD interference from the user's body, peripheral equipment, and connecting cables. Interference voltage caused by ESD interference may affect the power supply voltage of the chip, such as causing high-energy current pulses that last for a period of time such as tens of nanoseconds, and may have positive or negative polarity. Affected by the interference voltage on the power supply voltage of the chip, the power-on reset circuit inside the chip may erroneously output a reset signal, thereby causing a reset error, such as abnormally resetting a working functional module to the initial state or causing a certain function to suddenly disconnect. In the prior art, a solution to deal with abnormal reset caused by interference voltage such as ESD interference is to use a voltage divider design to reduce the voltage division coefficient of the reference node when the interference voltage causes the power supply voltage to increase rapidly, and to increase the voltage division coefficient of the reference node when the interference voltage causes the power supply voltage to decrease rapidly, thereby maintaining the level of the reference node stable, and then comparing the level of the reference node with the threshold voltage to output a reset signal. However, in the solution of the prior art, when the amplitude of the interference voltage is close to the amplitude of the power supply voltage and the polarity of the interference voltage is negative, in this case, the level of the reference node may erroneously exceed the threshold voltage after the power supply voltage is superimposed with the influence of the negative voltage interference voltage due to the high degree of interference, thereby erroneously outputting a reset signal. Therefore, the voltage divider-based solution in the prior art can deal with positive voltage interference voltage, but it is difficult to deal with negative voltage interference voltage. In addition, the filter circuit design used in the power-on reset circuit in the prior art generally adopts a resistor-capacitor filter circuit, but the resistor-capacitor time constant of the resistor-capacitor filter circuit generally adopts a fixed resistance value and a fixed capacitance value, and is therefore fixed. In this way, it is difficult to provide a high-quality filtering effect when the fixed resistor-capacitor time constant differs greatly from the frequency of the interference voltage signal, and thus it is difficult to meet the high-precision requirements of the chip. Adjustable resistors and adjustable capacitors require additional circuits and occupy additional volume, which is not conducive to meeting the requirements of high integration and miniaturization of the chip.

[0003] To this end, the present application provides a power-on reset circuit that can not only effectively cope with positive interference voltage and negative interference voltage, but also achieves high-precision control of the reset trigger point voltage over a wide frequency range, which contributes to the high integration and miniaturization of the chip. Summary of the invention In the first aspect, the present application provides a power-on reset circuit. The power-on reset circuit includes: a voltage divider module, wherein the voltage divider module is used to provide a voltage division result of a power supply voltage on a voltage division output node of the voltage divider module according to an adjustable voltage division coefficient; a high-frequency signal coupling network, wherein the high-frequency signal coupling network includes a first capacitor and a second capacitor, wherein the first capacitor is connected between the power supply voltage and the voltage division output node, and the second capacitor is connected between the voltage division output node and a ground terminal; a comparison module, wherein the comparison module is used to compare the voltage of the voltage division output node with a threshold voltage, thereby generating an output logic signal; and an output buffer module, wherein the output buffer module is used to drive and enhance the output logic signal, thereby generating a reset signal of the power-on reset circuit.

[0004] Through the first aspect of the present application, through the design of the high-frequency signal coupling network, the high-frequency jitter of the power supply voltage is superimposed on the voltage divider output node, so that the real-time voltage on the voltage divider output node is jointly determined by the voltage dividing effect of the voltage divider module and the coupling effect of the high-frequency signal coupling network; the ratio of the capacitance values ​​of the first capacitor and the second capacitor in the high-frequency signal coupling network is configured according to the setting of the threshold voltage, and various settings of the threshold voltage can be flexibly adapted, that is, the real-time voltage on the voltage divider output node can flexibly track the change of the threshold voltage; while enhancing the anti-interference ability of the power-on reset circuit to the positive voltage interference voltage signal, it also enhances the anti-interference ability of the power-on reset circuit to the negative voltage interference voltage signal; by utilizing the flexible setting of the threshold voltage, the reset trigger point voltage can be accurately controlled, and has the characteristics of being insensitive to process and temperature changes, which is conducive to highly integrated and miniaturized chip design, and can meet the high-precision control of the reset trigger point voltage over a wide frequency range.

[0005] In a possible implementation of the first aspect of the present application, the voltage divider module includes a voltage divider resistor and a voltage divider transistor, the adjustable voltage divider coefficient is determined based on the on-impedance of the voltage divider transistor, the on-impedance of the voltage divider transistor changes with the change of the power supply voltage, and the adjustable voltage divider coefficient decreases when the power supply voltage increases and increases when the power supply voltage decreases.

[0006] In a possible implementation of the first aspect of the present application, the voltage divider module has an output equivalent impedance at the voltage divider output node, the comparison module is an inverting comparator with a hysteresis function, and the high-frequency signal coupling loop is used to couple the interference voltage signal to the voltage divider output node.

[0007] In a possible implementation manner of the first aspect of the present application, a first ratio between a capacitance value of the first capacitor and a capacitance value of the second capacitor is determined based on a second ratio between the threshold voltage and the power supply voltage.

[0008] In a possible implementation manner of the first aspect of the present application, when the second ratio is 1:2, the first ratio is 1:1.

[0009] In a possible implementation of the first aspect of the present application, the preset stable value of the power supply voltage is used to determine whether the reset signal is a high level or a low level, and the preset stable value of the power supply voltage is determined based on the turn-on voltage of the voltage divider transistor of the voltage divider module and the threshold voltage of the comparison module.

[0010] In a possible implementation of the first aspect of the present application, the comparator includes a common-gate common-source transistor pair, the first capacitor or the second capacitor is an adjustable capacitor, the first ratio is adjustable, the first ratio is adjusted to adapt to the channel length-to-width ratio between the transistors included in the common-gate common-source transistor pair, and the second ratio is determined based on the channel length-to-width ratio between the transistors included in the common-gate common-source transistor pair.

[0011] In a possible implementation of the first aspect of the present application, the smaller capacitance value between the capacitance value of the first capacitor and the capacitance value of the second capacitor is at least three times the sum of the capacitance values ​​of the parasitic capacitance of the voltage divider output node.

[0012] In a possible implementation of the first aspect of the present application, the output equivalent impedance, the first capacitor and the second capacitor of the high-frequency signal coupling network together constitute a resistance-capacitance time constant, and the resistance-capacitance time constant is less than the rise and fall time of the power supply voltage.

[0013] In a possible implementation manner of the first aspect of the present application, the comparison module includes a hysteresis circuit, and the output buffer module is a Schmitt buffer.

[0014] In a possible implementation manner of the first aspect of the present application, the interference voltage signal comes from the power supply voltage or the ground terminal, and the interference voltage signal is electrostatic discharge interference or power surge interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0016] Figure 1 An application scenario of a power-on reset circuit provided in an embodiment of the present application; Figure 2 A schematic diagram of a power-on reset circuit according to a first embodiment of the present application; Figure 3 A schematic diagram of a power-on reset circuit according to a second implementation manner provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0018] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0019] Figure 1 This is an application scenario of a power-on reset circuit provided in an embodiment of the present application. Figure 1As shown, the chip 100 includes a plurality of functional modules, namely, a functional module A102, a functional module B103 and a functional module C104. The chip 100 also includes a power-on reset circuit A110. The power supply voltage A120 from the outside of the chip 100 provides an operating voltage to the plurality of functional modules of the chip 100. In addition, the power-on reset circuit A110 also generates reset signals for the plurality of functional modules respectively. The power-on reset circuit A110 is used to detect the change of the power supply voltage A120, and before the power supply voltage A120 reaches a preset stable value, generates a valid reset signal, so as to ensure that each functional module in the chip 100 can receive a valid reset signal and complete a reliable initialization reset operation, so that the entire chip 100 can start and run from a certain power-on initial state. In application scenarios such as high-speed digital signal processing, audio signal processing, analog-to-digital conversion, and vehicle-mounted systems, the power supply voltage may be affected by interference voltage signals, the source of which may be electrostatic discharge (ESD) interference, such as ESD interference from the user's body, peripheral equipment, and connecting cables, or power surge (EOS) interference, such as external current or voltage exceeding the device performance specification. The interference voltage signal may be a high-energy current pulse that lasts for a period of time, such as tens of nanoseconds, and may have positive or negative polarity. Due to the influence of the interference voltage signal on the power supply voltage A120 connected to the chip 100, the power-on reset circuit A110 inside the chip 100 may erroneously output a reset signal, thereby causing a reset error, such as abnormally resetting the working functional module A102 to the initial state or causing a function of the functional module B103 to suddenly go offline. The power-on reset circuit A110 determines whether the power supply voltage A120 has reached a preset stable value through built-in circuits and modules, and the interference voltage signal may cause a violent fluctuation of the power supply voltage A120, such as rapid rise or rapid decline, which may affect the judgment mechanism of the power-on reset circuit A110, thereby causing the power-on reset circuit A110 to make an erroneous judgment. For this reason, it is necessary to enhance the anti-interference ability of the power-on reset circuit A110, including the anti-interference ability to the positive voltage interference voltage signal and the anti-interference ability to the negative voltage interference voltage signal. In addition, the filter circuit part of the power-on reset circuit A110 has a resistor-capacitor time constant. When the resistor-capacitor time constant differs greatly from the frequency of the interference voltage signal, it is difficult to provide a high-quality filtering effect, and the high-frequency component or low-frequency component in the interference voltage signal may not be fully filtered, so it is difficult to meet the high-precision requirements of the chip. If the resistor-capacitor time constant is to be adjusted, an adjustable resistor or an adjustable capacitor needs to be provided, but both the adjustable resistor and the adjustable capacitor require additional devices and volume, which is not conducive to the design purpose of highly integrated and miniaturized chips.The power-on reset circuit provided in the embodiment of the present application is described below in combination with the drawings and specific embodiments of the present application, which is used for highly integrated and miniaturized chip design and can meet the high-precision control of the reset trigger point voltage over a wide frequency range.

[0020] Figure 2 The schematic diagram of the power-on reset circuit of the first implementation mode provided in the embodiment of the present application is shown in FIG. Figure 2 As shown, the power-on reset circuit B210 includes: a voltage divider module B230, wherein the voltage divider module B230 is used to provide a voltage division result of the power supply voltage B220 on the voltage division output node B250 of the voltage divider module B230 according to an adjustable voltage division coefficient; a high-frequency signal coupling network B232, wherein the high-frequency signal coupling network B232 includes a first capacitor B240 and a second capacitor B242, the first capacitor B240 is connected between the power supply voltage B220 and the voltage division output node B250, and the second capacitor B242 is connected between the voltage division output node B250 and the ground terminal B222; a comparison module B234, wherein the comparison module B234 is used to compare the voltage of the voltage division output node B250 and the threshold voltage, thereby generating an output logic signal; an output buffer module B236, wherein the output buffer module B236 is used to drive and enhance the output logic signal, thereby generating a reset signal B212 of the power-on reset circuit.

[0021] Figure 2The power-on reset circuit B210 shown can be applied in application scenarios such as high-speed digital signal processing, audio signal processing, analog-to-digital conversion, and vehicle-mounted systems, and can effectively deal with interference voltage signals that the power supply voltage B220 may be subjected to, including dealing with electrostatic discharge (ESD) interference, such as ESD interference from the user's body, peripheral equipment, and connecting cables, and dealing with power surge (EOS) interference, such as external current or voltage exceeding the device performance specification. Interference voltage signals may also be applied to the ground terminal B222, such as interference to the ground cable. Therefore, interference voltage signals such as ESD interference and EOS interference may interfere with the power-on reset circuit B210 through the power supply voltage B220 or the ground terminal B222, thereby possibly affecting the judgment mechanism of the comparison module B234. Here, the voltage divider module B230 and the comparison module B234 are both connected to the power supply voltage B220 and the ground terminal B222. Generally, the threshold voltage of the comparison module B234 used for the judgment mechanism is designed to be a certain proportion of the power supply voltage B220, such as half of the power supply voltage B220. The power-on reset circuit B210 can be used to detect the change of the power supply voltage B220. Before the power supply voltage B220 reaches a preset stable value, the comparison module B234 is controlled to output a pre-designed logic signal, and the output buffer module B236 is controlled to output a pre-designed reset signal B212, so as to ensure that the functional modules inside the chip complete a reliable initialization reset operation. For example, Figure 1The functional module A102 of the chip 100 shown receives the reset signal output by the power-on reset circuit A110 to complete a reliable initialization reset operation. The comparison module B234 is used to compare the voltage of the voltage-dividing output node B250 with the threshold voltage, thereby generating an output logic signal; therefore, when the voltage of the voltage-dividing output node B250 is lower than the threshold voltage, the comparison module B234 outputs a first logic signal, and conversely, when the voltage of the voltage-dividing output node B250 is higher than the threshold voltage, the comparison module B234 outputs a second logic signal. In addition, the voltage-dividing module B230 is used to provide a voltage-dividing result of the power supply voltage B220 on the voltage-dividing output node B250 of the voltage-dividing module B230 according to an adjustable voltage-dividing coefficient. Therefore, the real-time voltage on the voltage-dividing output node B250 is jointly determined by the voltage-dividing effect of the voltage-dividing module B230 and the coupling effect of the high-frequency signal coupling network B232. The adjustable voltage division coefficient of the voltage division module B230 is generally adjusted by changing the on-resistance of the voltage division transistor, thereby offsetting the influence of the violent fluctuation of the power supply voltage B220. It can be seen that when the interference voltage signal is of positive polarity, that is, a positive voltage interference voltage signal, this will cause the power supply voltage B220 to rise rapidly, and by reducing the adjustable voltage division coefficient of the voltage division module B230, the voltage division result of the power supply voltage B220 on the voltage division output node B250 of the voltage division module B230 can offset the rapid rise of the power supply voltage B220. Here, assuming that the threshold voltage is designed to be half of the power supply voltage B220, during the interference process of the entire positive voltage interference voltage signal (such as a positive voltage ESD signal), such as during a high-energy current pulse lasting tens of nanoseconds, as long as the voltage on the voltage division output node B250 is kept less than half of the power supply voltage B220 superimposed on the positive voltage interference voltage signal, it can be ensured that the comparison module B234 outputs a correct logic signal and the output buffer module B236 outputs a correct reset signal B212. Therefore, the power-on reset circuit B210 has the ability to resist positive voltage interference voltage signals.

[0022] Continue reading Figure 2As mentioned above, the power-on reset circuit B210 has the ability to resist positive voltage interference signals. When the interference voltage signal is of negative polarity, that is, a negative voltage interference voltage signal, this will cause the power supply voltage B220 to drop rapidly, and by increasing the adjustable voltage division coefficient of the voltage division module B230, for example, by changing the on-resistance of the voltage division transistor in the voltage division module B230, the voltage division result of the power supply voltage B220 on the voltage division output node B250 of the voltage division module B230 can offset the rapid drop of the power supply voltage B220. Here, assuming that the threshold voltage is designed to be half of the power supply voltage B220, during the interference process of the entire negative voltage interference voltage signal (such as a negative voltage ESD signal), such as during a high-energy current pulse lasting tens of nanoseconds, as long as the voltage on the voltage division output node B250 is kept less than half of the power supply voltage B220 superimposed on the negative voltage interference voltage signal, it can be ensured that the comparison module B234 outputs a correct logic signal and the output buffer module B236 outputs a correct reset signal B212. However, unlike the situation of the positive voltage interference voltage signal described above, during the period of action of the negative voltage interference voltage signal, the adjustable voltage division coefficient of the voltage divider module B230 is increased, thereby increasing the voltage division result of the power supply voltage B220 on the voltage divider output node B250 to offset the rapid drop in the power supply voltage B220. In this case, the threshold voltage is half of the power supply voltage B220 superimposed on the negative voltage interference voltage signal (it can also be one-third, one-quarter or other fixed proportions). Therefore, during the period of increasing the adjustable voltage division coefficient of the voltage divider module B230 and thereby increasing the voltage division result of the power supply voltage B220 on the voltage divider output node B250, the threshold voltage is the power supply voltage B220 superimposed on the negative voltage interference voltage signal and is therefore reduced. That is to say, during the period of the negative voltage interference voltage signal, the voltage division result of the power supply voltage B220 on the voltage division output node B250 is increased by the voltage division of the voltage division module B230, while facing the reduced threshold voltage. If the voltage on the voltage division output node B250 exceeds the reduced threshold voltage, the comparison module B234 will output an erroneous logic signal and the output buffer module B236 will output an erroneous reset signal. Therefore, unlike the case of the positive voltage interference voltage signal described above, during the period of the negative voltage interference voltage signal, if the interference level is too high, the real-time voltage value after the threshold voltage is superimposed on the negative voltage interference voltage signal may drop to a value lower than the real-time voltage on the voltage division output node B250, which may result in the output of an erroneous reset signal. In applications such as high-speed digital signal processing, audio signal processing, analog-to-digital conversion, etc., the source of the interference voltage ESD, i.e., electrostatic discharge, may be from the human body, equipment periphery, cables, etc., which may cause high-energy electrical pulses up to tens of nanoseconds, which is closer to the power supply voltage B220, thereby resulting in an erroneous output reset signal.In addition, the resistors in the voltage divider module B230 are generally fixed resistors and fixed capacitors, so the filtering circuit function provided by the voltage divider module B230 has a fixed resistor and capacitor time constant; when the resistor and capacitor time constant differ greatly from the frequency of the interference voltage signal, it is difficult to provide a high-quality filtering effect, and the high-frequency or low-frequency components in the interference voltage signal may not be fully filtered, which makes it difficult to meet the high-precision requirements of the chip. For this reason,. Figure 2 The power-on reset circuit B210 shown is designed around the optimized high-frequency signal coupling network B232, which enhances the anti-interference ability of the power-on reset circuit B210 to positive voltage interference voltage signals while also enhancing the anti-interference ability of the power-on reset circuit B210 to negative voltage interference voltage signals. In addition, by utilizing the optimized design of the high-frequency signal coupling network B232, high-precision control of the reset trigger point voltage in a wide frequency range is achieved, which can flexibly adapt to the frequency changes of the interference signal.

[0023] Continue reading Figure 2The high-frequency signal coupling network B232 includes a first capacitor B240 and a second capacitor B242, wherein the first capacitor B240 is connected between the power supply voltage B220 and the voltage-dividing output node B250, and the second capacitor B242 is connected between the voltage-dividing output node B250 and the ground terminal B222. Thus, by utilizing the optimized design of the high-frequency signal coupling network B232, the interference voltage signal from the power supply voltage B220 or from the ground terminal B222 will be coupled to the voltage-dividing output node B250, and by utilizing the ratio of the capacitance values ​​of the first capacitor B240 and the second capacitor B242, the high-frequency voltage fluctuation coupled to the voltage-dividing output node B250 can be set to be a certain proportion of the amplitude of the interference voltage signal. For example, the capacitance value of the first capacitor B240 can be set equal to the capacitance value of the second capacitor B242, which means that the high-frequency voltage fluctuation coupled to the voltage-dividing output node B250 based on the high-frequency signal coupling network B232 is half the amplitude of the interference voltage signal; in this way, the threshold voltage can be adapted to be designed as half of the power supply voltage B220. Therefore, during the period of the negative voltage interference voltage signal, the real-time voltage on the voltage-dividing output node B250 is jointly determined by the voltage-dividing effect of the voltage-dividing module B230 and the coupling effect of the high-frequency signal coupling network B232; this means that when the threshold voltage is reduced, that is, the threshold voltage is half of the power supply voltage B220 superimposed on the negative voltage interference voltage signal, at this time, half of the negative voltage interference voltage signal is also superimposed on the voltage-dividing output node B250 through the coupling effect of the high-frequency signal coupling network B232. That is to say, during the period when the negative voltage interference voltage signal is applied, while the voltage dividing result of the power supply voltage B220 on the voltage divider output node B250 is increased through the voltage dividing action of the voltage divider module B230, half of the negative voltage interference voltage signal is superimposed on the voltage divider output node B250 as a high-frequency voltage fluctuation through the coupling action of the high-frequency signal coupling network B232. This means that the voltage on the voltage divider output node B250 is the voltage dividing result of the power supply voltage B220 on the voltage divider output node B250 superimposed with the high-frequency voltage fluctuation coupled to the voltage divider output node B250 through the high-frequency signal coupling network B232. In this way, the voltage on the voltage divider output node B250 is effectively avoided from exceeding the reduced threshold voltage, thereby enhancing the anti-interference ability of the power-on reset circuit B210 against the negative voltage interference voltage signal.Furthermore, when the setting of the threshold voltage changes, for example, the threshold voltage is designed to be one-third, one-quarter or other proportions of the power supply voltage B220, by correspondingly changing the ratio of the capacitance values ​​of the first capacitor B240 and the second capacitor B242, the corresponding proportion of the interference voltage signal can be superimposed on the voltage divider output node B250 as a high-frequency voltage fluctuation through the high-frequency signal coupling network B232. This means that various settings of the threshold voltage can be flexibly adapted, that is, the real-time voltage on the voltage divider output node B250 can flexibly track changes in the threshold voltage, effectively avoiding the judgment errors of the comparison module B234 that may be caused by the interference voltage signal.

[0024] Continue reading Figure 2 In the rapid decay process of the positive voltage interference voltage signal, the high-frequency signal coupling network B232 couples the rapid decay information of the positive voltage interference voltage signal to the voltage-dividing output node B250 in real time, causing the instantaneous voltage of the voltage-dividing output node B250 to be mainly determined by capacitive coupling. Therefore, the voltage of the voltage-dividing output node B250 closely follows the decrease of the power supply voltage B220 and decreases synchronously, thereby enhancing the anti-interference ability of the positive voltage interference voltage signal. When the power supply voltage B220 decreases rapidly and abnormally due to the interference of the negative voltage interference voltage signal, the threshold voltage used by the comparison module B234 will also decrease, and the adjustable voltage-dividing coefficient of the voltage-dividing module B230 will increase. At this time, the rapid change information of the negative voltage interference voltage signal is coupled to the voltage-dividing output node B250 in real time through the high-frequency signal coupling network B232, causing the instantaneous voltage of the voltage-dividing output node B250 to be mainly determined by capacitive coupling. Therefore, the voltage of the voltage-dividing output node B250 closely follows the change of the power supply voltage B220 and decreases synchronously. Therefore, in the whole interference process of the negative voltage interference voltage signal, the voltage on the voltage-dividing output node B250 is kept less than the threshold voltage, ensuring that the comparison module B234 outputs the correct logic signal, thereby enhancing the anti-interference ability of the negative voltage interference voltage signal. In addition, the capacitor included in the high-frequency signal coupling network B232 has the characteristics of being connected at high frequencies and disconnected at low frequencies. Therefore, when the power supply voltage B220 is stable, the capacitor included in the high-frequency signal coupling network B232 is equivalent to being disconnected, thereby not affecting the normal operation of the chip.

[0025] In conclusion, Figure 2The power-on reset circuit B210 shown in the figure superimposes the high-frequency jitter of the power supply voltage B220 on the voltage-dividing output node B250 through the design of the high-frequency signal coupling network B232, so that the real-time voltage on the voltage-dividing output node B250 is jointly determined by the voltage-dividing effect of the voltage-dividing module B230 and the coupling effect of the high-frequency signal coupling network B232; the ratio of the capacitance values ​​of the first capacitor B240 and the second capacitor B242 in the high-frequency signal coupling network B232 is configured according to the setting of the threshold voltage, so that various threshold voltages can be flexibly adapted. Setting, that is, realizing that the real-time voltage on the voltage divider output node B250 can flexibly track the change of the threshold voltage; enhancing the anti-interference ability of the power-on reset circuit B210 to the positive voltage interference voltage signal while also enhancing the anti-interference ability of the power-on reset circuit B210 to the negative voltage interference voltage signal; utilizing the flexible setting of the threshold voltage, the reset trigger point voltage can be accurately controlled, and has the characteristics of being insensitive to process and temperature changes, which is conducive to highly integrated and miniaturized chip design, and can meet the high-precision control of the reset trigger point voltage over a wide frequency range.

[0026] Figure 3 The schematic diagram of the power-on reset circuit of the second implementation mode provided in the embodiment of the present application is as follows. Figure 3 As shown, the power-on reset circuit C310 includes: a voltage divider module C330, wherein the voltage divider module C330 is used to provide a voltage division result of the power supply voltage C320 on the voltage division output node C350 of the voltage divider module C330 according to an adjustable voltage division coefficient; a high-frequency signal coupling network C332, wherein the high-frequency signal coupling network C332 includes a first capacitor C1 and a second capacitor C2, the first capacitor C1 is connected between the power supply voltage C320 and the voltage division output node C350, and the second capacitor C2 is connected between the voltage division output node C350 and the ground terminal C322; a comparison module C334, wherein the comparison module C334 is used to compare the voltage of the voltage division output node C350 and the threshold voltage, thereby generating an output logic signal; an output buffer module C336, wherein the output buffer module C336 is used to drive and enhance the output logic signal, thereby generating a reset signal C312 of the power-on reset circuit.

[0027] See also Figure 3, the comparison module C334 is used to compare the voltage of the voltage-dividing output node C350 with the threshold voltage, thereby generating an output logic signal; therefore, when the voltage of the voltage-dividing output node C350 is lower than the threshold voltage, the comparison module C334 outputs the first logic signal, and conversely, when the voltage of the voltage-dividing output node C350 is higher than the threshold voltage, the comparison module C334 outputs the second logic signal. In addition, the voltage-dividing module C330 is used to provide the voltage-dividing result of the power supply voltage C320 on the voltage-dividing output node C350 of the voltage-dividing module C330 according to the adjustable voltage-dividing coefficient. Therefore, the real-time voltage on the voltage-dividing output node C350 is jointly determined by the voltage-dividing effect of the voltage-dividing module C330 and the coupling effect of the high-frequency signal coupling network C332. The adjustable voltage-dividing coefficient of the voltage-dividing module C330 is generally adjusted by changing the on-resistance of the voltage-dividing transistor, thereby offsetting the influence of the violent fluctuation of the power supply voltage C320. The voltage divider module C330 includes a voltage divider resistor R0 and voltage divider tubes M0, M1, and M2. It can be seen that when the interference voltage signal is of positive polarity, that is, a positive voltage interference voltage signal, this will cause the power supply voltage C320 to rise rapidly, the on-resistance of the voltage divider tube M1 to decrease, and the on-resistance of the voltage divider tube M2 to increase, which leads to a reduction in the adjustable voltage divider coefficient. By reducing the adjustable voltage divider coefficient of the voltage divider module C330, the voltage divider result of the power supply voltage C320 on the voltage divider output node C350 of the voltage divider module C330 can offset the rapid rise of the power supply voltage C320. Here, assuming that the threshold voltage is designed to be half of the power supply voltage C320, during the interference process of the entire positive voltage interference voltage signal (such as a positive voltage ESD signal), such as during a high-energy current pulse lasting tens of nanoseconds, as long as the voltage on the voltage-dividing output node C350 is kept less than half of the power supply voltage C320 superimposed on the positive voltage interference voltage signal, it can be ensured that the comparison module C334 outputs a correct logic signal and the output buffer module C336 outputs a correct reset signal C312. Therefore, the power-on reset circuit C310 has the ability to resist positive voltage interference voltage signals.

[0028] Continue reading Figure 3When the interference voltage signal is of negative polarity, that is, a negative voltage interference voltage signal, this will cause the power supply voltage C320 to drop rapidly, the on-resistance of the voltage divider tube M1 to increase, and the on-resistance of the voltage divider tube M2 to decrease, which leads to an increase in the adjustable voltage division coefficient. By increasing the adjustable voltage division coefficient of the voltage divider module C330, for example, by changing the on-resistance of the voltage divider transistor in the voltage divider module C330, the voltage division result of the power supply voltage C320 on the voltage division output node C350 of the voltage divider module C330 can offset the rapid drop of the power supply voltage C320. Here, assuming that the threshold voltage is designed to be half of the power supply voltage C320, during the interference process of the entire negative voltage interference voltage signal (such as a negative voltage ESD signal), such as during a high-energy current pulse lasting tens of nanoseconds, as long as the voltage on the voltage division output node C350 is kept less than half of the power supply voltage C320 superimposed on the negative voltage interference voltage signal, it can be ensured that the comparison module C334 outputs a correct logic signal and the output buffer module C336 outputs a correct reset signal C312. However, unlike the case of the positive voltage interference voltage signal described above, during the period of the negative voltage interference voltage signal, the adjustable voltage division coefficient of the voltage divider module C330 is increased to increase the voltage division result of the power supply voltage C320 on the voltage divider output node C350 to offset the rapid drop in the power supply voltage C320. In this case, the threshold voltage is half of the power supply voltage C320 superimposed on the negative voltage interference voltage signal (it can also be one-third, one-quarter or other fixed proportions). Therefore, during the period of increasing the adjustable voltage division coefficient of the voltage divider module C330 to increase the voltage division result of the power supply voltage C320 on the voltage divider output node C350, the threshold voltage is the power supply voltage C320 superimposed on the negative voltage interference voltage signal and is therefore reduced. That is to say, during the period of the negative voltage interference voltage signal, the voltage division result of the power supply voltage C320 on the voltage division output node C350 is increased by the voltage division of the voltage division module C330, while facing the reduced threshold voltage. If the voltage on the voltage division output node C350 exceeds the reduced threshold voltage, the comparison module C334 will output an erroneous logic signal and the output buffer module C336 will output an erroneous reset signal. Therefore, unlike the case of the positive voltage interference voltage signal described above, during the period of the negative voltage interference voltage signal, if the interference level is too high, the real-time voltage value after the threshold voltage is superimposed on the negative voltage interference voltage signal may drop to a value lower than the real-time voltage on the voltage division output node C350, which may result in the output of an erroneous reset signal. In applications such as high-speed digital signal processing, audio signal processing, analog-to-digital conversion, etc., the source of the interference voltage ESD, i.e., electrostatic discharge, may be from the human body, equipment periphery, cables, etc., which may cause high-energy electrical pulses up to tens of nanoseconds, which is closer to the power supply voltage C320, thereby resulting in an erroneous output reset signal.In addition, the resistors in the voltage divider module C330 are generally fixed resistors and fixed capacitors, so the filtering circuit function provided by the voltage divider module C330 has a fixed resistor and capacitor time constant; when the resistor and capacitor time constant differ greatly from the frequency of the interference voltage signal, it is difficult to provide a high-quality filtering effect, and the high-frequency or low-frequency components in the interference voltage signal may not be fully filtered, which makes it difficult to meet the high-precision requirements of the chip. For this reason,. Figure 3 The power-on reset circuit C310 shown is designed around the optimized high-frequency signal coupling network C332, which enhances the anti-interference ability of the power-on reset circuit C310 to positive interference voltage signals while also enhancing the anti-interference ability of the power-on reset circuit C310 to negative interference voltage signals. In addition, by utilizing the optimized design of the high-frequency signal coupling network C332, high-precision control of the reset trigger point voltage in a wide frequency range is achieved, which can flexibly adapt to the frequency changes of the interference signal.

[0029] Continue reading Figure 3, the high-frequency signal coupling network C332 includes a first capacitor C1 and a second capacitor C2, the first capacitor C1 is connected between the power supply voltage C320 and the voltage-dividing output node C350, and the second capacitor C2 is connected between the voltage-dividing output node C350 and the ground terminal C322. In this way, by using the optimized design of the high-frequency signal coupling network C332, the interference voltage signal from the power supply voltage C320 or from the ground terminal C322 will be coupled to the voltage-dividing output node C350, and by using the ratio of the capacitance values ​​of the first capacitor C1 and the second capacitor C2, the high-frequency voltage fluctuation coupled to the voltage-dividing output node C350 can be set to be a certain proportion of the amplitude of the interference voltage signal. For example, the capacitance value of the first capacitor C1 can be set to be equal to the capacitance value of the second capacitor C2, which means that the high-frequency voltage fluctuation coupled to the voltage-dividing output node C350 based on the high-frequency signal coupling network C332 is half of the amplitude of the interference voltage signal; in this way, the threshold voltage can be adapted to be designed to be half of the power supply voltage C320. Therefore, during the period of the negative voltage interference voltage signal, the real-time voltage on the voltage divider output node C350 is jointly determined by the voltage divider module C330 and the coupling effect of the high-frequency signal coupling network C332; this means that when the threshold voltage is reduced, that is, the threshold voltage is half of the power supply voltage C320 superimposed on the negative voltage interference voltage signal, at this time, half of the negative voltage interference voltage signal is also superimposed on the voltage divider output node C350 through the coupling effect of the high-frequency signal coupling network C332. That is to say, during the period of the action of the negative voltage interference voltage signal, while the voltage division result of the power supply voltage C320 on the voltage divider output node C350 is increased through the voltage division action of the voltage divider module C330, half of the negative voltage interference voltage signal is superimposed on the voltage divider output node C350 as a high-frequency voltage fluctuation through the coupling action of the high-frequency signal coupling network C332. This means that the voltage on the voltage divider output node C350 is the voltage division result of the power supply voltage C320 on the voltage divider output node C350 superimposed with the high-frequency voltage fluctuation coupled to the voltage divider output node C350 through the high-frequency signal coupling network C332. In this way, the voltage on the voltage divider output node C350 is effectively avoided from exceeding the reduced threshold voltage, thereby enhancing the anti-interference ability of the power-on reset circuit C310 to the negative voltage interference voltage signal.Furthermore, when the setting of the threshold voltage changes, for example, the threshold voltage is designed to be one-third, one-quarter or other proportions of the power supply voltage C320, by correspondingly changing the ratio of the capacitance values ​​of the first capacitor C1 and the second capacitor C2, the corresponding proportion of the interference voltage signal can be superimposed on the voltage divider output node C350 as a high-frequency voltage fluctuation through the high-frequency signal coupling network C332. This means that various settings of the threshold voltage can be flexibly adapted, that is, the real-time voltage on the voltage divider output node C350 can flexibly track changes in the threshold voltage, effectively avoiding the judgment errors of the comparison module C334 that may be caused by the interference voltage signal.

[0030] Continue reading Figure 3 In the rapid decay process of the positive voltage interference voltage signal, the high-frequency signal coupling network C332 couples the rapid decay information of the positive voltage interference voltage signal to the voltage divider output node C350 in real time, causing the instantaneous voltage of the voltage divider output node C350 to be mainly determined by the capacitive coupling. Therefore, the voltage of the voltage divider output node C350 closely follows the decrease of the power supply voltage C320 and decreases synchronously, thereby enhancing the anti-interference ability of the positive voltage interference voltage signal. When the power supply voltage C320 decreases rapidly and abnormally due to the interference of the negative voltage interference voltage signal, the threshold voltage used by the comparison module C334 will also decrease, and the adjustable voltage division coefficient of the voltage divider module C330 will increase. At this time, the rapid change information of the negative voltage interference voltage signal is coupled to the voltage divider output node C350 in real time through the high-frequency signal coupling network C332, causing the instantaneous voltage of the voltage divider output node C350 to be mainly determined by the capacitive coupling. Therefore, the voltage of the voltage divider output node C350 closely follows the change of the power supply voltage C320 and decreases synchronously. Therefore, in the whole interference process of the negative voltage interference voltage signal, the voltage on the voltage-dividing output node C350 is kept less than the threshold voltage, ensuring that the comparison module C334 outputs the correct logic signal, thereby enhancing the anti-interference ability of the negative voltage interference voltage signal. In addition, the capacitor included in the high-frequency signal coupling network C332 has the characteristics of being connected at high frequencies and disconnected at low frequencies. Therefore, when the power supply voltage C320 is stable, the capacitor included in the high-frequency signal coupling network C332 is equivalent to being disconnected, thereby not affecting the normal operation of the chip.

[0031] Continue reading Figure 3 The comparison module C334 includes a hysteresis feedback part and an inverting comparison part, wherein the hysteresis feedback part includes transistors M4 and M3, and the inverting comparison part includes transistors M5 and M6. Figure 3The circuit connection relationship of the common gate and common source is provided, thus providing an inverting comparison function. The output buffer module C336 includes a transistor M7, a transistor M8, a transistor M9, and a transistor M10. The output buffer module C336 is used to enhance the driving capability of the logic signal output by the comparison module C334, thereby serving as a reset signal C312 output by the power-on reset circuit C310 to the subsequent circuit. It should be understood that Figure 3 The specific circuit elements and connection relationships of the voltage divider module C330, the comparison module C334 and the output buffer module C336 shown in the figure are only exemplary and should not be construed as limitations. Figure 2 The power-on reset circuit B210 and Figure 3 The operating principle of the power-on reset circuit C310 shown in FIG. 3 may adopt various reasonable specific circuit designs, for example, a Schmitt trigger may be added between the inverting comparison part of the comparison module C334 and the output buffer module C336, or the output buffer module C336 may be replaced with a Schmitt trigger.

[0032] In conclusion, Figure 3 The power-on reset circuit C310 shown in the figure superimposes the high-frequency jitter of the power supply voltage C320 on the voltage-dividing output node C350 through the design of the high-frequency signal coupling network C332, so that the real-time voltage on the voltage-dividing output node C350 is jointly determined by the voltage-dividing effect of the voltage-dividing module C330 and the coupling effect of the high-frequency signal coupling network C332; the ratio of the capacitance values ​​of the first capacitor C1 and the second capacitor C2 in the high-frequency signal coupling network C332 is configured according to the setting of the threshold voltage, so that various settings of the threshold voltage can be flexibly adapted, that is, the real-time voltage on the voltage-dividing output node C350 can flexibly track the change of the threshold voltage; the anti-interference ability of the power-on reset circuit C310 to the positive voltage interference voltage signal is enhanced, and the anti-interference ability of the power-on reset circuit C310 to the negative voltage interference voltage signal is also enhanced; by using the flexible setting of the threshold voltage, the reset trigger point voltage can be accurately controlled, and it has the characteristics of being insensitive to process and temperature changes, which is conducive to the design of highly integrated and miniaturized chips, and can meet the high-precision control of the reset trigger point voltage in a wide frequency range.

[0033] See also Figure 1 , Figure 2 as well as Figure 3In a possible implementation, the voltage divider module includes a voltage divider resistor and a voltage divider transistor, the adjustable voltage divider coefficient is determined based on the on-resistance of the voltage divider transistor, the on-resistance of the voltage divider transistor changes with the change of the power supply voltage, and the adjustable voltage divider coefficient decreases when the power supply voltage rises and increases when the power supply voltage decreases. In this way, the ability of the power-on reset circuit to resist interference voltage signals is improved.

[0034] In a possible implementation, the voltage divider module has an output equivalent impedance on the voltage divider output node, the comparison module is an inverting comparator with a hysteresis function, and the high-frequency signal coupling loop is used to couple the interference voltage signal to the voltage divider output node. In this way, through the design of the high-frequency signal coupling network, the high-frequency jitter of the power supply voltage is superimposed on the voltage divider output node, so that the real-time voltage on the voltage divider output node is jointly determined by the voltage division effect of the voltage divider module and the coupling effect of the high-frequency signal coupling network; while enhancing the anti-interference ability of the power-on reset circuit to positive voltage interference voltage signals, it also enhances the anti-interference ability of the power-on reset circuit to negative voltage interference voltage signals; by using the flexible setting of the threshold voltage, the reset trigger point voltage can be accurately controlled, and it has the characteristics of being insensitive to process and temperature changes, which is conducive to highly integrated and miniaturized chip design, and can meet the high-precision control of the reset trigger point voltage over a wide frequency range.

[0035] In some embodiments, the first ratio between the capacitance value of the first capacitor and the capacitance value of the second capacitor is determined based on the second ratio between the threshold voltage and the power supply voltage. In this way, when the setting of the threshold voltage changes, for example, the threshold voltage is designed to be one-third, one-quarter or other proportions of the power supply voltage, by correspondingly changing the ratio of the capacitance values ​​of the first capacitor and the second capacitor, the corresponding proportion of the interference voltage signal can be superimposed on the voltage divider output node as a high-frequency voltage fluctuation through the high-frequency signal coupling network, which means that various settings of the threshold voltage can be flexibly adapted, that is, the real-time voltage on the voltage divider output node can flexibly track the changes in the threshold voltage, effectively avoiding the judgment errors of the comparison module B234 that may be caused by the interference voltage signal.

[0036] In some embodiments, when the second ratio is 1:2, the first ratio is 1:1. By using the ratio of the capacitance values ​​of the first capacitor and the second capacitor, the high-frequency voltage fluctuation coupled to the voltage divider output node can be set to be a certain proportion of the amplitude of the interference voltage signal. For example, the capacitance value of the first capacitor can be set equal to the capacitance value of the second capacitor, that is, the first ratio is 1:1. This means that the high-frequency voltage fluctuation coupled to the voltage divider output node based on the high-frequency signal coupling network is half the amplitude of the interference voltage signal; in this way, the threshold voltage can be adapted to be designed to be half of the power supply voltage, that is, the second ratio is 1:2.

[0037] In some embodiments, the preset stable value of the power supply voltage is used to determine whether the reset signal is a high level or a low level, and the preset stable value of the power supply voltage is determined based on the on-voltage of the voltage-dividing transistor of the voltage-dividing module and the threshold voltage of the comparison module. Here, from the user's perspective, the role of the power-on reset circuit is to ensure that the power supply voltage outputs a correct reset signal before reaching the preset stable value. Therefore, from a holistic perspective, the preset stable value of the power supply voltage is used to determine whether the reset signal is a high level or a low level, and the preset stable value of the power supply voltage is determined based on the on-voltage of the voltage-dividing transistor of the voltage-dividing module and the threshold voltage of the comparison module. In this way, a power-on reset circuit for a highly integrated and miniaturized chip design is implemented, and a high-precision control reset trigger point voltage over a wide frequency range can be met.

[0038] In some embodiments, the comparator includes a common-gate common-source transistor pair, the first capacitor or the second capacitor is an adjustable capacitor, the first ratio is adjustable, the first ratio is adjusted to adapt the channel length-width ratio between the transistors included in the common-gate common-source transistor pair, and the second ratio is determined based on the channel length-width ratio between the transistors included in the common-gate common-source transistor pair. In this way, the ratio of the capacitance value of the first capacitor relative to the capacitance value of the second capacitor in the high-frequency signal coupling network is flexibly adjusted, and the setting of the threshold voltage of the comparator can be adapted, so that the application scenario requirements of the power-on reset circuit can be more flexibly and widely met. For example, the power-on reset circuit can be used for application scenarios in which the threshold voltage is set to one-third, one-quarter or other ratios of the power supply voltage. The second ratio can be set by providing the corresponding channel length-width ratio between transistors through modular design, and then the corresponding adaptation can be provided by adjusting the first ratio.

[0039] In a possible implementation, the smaller capacitance value between the capacitance value of the first capacitor and the capacitance value of the second capacitor is at least three times the sum of the capacitance values ​​of the parasitic capacitance of the voltage-dividing output node. This is conducive to stabilizing the adjustable voltage-dividing coefficient of the voltage-dividing module, and is conducive to preventing the operation of the power-on reset circuit from being affected by the frequency of the interference voltage signal, so as to accurately control the release reset trigger point voltage.

[0040] In a possible implementation, the output equivalent impedance, the first capacitor and the second capacitor of the high-frequency signal coupling network together constitute a resistance-capacitance time constant, and the resistance-capacitance time constant is less than the rise and fall time of the power supply voltage. Generally, there is a lower limit for the rise and fall time of the power supply voltage, such as 10 microseconds. By setting the resistance-capacitance time constant to be less than the rise and fall time of the power supply voltage, it is beneficial to better improve the anti-interference ability of the power-on reset circuit, while ensuring normal operation after power-on. For example, it can be required in the design constraints that the resistance-capacitance time constant composed of the output equivalent impedance and the first capacitor and the second capacitor is significantly less than the rise and fall time of the power supply voltage.

[0041] In a possible implementation manner, the comparison module includes a hysteresis circuit, and the output buffer module is a Schmitt buffer, thereby improving the overall system performance.

[0042] In a possible implementation, the interference voltage signal comes from the power supply voltage or the ground terminal, and the interference voltage signal is electrostatic discharge interference or power surge interference. In this way, it can be used in various application scenarios to combat various possible interference factors.

[0043] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0044] The present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0045] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0046] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0047] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in sequence, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A power-on reset circuit, characterized in that: The power-on reset circuit comprises: A voltage division module, wherein the voltage division module is used to provide a voltage division result of a power supply voltage at a voltage division output node of the voltage division module according to an adjustable voltage division coefficient; A high-frequency signal coupling network, wherein the high-frequency signal coupling network comprises a first capacitor and a second capacitor, the first capacitor is connected between the power supply voltage and the voltage-dividing output node, and the second capacitor is connected between the voltage-dividing output node and a ground terminal; A comparison module, wherein the comparison module is used to compare the voltage of the voltage-divided output node with a threshold voltage, thereby generating an output logic signal; An output buffer module, wherein the output buffer module is used to drive and enhance the output logic signal, thereby generating a reset signal for the power-on reset circuit.

2. The power-on reset circuit according to claim 1, characterized in that: The voltage divider module includes a voltage divider resistor and a voltage divider transistor. The adjustable voltage divider coefficient is determined based on the on-resistance of the voltage divider transistor. The on-resistance of the voltage divider transistor changes with the change of the power supply voltage. The adjustable voltage divider coefficient decreases when the power supply voltage increases and increases when the power supply voltage decreases.

3. The power-on reset circuit according to claim 1, characterized in that: The voltage divider module has an output equivalent impedance at the voltage divider output node, the comparison module is an inverting comparator with a hysteresis function, and the high-frequency signal coupling loop is used to couple the interference voltage signal to the voltage divider output node.

4. The power-on reset circuit according to claim 3, characterized in that: A first ratio between a capacitance value of the first capacitor and a capacitance value of the second capacitor is determined based on a second ratio between the threshold voltage and the power supply voltage.

5. The power-on reset circuit according to claim 4, characterized in that: When the second ratio is 1:2, the first ratio is 1:

1.

6. The power-on reset circuit according to claim 4, characterized in that: The preset stable value of the power supply voltage is used to determine whether the reset signal is at a high level or a low level, and the preset stable value of the power supply voltage is determined based on the on-voltage of the voltage divider transistor of the voltage divider module and the threshold voltage of the comparison module.

7. The power-on reset circuit according to claim 4, characterized in that: The comparator includes a common-gate common-source transistor pair, the first capacitor or the second capacitor is an adjustable capacitor, the first ratio is adjustable, the first ratio is adjusted to adapt to the channel length-to-width ratio between the transistors included in the common-gate common-source transistor pair, and the second ratio is determined based on the channel length-to-width ratio between the transistors included in the common-gate common-source transistor pair.

8. The power-on reset circuit according to claim 3, characterized in that: The smaller capacitance value between the capacitance value of the first capacitor and the capacitance value of the second capacitor is at least three times the sum of the capacitance values ​​of the parasitic capacitance of the voltage-dividing output node.

9. The power-on reset circuit according to claim 3, characterized in that: The output equivalent impedance, the first capacitor and the second capacitor of the high-frequency signal coupling network together form a resistance-capacitance time constant, and the resistance-capacitance time constant is smaller than the rise and fall time of the power supply voltage.

10. The power-on reset circuit according to claim 3, characterized in that: The comparison module includes a hysteresis circuit, and the output buffer module is a Schmitt buffer.

11. The power-on reset circuit according to claim 3, characterized in that: The interference voltage signal comes from the power supply voltage or the ground terminal, and the interference voltage signal is electrostatic discharge interference or power surge interference.

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