Buck self-oscillation circuit, power supply circuit and electronic device

Abstract

The buck self-shutdown circuit, power supply circuit, and electronic device provided by the embodiments of the present disclosure include: an inductor current sampling module that obtains a sampled current within a sampling clock cycle and determines an inductor current sampling voltage based on the sampled current; a comparison module that outputs a first comparison voltage signal based on the relationship between the inductor current sampling voltage and a ramp voltage within the sampling clock cycle; a logic control module that outputs a control signal to a power transistor based on the clock control signal, the first comparison voltage signal, and a maximum on-time control signal; a maximum on-time generation module that determines whether to generate a maximum on-time control signal based on the relationship between the time corresponding to the first comparison voltage signal becoming high within the sampling clock cycle and the time corresponding to the sampling voltage being greater than a first reference voltage; and a counting module that outputs an enable signal to the buck circuit upon receiving the maximum on-time control signal for a target number of consecutive sampling clock cycles. These achieve self-shutdown of the buck circuit.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits and related technical fields, and in particular, to a BUCK self-turn-off circuit, a power supply circuit and an electronic device. BACKGROUND

[0002] PMIC (Power Management Integrated Circuit) is a highly integrated power supply circuit, mainly used for managing and regulating the power supply of electronic systems. Its main functions include voltage conversion, current control, multiple power rail provision, and power management. PMIC integrates multiple channel DCDC converters, linear voltage regulators LDO, high / low side switches, charge controllers, etc. inside, which can provide multiple channels of power to meet the power needs of different subsystems. PMIC has the advantages of high integration, small size, low cost, high efficiency, etc., and is increasingly widely used in automotive, communication, electronic, radar and other multi-field terminal devices.

[0003] However, for a multi-channel PMIC, in actual application, there will be a situation that not all BUCK channels are used, and for the unused BUCK channels, the BUCK circuit of the channel is usually selected to be turned off to save power consumption. In the prior art, there are the following methods to turn off the idle BUCK circuit: one is to increase external pins to configure pin voltage or timing to control the BUCK circuit corresponding to the idle BUCK channel to be turned off, which will significantly increase the chip area; the second is to use MCU to control the enable signal of the idle BUCK, so as to achieve the purpose of turning off the idle BUCK channel, which increases the peripheral configuration device and cost; the third is to increase the register configuration, and use the register configuration to turn off the enable signal of the idle BUCK channel after each boot, which will increase the complexity and area of chip design. SUMMARY

[0004] The embodiments described herein provide a BUCK self-turn-off circuit, a power supply circuit and an electronic device, which solve the problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, a BUCK self-turn-off circuit is provided, comprising: an inductor current sampling module, a comparison module, a logic control module, a maximum on-time generation module and a counting module;

[0006] The inductor current sampling module is configured to obtain a sampling current in a sampling clock period, and determine an inductor current sampling voltage according to the sampling current.

[0007] The comparison module is configured to output a first comparison voltage signal to the logic control module according to the relationship between the inductor current sampling voltage and a ramp voltage in the sampling clock period.

[0008] the logic control module is configured to output a control signal to the power tube according to a clock control signal, the first comparison voltage signal and a maximum on-time control signal;

[0009] the maximum on-time generation module is configured to determine whether to generate a maximum on-time control signal according to a relationship between a time corresponding to the first comparison voltage signal becoming high within the sampling clock period and a time corresponding to the sampling voltage being greater than a first reference voltage;

[0010] the counting module is configured to output an enable signal to the BUCK circuit when a continuous target number of sampling clock periods each receive the maximum on-time control signal.

[0011] In some embodiments of the present disclosure, the comparison module includes a first comparison unit and a second comparison unit;

[0012] the first comparison unit is configured to output a second comparison voltage signal to the second comparison unit according to a feedback voltage and a second reference voltage;

[0013] the second comparison unit is configured to output a first comparison voltage signal to the maximum on-time generation module according to the second comparison voltage signal and the inductor current sampling voltage and a sawtooth wave voltage.

[0014] In some embodiments of the present disclosure, the first comparison unit includes a first comparator, and the second comparison unit includes a second comparator, a positive input terminal of the first comparator receives a feedback voltage, a negative input terminal of the first comparator receives a second reference voltage, an output terminal of the first comparator outputs a second comparison voltage signal to a negative input terminal of the second comparator, positive input terminals of the second comparator respectively receive the inductor current sampling voltage and the sawtooth wave voltage, and an output terminal of the second comparator outputs a first comparison voltage signal.

[0015] In some embodiments of the present disclosure, the logic control module includes a logic control unit and a master control unit;

[0016] the logic control unit is configured to output a logic control signal according to the clock control signal, a feedback voltage and a maximum on-time control signal;

[0017] the master control unit is configured to control turn-on and turn-off of the power tube according to the first comparison voltage signal and the logic control signal, and generate a feedback voltage to the logic control unit according to a collected on-off state of the power tube.

[0018] In some embodiments of the present disclosure, the logic control unit comprises a first inverter, a second inverter, a third inverter, a first NAND gate and a second NAND gate, an input end of the first inverter receives a clock control signal, an output end of the first inverter is electrically connected with a first input end of the first NAND gate, a second input end of the first NAND gate is electrically connected with an output end of the second NAND gate, an output end of the first NAND gate is electrically connected with a first input end of the second NAND gate and outputs a control signal, an input end of the second inverter receives the feedback voltage, an output end of the second inverter is electrically connected with a second input end of the second NAND gate, an input end of the third inverter receives a maximum on-time control signal, and an output end of the third inverter is electrically connected with a third input end of the second NAND gate.

[0019] In some embodiments of the present disclosure, the maximum on-time generation module comprises a fourth inverter, a transistor, a current source, a capacitor and a third comparator, an input end of the fourth inverter receives a logic control signal, an output end of the fourth inverter is electrically connected with a control end of the transistor, a first end of the current source receives a power voltage signal, a second end of the current source, a first end of the capacitor and a first end of the transistor are respectively electrically connected with a positive input end of the third comparator, a second end of the capacitor and a second end of the transistor are electrically connected with a ground node, a reverse input end of the third comparator receives a second reference voltage, and an output end of the third comparator outputs a maximum on-time control signal.

[0020] In some embodiments of the present disclosure, the transistor is an NMOS transistor.

[0021] In some embodiments of the present disclosure, the counting module comprises a counter, the counter receives the maximum on-time control signal and the clock control signal, and outputs an enable signal to the BUCK circuit when a number of the maximum on-time control signals meets a target number.

[0022] In some embodiments of the present disclosure, the BUCK self-turn-off circuit further comprises a control module configured to control the turn-on and turn-off of the power transistor according to the control signal.

[0023] According to a second aspect of the present disclosure, a power supply circuit is provided, comprising the BUCK self-turn-off circuit of any one of the first aspect.

[0024] According to a third aspect of the present disclosure, an electronic device is provided, comprising the power supply circuit of the second aspect.

[0025] The BUCK self-turn-off circuit, the power supply circuit and the electronic device provided by the embodiments of the present disclosure, the inductor current sampling module obtains a sampling current in a sampling clock period, and determines an inductor current sampling voltage in the clock period according to the sampling current; the comparison module outputs a first comparison voltage signal to the logic control module according to the relationship between the inductor current sampling voltage and the slope voltage in the sampling clock period; the logic control module is configured to output a control signal to the power tube according to the clock control signal, the first comparison voltage signal and the maximum conduction time control signal; the maximum conduction time generation module determines whether to generate the maximum conduction time control signal according to the relationship between the time corresponding to the first comparison voltage signal becoming high in the sampling clock period and the time corresponding to the sampling voltage being greater than the first reference voltage; and the counting module outputs an enable signal to the BUCK circuit when the maximum conduction time control signal is received in a continuous target number of sampling clock periods. By collecting the maximum conduction time control signal generated by the maximum conduction time generation module in each BUCK circuit of the power supply circuit, and by the counting module counting the number of maximum conduction time control signals received in a plurality of continuous clock periods, when the counting module receives the maximum conduction time control signal in a continuous target number of sampling clock periods, the counting module outputs an enable signal to the BUCK circuit to turn off the BUCK circuit, that is, without additionally configuring an additional pin on the power supply circuit, the timing control is used to turn off the BUCK circuit that does not work in the power supply circuit, and it is not necessary to increase the MCU and the register and other additional modules to turn off the BUCK circuit that does not work. By collecting the number of maximum conduction time control signals of the BUCK circuit, the BUCK circuit that does not work can be turned off, and the design complexity and circuit area of the power supply circuit are reduced.

[0026] The above description is only a summary of the technical solutions of the embodiments of the present application. In order to more clearly understand the technical means of the embodiments of the present application, the embodiments of the present application can be implemented according to the content of the specification, and in order to make the above and other purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but not limit the present disclosure, wherein:

[0028] Figure 1 is a structural schematic diagram of a power supply circuit provided by the embodiments of the present disclosure;

[0029] Figure 2 is a structural schematic diagram of a BUCK self-turn-off circuit provided by the embodiments of the present disclosure;

[0030] Figure 3 is another structure schematic diagram of a BUCK self-turn-off circuit provided by an embodiment of the present disclosure;

[0031] Figure 4 is another structure schematic diagram of a BUCK self-turn-off circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person skilled in the art without any inventive effort are also within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together will mean that the parts are joined together either directly or through one or more intermediate parts.

[0034] In all embodiments of the present disclosure, terms such as "first" and "second" are only used to distinguish one component (or part of a component) from another component (or another part of a component).

[0035] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular form "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Accordingly, the use of "a," "an," or "the" will generally include a plurality of the referenced items. Similarly, the words "comprise," "comprises," and "comprising" are to be interpreted inclusively rather than exclusively. Likewise, the terms "include," "including," and "or" should be construed as inclusive rather than exclusive. Where the context requires, use of the term "example" herein, particularly when followed by a listing of terms, is merely exemplary and illustrative and should not be deemed exclusive or extensive.

[0036] Based on the problems existing in the prior art, the embodiments of the present disclosure provide a BUCK self-turn-off circuit, Figure 1 is a structure schematic diagram of a power supply circuit provided by an embodiment of the present disclosure, Figure 2is a structural schematic diagram of a BUCK self-off circuit provided by the embodiment of the present disclosure, combined with Figure 1 and Figure 2 The power supply circuit includes a plurality of BUCK circuits, and any one of the BUCK circuits includes an inductor current sampling module 10, a comparison module 20, a logic control module 30, a maximum conduction time generation module 40, and a counting module 50. The inductor current sampling module 10 in the BUCK circuit is configured to obtain a sampling current in a sampling clock period and determine an inductor current sampling voltage according to the sampling current. The comparison module 20 is configured to output a first comparison voltage signal to the logic control module 30 according to the relationship between the inductor current sampling voltage and the slope voltage in the sampling clock period. The logic control module 30 is configured to output a control signal to the power tube according to the clock control signal, the first comparison voltage signal, and the maximum conduction time control signal. The maximum conduction time generation module 40 is configured to determine whether to generate the maximum conduction time control signal according to the relationship between the time corresponding to the first comparison voltage signal becoming high level and the time corresponding to the sampling voltage being greater than the first reference voltage in the sampling clock period. The counting module 50 is configured to output an enable signal to the BUCK circuit when the maximum conduction time control signal is received in a continuous target number of sampling clock periods.

[0037] It should be noted that, Figure 1 The example shows that the power supply circuit includes three BUCK circuits, and the output channels of the BUCK circuits are connected to the load through output inductors. In other implementable manners, the number of BUCK circuits in the power supply circuit is not specifically limited by the embodiment of the present disclosure.

[0038] In a specific implementation, when the power supply circuit includes a plurality of BUCK circuits, one or more of the BUCK circuits may be in an inactive state. To reduce the overall power consumption of the power supply circuit, it is necessary to turn off the BUCK circuits in the power supply circuit that are in the inactive state. However, the existing method for turning off the inactive BUCK circuits in the power supply circuit needs to increase additional modules to realize the shutdown of the inactive BUCK circuits, which makes the chip design complex. Based on the problems in the prior art, the embodiment of the present disclosure provides a BUCK self-off circuit in a power supply circuit, which can realize the shutdown of the inactive BUCK circuits in the power supply circuit without increasing additional pins or functional modules in the power supply circuit.

[0039] The following embodiments will be specifically illustrated by the implementation logic of a BUCK self-off circuit in a power supply circuit.

[0040] In a specific embodiment, the inductor current sampling module 10 collects the sampling current of the switch node in each sampling clock cycle, and generates the inductor current sampling voltage according to the sampling current. Specifically, when the clock control signal changes from low level to high level, the BUCK circuit controls the lower power tube to be off and the upper power tube to be on, at this time, the sampling current collected by the inductor current sampling module gradually increases.

[0041] Specifically, the comparison module 20 compares the relationship between the inductor current sampling voltage and the slope voltage, and outputs the first comparison voltage signal to the logic control module 30. For example, in one sampling clock cycle, when the clock control signal changes from low level to high level, the logic control module 30 outputs the first control signal to control the lower power tube to be off and the upper power tube to be on. When the BUCK circuit is in a normal working state (i.e. the BUCK circuit in the power supply circuit is connected to the output inductor through the BUCK channel), as the upper power tube is turned on, the inductor current sampling voltage gradually increases, and when the inductor current sampling voltage gradually increases to be greater than the slope voltage, the first comparison voltage signal output by the comparison module 20 changes from low level to high level, at this time, the logic control module 30 outputs the second control signal to control the upper power tube to be off and the lower power tube to be on according to the first comparison voltage signal. When the BUCK circuit is in an abnormal working state (i.e. the BUCK circuit in the power supply circuit is not connected to the output inductor through the BUCK channel), at this time, the inductor current sampling voltage is 0, and the inductor current sampling voltage is always less than the slope voltage, the first comparison voltage signal output by the comparison module 20 always remains low level, at this time, the maximum on-time generation module 40 determines whether to generate the maximum on-time control signal according to the first comparison voltage signal received by the logic control module 30.

[0042] Specifically, the maximum on-time generation module 40 determines whether to generate the maximum on-time control signal according to the relationship between the time corresponding to the first comparison voltage signal becoming high level in the sampling clock cycle and the time corresponding to the sampling voltage being greater than the first reference voltage. For example, at the rising edge of a sampling clock cycle, the logic control module 30 outputs the first control signal to control the lower power tube to be off and the upper power tube to be on. The inductor current sampling module collects the sampling current, which gradually increases. The inductor current sampling voltage also gradually increases. As the inductor current sampling voltage gradually increases to be greater than the slope voltage, the first comparison voltage signal output by the comparison module changes from low level to high level. At this time, the logic control module 30 outputs the second control signal to control the upper power tube to be off and the lower power tube to be on. Until the rising edge of the next sampling clock cycle arrives, the first control signal is output again by the logic control module 30 to control the lower power tube to be off and the upper power tube to be on, and the cycle is repeated. When the BUCK circuit is in a normal working state (i.e., the BUCK circuit in the power supply circuit is connected to the output inductor through the BUCK channel), the time corresponding to the first comparison voltage signal output by the comparison module 20 changing from low level to high level will be before the time corresponding to the sampling voltage being greater than the first reference voltage. However, when one of the BUCK circuits in the power supply circuit is not connected to the output inductor, the inductor current sampling module 10 does not collect the sampling current, and the inductor current sampling voltage is 0. The inductor current sampling voltage will always be less than the slope voltage, and the first comparison voltage signal output by the comparison module 20 will always be low level. The time corresponding to the sampling voltage being greater than the first reference voltage will be before the time corresponding to the first comparison voltage signal changing to high level. At this time, the maximum on-time generation module 40 generates the maximum on-time control signal and outputs the maximum on-time control signal to the counting module 50 and the logic control module 30. The counting module 50 calculates the number of continuous maximum on-time control signals to determine the state of the BUCK circuit, and the logic control module 30 outputs the second control signal to control the upper power tube to be off and the lower power tube to be on.

[0043] Specifically, the counting module 50 outputs the enable signal to the BUCK circuit when the maximum on-time control signal is received in the continuous target number of sampling clock cycles. When the maximum on-time control signal is received in the continuous target number of sampling clock cycles, the counting module outputs the enable signal to the BUCK circuit to which the counting module belongs. After receiving the enable signal, the BUCK circuit to which the counting module belongs is turned off, i.e., the BUCK circuit to which the counting module belongs does not work, thereby reducing the overall power consumption of the power supply circuit.

[0044] The BUCK self-turn-off circuit provided by the embodiments of the present disclosure includes an inductor current sampling module, a comparison module, a logic control module, and a maximum conduction time generation module. The inductor current sampling module is configured to obtain a sampling current in a sampling clock period and determine an inductor current sampling voltage in the clock period according to the sampling current. The comparison module is configured to output a first comparison voltage signal to the logic control module according to a relationship between the inductor current sampling voltage and a slope voltage in the sampling clock period. The logic control module is configured to output a control signal to a power tube according to a clock control signal, the first comparison voltage signal, and a maximum conduction time control signal. The maximum conduction time generation module is configured to determine whether to generate the maximum conduction time control signal according to a relationship between a time corresponding to a time when the first comparison voltage signal becomes high and a time corresponding to a time when the sampling voltage is greater than a first reference voltage. The counting module is configured to output an enable signal to the BUCK circuit when the maximum conduction time control signal is received in a continuous target number of sampling clock periods. The maximum conduction time control signal generated by the maximum conduction time generation module is collected in each BUCK circuit of the power supply circuit, and the number of times when the maximum conduction time control signal is received in a plurality of continuous clock periods is counted by the counting module. When the maximum conduction time control signal is received in a continuous target number of sampling clock periods by the counting module, the counting module outputs the enable signal to the BUCK circuit, so that the BUCK circuit is turned off. That is, an additional pin does not need to be additionally configured on the power supply circuit, and the BUCK circuit that is not in operation is turned off by timing control. No additional modules such as MCUs and registers are needed to turn off the BUCK circuit that is not in operation. The number of times when the maximum conduction time control signal appears in the BUCK circuit is collected, so that the BUCK circuit that is not in operation is turned off, and the design complexity and circuit area of the power supply circuit are reduced.

[0045] In specific embodiments, Figure 3 is a specific structure diagram of a self-turn-off circuit provided by the embodiments of the present disclosure, as Figure 3 shown, the comparison module 20 includes a first comparison unit and a second comparison unit. The first comparison unit is configured to output a second comparison voltage signal to the second comparison unit according to a feedback voltage and a second reference voltage. The second comparison unit is configured to output a first comparison voltage signal to the maximum conduction time generation module according to the second comparison voltage signal, an inductor current sampling voltage, and a slope voltage.

[0046] The first comparison unit includes a first comparator COM1, and the second comparison unit includes a second comparator. The positive input terminal of the first comparator COM1 receives the feedback voltage VFB, the inverting input terminal of the first comparator COM1 receives the second reference voltage VREF1, the output terminal of the first comparator COM1 outputs the second comparison voltage signal VC2 to the inverting input terminal of the second comparator COM1, the positive input terminal of the second comparator COM2 receives the inductor current sampling voltage VCS and the sawtooth wave voltage VS respectively, and the output terminal of the second comparator COM2 outputs the first comparison voltage signal OFF_HS.

[0047] Combine Figure 3 The first comparison unit compares the feedback voltage VFB with the first reference voltage VREF1. Specifically, the positive input terminal of the first comparator COM1 receives the feedback voltage VFB, and the negative input terminal of the first comparator COM1 receives the first reference voltage VREF1. When the feedback voltage VFB is greater than the first reference voltage VREF1, the second comparison voltage signal VC2 output by the first comparison unit (i.e., the first comparator) is high level. When the feedback voltage VFB is less than the first reference voltage VREF1, the second comparison voltage signal VC2 output by the first comparison unit (i.e., the first comparator) is low level. The positive input terminal of the second comparator COM2 receives the inductor current sampling voltage VCS and the sawtooth wave voltage VS, and the negative input terminal of the second comparator COM2 receives the second comparison voltage VCS. The second comparing unit (i.e., the second comparator) first generates a ramp voltage VRAMP (VRAMP=VC2-VS) based on the second comparison voltage signal VC2 and the sawtooth wave voltage VS. Then, the second comparing unit (i.e., the second comparator) compares the inductor current sampling voltage VCS with the ramp voltage VRAMP and outputs a first comparison voltage signal OFF_HS. When the inductor current sampling voltage VCS is less than the ramp voltage VRAMP, the first comparison voltage signal OFF_HS output by the second comparing unit (i.e., the second comparator) is at a low level. When the inductor current sampling voltage VCS is greater than the ramp voltage VRAMP, the first comparison voltage signal OFF_HS output by the second comparing unit (i.e., the second comparator) is at a high level.

[0048] Based on the above embodiments, Figure 3 and Figure 4The logic control module 30 comprises a logic control unit 31 and a master control unit 32. The logic control unit 31 is configured to output a logic control signal ON1 according to a clock control signal CLK, a feedback voltage HS_OFF and a maximum on-time control signal Max_on. The master control unit 32 is configured to control the on and off of the power tube according to a first comparison voltage signal OFF_HS and the logic control signal ON1, and generate the feedback voltage HS_OFF to the logic control unit 31 according to the collected on-off state of the power tube.

[0049] The logic control unit 31 comprises a first inverter F1, a second inverter F2, a third inverter F3, a first NAND gate NAND1 and a second NAND gate NAND2. The input end of the first inverter F1 receives the clock control signal CLK. The output end of the first inverter F1 is electrically connected with the first input end of the first NAND gate NAND1. The second input end of the first NAND gate NAND1 is electrically connected with the output end of the second NAND gate NAND2. The output end of the first NAND gate NAND1 is electrically connected with the first input end of the second NAND gate NAND2 and outputs the logic control signal ON1. The input end of the second inverter F2 receives the feedback voltage HS_OFF. The output end of the second inverter F2 is electrically connected with the second input end of the second NAND gate NAND2. The input end of the third inverter F3 receives the maximum on-time control signal Max_on. The output end of the third inverter F3 is electrically connected with the third input end of the second NAND gate NAND2.

[0050] The maximum on-time generation module comprises a fourth inverter F4, a transistor NM, a current source Ibias, a capacitor C and a third comparator COM3. The input end of the fourth inverter F4 receives the logic control signal ON1. The output end of the fourth inverter F4 is electrically connected with the control end of the transistor NM. The first end of the current source Ibias receives a power voltage signal. The second end of the current source Ibias, the first end of the capacitor C and the first end of the transistor NM are respectively electrically connected with the positive input end of the third comparator COM3. The second end of the capacitor C and the second end of the transistor NM are electrically connected with a ground node. The reverse input end of the third comparator COM3 receives a second reference voltage VREF2. The output end of the third comparator COM3 outputs the maximum on-time control signal Max_on.

[0051] The transistor NM is an NMOS tube.

[0052] Specifically, in combination with Figure 3 and Figure 4, in a sampling clock cycle, the clock control signal changes from low to high, at this time, the first inverter F1 receives the clock control signal CLK, the first inverter F1 outputs low to the first NAND gate NAND1, the logic control signal ON1 output by the first NAND gate NAND1 is high, at this time, the master control unit 32 receives the high level output by the first NAND gate NAND1, and the master control unit 32 outputs the first control signal to control the lower power tube S2 to be turned off, the upper power tube S1 to be turned on, and the fourth inverter F4 receives the high level output by the first NAND gate NAND1, and the fourth inverter F4 outputs low to the transistor NM, which is turned off, at this time, the current source Ibias charges the capacitor C. When the BUCK circuit is in a normal working state, the time corresponding to the change of the first comparison voltage signal OFF_HS output by the comparison module 20 from low to high will be before the time corresponding to the sampling voltage being greater than the first reference voltage, that is, before the current source Ibias charges the capacitor C so that the first end voltage of the capacitor C (that is, the sampling voltage VA) is greater than the second reference voltage VREF2, due to the fact that the upper power tube S1 is turned on, the sampling current increases, and then the inductor current sampling voltage VCS increases, when the inductor current sampling voltage VCS increases to be greater than the slope voltage, the first comparison voltage signal OFF_HS output by the comparison module 20 is high, at this time, after the master control unit 32 receives the high level first comparison voltage signal OFF_HS output by the comparison module 20, the master control unit 32 outputs the second control signal to control the upper power tube S1 to be turned off, and the master control unit 32 generates the feedback voltage HS_OFF (high level) to the second inverter F2 of the logic control unit 31, the second inverter F2 outputs low, the second NAND gate NAND2 outputs high to the second input end of the first NAND gate NAND1, at this time, the first NAND gate NAND1 outputs low (that is, the logic control signal ON1 output by the first NAND gate NAND1 is low), at this time, the master control unit receives the low level output by the first NAND gate NAND1, and the master control unit outputs the second control signal to control the lower power tube S2 to be turned on according to the received low level output by the first NAND gate NAND1, and the fourth inverter F4 receives the low level output by the first NAND gate NAND1, the fourth inverter F4 outputs high to the transistor NM, which is turned on, at this time, the capacitor C is discharged, therefore, the sampling voltage VA received by the positive input end of the third comparator COM3 is less than the second reference voltage VREF2, and the third comparator COM3 will not output the maximum on time control signal Max_on to the logic control unit.When the BUCK circuit is in an abnormal working state, the time corresponding to the first comparison voltage signal output by the comparison module 20 changing from a low level to a high level will be after the time corresponding to the sampling voltage being greater than the first reference voltage. Specifically, since the BUCK circuit is in an abnormal working state (the output inductor is not connected), the sampling current is 0. At this time, the inductor current sampling voltage VCS is 0. The inductor current sampling voltage VCS will always be less than the ramp voltage. The first comparison voltage signal OFF_HS output by the comparison module 20 to the main control unit 32 is low, and the main control unit generates a feedback voltage HS_OFF (low level) to the second inverter F2 of the logic control unit. Since the feedback voltage HS_OFF output by the main control unit to the logic control unit is always low, the first NAND gate NAND1 outputs At a high level (i.e., the logic control signal ON1 output by the first NAND gate NAND1 is also always high), the fourth inverter F4 receives the high level output by the first NAND gate NAND1, and outputs a low level to the transistor NM. The transistor NM is turned off, and the current source Ibias charges the capacitor C. Since the inductor current sampling voltage is always lower than the ramp voltage, the second inverter F2 does not receive a high-level feedback voltage. Therefore, the first NAND gate does not output a low level, and the fourth inverter does not output a high level. As a result, the transistor does not turn on, allowing the capacitor to discharge. Therefore, the current source charges the capacitor so that the voltage at the first terminal of the capacitor (i.e., the sampling voltage) is greater than the first reference voltage. The third comparator COM3 outputs the maximum on-time control signal Max_on to the counting module. In addition, the third comparator COM3 also outputs a maximum on-time control signal to the input end of the third inverter F3 of the logic control unit. After receiving the maximum on-time control signal output by the third comparator COM3, the third inverter F3 outputs a low level to the second NAND gate NAND2. The second NAND gate NAND2 outputs a high level to the first NAND gate NAND1. The first NAND gate NAND1 outputs a low level (that is, the logic control signal ON1 output by the first NAND gate NAND1 is a low level). At this time, the main control unit receives the low level output by the first NAND gate, and the main control unit outputs a second control signal to control the upper power tube S1 to turn off and the lower power tube S2 to turn on.

[0053] In a specific embodiment, the counting module includes a counter, which receives the maximum on-time control signal and the clock control signal, and outputs an enable signal to the BUCK circuit when the number of the maximum on-time control signals meets the target number.

[0054] In a specific embodiment, the counter receives the maximum on-time control signal in one clock control signal, the counter records 1, the counter does not receive the maximum on-time control signal in one clock control signal, the counter records 0, and when the counter is 1 in a continuous target number of sampling clock periods, the counting module outputs an enable signal to the BUCK circuit to control the BUCK circuit to turn off.

[0055] It should be noted that the target number of the counter is not specifically limited in the embodiments of the present disclosure. For example, the target number can be 100 or 200, which is related to the BUCK circuit.

[0056] Based on the above-mentioned embodiments, as shown in Figure 3 The BUCK self-turn-off circuit further includes a control module 50 configured to control the on and off of the power tubes according to the control signal.

[0057] Specifically, when the control signal generated by the control unit in the maximum on-time generation module of the above-mentioned embodiments is high, the control module controls the lower power tube to turn off and the upper power tube to turn on. When the control signal generated by the control unit in the maximum on-time generation module of the above-mentioned embodiments is low, the control module controls the upper power tube to turn off and the lower power tube to turn on.

[0058] Based on the above-mentioned embodiments, the embodiments of the present disclosure further provide a power supply circuit including a plurality of BUCK self-turn-off circuits according to any one of the above-mentioned embodiments, which has the beneficial effects of any one of the above-mentioned embodiments. The embodiments of the present disclosure do not illustrate them one by one.

[0059] In a specific embodiment, when the output channel of any one of the BUCK self-turn-off circuits included in the power supply circuit is virtually soldered, that is, the OUT PIN of any one of the BUCK self-turn-off circuits is disconnected between the output capacitor and the output inductor, at this time, the BUCK self-turn-off circuit connected with the output channel will be self-turned off.

[0060] Based on the above-mentioned embodiments, the embodiments of the present disclosure further provide an electronic device including a power supply circuit according to any one of the above-mentioned embodiments, which has the beneficial effects of any one of the above-mentioned embodiments. The embodiments of the present disclosure do not illustrate them one by one.

[0061] The electronic device provided by the embodiments of the present disclosure can be applied to a flexible electronic device to implement technologies such as Augmented Reality (AR), Virtual Reality (VR), Extended Reality (XR), Mixed Reality (MR), and the like. For example, the display device can be a projection part of the electronic device, such as a projector, a Head Up Display (HUD), and the like; for another example, the display device can also be a display part of the electronic device, for example, the electronic device can include any device with a display screen, such as a smart phone, a smart watch, a notebook computer, a tablet computer, a driving recorder, a navigator, a head-mounted device, and the like.

[0062] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, devices, components and / or combinations thereof, but do not preclude the presence or addition of one or more other features, steps, operations, devices, components and / or combinations thereof.

[0063] It should be understood that all technological and scientific terms used herein that have acronyms also include full terms comprising same. For example, the term "CPU" includes Central Processing Unit. It should be understood that the term "one embodiment" or "an embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of steps / processes in various embodiments of the present application does not mean the order of execution, and the execution order of the steps / processes should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. Moreover, the sequence number of the above-mentioned embodiments of the present application is only for description, and does not represent the advantages and disadvantages of the embodiments.

[0064] It should be noted that the terms "first", "second", and the like, used in the description and the claims of the present application as well as above-mentioned figures are intended to distinguish similar objects and not to imply a specific order or chronology of events. It is to be understood that the data thus described can be interchanged, where appropriate, so that the embodiments of the present application described herein could be carried out in a different order than the one illustrated or described herein. Furthermore, the terms "comprising", "having", and any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product, or apparatus that comprises a list of steps or units can not necessarily be limited to those steps or units that are clearly listed, but can include other steps or units that are not expressly listed or inherent to such process, method, product, or apparatus.

[0065] The preferred embodiments of the present application are described above in detail. The present application, however, is not limited to the precise embodiments described, and variations and modifications exist which would be apparent to one skilled in the art. It is intended to cover in the claims all such modifications and equivalents.

Claims

1. A buck self-shutdown circuit, characterized in that: include: Inductor current sampling module, comparison module, logic control module, maximum on-time generation module and counting module; The inductor current sampling module is configured to obtain the inductor current within a sampling clock period and determine the inductor current sampling voltage according to the inductor current; The comparison module is configured to output a first comparison voltage signal to the logic control module according to the relationship between the inductor current sampling voltage and the ramp voltage within the sampling clock period; The logic control module is configured to output a control signal to the power tube according to the clock control signal, the first comparison voltage signal and the maximum on-time control signal; The maximum on-time generating module is configured to determine whether to generate a maximum on-time control signal based on a relationship between a time corresponding to when the first comparison voltage signal becomes high and a time corresponding to when the sampling voltage is greater than a second reference voltage within the sampling clock period; The counting module is configured to output an enable signal to the BUCK circuit when the maximum on-time control signal is received in a target number of consecutive sampling clock cycles; In which, the maximum on-time generation module includes a fourth inverter, a transistor, a current source, a capacitor and a third comparator, the input end of the fourth inverter receives a logic control signal, the output end of the fourth inverter is electrically connected to the control end of the transistor, the first end of the current source receives a power supply voltage signal, the second end of the current source, the first end of the capacitor and the first end of the transistor are respectively electrically connected to the positive input end of the third comparator, the second end of the capacitor and the second end of the transistor are electrically connected to the ground node, the inverting input end of the third comparator receives a second reference voltage, and the output end of the third comparator outputs a maximum on-time control signal.

2. The circuit according to claim 1, characterized in that The comparison module includes a first comparison unit and a second comparison unit; The first comparing unit is configured to output a second comparison voltage signal to the second comparing unit according to the feedback voltage and the first reference voltage; The second comparison unit is configured to output a first comparison voltage signal to the maximum on-time generation module according to the second comparison voltage signal, the inductor current sampling voltage, and the sawtooth wave voltage.

3. The circuit according to claim 2, characterized in that The first comparison unit includes a first comparator, and the second comparison unit includes a second comparator. The positive input terminal of the first comparator receives a feedback voltage, the inverting input terminal of the first comparator receives a first reference voltage, the output terminal of the first comparator outputs a second comparison voltage signal to the inverting input terminal of the second comparator, the positive input terminal of the second comparator receives the inductor current sampling voltage and the sawtooth wave voltage respectively, and the output terminal of the second comparator outputs the first comparison voltage signal.

4. The circuit according to claim 1, wherein: The logic control module includes a logic control unit and a main control unit; The logic control unit is configured to output a logic control signal according to the clock control signal, the feedback voltage and the maximum on-time control signal; The main control unit is configured to control the on and off of the power tube according to the first comparison voltage signal and the logic control signal, and generate a feedback voltage to the logic control unit according to the collected on and off states of the power tube.

5. The circuit according to claim 4, characterized in that The logic control unit includes a first inverter, a second inverter, a third inverter, a first NAND gate, and a second NAND gate. The input end of the first inverter receives a clock control signal, the output end of the first inverter is electrically connected to the first input end of the first NAND gate, the second input end of the first NAND gate is electrically connected to the output end of the second NAND gate, the output end of the first NAND gate is electrically connected to the first input end of the second NAND gate and outputs a control signal, the input end of the second inverter receives the feedback voltage, the output end of the second inverter is electrically connected to the second input end of the second NAND gate, the input end of the third inverter receives a maximum on-time control signal, and the output end of the third inverter is electrically connected to the third input end of the second NAND gate.

6. The circuit according to claim 1, wherein: The transistor is an NMOS transistor.

7. The circuit according to claim 1, wherein: The counting module includes a counter, which receives a maximum on-time control signal and a clock control signal, and outputs an enable signal to the BUCK circuit when the number of maximum on-time control signals meets a target number.

8. A power supply circuit, characterized in that: The invention comprises a plurality of BUCK self-shutdown circuits according to any one of claims 1 to 7.

9. An electronic device, characterized in that: The invention comprises the power supply circuit according to claim 8.

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