Comparator and delay unit-based negative single-particle transient reinforcing circuit and method
By designing a negative single-particle transient reinforcement circuit based on comparator and delay unit in LDO, the problem that LDO is susceptible to negative single-particle transient pulses is solved, and the stability and reliability of the circuit are improved.
Patent Information
- Application Number
- CN202510003662.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-05-06
AI Technical Summary
Existing low dropout linear regulators (LDOs) are susceptible to negative single-particle transient pulses, resulting in reduced circuit stability.
A negative single-particle transient reinforcement circuit based on a comparator and delay unit is designed. Through the cooperation of the comparator and delay unit, the power tube and error amplifier are isolated to reduce the influence of the negative single-particle transient pulse.
It effectively isolates the impact of negative single-particle transient pulses on LDO, improving the stability and reliability of the circuit.
Smart Images
Figure CN119945413A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of negative single particle transient reinforcement circuits, and in particular to a negative single particle transient reinforcement circuit and method based on a comparator and a delay unit. Background Art
[0002] Particle transient effects are caused by the energy transfer of particles to electrons in the medium. When a particle (such as an electron or photon) passes through a medium, it interacts with atoms or molecules in the medium, causing electrons to be excited or stripped from their atomic orbitals. These excited or ionized states exist only for a moment and decay rapidly. In this process, holes are formed, which move in the surrounding medium until they recombine with other electrons. The time scale of this recombination process is shorter than the time scale of the interaction between the electron and the medium, so it can be considered that all electrons recombine simultaneously in a period of time. Single particle transient effects can be used to develop highly sensitive single particle sensors. By combining sensitive media with electronic detectors, when particles pass through the medium and cause transient effects, this signal can be captured by the electronic detector. This single particle sensor can be used in environmental monitoring, life science research and other fields; single particle transient effects can be used to evaluate the reliability of electronic devices. In electronic devices, single particle transient effects may cause misoperation or device damage, so it is very important for the reliability evaluation of electronic devices. Through simulation or experiment, the response of electronic devices under single particle transient effects can be studied, and the resistance of Apple devices to particle radiation can be studied, thereby guiding the design and manufacture of electronic devices.
[0003] LDO refers to low dropout linear regulator, which is mainly used to convert unstable DC voltage into stable DC output voltage. Low dropout linear regulator is a new generation of integrated circuit regulator. The biggest difference between it and the three-terminal regulator is that the low dropout linear regulator is a micro-chip system with very low self-consumption. It can be used for current main channel control. The chip integrates hardware circuits such as mosfet with extremely low online on-resistance, Schottky diode, sampling resistor and voltage divider resistor, and has overcurrent protection, overtemperature protection, precision reference source, differential amplifier, delayer and other functions. Low dropout linear regulator usually has extremely low self-noise and high power supply rejection ratio. The current LDO does not have a reinforcement circuit. When a negative single-particle transient pulse arrives, it is easy to affect the LDO. Therefore, it is necessary to design a negative single-particle transient reinforcement circuit based on a comparator and a delay unit. Summary of the invention
[0004] The present application provides a negative single-particle transient reinforcement circuit and method based on a comparator and a delay unit to solve the problem that the current LDO is easily affected by negative single-particle transient pulses. When a negative single-particle transient pulse arrives, the power tube and the error amplifier are isolated, thereby reducing the effect of the negative single-particle transient pulse and playing a reinforcement role.
[0005] The present application provides a negative single-particle transient reinforcement circuit based on a comparator and a delay unit, wherein the negative single-particle transient reinforcement circuit includes a comparator, a resistor network, a delay unit, a connecting tube, a transistor, a capacitor, a fifth resistor, and a sixth resistor;
[0006] The positive input terminal of the comparator is connected to a reference voltage Vout_min formed by a resistor network, the negative input terminal of the comparator is connected to an output voltage Vout of a transistor source, and the control terminal of the comparator is connected to a control voltage Ven;
[0007] The delay unit includes an inverting delay unit and an AND gate, wherein the input end of the inverting delay unit is connected to the output end of the comparator, the output end of the inverting delay unit is connected to the input end of the AND gate, the negative input end of the comparator is connected to the other input end of the AND gate, and the output end of the AND gate is connected to the gate of the connection tube;
[0008] The source of the connecting tube is connected to the gate of the transistor and one end of the capacitor respectively, the other end of the capacitor is grounded, and the drain of the connecting tube is connected to the output end of the error amplifier;
[0009] The transistor source is connected to one end of a fifth resistor, the other end of the fifth resistor is connected to one end of a sixth resistor, and the other end of the sixth resistor is grounded;
[0010] The error amplifier has a positive input terminal connected to a reference voltage Vref, and a negative input terminal connected to a node between the fifth resistor and the sixth resistor.
[0011] Preferably, the resistor network is formed by a plurality of resistors connected in series, and the plurality of resistors include a seventh resistor, an eighth resistor, and an Nth resistor, where N is an integer greater than 7.
[0012] Preferably, the comparator is composed of a bias circuit, a first-stage differential amplifier circuit, a second-stage differential-to-single-ended output circuit and an output buffer circuit, and the bias circuit is sequentially connected to the first-stage differential amplifier circuit, the second-stage differential-to-single-ended output circuit and the output buffer circuit.
[0013] Preferably, the first-stage differential amplifier circuit includes a second transistor, a first differential input transistor, a second differential input transistor, a first load tube, a second load tube, a first reset tube and a second reset tube. The source of the second transistor is grounded, and the gate is connected to the gate of the eighth transistor in the bias circuit. The drain of the second transistor is respectively connected to the source of the first differential input transistor and the source of the second differential input transistor. The drain of the first differential input transistor is respectively connected to the drain of the first load tube and the drain of the first reset tube; the drain of the second differential input transistor is respectively connected to the drain of the second reset tube and the drain of the second load tube.
[0014] Preferably, the second-stage differential-to-single-ended output circuit comprises a third transistor, a third differential input transistor, a fourth differential input transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a third load transistor, a fourth load transistor, a fifth load transistor, a sixth load transistor, a third reset transistor and a fourth reset transistor, the gate of the third transistor is connected to the gate of the eighth transistor, the source of the third transistor is grounded, and the drain of the third transistor is respectively connected to the source of the third differential input transistor and the source of the fourth differential input transistor;
[0015] The drain of the third differential input transistor is connected to the drain of the fifth load transistor, the drain of the fourth differential input transistor is connected to the drain of the fourth load transistor, the gate of the third differential input transistor is respectively connected to the drain of the third load transistor and the drain of the sixth transistor, the source of the sixth transistor is grounded, and the drain of the sixth transistor is connected to the drain of the fourth transistor;
[0016] The drain of the fourth differential input transistor is respectively connected to the drain of the fourth load transistor and the drain of the fourth reset transistor, the gate of the fourth differential input transistor is respectively connected to the drain of the fourth load transistor and the drain of the seventh transistor, the source of the seventh transistor is grounded, and the drain of the seventh transistor is also connected to the drain of the fifth transistor;
[0017] The gate electrode of the fifth load tube is connected to the gate electrode of the sixth load tube and to the drain electrode of the third reset tube.
[0018] Preferably, the output buffer circuit is formed by three inverters connected in series, and the input end of the inverter is connected to the drain of the fourth differential input transistor.
[0019] Preferably, the bias circuit includes a fifth reset tube, a first transistor and an eighth transistor, a fourth resistor, a first resistor, a second resistor and a third resistor connected in series are connected between the drain of the fifth reset tube and the drain of the eighth transistor, the source of the eighth transistor is grounded, the drain of the first transistor is connected to the drain of the eighth transistor, and the source of the first transistor is grounded.
[0020] Preferably, the reinforcement method of the negative single-particle transient reinforcement circuit based on the comparator and the delay unit comprises the following steps:
[0021] A. Before LDO enters normal working state, the control voltage Ven of the comparator CMP is at a low level. At this time, the comparator CMP does not make comparisons, and the output of the comparator CMP is at a low level.
[0022] B. The output of the inverting delay unit INV is high level, the output of the AND gate AND is low level, and the connecting tube P11 is turned on;
[0023] C. When the LDO enters the normal working state, the control voltage Ven is at a high level, and the comparator CMP starts to compare. Since the LDO output voltage Vout is greater than the reference voltage Vout_min formed by the resistor network during normal working, the output of the comparator CMP is at a low level, the output of the inverting delay unit INV is at a high level, the output of the AND gate AND is at a low level, and the connecting tube P11 remains turned on;
[0024] D. When a negative pulse appears, the LDO output voltage Vout is less than the reference voltage Vout_min formed by the resistor network, and the comparator CMP outputs a high level. Since the inverting delay unit INV has a capacitor, the output of the inverting delay unit is affected by the capacitor and remains at a high level. The output of the AND gate AND is a high level, the connecting tube P11 is disconnected, and the capacitor C1 begins to maintain the gate voltage of the power tube N1, reducing the impact of the negative single-particle transient pulse.
[0025] E. After the capacitor in the inverting delay unit INV is discharged for a period of time, the output of the inverting delay unit INV is low level, the output voltage of the AND gate AND returns to low level, and the connecting tube P11 is turned on.
[0026] Beneficial effect: The negative single particle transient reinforcement circuit of the present invention forms an effect of isolating the power tube and the error amplifier when a negative single particle transient pulse arrives, thereby reducing the influence of the negative single particle transient pulse and playing a reinforcement role.
[0027] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0029] Figure 1 It is the circuit principle diagram of the present invention;
[0030] Figure 2 is a circuit diagram of a comparator of the present invention;
[0031] Figure 3 This is the schematic diagram of the LDO before reinforcement of the present invention;
[0032] Figure 4 Schematic diagram of LDO output results before and after reinforcement. DETAILED DESCRIPTION
[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used in the specification of the application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification, claims and drawings of this application are intended to cover non-exclusive inclusions.
[0035] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0036] In addition, the terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.
[0037] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.
[0038] See also Figure 1-Figure 2 , the present application discloses a negative single particle transient reinforcement circuit based on a comparator and a delay unit, the negative single particle transient reinforcement circuit includes a comparator, a resistor network, a delay unit, a connecting tube P11, a transistor N12, a capacitor C1, a fifth resistor R5 and a sixth resistor R6;
[0039] The positive input terminal of the comparator is connected to the reference voltage Vout_min formed by the resistor network, the negative input terminal of the comparator is connected to the output voltage Vout of the source of the transistor N12, and the control terminal of the comparator is connected to the control voltage Ven;
[0040] The delay unit includes an inverting delay unit INV and an AND gate AND. The input end of the inverting delay unit INV is connected to the output end of the comparator, the output end of the inverting delay unit INV is connected to the input end of the AND gate AND, the negative input end of the comparator is connected to the other input end of the AND gate AND, and the output end of the AND gate AND is connected to the gate of the connecting tube P11;
[0041] The source of the connecting tube P11 is connected to the gate of the transistor N12 and one end of the capacitor C1 respectively, the other end of the capacitor C1 is grounded, and the drain of the connecting tube P11 is connected to the output end of the error amplifier EA;
[0042] The source of the transistor N12 is connected to one end of a fifth resistor R5, the other end of the fifth resistor R5 is connected to one end of a sixth resistor R6, and the other end of the sixth resistor R6 is grounded;
[0043] The positive input terminal of the error amplifier EA is connected to the reference voltage Vref, and the negative input terminal is connected to the node between the fifth resistor R5 and the sixth resistor R6; the resistor network is composed of multiple resistors connected in series, and the multiple resistors include the seventh resistor R7, the eighth resistor R8, and the Nth resistor RN, where N is an integer greater than 7.
[0044] Among them, the inverting delay unit INV and the AND gate AND form a delay circuit. A reference voltage Vout_min is formed by a resistor network, which serves as the lower limit of the acceptable voltage variation. The positive input of the comparator CMP is connected to the reference voltage Vout_min formed by the resistor network, the negative input is the output voltage Vout of the LDO, and the control end is connected to the control voltage Ven. When the LDO enters the normal working state, the control voltage Ven enables the comparator CMP, and the comparator CMP starts to compare. The output of the comparator is connected to the input of the inverting delay unit INV and the input of the AND gate AND. The output of the inverting delay unit INV is connected to the other input of the AND gate. The output of the AND gate AND is connected to the gate of the connecting tube P11. The connecting tube P11 plays an isolation role, and controls the output of the error amplifier EA and the gate of the power tube N12 according to the output of the comparator CMP. The capacitor C1 is responsible for maintaining the stability of the gate voltage of the power tube N12 when the connecting tube P11 is disconnected, and also has a filtering effect.
[0045] In the present invention, the comparator is composed of a bias circuit, a first-stage differential amplifier circuit, a second-stage differential-to-single-ended output circuit and an output buffer circuit, and the bias circuit is sequentially connected to the first-stage differential amplifier circuit, the second-stage differential-to-single-ended output circuit and the output buffer circuit.
[0046] The first-stage differential amplifier circuit includes a second transistor N2, a first differential input transistor N3, a second differential input transistor N4, a first load tube P1, a second load tube P4, a first reset tube P2 and a second reset tube P3. The source of the second transistor N2 is grounded, and the gate is connected to the gate of the eighth transistor N0 in the bias circuit. The drain of the second transistor N2 is respectively connected to the source of the first differential input transistor N3 and the source of the second differential input transistor N4. The drain of the first differential input transistor N3 is respectively connected to the drain of the first load tube P1 and the drain of the first reset tube P2. The drain of the second differential input transistor N4 is respectively connected to the drain of the second reset tube P3. The drain of the second load transistor P4; the second-stage differential-to-single-ended output circuit includes a third transistor N5, a third differential input transistor N6, a fourth differential input transistor N7, a fourth transistor P5, a fifth transistor P6, a sixth transistor N8, a seventh transistor N11, a third load transistor N9, a fourth load transistor N10, a fifth load transistor P8, a sixth load transistor P10, a third reset transistor P7 and a fourth reset transistor P9, the gate of the third transistor N5 is connected to the gate of the eighth transistor N0, the source of the third transistor N5 is grounded, and the drain of the third transistor N5 is respectively connected to the source of the third differential input transistor N6 and the source of the fourth differential input transistor N7;
[0047] The drain of the third differential input transistor N6 is connected to the drain of the fifth load transistor P8, the drain of the fourth differential input transistor N7 is connected to the drain of the fourth load transistor N10, the gate of the third differential input transistor N6 is respectively connected to the drain of the third load transistor N9 and the drain of the sixth transistor N8, the source of the sixth transistor N8 is grounded, and the drain of the sixth transistor N8 is connected to the drain of the fourth transistor P5;
[0048] The drain of the fourth differential input transistor N7 is respectively connected to the drain of the fourth load transistor N10 and the drain of the fourth reset transistor P9, the gate of the fourth differential input transistor N7 is respectively connected to the drain of the fourth load transistor N10 and the drain of the seventh transistor N11, the source of the seventh transistor N11 is grounded, and the drain of the seventh transistor N11 is also connected to the drain of the fifth transistor P6;
[0049] The gate of the fifth load tube P8 is connected to the gate of the sixth load tube P10 and to the drain of the third reset tube P7.
[0050] The output buffer circuit is formed by three inverters connected in series, and the input end of the inverter is connected to the drain of the fourth differential input transistor N7.
[0051] The bias circuit includes a fifth reset tube P0, a first transistor N1 and an eighth transistor N0. A fourth resistor R0, a first resistor R1, a second resistor R2 and a third resistor R3 connected in series are connected between the drain of the fifth reset tube P0 and the drain of the eighth transistor N0. The source of the eighth transistor N0 is grounded, the drain of the first transistor N1 is connected to the drain of the eighth transistor N0, and the source of the first transistor N1 is grounded.
[0052] When the control terminal voltage Vcmp_en is at a high level, the comparator enters a normal working state. The second transistor N2 copies the current on the bias circuit. At this time, the differential amplifier receives two input voltages Vin_m and Vin_p. The end with a higher voltage gets more current, so the voltage Vom1 or Vop1 on its drain is smaller. These two voltages control the conduction state of the fourth transistor P5 and the fifth transistor P6. The end with a smaller voltage in Vom1 and Vop1 produces a larger current, which pulls up Vop2 or Vom2. At the same time, since the sixth transistor N8 and the seventh transistor N11 form a positive feedback, the voltage difference between Vop2 and Vom2 is amplified as a differential input for differential to single-ended conversion. The fifth load tube P8 and the sixth load tube P10 convert the differential signal into a single-ended signal as an output.
[0053] Working principle: The reinforcement method of the negative single-particle transient reinforcement circuit based on the comparator and the delay unit includes the following steps:
[0054] A. Before LDO enters normal working state, the control voltage Ven of the comparator CMP is at a low level. At this time, the comparator CMP does not make comparisons, and the output of the comparator CMP is at a low level.
[0055] B. The output of the inverting delay unit INV is high level, the output of the AND gate AND is low level, and the connecting tube P11 is turned on;
[0056] C. When the LDO enters the normal working state, the control voltage Ven is at a high level, and the comparator CMP starts to compare. Since the LDO output voltage Vout is greater than the reference voltage Vout_min formed by the resistor network during normal working, the output of the comparator CMP is at a low level, the output of the inverting delay unit INV is at a high level, the output of the AND gate AND is at a low level, and the connecting tube P11 remains turned on;
[0057] D. When a negative pulse appears, the LDO output voltage Vout is less than the reference voltage Vout_min formed by the resistor network, and the comparator CMP outputs a high level. Since the inverting delay unit INV has a capacitor, the output of the inverting delay unit is affected by the capacitor and remains at a high level. The output of the AND gate AND is a high level, the connecting tube P11 is disconnected, and the capacitor C1 begins to maintain the gate voltage of the power tube N1, reducing the impact of the negative single-particle transient pulse.
[0058] E. After the capacitor in the inverting delay unit INV is discharged for a period of time, the output of the inverting delay unit INV is low level, the output voltage of the AND gate AND returns to low level, and the connecting tube P11 is turned on.
[0059] In summary, the negative single particle transient reinforcement circuit of the present invention forms an effect of isolating the power tube and the error amplifier when a negative single particle transient pulse arrives, thereby reducing the influence of the negative single particle transient pulse and playing a reinforcement role.
[0060] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A negative single-event transient reinforcement circuit based on a comparator and a delay unit, characterized in that: The negative single-particle transient reinforcement circuit includes a comparator, a resistor network, a delay unit, a connecting tube P11, a transistor N12, a capacitor C1, a fifth resistor R5 and a sixth resistor R6; The positive input terminal of the comparator is connected to the reference voltage Vout_min formed by the resistor network, the negative input terminal of the comparator is connected to the output voltage Vout of the source of the transistor N12, and the control terminal of the comparator is connected to the control voltage Ven; The delay unit includes an inverting delay unit INV and an AND gate AND. The input end of the inverting delay unit INV is connected to the output end of the comparator, the output end of the inverting delay unit INV is connected to the input end of the AND gate AND, the negative input end of the comparator is connected to the other input end of the AND gate AND, and the output end of the AND gate AND is connected to the gate of the connecting tube P11; The source of the connecting tube P11 is connected to the gate of the transistor N12 and one end of the capacitor C1 respectively, the other end of the capacitor C1 is grounded, and the drain of the connecting tube P11 is connected to the output end of the error amplifier EA; The source of the transistor N12 is connected to one end of a fifth resistor R5, the other end of the fifth resistor R5 is connected to one end of a sixth resistor R6, and the other end of the sixth resistor R6 is grounded; The error amplifier EA has a positive input terminal connected to a reference voltage Vref, and a negative input terminal connected to a node between the fifth resistor R5 and the sixth resistor R6.
2. The negative single event transient reinforcement circuit based on a comparator and a delay unit according to claim 1, characterized in that: The resistor network is formed by a plurality of resistors connected in series, and the plurality of resistors include a seventh resistor R7, an eighth resistor R8, and an Nth resistor RN, where N is an integer greater than 7.
3. The negative single event transient reinforcement circuit based on a comparator and a delay unit according to claim 1, characterized in that: The comparator is composed of a bias circuit, a first-stage differential amplifier circuit, a second-stage differential-to-single-ended output circuit and an output buffer circuit. The bias circuit is sequentially connected to the first-stage differential amplifier circuit, the second-stage differential-to-single-ended output circuit and the output buffer circuit.
4. The negative single event transient reinforcement circuit based on a comparator and a delay unit according to claim 3, characterized in that: The first-stage differential amplifier circuit includes a second transistor N2, a first differential input transistor N3, a second differential input transistor N4, a first load tube P1, a second load tube P4, a first reset tube P2 and a second reset tube P3. The source of the second transistor N2 is grounded, and the gate is connected to the gate of the eighth transistor N0 in the bias circuit. The drain of the second transistor N2 is respectively connected to the source of the first differential input transistor N3 and the source of the second differential input transistor N4. The drain of the first differential input transistor N3 is respectively connected to the drain of the first load tube P1 and the drain of the first reset tube P2; the drain of the second differential input transistor N4 is respectively connected to the drain of the second reset tube P3 and the drain of the second load tube P4.
5. The negative single event transient reinforcement circuit based on a comparator and a delay unit according to claim 4, characterized in that: The second-stage differential-to-single-ended output circuit includes a third transistor N5, a third differential input transistor N6, a fourth differential input transistor N7, a fourth transistor P5, a fifth transistor P6, a sixth transistor N8, a seventh transistor N11, a third load transistor N9, a fourth load transistor N10, a fifth load transistor P8, a sixth load transistor P10, a third reset transistor P7 and a fourth reset transistor P9, the gate of the third transistor N5 is connected to the gate of the eighth transistor N0, the source of the third transistor N5 is grounded, and the drain of the third transistor N5 is respectively connected to the source of the third differential input transistor N6 and the source of the fourth differential input transistor N7; The drain of the third differential input transistor N6 is connected to the drain of the fifth load transistor P8, the drain of the fourth differential input transistor N7 is connected to the drain of the fourth load transistor N10, the gate of the third differential input transistor N6 is respectively connected to the drain of the third load transistor N9 and the drain of the sixth transistor N8, the source of the sixth transistor N8 is grounded, and the drain of the sixth transistor N8 is connected to the drain of the fourth transistor P5; The drain of the fourth differential input transistor N7 is respectively connected to the drain of the fourth load transistor N10 and the drain of the fourth reset transistor P9, the gate of the fourth differential input transistor N7 is respectively connected to the drain of the fourth load transistor N10 and the drain of the seventh transistor N11, the source of the seventh transistor N11 is grounded, and the drain of the seventh transistor N11 is also connected to the drain of the fifth transistor P6; The gate of the fifth load tube P8 is connected to the gate of the sixth load tube P10 and to the drain of the third reset tube P7.
6. The negative single event transient reinforcement circuit based on a comparator and a delay unit according to claim 3, characterized in that: The output buffer circuit is formed by three inverters connected in series, and the input end of the inverter is connected to the drain of the fourth differential input transistor N7.
7. The negative single event transient reinforcement circuit based on a comparator and a delay unit according to claim 3, characterized in that: The bias circuit includes a fifth reset tube P0, a first transistor N1 and an eighth transistor N0. A fourth resistor R0, a first resistor R1, a second resistor R2 and a third resistor R3 connected in series are connected between the drain of the fifth reset tube P0 and the drain of the eighth transistor N0. The source of the eighth transistor N0 is grounded, the drain of the first transistor N1 is connected to the drain of the eighth transistor N0, and the source of the first transistor N1 is grounded.
8. A method for reinforcing a negative single event transient reinforcement circuit based on a comparator and a delay unit according to claim 3, characterized in that: The reinforcement method includes the following steps: A. Before LDO enters normal working state, the control voltage Ven of the comparator CMP is at a low level. At this time, the comparator CMP does not make comparisons, and the output of the comparator CMP is at a low level. B. The output of the inverting delay unit INV is high level, the output of the AND gate AND is low level, and the connecting tube P11 is turned on; C. When the LDO enters the normal working state, the control voltage Ven is at a high level, and the comparator CMP starts to compare. Since the LDO output voltage Vout is greater than the reference voltage Vout_min formed by the resistor network during normal working, the output of the comparator CMP is at a low level, the output of the inverting delay unit INV is at a high level, the output of the AND gate AND is at a low level, and the connecting tube P11 remains turned on; D. When a negative pulse appears, the LDO output voltage Vout is less than the reference voltage Vout_min formed by the resistor network, and the comparator CMP outputs a high level. Since the inverting delay unit INV has a capacitor, the output of the inverting delay unit is affected by the capacitor and remains at a high level. The output of the AND gate AND is a high level, the connecting tube P11 is disconnected, and the capacitor C1 begins to maintain the gate voltage of the power tube N1, reducing the impact of the negative single-particle transient pulse. E. After the capacitor in the inverting delay unit INV is discharged for a period of time, the output of the inverting delay unit INV is low level, the output voltage of the AND gate AND returns to low level, and the connecting tube P11 is turned on.