Phase-locked loop, chip and electronic equipment

Abstract

The invention relates to a phase-locked loop, a chip and electronic equipment, and belongs to the field of electronic circuits. The phase-locked loop comprises a voltage drop detection circuit, a phase-locked loop circuit and a voltage regulation circuit, the voltage regulation circuit is connected with the voltage drop detection circuit and the phase-locked loop circuit; the voltage drop detection circuit is used for detecting the voltage drop of the system voltage of the chip to which the phase-locked loop belongs relative to a voltage threshold and converting the detected voltage drop into a target control word; the voltage regulation circuit is used for regulating the output voltage of the voltage regulation circuit according to the target control word; wherein the output voltage is used for supplying power to a VCO in the phase-locked loop circuit, the reduction amplitude of the output voltage is in positive correlation with the voltage drop amplitude of the system voltage, and the clock frequency output by the VCO in the phase-locked loop circuit is in positive correlation with the supply voltage of the VCO. According to the invention, the clock frequency output by the phase-locked loop can be adaptively adjusted according to the load change.

Description

Technical Field

[0001] The present application belongs to the field of electronic circuits, and specifically relates to a phase-locked loop, a chip and an electronic device. Background Art

[0002] Usually, the system voltage in the chip will change in real time with the change of load size. When under heavy load, the system voltage will generally have a voltage drop. At this time, the frequency of the clock signal output by the system phase-locked loop is almost unaffected by the voltage drop (that is, the clock frequency remains unchanged). However, for other circuits in the chip that use the clock signal, if the clock frequency remains unchanged, a drop in power supply voltage may cause a timing violation in the circuit, which in turn causes the entire system to malfunction and cause downtime. Summary of the invention

[0003] In view of this, the purpose of the present application is to provide a phase-locked loop, a chip and an electronic device to quickly reduce the clock frequency of the clock signal output by the phase-locked loop when the system voltage drops, thereby alleviating the timing violation of the circuit using the clock signal.

[0004] The embodiment of the present application is implemented as follows:

[0005] In a first aspect, an embodiment of the present application provides a method comprising: a voltage drop detection circuit, a phase-locked loop circuit, and a voltage regulation circuit; the voltage regulation circuit is connected to the voltage drop detection circuit and the phase-locked loop circuit; the voltage drop detection circuit is used to detect the voltage drop of the system voltage of the chip to which the phase-locked loop belongs relative to a voltage threshold, and convert the detected voltage drop into a target control word; the voltage regulation circuit is used to adjust the output voltage of the voltage regulation circuit according to the target control word; wherein the output voltage is used to power a VCO in the phase-locked loop circuit, the reduction amplitude of the output voltage is positively correlated with the voltage drop amplitude of the system voltage, and the clock frequency output by the VCO in the phase-locked loop circuit is positively correlated with the power supply voltage of the VCO.

[0006] In the above embodiment, a voltage regulation circuit and a voltage drop detection circuit are added to the phase-locked loop circuit, the voltage drop detection circuit is used to detect and quantify the voltage drop of the system voltage relative to the voltage threshold, and the voltage regulation circuit is used to adjust the supply voltage of the VCO according to the voltage drop, so that the phase-locked loop can adaptively adjust the clock frequency of the phase-locked loop output according to the system voltage change, thereby achieving a rapid reduction in the clock frequency of the clock signal output by the phase-locked loop when the system voltage drops, thereby alleviating the timing violation of the circuit using the clock signal.

[0007] In combination with a possible implementation manner of the first aspect embodiment, the voltage drop detection circuit includes: a flash analog-to-digital converter, used to detect the voltage drop of the system voltage relative to the voltage threshold, and convert the detected voltage drop into the target control word.

[0008] In the above embodiment, a flash analog-to-digital converter is used to implement rapid voltage drop detection and quantification, which is beneficial to improving response speed and detection accuracy.

[0009] In combination with a possible implementation manner of the first aspect embodiment, if the target control word is a thermometer code containing at least one valid bit; the voltage drop detection circuit includes: a flash analog-to-digital converter and a decoder; the flash analog-to-digital converter is used to detect the voltage drop of the system voltage relative to the voltage threshold, and convert the detected voltage drop into a control word; the decoder is used to convert the control word output by the flash analog-to-digital converter into a corresponding thermometer code output containing at least one valid bit.

[0010] In the above embodiment, a flash analog-to-digital converter is used to achieve fast voltage drop detection and quantification, and a decoder is used to convert the control word output by the flash analog-to-digital converter into a corresponding thermometer code output containing at least one valid bit, which facilitates precise control and helps improve accuracy.

[0011] In combination with a possible implementation manner of the first aspect, if the target control word is a thermometer code containing at least one valid bit; the voltage regulation circuit includes: an adjustable reference voltage circuit, a voltage regulator, the voltage regulator is connected to the adjustable reference voltage circuit; the adjustable reference voltage circuit is used to adjust the regulated output voltage of the adjustable reference voltage circuit according to the target control word; the voltage regulator is used to stabilize the output voltage of the adjustable reference voltage circuit.

[0012] In the above embodiment, the voltage regulating circuit with the above structure can achieve accurate regulation of the power supply voltage of the VCO while simplifying the circuit structure and reducing the circuit cost.

[0013] In combination with a possible implementation manner of the embodiment of the first aspect, the voltage regulation circuit includes: a decoder, an adjustable reference voltage circuit, and a voltage regulator; the adjustable reference voltage circuit is connected to the decoder, and the voltage regulator is connected to the adjustable reference voltage circuit; the decoder is used to convert the target control word into a corresponding thermometer code output containing at least one valid bit; the adjustable reference voltage circuit is used to adjust the output voltage of the adjustable reference voltage circuit according to the thermometer code corresponding to the target control word; the voltage regulator is used to stabilize the output voltage of the adjustable reference voltage circuit.

[0014] In the above embodiment, if the target control word is not a thermometer code containing at least one valid bit, the voltage regulating circuit with the above structure can quickly convert the target control word into a corresponding thermometer code output containing at least one valid bit, thereby achieving precise control.

[0015] In combination with a possible implementation manner of the embodiment of the first aspect, the adjustable reference voltage circuit includes a resistor string and a plurality of switches; a first end of the resistor string is connected to a power supply, a second end of the resistor string is grounded, the resistor string includes a plurality of output ends corresponding one to one to the plurality of switches, each output end is connected to a switch, and each output end is connected to an input end of the voltage regulator; states of the plurality of switches are controlled by the target control word, and states of the plurality of switches are related to the output voltage of the adjustable reference voltage circuit.

[0016] In the above embodiment, the adjustable reference voltage circuit with the above structure can change the internal structure of the adjustable reference voltage circuit by only controlling the states of multiple switches, thereby adjusting the output voltage thereof, which has the advantages of simple control logic and convenient design.

[0017] In combination with a possible implementation manner of the embodiment of the first aspect, during the period when the voltage regulation circuit regulates the output voltage of the voltage regulation circuit according to the target control word, the loop in the phase-locked loop circuit is in an open-loop state.

[0018] In the above embodiment, during the period when the output voltage of the voltage regulating circuit is adjusted according to the target control word, the loop in the phase-locked loop circuit is in an open-loop state, thereby preventing the loop from locking the clock frequency to the initial state (the state of the phase-locked loop when no voltage drop occurs), compared to the period when the output voltage of the voltage regulating circuit is adjusted according to the target control word, the loop in the phase-locked loop circuit is in a closed-loop state, which can make the phase-locked loop have lower power consumption than when the same clock frequency is obtained in the closed-loop state, or obtain a higher clock frequency while achieving the same power consumption. At the same time, it also avoids frequency overshoot caused by sudden change in clock frequency after voltage recovery.

[0019] In combination with a possible implementation manner of the embodiment of the first aspect, the voltage drop detection circuit is also connected to the phase-locked loop circuit, and the voltage drop detection circuit is also used to output a loop signal, and the loop signal is used to control the loop in the phase-locked loop circuit to be in an open-loop state.

[0020] In the above embodiment, a part of the control word obtained by quantifying the voltage drop by the voltage drop detection circuit is used as a loop signal to control the phase-locked loop circuit to be in an open-loop state without introducing a new control signal, which can simplify the circuit design and reduce the control difficulty while achieving its purpose.

[0021] In a second aspect, an embodiment of the present application further provides a chip, comprising a phase-locked loop provided in the embodiment of the first aspect described above and / or in any possible implementation manner in combination with the embodiment of the first aspect.

[0022] In a third aspect, an embodiment of the present application further provides an electronic device, including: a chip as provided in the embodiment of the first aspect above.

[0023] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. The above and other purposes, features and advantages of the present application will be more clearly shown in the drawings.

[0025] Figure 1 A first structural schematic diagram of a phase-locked loop provided in an embodiment of the present application is shown.

[0026] Figure 2 A schematic structural diagram of a phase-locked loop circuit provided in an embodiment of the present application is shown.

[0027] Figure 3 A schematic diagram of an input signal and an output signal of a decoder provided in an embodiment of the present application is shown.

[0028] Figure 4a A first correspondence diagram between therm[15:0] and sel[15:0] provided in an embodiment of the present application is shown.

[0029] Figure 4b A second correspondence diagram between therm[15:0] and sel[15:0] provided in an embodiment of the present application is shown.

[0030] Figure 5 A schematic diagram of an adjustable reference voltage circuit provided in an embodiment of the present application is shown.

[0031] Figure 6a A second structural schematic diagram of a phase-locked loop provided in an embodiment of the present application is shown.

[0032] Figure 6b A third structural schematic diagram of the phase-locked loop provided in an embodiment of the present application is shown.

[0033] Figure 7 A waveform diagram of a phase-locked loop frequency reduction provided in an embodiment of the present application is shown.

[0034] Figure 8 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.

[0036] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device.

[0037] Furthermore, the term "and / or" in this application is merely a term used to describe the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0038] In the description of the embodiments of the present application, unless otherwise clearly specified or limited, the technical term "connection" may refer to a direct connection or an indirect connection through an intermediate medium.

[0039] The embodiment of the present application provides a frequency-variable phase-locked loop (PLL), which can adapt to load changes (usually the system voltage in the chip changes with the load size), and can automatically reduce the clock frequency of the output clock signal when the load is heavy, and can automatically increase the clock frequency of the output clock signal when switching from heavy load to light load, so as to adapt to load changes. Usually, when the load is heavy, the system voltage will have a voltage drop. The phase-locked loop provided by the present application can reduce the clock frequency of the phase-locked loop output accordingly when the load is heavy, thereby reducing the timing requirements of the circuit using the clock signal, and alleviating timing violations and system function errors.

[0040] Combine the following Figure 1The phase-locked loop provided in the embodiment of the present application is described. The main structure of the phase-locked loop may include: a phase-locked loop circuit, a voltage regulating circuit and a voltage drop detection circuit. The voltage regulating circuit is connected to the voltage drop detection circuit and the phase-locked loop circuit. The present application adds a voltage regulating circuit and a voltage drop detection circuit on the basis of the phase-locked loop circuit, so that the phase-locked loop can adjust the clock frequency of the phase-locked loop output according to the system voltage change, and then quickly reduce the clock frequency of the clock signal output by the phase-locked loop when the system voltage drops, thereby alleviating the timing violation of the circuit using the clock signal.

[0041] like Figure 2 As shown, the phase-locked loop circuit may include: a voltage controlled oscillator (VCO), a divider (DIV), a low pass filter (LPF), a phase frequency detector (PFD), and a charge pump (CP).

[0042] DIV is used to divide the clock signal (clkout) output by the VCO, and input the divided signal as a feedback signal (feedclk) into the PFD. The PFD is used to compare the frequency and phase of two input signals (one is the reference signal refclk, and the other is the feedback signal feedclk). The CP is used to convert the phase difference signal detected by the PFD into a current signal and transmit it to the LPF. The LPF is used to filter out the high-frequency components and noise in the CP output signal, and only retain the low-frequency components to control the frequency change of the VCO and ensure the stability and accuracy of the PLL. The VCO adjusts its output frequency according to the control voltage output by the LPF, and its frequency change is determined by the size of the input control voltage.

[0043] In a possible implementation, the voltage drop detection circuit is used to detect the voltage drop of the system voltage (VDD) of the chip to which the phase-locked loop belongs relative to the voltage threshold (such as Vthres), and convert the detected voltage drop into a target control word. The target control word output by the voltage drop detection circuit can be a thermometer code containing at least one valid bit at any time, or it can be a thermometer code that does not contain at least one valid bit at any time. In this case, the target control word can represent the voltage drop size.

[0044] In a possible implementation, the target control word may represent the voltage drop. In this case, the voltage drop detection circuit includes: an error amplifier for detecting a voltage drop of the system voltage relative to a voltage threshold and converting the detected voltage drop into a corresponding control word.

[0045] In one possible implementation, the voltage drop detection circuit includes: a flash analog-to-digital converter (flash ADC (Analog Digital Converter)). The flash analog-to-digital converter is used to detect the voltage drop of the system voltage relative to the voltage threshold, and convert the detected voltage drop into a target control word. In this implementation, the target control word represents the voltage drop size. Using the flash ADC to achieve fast voltage drop detection and quantification is conducive to improving response speed and detection accuracy.

[0046] In one possible implementation, the target control word may be a thermometer code containing at least one valid bit at any time. In this implementation, the voltage drop detection circuit includes: a flash analog-to-digital converter and a decoder, wherein the flash analog-to-digital converter and the decoder are connected. In this implementation, the flash analog-to-digital converter is used to detect the voltage drop of the system voltage relative to the voltage threshold, and convert the detected voltage drop into a control word (characterizing the voltage drop size). The decoder is used to convert the control word output by the flash analog-to-digital converter into a corresponding thermometer code output containing at least one valid bit.

[0047] The voltage regulation circuit is used to adjust its own (i.e., voltage regulation circuit) output voltage according to the target control word. The output voltage is used to power the VCO in the phase-locked loop circuit. The reduction of the output voltage is positively correlated with the voltage drop of the system voltage. The clock frequency output by the VCO in the phase-locked loop circuit is positively correlated with the power supply voltage of the VCO. The greater the voltage drop, the smaller the output voltage, and the corresponding clock frequency output by the VCO is also smaller.

[0048] In one possible implementation, when the target control word represents the size of the voltage drop, the voltage regulation circuit may include a programmable logic controller, which stores the correspondence between different input values ​​and output voltages. The programmable logic controller may match the preset correspondence based on the control word representing the size of the voltage drop output by the voltage drop detection circuit, find the correspondence that matches the control word, and thereby output an output voltage value corresponding to the control word.

[0049] When the target control word is a thermometer code including at least one valid bit, the voltage regulation circuit may include: an adjustable reference voltage circuit (Voltage Reference, VREF) and a voltage regulator, wherein the adjustable reference voltage circuit and the voltage regulator are connected. The adjustable reference voltage circuit is used to adjust the regulated output voltage of the adjustable reference voltage circuit according to the target control word. The voltage regulator is used to stabilize the output voltage of the adjustable reference voltage circuit and provide a constant power supply.

[0050] In some possible implementations, the voltage regulating circuit is specifically used to convert the target control word into a corresponding thermometer code containing at least one valid bit, and adjust the output voltage of the voltage regulating circuit according to the thermometer code corresponding to the target control word. In this implementation, the voltage regulating circuit includes: a decoder, an adjustable reference voltage circuit and a voltage regulator, wherein the decoder is connected to the adjustable reference voltage circuit, and the adjustable reference voltage circuit is connected to the voltage regulator. The decoder is used to convert the target control word into a corresponding thermometer code output containing at least one valid bit. The adjustable reference voltage circuit is used to adjust the output voltage of the adjustable reference voltage circuit according to the thermometer code corresponding to the target control word. The voltage regulator is used to stabilize the output voltage of the adjustable reference voltage circuit.

[0051] In a possible implementation, the input signal of the decoder may be an N-bit control word, and the output signal may also be an N-bit control word, where N is an integer greater than or equal to 2. Taking N=16 as an example, the value of N is not limited to 16. Figure 3 As shown in the figure, the decoder is used to convert the input 16-bit therm[15:0] into a 16-bit sel[15:0] output. Among them, therm[15:0] indicates the voltage drop, and sel[15:0] indicates the thermometer code corresponding to the voltage drop. The minimum value of therm[15:0] is 0000000000000000, and the maximum value is 1111111111111111. The minimum value of sel[15:0] is 000000000000001, and the maximum value can be 11111111111111111. Among them, therm[15:0] is all 0, indicating no voltage drop, and therm[15:0] is all 1, indicating the maximum voltage drop.

[0052] In a possible implementation, the corresponding relationship between therm[15:0] and sel[15:0] can be as follows: Figure 4a shown. Figure 4a Only the case where sel[15:0] contains only one valid bit of the thermometer code at any time is shown, and the "1" in sel[15:0] represents a valid bit.

[0053] In some implementations, the valid bit may also be represented by "0". In this case, therm[15:0]: 0000000000000000 corresponding to sel[15:0] may be 1111111111111110; therm[15:0]: 0000000000000001 corresponding to sel[15:0] may be 111111111111110; therm[15:0]: 000000000000001 corresponding to sel[15:0] may be 111111111 11111100; therm[15:0]: 0000000000000111 corresponding to sel[15:0] may be 11111111111111000; and so on, therm[15:0]: 01111111111111111 corresponding to sel[15:0] may be 10000000000000000; therm[15:0]: 111111111111111111 may correspond to sel[15:0] 00000000000000000. In this implementation manner, "0" in sel[15:0] indicates a valid bit.

[0054] In a possible implementation, the corresponding relationship between therm[15:0] and sel[15:0] can be as follows: Figure 4b shown. Figure 4b The figure shows the case where sel[15:0] contains at least one valid bit of the thermometer code at any time, and the "1" in sel[15:0] indicates a valid bit. Of course, the corresponding relationship between therm[15:0] and sel[15:0] is not limited to Figure 4a , Figure 4b As shown in the figure, any correspondence between therm[15:0] and sel[15:0] is acceptable, provided that the reduction in output voltage is positively correlated with the voltage drop in the system voltage.

[0055] In addition, therm[15:0] values ​​are not limited to Figure 4a or Figure 4b As shown, the value of therm[15:0] can be any value between 0000000000000000 and 111111111111111111.

[0056] In some possible implementations, when the adjustable reference voltage circuit adjusts the output voltage of the adjustable reference voltage circuit according to the target control word (or the thermometer code corresponding to the target control word), the internal structure of the adjustable reference voltage circuit may be adjusted to adjust the output voltage. In some implementations, the adjustable reference voltage circuit may also adjust the output voltage according to the input value (i.e., the target control word or the thermometer code corresponding to the target control word) based on the correspondence between the input value and the output voltage stored internally.

[0057] In one possible implementation, Figure 5 As shown, the adjustable reference voltage circuit includes a resistor string and a plurality of switches. The first end of the resistor string is connected to the power supply VDD, the second end of the resistor string is grounded GND, the resistor string includes a plurality of output ends corresponding to the plurality of switches, each output end is connected to a switch, and each output end is connected to the input end of the voltage regulator. The states of the plurality of switches are controlled by the target control word, and the states of the plurality of switches are related to the output voltage of the adjustable reference voltage circuit. By controlling the states of the switches, the internal structure of the adjustable reference voltage circuit can be changed, thereby adjusting the magnitude of the output voltage. Figure 5 In the example shown, the adjustable reference voltage circuit includes 16 switches, each of which is controlled by a bit in sel[15:0]. The resistor string may include 17 resistors, and an output terminal may be included between two adjacent resistors. In a possible implementation, the resistance values ​​of the 17 resistors may be equal.

[0058] In one implementation, the switch may be turned on (closed) at a high level "1" and turned off (open) at a low level "0". In some possible implementations, the switch may be turned off at a high level "1" and turned on at a low level "0".

[0059] Different valid bits of sel[15:0] result in different switches that are turned on, and different internal structures of the corresponding adjustable reference voltage circuits, which result in different output voltages. For example, assuming that the resistance values ​​of the 17 resistors are equal, when the switch controlled by sel[0] is closed and the other switches are open, the output voltage vref = 16 / 17*VDD; when the switch controlled by sel[1] is closed and the other switches are open, the output voltage vref = 15 / 17*VDD; when the switch controlled by sel

[15] is closed and the other switches are open, the output voltage vref = 1 / 17*VDD.

[0060] In some possible implementations, during the period when the voltage regulation circuit adjusts the output voltage of the voltage regulation circuit according to the target control word, the loop in the phase-locked loop circuit is in an open-loop state, thereby preventing the loop from locking the clock frequency to the initial state (the state of the phase-locked loop when no voltage drop occurs), compared to the period when the output voltage of the voltage regulation circuit is adjusted according to the target control word, the loop in the phase-locked loop circuit is in a closed-loop state, which can make the phase-locked loop have lower power consumption than when the same clock frequency is obtained in the closed-loop state, or obtain a higher clock frequency while achieving the same power consumption. At the same time, it also avoids frequency overshoot caused by sudden change in clock frequency after voltage recovery.

[0061] In a possible implementation, the voltage drop detection circuit may also be connected to a phase-locked loop circuit, and the voltage drop detection circuit may also be used to output a loop signal, and the loop signal may be used to control the loop in the phase-locked loop circuit to be in an open-loop state. For example, the loop signal may be a part of therm[15:0] described above, for example, therm[0]. Therm[0] is used as a loop signal to control the phase-locked loop circuit to be in an open-loop state without introducing a new control signal, thereby achieving its purpose while simplifying circuit design and reducing control difficulty.

[0062] The loop signal therm[0] can be used to control the PFD and / or CP in the phase-locked loop circuit to put the loop in an open-loop state. For example, the loop signal can be used as an enable signal of the PFD and / or CP to control whether the FD and / or CP are enabled to work, thereby achieving control of the loop state of the phase-locked loop circuit. The PFD and / or CP can be enabled at a low level, that is, when therm[0]=0, the PFD and / or CP work normally.

[0063] In order to better illustrate the above phase-locked loop, the following Figure 4a and 6a (or Figure 6b ) is used to illustrate the schematic diagram shown in FIG. A flash ADC is used to quickly quantize the random voltage drop therm[15:0], and a decoder is used to convert the quantized voltage drop into a thermometer code sel[15:0], and therm[0] in therm[15:0] is used as a loop signal to control the loop state of the phase-locked loop circuit.

[0064] When the system voltage VDD has no voltage drop, that is, VDD ≥ Vthres, therm[15:0] is all 0, and the lowest bit therm[0] is sent to PFD / CP (i.e. PFD or CP). When therm[0] is 0, it has no effect on PFD / CP. The lowest bit of sel[15:0] is 1, the VREF circuit selects the default gear, and the voltage VA is generated by the regulator to power the VCO, and the entire PLL loop is locked normally. If the frequency of refclk is Frefclk, if the division ratio of the divider (DIV) is M, the frequency of the output clkout of the locked PLL = Frefclk*M.

[0065] When the system voltage has a small voltage drop, that is, VDD<Vthres, and the lowest bit of therm[15:0] output by the flash ADC is 1, the output current of PFD / CP is forced to 0 by therm[0], so that the loop is disconnected and the loop maintains the previous state and is no longer updated. The lowest bit of sel[15:0] is 1, at this time the VCO supply voltage VA remains unchanged, and the loop is in a non-updated state, then the output clock still maintains the frequency Frefclk*M when it was locked before.

[0066] When the voltage drop of the system voltage continues to increase, and therm[15:0] output by the flash ADC has two or more 1s, sel[15:0] will select a voltage value smaller than the default value in the VREF circuit, and generate a lower supply voltage VA through the voltage regulator. The magnitude of the VA drop is proportional to the voltage drop of the system voltage VDD. Since therm[0] is 1, the loop is in a non-updated state, preventing the PLL loop from locking the clock frequency in the initial direction when the frequency is reduced. It also avoids frequency overshoot caused by sudden changes in the clock frequency after the voltage is restored. The oscillation frequency of the free-running VCO is proportional to the drop in the supply voltage, so the voltage drop of VDD is quantified as a drop in the VCO output frequency, and finally the reduced-frequency clock clkout is output.

[0067] Figure 7 The waveform diagram of the phase-locked loop frequency reduction is shown. When therm[15:0] is 0, the loop is established and locked to generate a clock of the target frequency. As the voltage drop increases, when therm[15:0] ≥ 16'h2 (the thermometer code 11 is represented by hexadecimal 2 in the figure), the output frequency will decrease proportionally. The greater the voltage drop, the more the clock frequency decreases. During the frequency reduction process, the loop of the phase-locked loop is in a non-updating state, which is similar to the open-loop working state. At this time, the VCO is in a free oscillation state. In this state, the period jitter of the VCO under free oscillation will not increase significantly, and will not affect the timing of the digital circuit.

[0068] The embodiment of the present application also provides a chip, which may include the above-mentioned phase-locked loop. In some possible implementations, the chip may be an integrated circuit chip with signal processing capabilities. The above-mentioned chip may include a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), an AI (Artificial Intelligence), an NPU (Neural Network Processing Unit), an ISP (Image Signal Processor), a DPU (Display Processing Unit), a VPU (Video Processing Unit), a DSP (Digital Signal Processor) data processing core, etc., and may also be a processor chip used in some large-scale data computing scenarios.

[0069] The phase-locked loop provided by the chip embodiment has the same implementation principle and technical effects as those of the aforementioned phase-locked loop embodiment. For the sake of brief description, for matters not mentioned in the chip embodiment, reference may be made to the corresponding contents in the aforementioned phase-locked loop embodiment.

[0070] The present application also provides an electronic device, which includes the above-mentioned chip. In some possible implementations, such as Figure 8 As shown, the electronic device includes: a transceiver, a memory, a communication bus and a processor. In this embodiment, the specific structure of the above chip can be a processor.

[0071] The transceiver, the memory, and the processor are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses or signal lines. Among them, the transceiver is used to send and receive data. The memory is used to store a computer program, wherein the computer program includes at least one software function module that can be stored in the memory in the form of software or firmware or solidified in the operating system (OS) of the electronic device. The processor is used to execute the software function module or computer program stored in the memory.

[0072] Among them, the memory can be, but is not limited to, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

[0073] The processor may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), an accelerated processing unit (Accelerated Processing Unit), a multimedia application processor (MAP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. Or the processor may also be any conventional processor, etc.

[0074] Among them, the above-mentioned electronic devices include but are not limited to mobile phones, tablets, notebooks, computers, etc.

[0075] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0076] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0077] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A phase-locked loop, characterized in that: include: A voltage drop detection circuit, used for detecting a voltage drop of a system voltage of a chip to which the phase-locked loop belongs relative to a voltage threshold, and converting the detected voltage drop into a target control word; a voltage regulating circuit, connected to the voltage drop detection circuit, the voltage regulating circuit being used to adjust the output voltage of the voltage regulating circuit according to the target control word; A phase-locked loop circuit is connected to the voltage regulation circuit; wherein the output voltage is used to power the VCO in the phase-locked loop circuit, the reduction amplitude of the output voltage is positively correlated with the voltage drop amplitude of the system voltage, and the clock frequency output by the VCO in the phase-locked loop circuit is positively correlated with the power supply voltage of the VCO.

2. The phase-locked loop according to claim 1, characterized in that: The voltage drop detection circuit comprises: A flash analog-to-digital converter is used to detect a voltage drop of the system voltage relative to the voltage threshold and convert the detected voltage drop into the target control word.

3. The phase-locked loop according to claim 1, characterized in that: If the target control word is a thermometer code including at least one valid bit; the voltage drop detection circuit includes: a flash analog-to-digital converter, configured to detect a voltage drop of the system voltage relative to the voltage threshold, and convert the detected voltage drop into a control word; A decoder is used to convert the control word output by the flash analog-to-digital converter into a corresponding thermometer code output containing at least one valid bit.

4. The phase-locked loop according to claim 1, characterized in that: If the target control word is a thermometer code including at least one valid bit; the voltage regulating circuit comprises: An adjustable reference voltage circuit, used for adjusting the output voltage of the adjustable reference voltage circuit according to the target control word; A voltage stabilizer is connected to the adjustable reference voltage circuit, and the voltage stabilizer is used to stabilize the output voltage of the adjustable reference voltage circuit.

5. The phase-locked loop according to claim 1, characterized in that: The voltage regulating circuit comprises: A decoder, for converting the target control word into a corresponding thermometer code output including at least one valid bit; an adjustable reference voltage circuit, connected to the decoder, and configured to adjust an output voltage of the adjustable reference voltage circuit according to a thermometer code corresponding to the target control word; A voltage stabilizer is connected to the adjustable reference voltage circuit, and the voltage stabilizer is used to stabilize the output voltage of the adjustable reference voltage circuit.

6. The phase-locked loop according to claim 4 or 5, characterized in that: The adjustable reference voltage circuit comprises a resistor string and a plurality of switches; The first end of the resistor string is connected to a power supply, the second end of the resistor string is grounded, the resistor string comprises a plurality of output ends corresponding to the plurality of switches one by one, each output end is connected to a switch, and each output end is connected to an input end of the voltage regulator; The states of the plurality of switches are controlled by the target control word, and the states of the plurality of switches are related to the output voltage of the adjustable reference voltage circuit.

7. The phase-locked loop according to any one of claims 1 to 5, characterized in that: During the period when the voltage regulating circuit regulates the output voltage of the voltage regulating circuit according to the target control word, the loop in the phase-locked loop circuit is in an open-loop state.

8. The phase-locked loop according to claim 7, characterized in that: The voltage drop detection circuit is also connected to the phase-locked loop circuit. The voltage drop detection circuit is also used to output a loop signal. The loop signal is used to control the loop in the phase-locked loop circuit to be in an open-loop state.

9. A chip, characterized in that: Comprising a phase-locked loop as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: include: The chip as claimed in claim 9.

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