Background digital calibration circuit for correcting time skew of time-interleaved analog-to-digital converter

Abstract

The invention provides a background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter. The circuit comprises a code word preprocessing circuit, a zero-cross detection circuit, a self-return-to-zero and self-add counter, an edge counting circuit, a counting storage circuit and a polarity decision circuit, the output end of the codeword preprocessing circuit is connected with the input end of the zero-cross detection circuit and is used for detecting whether an input signal passes through a zero point or not; the output end of the zero-cross detection circuit is connected with the input end of the self-return-to-zero and self-add counter, and the zero-cross detection circuit is used as data information of self-return-to-zero and self-add counting; the output end of the self-zeroing and self-adding counter is connected with the input end of the edge counting circuit and is used as timing information of self-zeroing and self-adding counting; the input end of the counting storage circuit is connected with the output end of the edge counting circuit and is used for storing the output of the edge counting circuit; the input end of the polarity decision circuit is connected with the output end of the counting storage circuit and used for judging the polarity of the output signal. The area and power consumption of the circuit are saved.

Description

Technical Field

[0001] The invention relates to the technical field of analog-digital hybrid circuits, and in particular to a background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter. Background Art

[0002] Time-interleaved Analog-to-Digital Converters (TI-ADC) are a popular analog-to-digital conversion technology in ultra-wideband communications, high-speed serial links, and RF transceivers. A time-interleaved analog-to-digital converter consists of several analog-to-digital converters (ADCs) that sample alternately in sequence. Ideally, N analog-to-digital converters with a sampling rate of Fs work together to build a time-interleaved analog-to-digital converter with a sampling rate of N times Fs. This ingenious design solves the limitation of the sampling rate of a single-channel analog-to-digital converter and significantly improves the overall sampling rate through parallel processing.

[0003] Although time-interleaved ADCs have significant advantages in sampling rate, they also face many challenges. Due to the mismatch problem in the actual process manufacturing process, some relative mismatches may occur between the channels of the time-interleaved ADC, which will reduce the signal-to-noise and distortion ratio (SNDR). Specifically, these mismatches include offset mismatch, gain mismatch, and timing-skew. These mismatches need to be controlled through precise design and calibration to ensure that the time-interleaved ADC can maintain a high signal-to-noise and distortion ratio while maintaining the advantage of high sampling rate.

[0004] Although the method of extracting time offset information based on autocorrelation operation has achieved certain results in correcting the time offset of the input signal within a specific normalized frequency band in the background, it still faces some challenges. One of the problems is that the time offset detection method based on autocorrelation operation relies on the effective information of the input signal, and the effectiveness of this information will change with the change of the input signal frequency. Especially in the high-frequency region, the accuracy of this detection method will be affected, resulting in misdetection or divergence in the calibration process of the time offset under certain input conditions. Another problem is that in the autocorrelation operation scheme, the balance between the convergence speed and accuracy of the algorithm depends largely on the choice of iterative compensation in the time offset detection process. In the process of seeking this balance, some improved methods using intelligent algorithms can improve the detection accuracy and convergence speed, but at the same time they also significantly increase the complexity of the circuit, which may even lead to non-convergence problems in the system. Summary of the invention

[0005] The purpose of the present invention is to provide a background digital calibration circuit for correcting the time skew of a time-interleaved analog-to-digital converter, which avoids the use of digital filters, does not require multiplier overhead, saves circuit area and power consumption, improves the calibration effect of the calibration circuit on input signals with different biases, different swings, and different mismatch information, improves the generalization ability of time skew calibration for input signals in different normalized Nyquist bands, and can be applied to time-interleaved analog-to-digital converters with any number of channels. Compared with the filter solution, the circuit resources and area of ​​this solution are more economical.

[0006] A background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter comprises: a code word preprocessing circuit, a zero-crossing detection circuit, a self-zeroing self-adding counter, an edge counting circuit, a counting storage circuit and a polarity decision circuit;

[0007] The output end of the code word preprocessing circuit is connected to the input end of the zero-crossing detection circuit to detect whether the input signal passes through the zero point;

[0008] The output end of the zero-crossing detection circuit is connected to the input end of the self-returning-to-zero self-adding counter, and is used as data information of the self-returning-to-zero self-adding counter;

[0009] The output end of the self-returning-to-zero self-adding counter is connected to the input end of the edge counting circuit, and is used as the timing information of the self-returning-to-zero self-adding counter;

[0010] The input end of the counting storage circuit is connected to the output end of the edge counting circuit, and is used to store the output of the edge counting circuit;

[0011] The input end of the polarity determination circuit is connected to the output end of the counting storage circuit for determining the polarity of the output signal.

[0012] Preferably, the codeword preprocessing circuit comprises: an adder;

[0013] The positive input terminal of the adder is connected to the input signal, and the negative input terminal is connected to the middle value of the signal, that is, the 128 code word.

[0014] Preferably, the zero-crossing detection circuit comprises: a first relational operation circuit (BU1), a second relational operation circuit (BU2), a D flip-flop circuit (BU4), and an AND logic operation circuit (BU5);

[0015] The input end of the first relational operation circuit (BU1) is connected to the output end of the D flip-flop circuit (BU4);

[0016] The input end of the second relational operation circuit (BU2) is connected to the output end of the codeword preprocessing circuit;

[0017] The input end of the D flip-flop circuit (BU4) is connected to the output end of the codeword preprocessing circuit;

[0018] The input end of the AND logic operation circuit (BU5) is respectively connected to the output end of the first relational operation circuit (BU1) and the output end of the second relational operation circuit (BU2).

[0019] Preferably, the self-returning-to-zero self-adding counter comprises: an adding circuit (CU1), a D flip-flop circuit (CU2), a relational operation circuit (CU3) and a selector (CU5);

[0020] The output end of the selector (CU5) is connected to the input end of the adding circuit (CU1);

[0021] The output end of the adding circuit (CU1) is connected to the input end of the D flip-flop circuit (CU2);

[0022] The input end of the relational operation circuit (CU3) is connected to the output end of the D flip-flop circuit (CU2);

[0023] The input end of the selector (CU5) is connected to the output end of the relational operation circuit (CU3), and the output end is connected to the input end of the adding circuit (CU1).

[0024] Preferably, the edge counting circuit comprises: an adding circuit (DU1), a D flip-flop circuit (DU2), a relational operation circuit (DU3) and a selector circuit (DU5);

[0025] The input end of the adding circuit (DU1) is connected to the output end of the D flip-flop circuit (DU2), and the output end is connected to the input end of the selector circuit (DU5);

[0026] The input end of the selector circuit (DU5) is connected to the output end of the relational operation circuit (DU3), and the output end is connected to the input end of the D flip-flop circuit (DU2).

[0027] Preferably, the counting storage circuit comprises: a relational operation circuit (EU3), a D flip-flop circuit (EU1) and a selector circuit (EU2);

[0028] The output end of the relational operation circuit (EU3) is connected to the input end of the selector circuit (EU2);

[0029] The output end of the selector circuit (EU2) is connected to the input end of the D flip-flop circuit (EU1);

[0030] An output end of the D flip-flop circuit (EU1) is connected to an input end of the selector circuit (EU2).

[0031] Preferably, the polarity determination circuit comprises:

[0032] Selector circuit (FU5) and polarity input (FU3) and polarity input (FU4);

[0033] The input end of the selector circuit (FU5) is connected to the polarity input (FU3), the polarity input (FU4) and the output of the counting storage circuit, and the polarity is determined according to the output of the counting storage circuit.

[0034] A control method for a background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter is applied to a background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter, comprising:

[0035] The preprocessing circuit converts the unipolar codeword into a bipolar codeword;

[0036] Whenever the bipolar code passes through the zero point, the output of the zero-crossing detection circuit (BU5) is 1, otherwise it is 0;

[0037] The selector (DU5) of the edge counting circuit will continue to accumulate the number of zero crossings when the output CNT of the self-returning self-adding counter is less than 1023 (CU7), otherwise it will be reset to zero;

[0038] When the output CNT of the self-returning self-adding counter is equal to 1022 and is about to reach 1023, the counting storage circuit latches the number of zero crossings accumulated by the edge counting circuit in advance and allows the polarity judgment circuit to output the corresponding polarity.

[0039] The beneficial effects of the present invention are as follows: 1. The present invention avoids the use of digital filters, does not require multiplier overhead, and saves circuit area and power consumption; 2. The present invention improves the calibration effect of the calibration circuit on input signals with different biases, different swings, and different mismatch information, and improves the generalization ability of time skew calibration for input signals with different normalized Nyquist frequency bands; 3. The present invention can be applied to time-interleaved analog-to-digital converters with any number of channels. Compared with the filter solution, the circuit resources and area of ​​this solution are more economical. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0042] Figure 1 A schematic diagram of the structure of a background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter according to the present invention;

[0043] Figure 2 It is a code word preprocessing circuit diagram of the present invention;

[0044] Figure 3 It is a zero-crossing detection circuit diagram of the present invention;

[0045] Figure 4 A diagram of a self-resetting-to-zero self-increasing counter according to the present invention;

[0046] Figure 5 is an edge counting circuit diagram of the present invention;

[0047] Figure 6 It is a counting storage circuit diagram of the present invention;

[0048] Figure 7 The polarity determination circuit diagram of the present invention;

[0049] Figure 8 It is a simulation waveform diagram of the key nodes of the present invention. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0052] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0053] Example 1

[0054] A background digital calibration circuit for correcting time skew of time-interleaved analog-to-digital converters, referring to Figure 1 , including: code word preprocessing circuit, zero crossing detection circuit, self-returning to zero self-adding counter, edge counting circuit, counting storage circuit and polarity judgment circuit;

[0055] The output end of the code word preprocessing circuit is connected to the input end of the zero-crossing detection circuit to detect whether the input signal passes through the zero point;

[0056] The output end of the zero-crossing detection circuit is connected to the input end of the self-returning-to-zero self-adding counter, and is used as data information of the self-returning-to-zero self-adding counter;

[0057] The output end of the self-returning-to-zero self-adding counter is connected to the input end of the edge counting circuit, and is used as the timing information of the self-returning-to-zero self-adding counter;

[0058] The input end of the counting storage circuit is connected to the output end of the edge counting circuit, and is used to store the output of the edge counting circuit;

[0059] The input end of the polarity judgment circuit is connected to the output end of the counting storage circuit for judging the polarity of the output signal.

[0060] Although the method of extracting time offset information based on autocorrelation operation has achieved certain results in correcting the time offset of the input signal within a specific normalized frequency band in the background, it still faces some challenges. One of the problems is that the time offset detection method based on autocorrelation operation relies on the effective information of the input signal, and the effectiveness of this information will change with the change of the input signal frequency. Especially in the high-frequency region, the accuracy of this detection method will be affected, resulting in misdetection or divergence in the calibration process of the time offset under certain input conditions. Another problem is that in the autocorrelation operation scheme, the balance between the convergence speed and accuracy of the algorithm depends largely on the choice of iterative compensation in the time offset detection process. In the process of seeking this balance, some improved methods using intelligent algorithms can improve the detection accuracy and convergence speed, but at the same time they also significantly increase the complexity of the circuit, which may even lead to non-convergence problems in the system.

[0061] Taking a time-interleaved analog-to-digital converter with two channels sampled alternately as an example, we use x 1 and x 3 represents the sampling point of a channel and serves as a reference, while x 2 represents the sampling point of another channel. Due to non-ideal factors in the actual manufacturing process, x 1 and x 2 The time interval between 2 and x 3 The time intervals between them are not completely equal, and there is a time difference ΔT between them. Since the two channels are actually sampling the same input signal, for:

[0062]

[0063] Among them, the left side of the formula E[(x 2 -x 1 ) 2 ] and E[(x 3 -x 2 ) 2 ] uses mathematical expectation to express the change between the sampling points of the two channels. The right side of the formula and Represents the average power of the sampled signals of the two channels. Since the two channels actually collect the same input signal, At the same time R(T s +ΔT)=E[x(t 1 )x(t 1 +T s +ΔT)] represents the correlation of the signal. It can be defined in combination with mathematical derivatives:

[0064]

[0065] Further deducing

[0066] |E[(x 3 -x 2 ) 2 ]-E[(x 2 -x 1 ) 2 ]|≈kΔT

[0067] This conclusion shows that the time offset ΔT is related to |E[(x 3 -x 2 ) 2 ]-E[(x 2 -x 1 ) 2 ]|≈kΔT is in a linear relationship.

[0068] For the following two sampling signals y 1 and 2 :

[0069]

[0070] Although 1 and 2 can alias to the same frequency point in the first Nyquist interval, but y 1 and 2 The sum in the time domain is zero, which means that y 1 and 2 A pair of opposite signs is required to perform time offset detection correctly.

[0071] In order to identify the normalized Nyquist frequency band where the input signal frequency is located, the existing self-regulating circuit adopts a filter solution, but the filter solution has the disadvantage of being easily interfered by the input signal bias and the input signal swing.

[0072] In order to meet the above challenges, the present invention introduces an innovative circuit design scheme, adopts edge-triggered circuits, timing latch circuits and combinatorial logic operations, and performs additional auxiliary design on the circuit used to correct the time offset of the time-interleaved analog-to-digital converter. This design not only optimizes resource utilization, but also improves the performance of the calibration circuit, enabling it to better adapt to signal conditions in different frequency bands, and provides an efficient and practical solution for time offset correction of time-interleaved analog-to-digital converters.

[0073] The algorithm used in the time deskew circuit used in many time-interleaved ADCs (all-digital background compensation algorithm) suffers from the fact that for signals in the first, third or other odd Nyquist bands, the error extracted by the algorithm is proportional to time, but for signals in the second, fourth or other even Nyquist bands, this error requires the sign of the feedback to be inverted. Therefore, in order to apply the time deskew error extracted by the all-digital background time deskew algorithm, it is necessary to determine the Nyquist band in which the input signal is located so that the matching feedback sign is used.

[0074] The polarity decision circuit in the existing time-interleaved ADC time skew calibration scheme adopts the finite impulse response digital filter (FIR filter) scheme. The FIR filter is composed of several multiplier circuits, adder circuits, and D flip-flops; although the linear phase structure FIR filter saves half the number of multipliers by using symmetry, the use of FIR filter cannot be separated from the existence of multipliers.

[0075] Therefore, the input signal can be passed through a bandpass or bandstop FIR filter, and an amplitude threshold of the amplitude-frequency response curve can be set. By comparing the output of the FIR filter with the amplitude threshold, the frequency band range of the input signal can be determined, thereby giving the corresponding polarity sign.

[0076] However, it is difficult to avoid the overhead of the multiplier when using FIR filters, and the longer logic circuit prolongs the critical path. In addition, filters are divided into low-pass, high-pass, band-pass, and band-stop types. In order to meet the needs of more channels, more filters are needed to complete the task together.

[0077] Preferably, reference Figure 2 ,The codeword preprocessing circuit includes: an adder;

[0078] The positive input terminal of the adder is connected to the input signal, and the negative input terminal is connected to the middle value of the signal, that is, the 128 code word.

[0079] Assuming the ADC has 8 bits, the unipolar code is represented in binary as 8'b0000_0000 to 8'b1111_1111, which is 0 to 255 in decimal. This circuit is used to convert the range from 0 to 255 to -256 to 255, serving the subsequent zero-crossing detection circuit.

[0080] Preferably, reference Figure 3 The zero-crossing detection circuit comprises: a first relational operation circuit (BU1), a second relational operation circuit (BU2), a D flip-flop circuit (BU4), and an AND logic operation circuit (BU5);

[0081] An input end of the first relational operation circuit (BU1) is connected to an output end of the D flip-flop circuit (BU4);

[0082] The input end of the second relational operation circuit (BU2) is connected to the output end of the codeword preprocessing circuit;

[0083] The input end of the D flip-flop circuit (BU4) is connected to the output end of the codeword preprocessing circuit;

[0084] An input terminal of the AND logic operation circuit (BU5) is connected to an output terminal of the first relational operation circuit (BU1) and an output terminal of the second relational operation circuit (BU2), respectively.

[0085] The zero-crossing detection circuit includes two relational operation circuits (BU1 and BU2), a D flip-flop circuit (BU4), and an AND logic operation circuit (BU5). Among them, the D flip-flop (BU4) outputs the value of the input signal at the previous moment. If the input signal at this moment is greater than or equal to 0 (BU3), and the input signal at the previous moment is not greater than 0 (BU3), then the logic outputs of BU1 and BU2 are both 1, and the logic output of BU5 is also 1, indicating that the input signal passes through the zero point.

[0086] Preferably, reference Figure 4 The self-returning-to-zero self-adding counter comprises: an adding circuit (CU1), a D flip-flop circuit (CU2), a relational operation circuit (CU3) and a selector (CU5);

[0087] The output terminal of the selector (CU5) is connected to the input terminal of the adding circuit (CU1);

[0088] The output terminal of the adding circuit (CU1) is connected to the input terminal of the D flip-flop circuit (CU2);

[0089] An input end of the relational operation circuit (CU3) is connected to an output end of the D flip-flop circuit (CU2);

[0090] The input end of the selector (CU5) is connected to the output end of the relational operation circuit (CU3), and the output end is connected to the input end of the adding circuit (CU1).

[0091] The self-returning-to-zero self-adding counter includes an adding circuit (CU1), a D flip-flop circuit (CU2), a relational operation circuit (CU3), and a selector (CU5). When the output of the D flip-flop (CU2) is greater than or equal to 1023 (CU7), the output of CU5 is cleared (CU4), otherwise the value is added by 1 (CU6). Thus, the self-returning-to-zero self-adding counter is realized, so that the output of the D flip-flop (CU2) is 0 (CU4) to 1023 (CU7).

[0092] Preferably, reference Figure 5 , the edge counting circuit includes: an adding circuit (DU1), a D flip-flop circuit (DU2), a relational operation circuit (DU3) and a selector circuit (DU5);

[0093] The input end of the adding circuit (DU1) is connected to the output end of the D flip-flop circuit (DU2), and the output end is connected to the input end of the selector circuit (DU5);

[0094] The input end of the selector circuit (DU5) is connected to the output end of the relational operation circuit (DU3), and the output end is connected to the input end of the D flip-flop circuit (DU2).

[0095] The edge counting circuit includes an adding circuit (DU1), a D flip-flop circuit (DU2), a relational operation circuit (DU3), and a selector circuit (DU5). Figure 6 ) is less than 1023 (DU6), the logic output of the relational operation circuit (DU3) is 0, and the output of the selector circuit (DU5) will continue to accumulate with the value of Valid; when the self-returning self-adding counter (see Figure 6 ) when the output CNT is greater than or equal to 1023 (DU6), the output of the selector circuit (DU5) will be cleared to zero (DU4). Therefore, the output of the selector circuit (DU5) records the number of times the input signal passes through zero points within 1023 (DU6) sampling cycles, and has an upper limit of 1023 (DU6).

[0096] Preferably, reference Figure 6 , the counting storage circuit includes: a relational operation circuit (EU3), a D flip-flop circuit (EU1) and a selector circuit (EU2);

[0097] The output end of the relational operation circuit (EU3) is connected to the input end of the selector circuit (EU2);

[0098] An output terminal of the selector circuit (EU2) is connected to an input terminal of the D flip-flop circuit (EU1);

[0099] An output terminal of the D flip-flop circuit (EU1) is connected to an input terminal of the selector circuit (EU2).

[0100] The counting storage circuit includes a relational operation circuit (EU3), a D flip-flop circuit (EU1), and a selector circuit (EU2). When the output CNT of the counter circuit reaches 1022 (EU4), that is, 1023 minus 1, the output AccLock of the selector circuit is refreshed to the input edgeAcc in advance; otherwise, the selector circuit maintains the original value through the D flip-flop (EU1) in each sampling cycle, thereby Figure 7) output realizes storage.

[0101] Preferably, reference Figure 7 , the polarity decision circuit includes:

[0102] Selector circuit (FU5) and polarity input (FU3) and polarity input (FU4);

[0103] The input end of the selector circuit (FU5) is connected to the polarity input (FU3), the polarity input (FU4) and the output of the counting storage circuit, and the polarity is determined according to the output of the counting storage circuit.

[0104] When the condition is met, the output of the selector circuit (FU5) is -1 (FU3), otherwise, the output of the selector circuit (FU5) is +1 (FU4). Figure 8 ) output AccLock as the input of this circuit, it can output the polarity SymOut (+1 or -1) corresponding to different frequency signals.

[0105] The simulation waveforms of the key nodes of the overall circuit are as follows: Figure 8 , it can be observed that as the frequency of the input signal (IN) increases, the latch value (EU2) also increases and the polarity of the output (FU5) changes automatically.

[0106] Example 2

[0107] A control method for a background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter is applied to a background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter, comprising:

[0108] S100, the preprocessing circuit converts the unipolar codeword into a bipolar codeword;

[0109] S200, whenever the bipolar code passes through the zero point, the output (BU5) of the zero-crossing detection circuit is 1, otherwise it is 0;

[0110] S300, the selector (DU5) of the edge counting circuit will continuously accumulate the number of zero crossings when the output CNT of the self-returning self-adding counter is less than 1023 (CU7), otherwise it will be reset to zero;

[0111] S400, when the output CNT of the self-returning self-adding counter is equal to 1022 and is about to reach 1023, the counting storage circuit latches the number of zero crossings accumulated by the edge counting circuit in advance and allows the polarity determination circuit to output the corresponding polarity.

[0112] Take the 8-bit input codeword IN as an example. The preprocessing circuit (A) converts the unipolar codeword (0 to 255) into a bipolar codeword (-256 to 255); on the one hand, whenever the bipolar code passes through the zero point, the output (BU5) of the zero-crossing detection circuit (B) is 1, otherwise it is 0; on the other hand, the selector (DU5) of the edge counting circuit (D) will continuously accumulate the number of zero crossings when the output CNT of the self-zeroing self-adding counter (C) is less than 1023 (CU7), otherwise it will be cleared. When the output CNT of the self-zeroing self-adding counter (C) is equal to 1022 (about to reach 1023), the counting storage circuit (E) will latch the number of zero crossings accumulated by the edge counting circuit (D) in advance, and let the polarity decision circuit (F) output the corresponding polarity (SymOut).

[0113] The present invention avoids the use of digital filters, does not require multiplier overhead, and saves circuit area and power consumption; the present invention improves the calibration effect of the calibration circuit on input signals with different biases, different swings, and different mismatch information, and improves the generalization ability of time skew calibration for input signals with different normalized Nyquist frequency bands; the present invention can be applied to time-interleaved analog-to-digital converters with any number of channels. Compared with the filter solution, the circuit resources and area of ​​this solution are more economical.

[0114] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter, characterized in that: include: Code word preprocessing circuit, zero crossing detection circuit, self-returning to zero self-adding counter, edge counting circuit, counting storage circuit and polarity decision circuit; The output end of the code word preprocessing circuit is connected to the input end of the zero-crossing detection circuit to detect whether the input signal passes through the zero point; The output end of the zero-crossing detection circuit is connected to the input end of the self-returning-to-zero self-adding counter, and is used as data information of the self-returning-to-zero self-adding counter; The output end of the self-returning-to-zero self-adding counter is connected to the input end of the edge counting circuit, and is used as the timing information of the self-returning-to-zero self-adding counter; The input end of the counting storage circuit is connected to the output end of the edge counting circuit, and is used to store the output of the edge counting circuit; The input end of the polarity determination circuit is connected to the output end of the counting storage circuit for determining the polarity of the output signal.

2. A background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter according to claim 1, characterized in that: The codeword preprocessing circuit comprises: an adder; The positive input terminal of the adder is connected to the input signal, and the negative input terminal is connected to the middle value of the signal, that is, the 128 code word.

3. The background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter according to claim 1, characterized in that: The zero-crossing detection circuit comprises: a first relational operation circuit (BU1), a second relational operation circuit (BU2), a D flip-flop circuit (BU4), and an AND logic operation circuit (BU5); The input end of the first relational operation circuit (BU1) is connected to the output end of the D flip-flop circuit (BU4); The input end of the second relational operation circuit (BU2) is connected to the output end of the codeword preprocessing circuit; The input end of the D flip-flop circuit (BU4) is connected to the output end of the codeword preprocessing circuit; The input end of the AND logic operation circuit (BU5) is connected to the output end of the first relational operation circuit (BU1) and the output end of the second relational operation circuit (BU2) respectively.

4. The background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter according to claim 1, characterized in that: The self-returning-to-zero self-adding counter comprises: an adding circuit (CU1), a D flip-flop circuit (CU2), a relational operation circuit (CU3) and a selector (CU5); The output end of the selector (CU5) is connected to the input end of the adding circuit (CU1); The output end of the adding circuit (CU1) is connected to the input end of the D flip-flop circuit (CU2); The input end of the relational operation circuit (CU3) is connected to the output end of the D flip-flop circuit (CU2); The input end of the selector (CU5) is connected to the output end of the relational operation circuit (CU3), and the output end is connected to the input end of the adding circuit (CU1).

5. The background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter according to claim 1, characterized in that: The edge counting circuit comprises: an adding circuit (DU1), a D flip-flop circuit (DU2), a relational operation circuit (DU3) and a selector circuit (DU5); The input end of the adding circuit (DU1) is connected to the output end of the D flip-flop circuit (DU2), and the output end is connected to the input end of the selector circuit (DU5); The input end of the selector circuit (DU5) is connected to the output end of the relational operation circuit (DU3), and the output end is connected to the input end of the D flip-flop circuit (DU2).

6. The background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter according to claim 1, characterized in that: The counting storage circuit comprises: a relational operation circuit (EU3), a D flip-flop circuit (EU1) and a selector circuit (EU2); The output end of the relational operation circuit (EU3) is connected to the input end of the selector circuit (EU2); The output end of the selector circuit (EU2) is connected to the input end of the D flip-flop circuit (EU1); An output end of the D flip-flop circuit (EU1) is connected to an input end of the selector circuit (EU2).

7. The background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter according to claim 1, characterized in that: The polarity decision circuit comprises: a selector circuit (FU5), a polarity input (FU3) and a polarity input (FU4); The input end of the selector circuit (FU5) is connected to the polarity input (FU3), the polarity input (FU4) and the output of the counting storage circuit, and the polarity is determined according to the output of the counting storage circuit.

8. A method for controlling a background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter, applied to a background digital calibration circuit for correcting time skew of a time-interleaved analog-to-digital converter as claimed in any one of claims 1 to 7, characterized in that: include: The preprocessing circuit converts the unipolar codeword into a bipolar codeword; Whenever the bipolar code passes through the zero point, the output of the zero-crossing detection circuit (BU5) is 1, otherwise it is 0; The selector (DU5) of the edge counting circuit will continue to accumulate the number of zero crossings when the output CNT of the self-returning self-adding counter is less than 1023 (CU7), otherwise it will be reset to zero; When the output CNT of the self-returning self-adding counter is equal to 1022 and is about to reach 1023, the counting storage circuit latches the number of zero crossings accumulated by the edge counting circuit in advance and allows the polarity judgment circuit to output the corresponding polarity.

Images